smemc.c 2.5 KB

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  1. /*
  2. * Static Memory Controller
  3. */
  4. #include <linux/module.h>
  5. #include <linux/kernel.h>
  6. #include <linux/init.h>
  7. #include <linux/io.h>
  8. #include <linux/sysdev.h>
  9. #include <mach/hardware.h>
  10. #define SMEMC_PHYS_BASE (0x4A000000)
  11. #define SMEMC_PHYS_SIZE (0x90)
  12. #define MSC0 (0x08) /* Static Memory Controller Register 0 */
  13. #define MSC1 (0x0C) /* Static Memory Controller Register 1 */
  14. #define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */
  15. #define MEMCLKCFG (0x68) /* Clock Configuration */
  16. #define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */
  17. #define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */
  18. #define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */
  19. #define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */
  20. #ifdef CONFIG_PM
  21. static void __iomem *smemc_mmio_base;
  22. static unsigned long msc[2];
  23. static unsigned long sxcnfg, memclkcfg;
  24. static unsigned long csadrcfg[4];
  25. static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state)
  26. {
  27. msc[0] = __raw_readl(smemc_mmio_base + MSC0);
  28. msc[1] = __raw_readl(smemc_mmio_base + MSC1);
  29. sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG);
  30. memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG);
  31. csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0);
  32. csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1);
  33. csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2);
  34. csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3);
  35. return 0;
  36. }
  37. static int pxa3xx_smemc_resume(struct sys_device *dev)
  38. {
  39. __raw_writel(msc[0], smemc_mmio_base + MSC0);
  40. __raw_writel(msc[1], smemc_mmio_base + MSC1);
  41. __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG);
  42. __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG);
  43. __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0);
  44. __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1);
  45. __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2);
  46. __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3);
  47. return 0;
  48. }
  49. static struct sysdev_class smemc_sysclass = {
  50. .name = "smemc",
  51. .suspend = pxa3xx_smemc_suspend,
  52. .resume = pxa3xx_smemc_resume,
  53. };
  54. static struct sys_device smemc_sysdev = {
  55. .id = 0,
  56. .cls = &smemc_sysclass,
  57. };
  58. static int __init smemc_init(void)
  59. {
  60. int ret = 0;
  61. if (cpu_is_pxa3xx()) {
  62. smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
  63. if (smemc_mmio_base == NULL)
  64. return -ENODEV;
  65. ret = sysdev_class_register(&smemc_sysclass);
  66. if (ret)
  67. return ret;
  68. ret = sysdev_register(&smemc_sysdev);
  69. }
  70. return ret;
  71. }
  72. subsys_initcall(smemc_init);
  73. #endif