lpd270.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/lpd270.c
  3. *
  4. * Support for the LogicPD PXA270 Card Engine.
  5. * Derived from the mainstone code, which carries these notices:
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/pwm_backlight.h>
  26. #include <asm/types.h>
  27. #include <asm/setup.h>
  28. #include <asm/memory.h>
  29. #include <asm/mach-types.h>
  30. #include <mach/hardware.h>
  31. #include <asm/irq.h>
  32. #include <asm/sizes.h>
  33. #include <asm/mach/arch.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/mach/irq.h>
  36. #include <asm/mach/flash.h>
  37. #include <mach/pxa27x.h>
  38. #include <mach/gpio.h>
  39. #include <mach/lpd270.h>
  40. #include <mach/audio.h>
  41. #include <mach/pxafb.h>
  42. #include <mach/mmc.h>
  43. #include <mach/irda.h>
  44. #include <mach/ohci.h>
  45. #include "generic.h"
  46. #include "devices.h"
  47. static unsigned long lpd270_pin_config[] __initdata = {
  48. /* Chip Selects */
  49. GPIO15_nCS_1, /* Mainboard Flash */
  50. GPIO78_nCS_2, /* CPLD + Ethernet */
  51. /* LCD - 16bpp Active TFT */
  52. GPIO58_LCD_LDD_0,
  53. GPIO59_LCD_LDD_1,
  54. GPIO60_LCD_LDD_2,
  55. GPIO61_LCD_LDD_3,
  56. GPIO62_LCD_LDD_4,
  57. GPIO63_LCD_LDD_5,
  58. GPIO64_LCD_LDD_6,
  59. GPIO65_LCD_LDD_7,
  60. GPIO66_LCD_LDD_8,
  61. GPIO67_LCD_LDD_9,
  62. GPIO68_LCD_LDD_10,
  63. GPIO69_LCD_LDD_11,
  64. GPIO70_LCD_LDD_12,
  65. GPIO71_LCD_LDD_13,
  66. GPIO72_LCD_LDD_14,
  67. GPIO73_LCD_LDD_15,
  68. GPIO74_LCD_FCLK,
  69. GPIO75_LCD_LCLK,
  70. GPIO76_LCD_PCLK,
  71. GPIO77_LCD_BIAS,
  72. GPIO16_PWM0_OUT, /* Backlight */
  73. /* USB Host */
  74. GPIO88_USBH1_PWR,
  75. GPIO89_USBH1_PEN,
  76. /* AC97 */
  77. GPIO45_AC97_SYSCLK,
  78. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  79. };
  80. static unsigned int lpd270_irq_enabled;
  81. static void lpd270_mask_irq(unsigned int irq)
  82. {
  83. int lpd270_irq = irq - LPD270_IRQ(0);
  84. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  85. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  86. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  87. }
  88. static void lpd270_unmask_irq(unsigned int irq)
  89. {
  90. int lpd270_irq = irq - LPD270_IRQ(0);
  91. lpd270_irq_enabled |= 1 << lpd270_irq;
  92. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  93. }
  94. static struct irq_chip lpd270_irq_chip = {
  95. .name = "CPLD",
  96. .ack = lpd270_mask_irq,
  97. .mask = lpd270_mask_irq,
  98. .unmask = lpd270_unmask_irq,
  99. };
  100. static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
  101. {
  102. unsigned long pending;
  103. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  104. do {
  105. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  106. if (likely(pending)) {
  107. irq = LPD270_IRQ(0) + __ffs(pending);
  108. generic_handle_irq(irq);
  109. pending = __raw_readw(LPD270_INT_STATUS) &
  110. lpd270_irq_enabled;
  111. }
  112. } while (pending);
  113. }
  114. static void __init lpd270_init_irq(void)
  115. {
  116. int irq;
  117. pxa27x_init_irq();
  118. __raw_writew(0, LPD270_INT_MASK);
  119. __raw_writew(0, LPD270_INT_STATUS);
  120. /* setup extra LogicPD PXA270 irqs */
  121. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  122. set_irq_chip(irq, &lpd270_irq_chip);
  123. set_irq_handler(irq, handle_level_irq);
  124. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  125. }
  126. set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
  127. set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
  128. }
  129. #ifdef CONFIG_PM
  130. static int lpd270_irq_resume(struct sys_device *dev)
  131. {
  132. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  133. return 0;
  134. }
  135. static struct sysdev_class lpd270_irq_sysclass = {
  136. .name = "cpld_irq",
  137. .resume = lpd270_irq_resume,
  138. };
  139. static struct sys_device lpd270_irq_device = {
  140. .cls = &lpd270_irq_sysclass,
  141. };
  142. static int __init lpd270_irq_device_init(void)
  143. {
  144. int ret = -ENODEV;
  145. if (machine_is_logicpd_pxa270()) {
  146. ret = sysdev_class_register(&lpd270_irq_sysclass);
  147. if (ret == 0)
  148. ret = sysdev_register(&lpd270_irq_device);
  149. }
  150. return ret;
  151. }
  152. device_initcall(lpd270_irq_device_init);
  153. #endif
  154. static struct resource smc91x_resources[] = {
  155. [0] = {
  156. .start = LPD270_ETH_PHYS,
  157. .end = (LPD270_ETH_PHYS + 0xfffff),
  158. .flags = IORESOURCE_MEM,
  159. },
  160. [1] = {
  161. .start = LPD270_ETHERNET_IRQ,
  162. .end = LPD270_ETHERNET_IRQ,
  163. .flags = IORESOURCE_IRQ,
  164. },
  165. };
  166. static struct platform_device smc91x_device = {
  167. .name = "smc91x",
  168. .id = 0,
  169. .num_resources = ARRAY_SIZE(smc91x_resources),
  170. .resource = smc91x_resources,
  171. };
  172. static struct resource lpd270_flash_resources[] = {
  173. [0] = {
  174. .start = PXA_CS0_PHYS,
  175. .end = PXA_CS0_PHYS + SZ_64M - 1,
  176. .flags = IORESOURCE_MEM,
  177. },
  178. [1] = {
  179. .start = PXA_CS1_PHYS,
  180. .end = PXA_CS1_PHYS + SZ_64M - 1,
  181. .flags = IORESOURCE_MEM,
  182. },
  183. };
  184. static struct mtd_partition lpd270_flash0_partitions[] = {
  185. {
  186. .name = "Bootloader",
  187. .size = 0x00040000,
  188. .offset = 0,
  189. .mask_flags = MTD_WRITEABLE /* force read-only */
  190. }, {
  191. .name = "Kernel",
  192. .size = 0x00400000,
  193. .offset = 0x00040000,
  194. }, {
  195. .name = "Filesystem",
  196. .size = MTDPART_SIZ_FULL,
  197. .offset = 0x00440000
  198. },
  199. };
  200. static struct flash_platform_data lpd270_flash_data[2] = {
  201. {
  202. .name = "processor-flash",
  203. .map_name = "cfi_probe",
  204. .parts = lpd270_flash0_partitions,
  205. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  206. }, {
  207. .name = "mainboard-flash",
  208. .map_name = "cfi_probe",
  209. .parts = NULL,
  210. .nr_parts = 0,
  211. }
  212. };
  213. static struct platform_device lpd270_flash_device[2] = {
  214. {
  215. .name = "pxa2xx-flash",
  216. .id = 0,
  217. .dev = {
  218. .platform_data = &lpd270_flash_data[0],
  219. },
  220. .resource = &lpd270_flash_resources[0],
  221. .num_resources = 1,
  222. }, {
  223. .name = "pxa2xx-flash",
  224. .id = 1,
  225. .dev = {
  226. .platform_data = &lpd270_flash_data[1],
  227. },
  228. .resource = &lpd270_flash_resources[1],
  229. .num_resources = 1,
  230. },
  231. };
  232. static struct platform_pwm_backlight_data lpd270_backlight_data = {
  233. .pwm_id = 0,
  234. .max_brightness = 1,
  235. .dft_brightness = 1,
  236. .pwm_period_ns = 78770,
  237. };
  238. static struct platform_device lpd270_backlight_device = {
  239. .name = "pwm-backlight",
  240. .dev = {
  241. .parent = &pxa27x_device_pwm0.dev,
  242. .platform_data = &lpd270_backlight_data,
  243. },
  244. };
  245. /* 5.7" TFT QVGA (LoLo display number 1) */
  246. static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
  247. .pixclock = 150000,
  248. .xres = 320,
  249. .yres = 240,
  250. .bpp = 16,
  251. .hsync_len = 0x14,
  252. .left_margin = 0x28,
  253. .right_margin = 0x0a,
  254. .vsync_len = 0x02,
  255. .upper_margin = 0x08,
  256. .lower_margin = 0x14,
  257. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  258. };
  259. static struct pxafb_mach_info sharp_lq057q3dc02 = {
  260. .modes = &sharp_lq057q3dc02_mode,
  261. .num_modes = 1,
  262. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  263. LCD_ALTERNATE_MAPPING,
  264. };
  265. /* 12.1" TFT SVGA (LoLo display number 2) */
  266. static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
  267. .pixclock = 50000,
  268. .xres = 800,
  269. .yres = 600,
  270. .bpp = 16,
  271. .hsync_len = 0x05,
  272. .left_margin = 0x52,
  273. .right_margin = 0x05,
  274. .vsync_len = 0x04,
  275. .upper_margin = 0x14,
  276. .lower_margin = 0x0a,
  277. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  278. };
  279. static struct pxafb_mach_info sharp_lq121s1dg31 = {
  280. .modes = &sharp_lq121s1dg31_mode,
  281. .num_modes = 1,
  282. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  283. LCD_ALTERNATE_MAPPING,
  284. };
  285. /* 3.6" TFT QVGA (LoLo display number 3) */
  286. static struct pxafb_mode_info sharp_lq036q1da01_mode = {
  287. .pixclock = 150000,
  288. .xres = 320,
  289. .yres = 240,
  290. .bpp = 16,
  291. .hsync_len = 0x0e,
  292. .left_margin = 0x04,
  293. .right_margin = 0x0a,
  294. .vsync_len = 0x03,
  295. .upper_margin = 0x03,
  296. .lower_margin = 0x03,
  297. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  298. };
  299. static struct pxafb_mach_info sharp_lq036q1da01 = {
  300. .modes = &sharp_lq036q1da01_mode,
  301. .num_modes = 1,
  302. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  303. LCD_ALTERNATE_MAPPING,
  304. };
  305. /* 6.4" TFT VGA (LoLo display number 5) */
  306. static struct pxafb_mode_info sharp_lq64d343_mode = {
  307. .pixclock = 25000,
  308. .xres = 640,
  309. .yres = 480,
  310. .bpp = 16,
  311. .hsync_len = 0x31,
  312. .left_margin = 0x89,
  313. .right_margin = 0x19,
  314. .vsync_len = 0x12,
  315. .upper_margin = 0x22,
  316. .lower_margin = 0x00,
  317. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  318. };
  319. static struct pxafb_mach_info sharp_lq64d343 = {
  320. .modes = &sharp_lq64d343_mode,
  321. .num_modes = 1,
  322. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  323. LCD_ALTERNATE_MAPPING,
  324. };
  325. /* 10.4" TFT VGA (LoLo display number 7) */
  326. static struct pxafb_mode_info sharp_lq10d368_mode = {
  327. .pixclock = 25000,
  328. .xres = 640,
  329. .yres = 480,
  330. .bpp = 16,
  331. .hsync_len = 0x31,
  332. .left_margin = 0x89,
  333. .right_margin = 0x19,
  334. .vsync_len = 0x12,
  335. .upper_margin = 0x22,
  336. .lower_margin = 0x00,
  337. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  338. };
  339. static struct pxafb_mach_info sharp_lq10d368 = {
  340. .modes = &sharp_lq10d368_mode,
  341. .num_modes = 1,
  342. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  343. LCD_ALTERNATE_MAPPING,
  344. };
  345. /* 3.5" TFT QVGA (LoLo display number 8) */
  346. static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
  347. .pixclock = 150000,
  348. .xres = 240,
  349. .yres = 320,
  350. .bpp = 16,
  351. .hsync_len = 0x0e,
  352. .left_margin = 0x0a,
  353. .right_margin = 0x0a,
  354. .vsync_len = 0x03,
  355. .upper_margin = 0x05,
  356. .lower_margin = 0x14,
  357. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  358. };
  359. static struct pxafb_mach_info sharp_lq035q7db02_20 = {
  360. .modes = &sharp_lq035q7db02_20_mode,
  361. .num_modes = 1,
  362. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  363. LCD_ALTERNATE_MAPPING,
  364. };
  365. static struct pxafb_mach_info *lpd270_lcd_to_use;
  366. static int __init lpd270_set_lcd(char *str)
  367. {
  368. if (!strnicmp(str, "lq057q3dc02", 11)) {
  369. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  370. } else if (!strnicmp(str, "lq121s1dg31", 11)) {
  371. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  372. } else if (!strnicmp(str, "lq036q1da01", 11)) {
  373. lpd270_lcd_to_use = &sharp_lq036q1da01;
  374. } else if (!strnicmp(str, "lq64d343", 8)) {
  375. lpd270_lcd_to_use = &sharp_lq64d343;
  376. } else if (!strnicmp(str, "lq10d368", 8)) {
  377. lpd270_lcd_to_use = &sharp_lq10d368;
  378. } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
  379. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  380. } else {
  381. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  382. }
  383. return 1;
  384. }
  385. __setup("lcd=", lpd270_set_lcd);
  386. static struct platform_device *platform_devices[] __initdata = {
  387. &smc91x_device,
  388. &lpd270_backlight_device,
  389. &lpd270_flash_device[0],
  390. &lpd270_flash_device[1],
  391. };
  392. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  393. .port_mode = PMM_PERPORT_MODE,
  394. .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
  395. };
  396. static void __init lpd270_init(void)
  397. {
  398. pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
  399. lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  400. lpd270_flash_data[1].width = 4;
  401. /*
  402. * System bus arbiter setting:
  403. * - Core_Park
  404. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  405. */
  406. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  407. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  408. pxa_set_ac97_info(NULL);
  409. if (lpd270_lcd_to_use != NULL)
  410. set_pxa_fb_info(lpd270_lcd_to_use);
  411. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  412. }
  413. static struct map_desc lpd270_io_desc[] __initdata = {
  414. {
  415. .virtual = LPD270_CPLD_VIRT,
  416. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  417. .length = LPD270_CPLD_SIZE,
  418. .type = MT_DEVICE,
  419. },
  420. };
  421. static void __init lpd270_map_io(void)
  422. {
  423. pxa_map_io();
  424. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  425. /* for use I SRAM as framebuffer. */
  426. PSLR |= 0x00000F04;
  427. PCFR = 0x00000066;
  428. }
  429. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  430. /* Maintainer: Peter Barada */
  431. .phys_io = 0x40000000,
  432. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  433. .boot_params = 0xa0000100,
  434. .map_io = lpd270_map_io,
  435. .init_irq = lpd270_init_irq,
  436. .timer = &pxa_timer,
  437. .init_machine = lpd270_init,
  438. MACHINE_END