timer-gp.c 6.1 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/timer-gp.c
  3. *
  4. * OMAP2 GP timer support.
  5. *
  6. * Copyright (C) 2009 Nokia Corporation
  7. *
  8. * Update to use new clocksource/clockevent layers
  9. * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10. * Copyright (C) 2007 MontaVista Software, Inc.
  11. *
  12. * Original driver:
  13. * Copyright (C) 2005 Nokia Corporation
  14. * Author: Paul Mundt <paul.mundt@nokia.com>
  15. * Juha Yrjölä <juha.yrjola@nokia.com>
  16. * OMAP Dual-mode timer framework support by Timo Teras
  17. *
  18. * Some parts based off of TI's 24xx code:
  19. *
  20. * Copyright (C) 2004 Texas Instruments, Inc.
  21. *
  22. * Roughly modelled after the OMAP1 MPU timer code.
  23. *
  24. * This file is subject to the terms and conditions of the GNU General Public
  25. * License. See the file "COPYING" in the main directory of this archive
  26. * for more details.
  27. */
  28. #include <linux/init.h>
  29. #include <linux/time.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/err.h>
  32. #include <linux/clk.h>
  33. #include <linux/delay.h>
  34. #include <linux/irq.h>
  35. #include <linux/clocksource.h>
  36. #include <linux/clockchips.h>
  37. #include <asm/mach/time.h>
  38. #include <mach/dmtimer.h>
  39. /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  40. #define MAX_GPTIMER_ID 12
  41. static struct omap_dm_timer *gptimer;
  42. static struct clock_event_device clockevent_gpt;
  43. static u8 __initdata gptimer_id = 1;
  44. static u8 __initdata inited;
  45. static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  46. {
  47. struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
  48. struct clock_event_device *evt = &clockevent_gpt;
  49. omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
  50. evt->event_handler(evt);
  51. return IRQ_HANDLED;
  52. }
  53. static struct irqaction omap2_gp_timer_irq = {
  54. .name = "gp timer",
  55. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  56. .handler = omap2_gp_timer_interrupt,
  57. };
  58. static int omap2_gp_timer_set_next_event(unsigned long cycles,
  59. struct clock_event_device *evt)
  60. {
  61. omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
  62. return 0;
  63. }
  64. static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
  65. struct clock_event_device *evt)
  66. {
  67. u32 period;
  68. omap_dm_timer_stop(gptimer);
  69. switch (mode) {
  70. case CLOCK_EVT_MODE_PERIODIC:
  71. period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
  72. period -= 1;
  73. omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
  74. break;
  75. case CLOCK_EVT_MODE_ONESHOT:
  76. break;
  77. case CLOCK_EVT_MODE_UNUSED:
  78. case CLOCK_EVT_MODE_SHUTDOWN:
  79. case CLOCK_EVT_MODE_RESUME:
  80. break;
  81. }
  82. }
  83. static struct clock_event_device clockevent_gpt = {
  84. .name = "gp timer",
  85. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  86. .shift = 32,
  87. .set_next_event = omap2_gp_timer_set_next_event,
  88. .set_mode = omap2_gp_timer_set_mode,
  89. };
  90. /**
  91. * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
  92. * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
  93. *
  94. * Define the GPTIMER that the system should use for the tick timer.
  95. * Meant to be called from board-*.c files in the event that GPTIMER1, the
  96. * default, is unsuitable. Returns -EINVAL on error or 0 on success.
  97. */
  98. int __init omap2_gp_clockevent_set_gptimer(u8 id)
  99. {
  100. if (id < 1 || id > MAX_GPTIMER_ID)
  101. return -EINVAL;
  102. BUG_ON(inited);
  103. gptimer_id = id;
  104. return 0;
  105. }
  106. static void __init omap2_gp_clockevent_init(void)
  107. {
  108. u32 tick_rate;
  109. int src;
  110. inited = 1;
  111. gptimer = omap_dm_timer_request_specific(gptimer_id);
  112. BUG_ON(gptimer == NULL);
  113. #if defined(CONFIG_OMAP_32K_TIMER)
  114. src = OMAP_TIMER_SRC_32_KHZ;
  115. #else
  116. src = OMAP_TIMER_SRC_SYS_CLK;
  117. WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
  118. "secure 32KiHz clock source\n");
  119. #endif
  120. if (gptimer_id != 12)
  121. WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
  122. "timer-gp: omap_dm_timer_set_source() failed\n");
  123. tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
  124. pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
  125. gptimer_id, tick_rate);
  126. omap2_gp_timer_irq.dev_id = (void *)gptimer;
  127. setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
  128. omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
  129. clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
  130. clockevent_gpt.shift);
  131. clockevent_gpt.max_delta_ns =
  132. clockevent_delta2ns(0xffffffff, &clockevent_gpt);
  133. clockevent_gpt.min_delta_ns =
  134. clockevent_delta2ns(3, &clockevent_gpt);
  135. /* Timer internal resynch latency. */
  136. clockevent_gpt.cpumask = cpumask_of(0);
  137. clockevents_register_device(&clockevent_gpt);
  138. }
  139. /* Clocksource code */
  140. #ifdef CONFIG_OMAP_32K_TIMER
  141. /*
  142. * When 32k-timer is enabled, don't use GPTimer for clocksource
  143. * instead, just leave default clocksource which uses the 32k
  144. * sync counter. See clocksource setup in see plat-omap/common.c.
  145. */
  146. static inline void __init omap2_gp_clocksource_init(void) {}
  147. #else
  148. /*
  149. * clocksource
  150. */
  151. static struct omap_dm_timer *gpt_clocksource;
  152. static cycle_t clocksource_read_cycles(struct clocksource *cs)
  153. {
  154. return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
  155. }
  156. static struct clocksource clocksource_gpt = {
  157. .name = "gp timer",
  158. .rating = 300,
  159. .read = clocksource_read_cycles,
  160. .mask = CLOCKSOURCE_MASK(32),
  161. .shift = 24,
  162. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  163. };
  164. /* Setup free-running counter for clocksource */
  165. static void __init omap2_gp_clocksource_init(void)
  166. {
  167. static struct omap_dm_timer *gpt;
  168. u32 tick_rate, tick_period;
  169. static char err1[] __initdata = KERN_ERR
  170. "%s: failed to request dm-timer\n";
  171. static char err2[] __initdata = KERN_ERR
  172. "%s: can't register clocksource!\n";
  173. gpt = omap_dm_timer_request();
  174. if (!gpt)
  175. printk(err1, clocksource_gpt.name);
  176. gpt_clocksource = gpt;
  177. omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
  178. tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
  179. tick_period = (tick_rate / HZ) - 1;
  180. omap_dm_timer_set_load_start(gpt, 1, 0);
  181. clocksource_gpt.mult =
  182. clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
  183. if (clocksource_register(&clocksource_gpt))
  184. printk(err2, clocksource_gpt.name);
  185. }
  186. #endif
  187. static void __init omap2_gp_timer_init(void)
  188. {
  189. omap_dm_timer_init();
  190. omap2_gp_clockevent_init();
  191. omap2_gp_clocksource_init();
  192. }
  193. struct sys_timer omap_timer = {
  194. .init = omap2_gp_timer_init,
  195. };