sram243x.S 10.0 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/sram243x.S
  3. *
  4. * Omap2 specific functions that need to be run in internal SRAM
  5. *
  6. * (C) Copyright 2004
  7. * Texas Instruments, <www.ti.com>
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <linux/linkage.h>
  26. #include <asm/assembler.h>
  27. #include <mach/io.h>
  28. #include <mach/hardware.h>
  29. #include "prm.h"
  30. #include "cm.h"
  31. #include "sdrc.h"
  32. .text
  33. ENTRY(omap243x_sram_ddr_init)
  34. stmfd sp!, {r0 - r12, lr} @ save registers on stack
  35. mov r12, r2 @ capture CS1 vs CS0
  36. mov r8, r3 @ capture force parameter
  37. /* frequency shift down */
  38. ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
  39. mov r3, #0x1 @ value for 1x operation
  40. str r3, [r2] @ go to L1-freq operation
  41. /* voltage shift down */
  42. mov r9, #0x1 @ set up for L1 voltage call
  43. bl voltage_shift @ go drop voltage
  44. /* dll lock mode */
  45. ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
  46. ldr r10, [r11] @ get current val
  47. cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
  48. addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
  49. mvn r9, #0x4 @ mask to get clear bit2
  50. and r10, r10, r9 @ clear bit2 for lock mode.
  51. orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
  52. orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
  53. str r10, [r11] @ commit to DLLA_CTRL
  54. bl i_dll_wait @ wait for dll to lock
  55. /* get dll value */
  56. add r11, r11, #0x4 @ get addr of status reg
  57. ldr r10, [r11] @ get locked value
  58. /* voltage shift up */
  59. mov r9, #0x0 @ shift back to L0-voltage
  60. bl voltage_shift @ go raise voltage
  61. /* frequency shift up */
  62. mov r3, #0x2 @ value for 2x operation
  63. str r3, [r2] @ go to L0-freq operation
  64. /* reset entry mode for dllctrl */
  65. sub r11, r11, #0x4 @ move from status to ctrl
  66. cmp r12, #0x1 @ normalize if cs1 based
  67. subeq r11, r11, #0x8 @ possibly back to DLLA
  68. cmp r8, #0x1 @ if forced unlock exit
  69. orreq r1, r1, #0x4 @ make sure exit with unlocked value
  70. str r1, [r11] @ restore DLLA_CTRL high value
  71. add r11, r11, #0x8 @ move to DLLB_CTRL addr
  72. str r1, [r11] @ set value DLLB_CTRL
  73. bl i_dll_wait @ wait for possible lock
  74. /* set up for return, DDR should be good */
  75. str r10, [r0] @ write dll_status and return counter
  76. ldmfd sp!, {r0 - r12, pc} @ restore regs and return
  77. /* ensure the DLL has relocked */
  78. i_dll_wait:
  79. mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
  80. i_dll_delay:
  81. subs r4, r4, #0x1
  82. bne i_dll_delay
  83. mov pc, lr
  84. /*
  85. * shift up or down voltage, use R9 as input to tell level.
  86. * wait for it to finish, use 32k sync counter, 1tick=31uS.
  87. */
  88. voltage_shift:
  89. ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
  90. ldr r5, [r4] @ get value.
  91. ldr r6, prcm_mask_val @ get value of mask
  92. and r5, r5, r6 @ apply mask to clear bits
  93. orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
  94. str r5, [r4] @ set up for change.
  95. mov r3, #0x4000 @ get val for force
  96. orr r5, r5, r3 @ build value for force
  97. str r5, [r4] @ Force transition to L1
  98. ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
  99. ldr r5, [r3] @ get value
  100. add r5, r5, #0x3 @ give it at most 93uS
  101. volt_delay:
  102. ldr r7, [r3] @ get timer value
  103. cmp r5, r7 @ time up?
  104. bhi volt_delay @ not yet->branch
  105. mov pc, lr @ back to caller.
  106. omap243x_sdi_cm_clksel2_pll:
  107. .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
  108. omap243x_sdi_sdrc_dlla_ctrl:
  109. .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
  110. omap243x_sdi_prcm_voltctrl:
  111. .word OMAP243X_PRCM_VOLTCTRL
  112. prcm_mask_val:
  113. .word 0xFFFF3FFC
  114. omap243x_sdi_timer_32ksynct_cr:
  115. .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
  116. ENTRY(omap243x_sram_ddr_init_sz)
  117. .word . - omap243x_sram_ddr_init
  118. /*
  119. * Reprograms memory timings.
  120. * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
  121. * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
  122. */
  123. ENTRY(omap243x_sram_reprogram_sdrc)
  124. stmfd sp!, {r0 - r10, lr} @ save registers on stack
  125. mov r3, #0x0 @ clear for mrc call
  126. mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
  127. nop
  128. nop
  129. ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
  130. ldr r5, [r6] @ get value
  131. mov r5, r5, lsr #8 @ isolate rfr field and drop burst
  132. cmp r0, #0x1 @ going to half speed?
  133. movne r9, #0x0 @ if up set flag up for pre up, hi volt
  134. blne voltage_shift_c @ adjust voltage
  135. cmp r0, #0x1 @ going to half speed (post branch link)
  136. moveq r5, r5, lsr #1 @ divide by 2 if to half
  137. movne r5, r5, lsl #1 @ mult by 2 if to full
  138. mov r5, r5, lsl #8 @ put rfr field back into place
  139. add r5, r5, #0x1 @ turn on burst of 1
  140. ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
  141. ldr r3, [r4] @ get curr value
  142. orr r3, r3, #0x3
  143. bic r3, r3, #0x3 @ clear lower bits
  144. orr r3, r3, r0 @ new state value
  145. str r3, [r4] @ set new state (pll/x, x=1 or 2)
  146. nop
  147. nop
  148. moveq r9, #0x1 @ if speed down, post down, drop volt
  149. bleq voltage_shift_c
  150. mcr p15, 0, r3, c7, c10, 4 @ memory barrier
  151. str r5, [r6] @ set new RFR_1 value
  152. add r6, r6, #0x30 @ get RFR_2 addr
  153. str r5, [r6] @ set RFR_2
  154. nop
  155. cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
  156. bne freq_out @ leave if SDR, no DLL function
  157. /* With DDR, we need to take care of the DLL for the frequency change */
  158. ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
  159. str r1, [r2] @ write out new SDRC_DLLA_CTRL
  160. add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
  161. str r1, [r2] @ commit to SDRC_DLLB_CTRL
  162. mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
  163. dll_wait:
  164. subs r1, r1, #0x1
  165. bne dll_wait
  166. freq_out:
  167. ldmfd sp!, {r0 - r10, pc} @ restore regs and return
  168. /*
  169. * shift up or down voltage, use R9 as input to tell level.
  170. * wait for it to finish, use 32k sync counter, 1tick=31uS.
  171. */
  172. voltage_shift_c:
  173. ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
  174. ldr r8, [r10] @ get value
  175. ldr r7, ddr_prcm_mask_val @ get value of mask
  176. and r8, r8, r7 @ apply mask to clear bits
  177. orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
  178. str r8, [r10] @ set up for change.
  179. mov r7, #0x4000 @ get val for force
  180. orr r8, r8, r7 @ build value for force
  181. str r8, [r10] @ Force transition to L1
  182. ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
  183. ldr r8, [r10] @ get value
  184. add r8, r8, #0x2 @ give it at most 62uS (min 31+)
  185. volt_delay_c:
  186. ldr r7, [r10] @ get timer value
  187. cmp r8, r7 @ time up?
  188. bhi volt_delay_c @ not yet->branch
  189. mov pc, lr @ back to caller
  190. omap243x_srs_cm_clksel2_pll:
  191. .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
  192. omap243x_srs_sdrc_dlla_ctrl:
  193. .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
  194. omap243x_srs_sdrc_rfr_ctrl:
  195. .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
  196. omap243x_srs_prcm_voltctrl:
  197. .word OMAP243X_PRCM_VOLTCTRL
  198. ddr_prcm_mask_val:
  199. .word 0xFFFF3FFC
  200. omap243x_srs_timer_32ksynct:
  201. .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
  202. ENTRY(omap243x_sram_reprogram_sdrc_sz)
  203. .word . - omap243x_sram_reprogram_sdrc
  204. /*
  205. * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  206. */
  207. ENTRY(omap243x_sram_set_prcm)
  208. stmfd sp!, {r0-r12, lr} @ regs to stack
  209. adr r4, pbegin @ addr of preload start
  210. adr r8, pend @ addr of preload end
  211. mcrr p15, 1, r8, r4, c12 @ preload into icache
  212. pbegin:
  213. /* move into fast relock bypass */
  214. ldr r8, omap243x_ssp_pll_ctl @ get addr
  215. ldr r5, [r8] @ get val
  216. mvn r6, #0x3 @ clear mask
  217. and r5, r5, r6 @ clear field
  218. orr r7, r5, #0x2 @ fast relock val
  219. str r7, [r8] @ go to fast relock
  220. ldr r4, omap243x_ssp_pll_stat @ addr of stat
  221. block:
  222. /* wait for bypass */
  223. ldr r8, [r4] @ stat value
  224. and r8, r8, #0x3 @ mask for stat
  225. cmp r8, #0x1 @ there yet
  226. bne block @ loop if not
  227. /* set new dpll dividers _after_ in bypass */
  228. ldr r4, omap243x_ssp_pll_div @ get addr
  229. str r0, [r4] @ set dpll ctrl val
  230. ldr r4, omap243x_ssp_set_config @ get addr
  231. mov r8, #1 @ valid cfg msk
  232. str r8, [r4] @ make dividers take
  233. mov r4, #100 @ dead spin a bit
  234. wait_a_bit:
  235. subs r4, r4, #1 @ dec loop
  236. bne wait_a_bit @ delay done?
  237. /* check if staying in bypass */
  238. cmp r2, #0x1 @ stay in bypass?
  239. beq pend @ jump over dpll relock
  240. /* relock DPLL with new vals */
  241. ldr r5, omap243x_ssp_pll_stat @ get addr
  242. ldr r4, omap243x_ssp_pll_ctl @ get addr
  243. orr r8, r7, #0x3 @ val for lock dpll
  244. str r8, [r4] @ set val
  245. mov r0, #1000 @ dead spin a bit
  246. wait_more:
  247. subs r0, r0, #1 @ dec loop
  248. bne wait_more @ delay done?
  249. wait_lock:
  250. ldr r8, [r5] @ get lock val
  251. and r8, r8, #3 @ isolate field
  252. cmp r8, #2 @ locked?
  253. bne wait_lock @ wait if not
  254. pend:
  255. /* update memory timings & briefly lock dll */
  256. ldr r4, omap243x_ssp_sdrc_rfr @ get addr
  257. str r1, [r4] @ update refresh timing
  258. ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
  259. ldr r10, [r11] @ get current val
  260. mvn r9, #0x4 @ mask to get clear bit2
  261. and r10, r10, r9 @ clear bit2 for lock mode
  262. orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
  263. str r10, [r11] @ commit to DLLA_CTRL
  264. add r11, r11, #0x8 @ move to dllb
  265. str r10, [r11] @ hit DLLB also
  266. mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
  267. wait_dll_lock:
  268. subs r4, r4, #0x1
  269. bne wait_dll_lock
  270. nop
  271. ldmfd sp!, {r0-r12, pc} @ restore regs and return
  272. omap243x_ssp_set_config:
  273. .word OMAP243X_PRCM_CLKCFG_CTRL
  274. omap243x_ssp_pll_ctl:
  275. .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
  276. omap243x_ssp_pll_stat:
  277. .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
  278. omap243x_ssp_pll_div:
  279. .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
  280. omap243x_ssp_sdrc_rfr:
  281. .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
  282. omap243x_ssp_dlla_ctrl:
  283. .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
  284. ENTRY(omap243x_sram_set_prcm_sz)
  285. .word . - omap243x_sram_set_prcm