ucc_slow.c 9.7 KB

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  1. /*
  2. * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
  3. *
  4. * Authors: Shlomi Gridish <gridish@freescale.com>
  5. * Li Yang <leoli@freescale.com>
  6. *
  7. * Description:
  8. * QE UCC Slow API Set - UCC Slow specific routines implementations.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/errno.h>
  18. #include <linux/slab.h>
  19. #include <linux/stddef.h>
  20. #include <linux/interrupt.h>
  21. #include <asm/io.h>
  22. #include <asm/immap_qe.h>
  23. #include <asm/qe.h>
  24. #include <asm/ucc.h>
  25. #include <asm/ucc_slow.h>
  26. u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
  27. {
  28. switch (uccs_num) {
  29. case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
  30. case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
  31. case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
  32. case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
  33. case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
  34. case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
  35. case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
  36. case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
  37. default: return QE_CR_SUBBLOCK_INVALID;
  38. }
  39. }
  40. void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
  41. {
  42. out_be16(&uccs->us_regs->utodr, UCC_SLOW_TOD);
  43. }
  44. void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
  45. {
  46. struct ucc_slow_info *us_info = uccs->us_info;
  47. u32 id;
  48. id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  49. qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
  50. QE_CR_PROTOCOL_UNSPECIFIED, 0);
  51. }
  52. void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
  53. {
  54. struct ucc_slow_info *us_info = uccs->us_info;
  55. u32 id;
  56. id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  57. qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  58. }
  59. void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
  60. {
  61. struct ucc_slow_info *us_info = uccs->us_info;
  62. u32 id;
  63. id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  64. qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  65. }
  66. void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
  67. {
  68. struct ucc_slow *us_regs;
  69. u32 gumr_l;
  70. us_regs = uccs->us_regs;
  71. /* Enable reception and/or transmission on this UCC. */
  72. gumr_l = in_be32(&us_regs->gumr_l);
  73. if (mode & COMM_DIR_TX) {
  74. gumr_l |= UCC_SLOW_GUMR_L_ENT;
  75. uccs->enabled_tx = 1;
  76. }
  77. if (mode & COMM_DIR_RX) {
  78. gumr_l |= UCC_SLOW_GUMR_L_ENR;
  79. uccs->enabled_rx = 1;
  80. }
  81. out_be32(&us_regs->gumr_l, gumr_l);
  82. }
  83. void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
  84. {
  85. struct ucc_slow *us_regs;
  86. u32 gumr_l;
  87. us_regs = uccs->us_regs;
  88. /* Disable reception and/or transmission on this UCC. */
  89. gumr_l = in_be32(&us_regs->gumr_l);
  90. if (mode & COMM_DIR_TX) {
  91. gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
  92. uccs->enabled_tx = 0;
  93. }
  94. if (mode & COMM_DIR_RX) {
  95. gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
  96. uccs->enabled_rx = 0;
  97. }
  98. out_be32(&us_regs->gumr_l, gumr_l);
  99. }
  100. int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
  101. {
  102. struct ucc_slow_private *uccs;
  103. u32 i;
  104. struct ucc_slow *us_regs;
  105. u32 gumr;
  106. struct qe_bd *bd;
  107. u32 id;
  108. u32 command;
  109. int ret = 0;
  110. if (!us_info)
  111. return -EINVAL;
  112. /* check if the UCC port number is in range. */
  113. if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
  114. printk(KERN_ERR "%s: illegal UCC number", __FUNCTION__);
  115. return -EINVAL;
  116. }
  117. /*
  118. * Set mrblr
  119. * Check that 'max_rx_buf_length' is properly aligned (4), unless
  120. * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
  121. * case when QE accepts 32 bits at a time.
  122. */
  123. if ((!us_info->rfw) &&
  124. (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
  125. printk(KERN_ERR "max_rx_buf_length not aligned.");
  126. return -EINVAL;
  127. }
  128. uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
  129. if (!uccs) {
  130. printk(KERN_ERR "%s: Cannot allocate private data", __FUNCTION__);
  131. return -ENOMEM;
  132. }
  133. /* Fill slow UCC structure */
  134. uccs->us_info = us_info;
  135. /* Set the PHY base address */
  136. uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
  137. if (uccs->us_regs == NULL) {
  138. printk(KERN_ERR "%s: Cannot map UCC registers", __FUNCTION__);
  139. return -ENOMEM;
  140. }
  141. uccs->saved_uccm = 0;
  142. uccs->p_rx_frame = 0;
  143. us_regs = uccs->us_regs;
  144. uccs->p_ucce = (u16 *) & (us_regs->ucce);
  145. uccs->p_uccm = (u16 *) & (us_regs->uccm);
  146. #ifdef STATISTICS
  147. uccs->rx_frames = 0;
  148. uccs->tx_frames = 0;
  149. uccs->rx_discarded = 0;
  150. #endif /* STATISTICS */
  151. /* Get PRAM base */
  152. uccs->us_pram_offset =
  153. qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
  154. if (IS_MURAM_ERR(uccs->us_pram_offset)) {
  155. printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __FUNCTION__);
  156. ucc_slow_free(uccs);
  157. return -ENOMEM;
  158. }
  159. id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  160. qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, QE_CR_PROTOCOL_UNSPECIFIED,
  161. uccs->us_pram_offset);
  162. uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
  163. /* Init Guemr register */
  164. if ((ret = ucc_init_guemr((struct ucc_common *) (us_info->regs)))) {
  165. printk(KERN_ERR "%s: cannot init GUEMR", __FUNCTION__);
  166. ucc_slow_free(uccs);
  167. return ret;
  168. }
  169. /* Set UCC to slow type */
  170. if ((ret = ucc_set_type(us_info->ucc_num,
  171. (struct ucc_common *) (us_info->regs),
  172. UCC_SPEED_TYPE_SLOW))) {
  173. printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
  174. ucc_slow_free(uccs);
  175. return ret;
  176. }
  177. out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
  178. INIT_LIST_HEAD(&uccs->confQ);
  179. /* Allocate BDs. */
  180. uccs->rx_base_offset =
  181. qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
  182. QE_ALIGNMENT_OF_BD);
  183. if (IS_MURAM_ERR(uccs->rx_base_offset)) {
  184. printk(KERN_ERR "%s: cannot allocate RX BDs", __FUNCTION__);
  185. uccs->rx_base_offset = 0;
  186. ucc_slow_free(uccs);
  187. return -ENOMEM;
  188. }
  189. uccs->tx_base_offset =
  190. qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
  191. QE_ALIGNMENT_OF_BD);
  192. if (IS_MURAM_ERR(uccs->tx_base_offset)) {
  193. printk(KERN_ERR "%s: cannot allocate TX BDs", __FUNCTION__);
  194. uccs->tx_base_offset = 0;
  195. ucc_slow_free(uccs);
  196. return -ENOMEM;
  197. }
  198. /* Init Tx bds */
  199. bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
  200. for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
  201. /* clear bd buffer */
  202. out_be32(&bd->buf, 0);
  203. /* set bd status and length */
  204. out_be32((u32 *) bd, 0);
  205. bd++;
  206. }
  207. /* for last BD set Wrap bit */
  208. out_be32(&bd->buf, 0);
  209. out_be32((u32 *) bd, cpu_to_be32(T_W));
  210. /* Init Rx bds */
  211. bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
  212. for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
  213. /* set bd status and length */
  214. out_be32((u32*)bd, 0);
  215. /* clear bd buffer */
  216. out_be32(&bd->buf, 0);
  217. bd++;
  218. }
  219. /* for last BD set Wrap bit */
  220. out_be32((u32*)bd, cpu_to_be32(R_W));
  221. out_be32(&bd->buf, 0);
  222. /* Set GUMR (For more details see the hardware spec.). */
  223. /* gumr_h */
  224. gumr = us_info->tcrc;
  225. if (us_info->cdp)
  226. gumr |= UCC_SLOW_GUMR_H_CDP;
  227. if (us_info->ctsp)
  228. gumr |= UCC_SLOW_GUMR_H_CTSP;
  229. if (us_info->cds)
  230. gumr |= UCC_SLOW_GUMR_H_CDS;
  231. if (us_info->ctss)
  232. gumr |= UCC_SLOW_GUMR_H_CTSS;
  233. if (us_info->tfl)
  234. gumr |= UCC_SLOW_GUMR_H_TFL;
  235. if (us_info->rfw)
  236. gumr |= UCC_SLOW_GUMR_H_RFW;
  237. if (us_info->txsy)
  238. gumr |= UCC_SLOW_GUMR_H_TXSY;
  239. if (us_info->rtsm)
  240. gumr |= UCC_SLOW_GUMR_H_RTSM;
  241. out_be32(&us_regs->gumr_h, gumr);
  242. /* gumr_l */
  243. gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
  244. us_info->diag | us_info->mode;
  245. if (us_info->tci)
  246. gumr |= UCC_SLOW_GUMR_L_TCI;
  247. if (us_info->rinv)
  248. gumr |= UCC_SLOW_GUMR_L_RINV;
  249. if (us_info->tinv)
  250. gumr |= UCC_SLOW_GUMR_L_TINV;
  251. if (us_info->tend)
  252. gumr |= UCC_SLOW_GUMR_L_TEND;
  253. out_be32(&us_regs->gumr_l, gumr);
  254. /* Function code registers */
  255. /* if the data is in cachable memory, the 'global' */
  256. /* in the function code should be set. */
  257. uccs->us_pram->tfcr = uccs->us_pram->rfcr =
  258. us_info->data_mem_part | QE_BMR_BYTE_ORDER_BO_MOT;
  259. /* rbase, tbase are offsets from MURAM base */
  260. out_be16(&uccs->us_pram->rbase, uccs->us_pram_offset);
  261. out_be16(&uccs->us_pram->tbase, uccs->us_pram_offset);
  262. /* Mux clocking */
  263. /* Grant Support */
  264. ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
  265. /* Breakpoint Support */
  266. ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
  267. /* Set Tsa or NMSI mode. */
  268. ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
  269. /* If NMSI (not Tsa), set Tx and Rx clock. */
  270. if (!us_info->tsa) {
  271. /* Rx clock routing */
  272. if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
  273. COMM_DIR_RX)) {
  274. printk(KERN_ERR "%s: illegal value for RX clock",
  275. __FUNCTION__);
  276. ucc_slow_free(uccs);
  277. return -EINVAL;
  278. }
  279. /* Tx clock routing */
  280. if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
  281. COMM_DIR_TX)) {
  282. printk(KERN_ERR "%s: illegal value for TX clock",
  283. __FUNCTION__);
  284. ucc_slow_free(uccs);
  285. return -EINVAL;
  286. }
  287. }
  288. /* Set interrupt mask register at UCC level. */
  289. out_be16(&us_regs->uccm, us_info->uccm_mask);
  290. /* First, clear anything pending at UCC level,
  291. * otherwise, old garbage may come through
  292. * as soon as the dam is opened. */
  293. /* Writing '1' clears */
  294. out_be16(&us_regs->ucce, 0xffff);
  295. /* Issue QE Init command */
  296. if (us_info->init_tx && us_info->init_rx)
  297. command = QE_INIT_TX_RX;
  298. else if (us_info->init_tx)
  299. command = QE_INIT_TX;
  300. else
  301. command = QE_INIT_RX; /* We know at least one is TRUE */
  302. id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  303. qe_issue_cmd(command, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  304. *uccs_ret = uccs;
  305. return 0;
  306. }
  307. void ucc_slow_free(struct ucc_slow_private * uccs)
  308. {
  309. if (!uccs)
  310. return;
  311. if (uccs->rx_base_offset)
  312. qe_muram_free(uccs->rx_base_offset);
  313. if (uccs->tx_base_offset)
  314. qe_muram_free(uccs->tx_base_offset);
  315. if (uccs->us_pram) {
  316. qe_muram_free(uccs->us_pram_offset);
  317. uccs->us_pram = NULL;
  318. }
  319. kfree(uccs);
  320. }