mpic.c 41 KB

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  1. /*
  2. * arch/powerpc/kernel/mpic.c
  3. *
  4. * Driver for interrupt controllers following the OpenPIC standard, the
  5. * common implementation beeing IBM's MPIC. This driver also can deal
  6. * with various broken implementations of this HW.
  7. *
  8. * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
  9. *
  10. * This file is subject to the terms and conditions of the GNU General Public
  11. * License. See the file COPYING in the main directory of this archive
  12. * for more details.
  13. */
  14. #undef DEBUG
  15. #undef DEBUG_IPI
  16. #undef DEBUG_IRQ
  17. #undef DEBUG_LOW
  18. #include <linux/types.h>
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/irq.h>
  22. #include <linux/smp.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/bootmem.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/pci.h>
  27. #include <asm/ptrace.h>
  28. #include <asm/signal.h>
  29. #include <asm/io.h>
  30. #include <asm/pgtable.h>
  31. #include <asm/irq.h>
  32. #include <asm/machdep.h>
  33. #include <asm/mpic.h>
  34. #include <asm/smp.h>
  35. #include "mpic.h"
  36. #ifdef DEBUG
  37. #define DBG(fmt...) printk(fmt)
  38. #else
  39. #define DBG(fmt...)
  40. #endif
  41. static struct mpic *mpics;
  42. static struct mpic *mpic_primary;
  43. static DEFINE_SPINLOCK(mpic_lock);
  44. #ifdef CONFIG_PPC32 /* XXX for now */
  45. #ifdef CONFIG_IRQ_ALL_CPUS
  46. #define distribute_irqs (1)
  47. #else
  48. #define distribute_irqs (0)
  49. #endif
  50. #endif
  51. #ifdef CONFIG_MPIC_WEIRD
  52. static u32 mpic_infos[][MPIC_IDX_END] = {
  53. [0] = { /* Original OpenPIC compatible MPIC */
  54. MPIC_GREG_BASE,
  55. MPIC_GREG_FEATURE_0,
  56. MPIC_GREG_GLOBAL_CONF_0,
  57. MPIC_GREG_VENDOR_ID,
  58. MPIC_GREG_IPI_VECTOR_PRI_0,
  59. MPIC_GREG_IPI_STRIDE,
  60. MPIC_GREG_SPURIOUS,
  61. MPIC_GREG_TIMER_FREQ,
  62. MPIC_TIMER_BASE,
  63. MPIC_TIMER_STRIDE,
  64. MPIC_TIMER_CURRENT_CNT,
  65. MPIC_TIMER_BASE_CNT,
  66. MPIC_TIMER_VECTOR_PRI,
  67. MPIC_TIMER_DESTINATION,
  68. MPIC_CPU_BASE,
  69. MPIC_CPU_STRIDE,
  70. MPIC_CPU_IPI_DISPATCH_0,
  71. MPIC_CPU_IPI_DISPATCH_STRIDE,
  72. MPIC_CPU_CURRENT_TASK_PRI,
  73. MPIC_CPU_WHOAMI,
  74. MPIC_CPU_INTACK,
  75. MPIC_CPU_EOI,
  76. MPIC_IRQ_BASE,
  77. MPIC_IRQ_STRIDE,
  78. MPIC_IRQ_VECTOR_PRI,
  79. MPIC_VECPRI_VECTOR_MASK,
  80. MPIC_VECPRI_POLARITY_POSITIVE,
  81. MPIC_VECPRI_POLARITY_NEGATIVE,
  82. MPIC_VECPRI_SENSE_LEVEL,
  83. MPIC_VECPRI_SENSE_EDGE,
  84. MPIC_VECPRI_POLARITY_MASK,
  85. MPIC_VECPRI_SENSE_MASK,
  86. MPIC_IRQ_DESTINATION
  87. },
  88. [1] = { /* Tsi108/109 PIC */
  89. TSI108_GREG_BASE,
  90. TSI108_GREG_FEATURE_0,
  91. TSI108_GREG_GLOBAL_CONF_0,
  92. TSI108_GREG_VENDOR_ID,
  93. TSI108_GREG_IPI_VECTOR_PRI_0,
  94. TSI108_GREG_IPI_STRIDE,
  95. TSI108_GREG_SPURIOUS,
  96. TSI108_GREG_TIMER_FREQ,
  97. TSI108_TIMER_BASE,
  98. TSI108_TIMER_STRIDE,
  99. TSI108_TIMER_CURRENT_CNT,
  100. TSI108_TIMER_BASE_CNT,
  101. TSI108_TIMER_VECTOR_PRI,
  102. TSI108_TIMER_DESTINATION,
  103. TSI108_CPU_BASE,
  104. TSI108_CPU_STRIDE,
  105. TSI108_CPU_IPI_DISPATCH_0,
  106. TSI108_CPU_IPI_DISPATCH_STRIDE,
  107. TSI108_CPU_CURRENT_TASK_PRI,
  108. TSI108_CPU_WHOAMI,
  109. TSI108_CPU_INTACK,
  110. TSI108_CPU_EOI,
  111. TSI108_IRQ_BASE,
  112. TSI108_IRQ_STRIDE,
  113. TSI108_IRQ_VECTOR_PRI,
  114. TSI108_VECPRI_VECTOR_MASK,
  115. TSI108_VECPRI_POLARITY_POSITIVE,
  116. TSI108_VECPRI_POLARITY_NEGATIVE,
  117. TSI108_VECPRI_SENSE_LEVEL,
  118. TSI108_VECPRI_SENSE_EDGE,
  119. TSI108_VECPRI_POLARITY_MASK,
  120. TSI108_VECPRI_SENSE_MASK,
  121. TSI108_IRQ_DESTINATION
  122. },
  123. };
  124. #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
  125. #else /* CONFIG_MPIC_WEIRD */
  126. #define MPIC_INFO(name) MPIC_##name
  127. #endif /* CONFIG_MPIC_WEIRD */
  128. /*
  129. * Register accessor functions
  130. */
  131. static inline u32 _mpic_read(enum mpic_reg_type type,
  132. struct mpic_reg_bank *rb,
  133. unsigned int reg)
  134. {
  135. switch(type) {
  136. #ifdef CONFIG_PPC_DCR
  137. case mpic_access_dcr:
  138. return dcr_read(rb->dhost, reg);
  139. #endif
  140. case mpic_access_mmio_be:
  141. return in_be32(rb->base + (reg >> 2));
  142. case mpic_access_mmio_le:
  143. default:
  144. return in_le32(rb->base + (reg >> 2));
  145. }
  146. }
  147. static inline void _mpic_write(enum mpic_reg_type type,
  148. struct mpic_reg_bank *rb,
  149. unsigned int reg, u32 value)
  150. {
  151. switch(type) {
  152. #ifdef CONFIG_PPC_DCR
  153. case mpic_access_dcr:
  154. return dcr_write(rb->dhost, reg, value);
  155. #endif
  156. case mpic_access_mmio_be:
  157. return out_be32(rb->base + (reg >> 2), value);
  158. case mpic_access_mmio_le:
  159. default:
  160. return out_le32(rb->base + (reg >> 2), value);
  161. }
  162. }
  163. static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
  164. {
  165. enum mpic_reg_type type = mpic->reg_type;
  166. unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
  167. (ipi * MPIC_INFO(GREG_IPI_STRIDE));
  168. if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
  169. type = mpic_access_mmio_be;
  170. return _mpic_read(type, &mpic->gregs, offset);
  171. }
  172. static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
  173. {
  174. unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
  175. (ipi * MPIC_INFO(GREG_IPI_STRIDE));
  176. _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
  177. }
  178. static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
  179. {
  180. unsigned int cpu = 0;
  181. if (mpic->flags & MPIC_PRIMARY)
  182. cpu = hard_smp_processor_id();
  183. return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
  184. }
  185. static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
  186. {
  187. unsigned int cpu = 0;
  188. if (mpic->flags & MPIC_PRIMARY)
  189. cpu = hard_smp_processor_id();
  190. _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
  191. }
  192. static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
  193. {
  194. unsigned int isu = src_no >> mpic->isu_shift;
  195. unsigned int idx = src_no & mpic->isu_mask;
  196. #ifdef CONFIG_MPIC_BROKEN_REGREAD
  197. if (reg == 0)
  198. return mpic->isu_reg0_shadow[idx];
  199. else
  200. #endif
  201. return _mpic_read(mpic->reg_type, &mpic->isus[isu],
  202. reg + (idx * MPIC_INFO(IRQ_STRIDE)));
  203. }
  204. static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
  205. unsigned int reg, u32 value)
  206. {
  207. unsigned int isu = src_no >> mpic->isu_shift;
  208. unsigned int idx = src_no & mpic->isu_mask;
  209. _mpic_write(mpic->reg_type, &mpic->isus[isu],
  210. reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
  211. #ifdef CONFIG_MPIC_BROKEN_REGREAD
  212. if (reg == 0)
  213. mpic->isu_reg0_shadow[idx] = value;
  214. #endif
  215. }
  216. #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
  217. #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
  218. #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
  219. #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
  220. #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
  221. #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
  222. #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
  223. #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
  224. /*
  225. * Low level utility functions
  226. */
  227. static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
  228. struct mpic_reg_bank *rb, unsigned int offset,
  229. unsigned int size)
  230. {
  231. rb->base = ioremap(phys_addr + offset, size);
  232. BUG_ON(rb->base == NULL);
  233. }
  234. #ifdef CONFIG_PPC_DCR
  235. static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
  236. unsigned int offset, unsigned int size)
  237. {
  238. const u32 *dbasep;
  239. dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
  240. rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
  241. BUG_ON(!DCR_MAP_OK(rb->dhost));
  242. }
  243. static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
  244. struct mpic_reg_bank *rb, unsigned int offset,
  245. unsigned int size)
  246. {
  247. if (mpic->flags & MPIC_USES_DCR)
  248. _mpic_map_dcr(mpic, rb, offset, size);
  249. else
  250. _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
  251. }
  252. #else /* CONFIG_PPC_DCR */
  253. #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
  254. #endif /* !CONFIG_PPC_DCR */
  255. /* Check if we have one of those nice broken MPICs with a flipped endian on
  256. * reads from IPI registers
  257. */
  258. static void __init mpic_test_broken_ipi(struct mpic *mpic)
  259. {
  260. u32 r;
  261. mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
  262. r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
  263. if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
  264. printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
  265. mpic->flags |= MPIC_BROKEN_IPI;
  266. }
  267. }
  268. #ifdef CONFIG_MPIC_U3_HT_IRQS
  269. /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
  270. * to force the edge setting on the MPIC and do the ack workaround.
  271. */
  272. static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
  273. {
  274. if (source >= 128 || !mpic->fixups)
  275. return 0;
  276. return mpic->fixups[source].base != NULL;
  277. }
  278. static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
  279. {
  280. struct mpic_irq_fixup *fixup = &mpic->fixups[source];
  281. if (fixup->applebase) {
  282. unsigned int soff = (fixup->index >> 3) & ~3;
  283. unsigned int mask = 1U << (fixup->index & 0x1f);
  284. writel(mask, fixup->applebase + soff);
  285. } else {
  286. spin_lock(&mpic->fixup_lock);
  287. writeb(0x11 + 2 * fixup->index, fixup->base + 2);
  288. writel(fixup->data, fixup->base + 4);
  289. spin_unlock(&mpic->fixup_lock);
  290. }
  291. }
  292. static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
  293. unsigned int irqflags)
  294. {
  295. struct mpic_irq_fixup *fixup = &mpic->fixups[source];
  296. unsigned long flags;
  297. u32 tmp;
  298. if (fixup->base == NULL)
  299. return;
  300. DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
  301. source, irqflags, fixup->index);
  302. spin_lock_irqsave(&mpic->fixup_lock, flags);
  303. /* Enable and configure */
  304. writeb(0x10 + 2 * fixup->index, fixup->base + 2);
  305. tmp = readl(fixup->base + 4);
  306. tmp &= ~(0x23U);
  307. if (irqflags & IRQ_LEVEL)
  308. tmp |= 0x22;
  309. writel(tmp, fixup->base + 4);
  310. spin_unlock_irqrestore(&mpic->fixup_lock, flags);
  311. #ifdef CONFIG_PM
  312. /* use the lowest bit inverted to the actual HW,
  313. * set if this fixup was enabled, clear otherwise */
  314. mpic->save_data[source].fixup_data = tmp | 1;
  315. #endif
  316. }
  317. static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
  318. unsigned int irqflags)
  319. {
  320. struct mpic_irq_fixup *fixup = &mpic->fixups[source];
  321. unsigned long flags;
  322. u32 tmp;
  323. if (fixup->base == NULL)
  324. return;
  325. DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
  326. /* Disable */
  327. spin_lock_irqsave(&mpic->fixup_lock, flags);
  328. writeb(0x10 + 2 * fixup->index, fixup->base + 2);
  329. tmp = readl(fixup->base + 4);
  330. tmp |= 1;
  331. writel(tmp, fixup->base + 4);
  332. spin_unlock_irqrestore(&mpic->fixup_lock, flags);
  333. #ifdef CONFIG_PM
  334. /* use the lowest bit inverted to the actual HW,
  335. * set if this fixup was enabled, clear otherwise */
  336. mpic->save_data[source].fixup_data = tmp & ~1;
  337. #endif
  338. }
  339. #ifdef CONFIG_PCI_MSI
  340. static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
  341. unsigned int devfn)
  342. {
  343. u8 __iomem *base;
  344. u8 pos, flags;
  345. u64 addr = 0;
  346. for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
  347. pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
  348. u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
  349. if (id == PCI_CAP_ID_HT) {
  350. id = readb(devbase + pos + 3);
  351. if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
  352. break;
  353. }
  354. }
  355. if (pos == 0)
  356. return;
  357. base = devbase + pos;
  358. flags = readb(base + HT_MSI_FLAGS);
  359. if (!(flags & HT_MSI_FLAGS_FIXED)) {
  360. addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
  361. addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
  362. }
  363. printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
  364. PCI_SLOT(devfn), PCI_FUNC(devfn),
  365. flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
  366. if (!(flags & HT_MSI_FLAGS_ENABLE))
  367. writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
  368. }
  369. #else
  370. static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
  371. unsigned int devfn)
  372. {
  373. return;
  374. }
  375. #endif
  376. static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
  377. unsigned int devfn, u32 vdid)
  378. {
  379. int i, irq, n;
  380. u8 __iomem *base;
  381. u32 tmp;
  382. u8 pos;
  383. for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
  384. pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
  385. u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
  386. if (id == PCI_CAP_ID_HT) {
  387. id = readb(devbase + pos + 3);
  388. if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
  389. break;
  390. }
  391. }
  392. if (pos == 0)
  393. return;
  394. base = devbase + pos;
  395. writeb(0x01, base + 2);
  396. n = (readl(base + 4) >> 16) & 0xff;
  397. printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
  398. " has %d irqs\n",
  399. devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
  400. for (i = 0; i <= n; i++) {
  401. writeb(0x10 + 2 * i, base + 2);
  402. tmp = readl(base + 4);
  403. irq = (tmp >> 16) & 0xff;
  404. DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
  405. /* mask it , will be unmasked later */
  406. tmp |= 0x1;
  407. writel(tmp, base + 4);
  408. mpic->fixups[irq].index = i;
  409. mpic->fixups[irq].base = base;
  410. /* Apple HT PIC has a non-standard way of doing EOIs */
  411. if ((vdid & 0xffff) == 0x106b)
  412. mpic->fixups[irq].applebase = devbase + 0x60;
  413. else
  414. mpic->fixups[irq].applebase = NULL;
  415. writeb(0x11 + 2 * i, base + 2);
  416. mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
  417. }
  418. }
  419. static void __init mpic_scan_ht_pics(struct mpic *mpic)
  420. {
  421. unsigned int devfn;
  422. u8 __iomem *cfgspace;
  423. printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
  424. /* Allocate fixups array */
  425. mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
  426. BUG_ON(mpic->fixups == NULL);
  427. memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
  428. /* Init spinlock */
  429. spin_lock_init(&mpic->fixup_lock);
  430. /* Map U3 config space. We assume all IO-APICs are on the primary bus
  431. * so we only need to map 64kB.
  432. */
  433. cfgspace = ioremap(0xf2000000, 0x10000);
  434. BUG_ON(cfgspace == NULL);
  435. /* Now we scan all slots. We do a very quick scan, we read the header
  436. * type, vendor ID and device ID only, that's plenty enough
  437. */
  438. for (devfn = 0; devfn < 0x100; devfn++) {
  439. u8 __iomem *devbase = cfgspace + (devfn << 8);
  440. u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
  441. u32 l = readl(devbase + PCI_VENDOR_ID);
  442. u16 s;
  443. DBG("devfn %x, l: %x\n", devfn, l);
  444. /* If no device, skip */
  445. if (l == 0xffffffff || l == 0x00000000 ||
  446. l == 0x0000ffff || l == 0xffff0000)
  447. goto next;
  448. /* Check if is supports capability lists */
  449. s = readw(devbase + PCI_STATUS);
  450. if (!(s & PCI_STATUS_CAP_LIST))
  451. goto next;
  452. mpic_scan_ht_pic(mpic, devbase, devfn, l);
  453. mpic_scan_ht_msi(mpic, devbase, devfn);
  454. next:
  455. /* next device, if function 0 */
  456. if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
  457. devfn += 7;
  458. }
  459. }
  460. #else /* CONFIG_MPIC_U3_HT_IRQS */
  461. static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
  462. {
  463. return 0;
  464. }
  465. static void __init mpic_scan_ht_pics(struct mpic *mpic)
  466. {
  467. }
  468. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  469. #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
  470. /* Find an mpic associated with a given linux interrupt */
  471. static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
  472. {
  473. unsigned int src = mpic_irq_to_hw(irq);
  474. struct mpic *mpic;
  475. if (irq < NUM_ISA_INTERRUPTS)
  476. return NULL;
  477. mpic = irq_desc[irq].chip_data;
  478. if (is_ipi)
  479. *is_ipi = (src >= mpic->ipi_vecs[0] &&
  480. src <= mpic->ipi_vecs[3]);
  481. return mpic;
  482. }
  483. /* Convert a cpu mask from logical to physical cpu numbers. */
  484. static inline u32 mpic_physmask(u32 cpumask)
  485. {
  486. int i;
  487. u32 mask = 0;
  488. for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
  489. mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
  490. return mask;
  491. }
  492. #ifdef CONFIG_SMP
  493. /* Get the mpic structure from the IPI number */
  494. static inline struct mpic * mpic_from_ipi(unsigned int ipi)
  495. {
  496. return irq_desc[ipi].chip_data;
  497. }
  498. #endif
  499. /* Get the mpic structure from the irq number */
  500. static inline struct mpic * mpic_from_irq(unsigned int irq)
  501. {
  502. return irq_desc[irq].chip_data;
  503. }
  504. /* Send an EOI */
  505. static inline void mpic_eoi(struct mpic *mpic)
  506. {
  507. mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
  508. (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
  509. }
  510. #ifdef CONFIG_SMP
  511. static irqreturn_t mpic_ipi_action(int irq, void *data)
  512. {
  513. long ipi = (long)data;
  514. smp_message_recv(ipi);
  515. return IRQ_HANDLED;
  516. }
  517. #endif /* CONFIG_SMP */
  518. /*
  519. * Linux descriptor level callbacks
  520. */
  521. void mpic_unmask_irq(unsigned int irq)
  522. {
  523. unsigned int loops = 100000;
  524. struct mpic *mpic = mpic_from_irq(irq);
  525. unsigned int src = mpic_irq_to_hw(irq);
  526. DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
  527. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
  528. mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
  529. ~MPIC_VECPRI_MASK);
  530. /* make sure mask gets to controller before we return to user */
  531. do {
  532. if (!loops--) {
  533. printk(KERN_ERR "mpic_enable_irq timeout\n");
  534. break;
  535. }
  536. } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
  537. }
  538. void mpic_mask_irq(unsigned int irq)
  539. {
  540. unsigned int loops = 100000;
  541. struct mpic *mpic = mpic_from_irq(irq);
  542. unsigned int src = mpic_irq_to_hw(irq);
  543. DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
  544. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
  545. mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
  546. MPIC_VECPRI_MASK);
  547. /* make sure mask gets to controller before we return to user */
  548. do {
  549. if (!loops--) {
  550. printk(KERN_ERR "mpic_enable_irq timeout\n");
  551. break;
  552. }
  553. } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
  554. }
  555. void mpic_end_irq(unsigned int irq)
  556. {
  557. struct mpic *mpic = mpic_from_irq(irq);
  558. #ifdef DEBUG_IRQ
  559. DBG("%s: end_irq: %d\n", mpic->name, irq);
  560. #endif
  561. /* We always EOI on end_irq() even for edge interrupts since that
  562. * should only lower the priority, the MPIC should have properly
  563. * latched another edge interrupt coming in anyway
  564. */
  565. mpic_eoi(mpic);
  566. }
  567. #ifdef CONFIG_MPIC_U3_HT_IRQS
  568. static void mpic_unmask_ht_irq(unsigned int irq)
  569. {
  570. struct mpic *mpic = mpic_from_irq(irq);
  571. unsigned int src = mpic_irq_to_hw(irq);
  572. mpic_unmask_irq(irq);
  573. if (irq_desc[irq].status & IRQ_LEVEL)
  574. mpic_ht_end_irq(mpic, src);
  575. }
  576. static unsigned int mpic_startup_ht_irq(unsigned int irq)
  577. {
  578. struct mpic *mpic = mpic_from_irq(irq);
  579. unsigned int src = mpic_irq_to_hw(irq);
  580. mpic_unmask_irq(irq);
  581. mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
  582. return 0;
  583. }
  584. static void mpic_shutdown_ht_irq(unsigned int irq)
  585. {
  586. struct mpic *mpic = mpic_from_irq(irq);
  587. unsigned int src = mpic_irq_to_hw(irq);
  588. mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
  589. mpic_mask_irq(irq);
  590. }
  591. static void mpic_end_ht_irq(unsigned int irq)
  592. {
  593. struct mpic *mpic = mpic_from_irq(irq);
  594. unsigned int src = mpic_irq_to_hw(irq);
  595. #ifdef DEBUG_IRQ
  596. DBG("%s: end_irq: %d\n", mpic->name, irq);
  597. #endif
  598. /* We always EOI on end_irq() even for edge interrupts since that
  599. * should only lower the priority, the MPIC should have properly
  600. * latched another edge interrupt coming in anyway
  601. */
  602. if (irq_desc[irq].status & IRQ_LEVEL)
  603. mpic_ht_end_irq(mpic, src);
  604. mpic_eoi(mpic);
  605. }
  606. #endif /* !CONFIG_MPIC_U3_HT_IRQS */
  607. #ifdef CONFIG_SMP
  608. static void mpic_unmask_ipi(unsigned int irq)
  609. {
  610. struct mpic *mpic = mpic_from_ipi(irq);
  611. unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
  612. DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
  613. mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
  614. }
  615. static void mpic_mask_ipi(unsigned int irq)
  616. {
  617. /* NEVER disable an IPI... that's just plain wrong! */
  618. }
  619. static void mpic_end_ipi(unsigned int irq)
  620. {
  621. struct mpic *mpic = mpic_from_ipi(irq);
  622. /*
  623. * IPIs are marked IRQ_PER_CPU. This has the side effect of
  624. * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
  625. * applying to them. We EOI them late to avoid re-entering.
  626. * We mark IPI's with IRQF_DISABLED as they must run with
  627. * irqs disabled.
  628. */
  629. mpic_eoi(mpic);
  630. }
  631. #endif /* CONFIG_SMP */
  632. void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
  633. {
  634. struct mpic *mpic = mpic_from_irq(irq);
  635. unsigned int src = mpic_irq_to_hw(irq);
  636. cpumask_t tmp;
  637. cpus_and(tmp, cpumask, cpu_online_map);
  638. mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
  639. mpic_physmask(cpus_addr(tmp)[0]));
  640. }
  641. static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
  642. {
  643. /* Now convert sense value */
  644. switch(type & IRQ_TYPE_SENSE_MASK) {
  645. case IRQ_TYPE_EDGE_RISING:
  646. return MPIC_INFO(VECPRI_SENSE_EDGE) |
  647. MPIC_INFO(VECPRI_POLARITY_POSITIVE);
  648. case IRQ_TYPE_EDGE_FALLING:
  649. case IRQ_TYPE_EDGE_BOTH:
  650. return MPIC_INFO(VECPRI_SENSE_EDGE) |
  651. MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
  652. case IRQ_TYPE_LEVEL_HIGH:
  653. return MPIC_INFO(VECPRI_SENSE_LEVEL) |
  654. MPIC_INFO(VECPRI_POLARITY_POSITIVE);
  655. case IRQ_TYPE_LEVEL_LOW:
  656. default:
  657. return MPIC_INFO(VECPRI_SENSE_LEVEL) |
  658. MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
  659. }
  660. }
  661. int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
  662. {
  663. struct mpic *mpic = mpic_from_irq(virq);
  664. unsigned int src = mpic_irq_to_hw(virq);
  665. struct irq_desc *desc = get_irq_desc(virq);
  666. unsigned int vecpri, vold, vnew;
  667. DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
  668. mpic, virq, src, flow_type);
  669. if (src >= mpic->irq_count)
  670. return -EINVAL;
  671. if (flow_type == IRQ_TYPE_NONE)
  672. if (mpic->senses && src < mpic->senses_count)
  673. flow_type = mpic->senses[src];
  674. if (flow_type == IRQ_TYPE_NONE)
  675. flow_type = IRQ_TYPE_LEVEL_LOW;
  676. desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
  677. desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
  678. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  679. desc->status |= IRQ_LEVEL;
  680. if (mpic_is_ht_interrupt(mpic, src))
  681. vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
  682. MPIC_VECPRI_SENSE_EDGE;
  683. else
  684. vecpri = mpic_type_to_vecpri(mpic, flow_type);
  685. vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
  686. vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
  687. MPIC_INFO(VECPRI_SENSE_MASK));
  688. vnew |= vecpri;
  689. if (vold != vnew)
  690. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
  691. return 0;
  692. }
  693. void mpic_set_vector(unsigned int virq, unsigned int vector)
  694. {
  695. struct mpic *mpic = mpic_from_irq(virq);
  696. unsigned int src = mpic_irq_to_hw(virq);
  697. unsigned int vecpri;
  698. DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
  699. mpic, virq, src, vector);
  700. if (src >= mpic->irq_count)
  701. return;
  702. vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
  703. vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
  704. vecpri |= vector;
  705. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
  706. }
  707. static struct irq_chip mpic_irq_chip = {
  708. .mask = mpic_mask_irq,
  709. .unmask = mpic_unmask_irq,
  710. .eoi = mpic_end_irq,
  711. .set_type = mpic_set_irq_type,
  712. };
  713. #ifdef CONFIG_SMP
  714. static struct irq_chip mpic_ipi_chip = {
  715. .mask = mpic_mask_ipi,
  716. .unmask = mpic_unmask_ipi,
  717. .eoi = mpic_end_ipi,
  718. };
  719. #endif /* CONFIG_SMP */
  720. #ifdef CONFIG_MPIC_U3_HT_IRQS
  721. static struct irq_chip mpic_irq_ht_chip = {
  722. .startup = mpic_startup_ht_irq,
  723. .shutdown = mpic_shutdown_ht_irq,
  724. .mask = mpic_mask_irq,
  725. .unmask = mpic_unmask_ht_irq,
  726. .eoi = mpic_end_ht_irq,
  727. .set_type = mpic_set_irq_type,
  728. };
  729. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  730. static int mpic_host_match(struct irq_host *h, struct device_node *node)
  731. {
  732. /* Exact match, unless mpic node is NULL */
  733. return h->of_node == NULL || h->of_node == node;
  734. }
  735. static int mpic_host_map(struct irq_host *h, unsigned int virq,
  736. irq_hw_number_t hw)
  737. {
  738. struct mpic *mpic = h->host_data;
  739. struct irq_chip *chip;
  740. DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
  741. if (hw == mpic->spurious_vec)
  742. return -EINVAL;
  743. if (mpic->protected && test_bit(hw, mpic->protected))
  744. return -EINVAL;
  745. #ifdef CONFIG_SMP
  746. else if (hw >= mpic->ipi_vecs[0]) {
  747. WARN_ON(!(mpic->flags & MPIC_PRIMARY));
  748. DBG("mpic: mapping as IPI\n");
  749. set_irq_chip_data(virq, mpic);
  750. set_irq_chip_and_handler(virq, &mpic->hc_ipi,
  751. handle_percpu_irq);
  752. return 0;
  753. }
  754. #endif /* CONFIG_SMP */
  755. if (hw >= mpic->irq_count)
  756. return -EINVAL;
  757. mpic_msi_reserve_hwirq(mpic, hw);
  758. /* Default chip */
  759. chip = &mpic->hc_irq;
  760. #ifdef CONFIG_MPIC_U3_HT_IRQS
  761. /* Check for HT interrupts, override vecpri */
  762. if (mpic_is_ht_interrupt(mpic, hw))
  763. chip = &mpic->hc_ht_irq;
  764. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  765. DBG("mpic: mapping to irq chip @%p\n", chip);
  766. set_irq_chip_data(virq, mpic);
  767. set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
  768. /* Set default irq type */
  769. set_irq_type(virq, IRQ_TYPE_NONE);
  770. return 0;
  771. }
  772. static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
  773. u32 *intspec, unsigned int intsize,
  774. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  775. {
  776. static unsigned char map_mpic_senses[4] = {
  777. IRQ_TYPE_EDGE_RISING,
  778. IRQ_TYPE_LEVEL_LOW,
  779. IRQ_TYPE_LEVEL_HIGH,
  780. IRQ_TYPE_EDGE_FALLING,
  781. };
  782. *out_hwirq = intspec[0];
  783. if (intsize > 1) {
  784. u32 mask = 0x3;
  785. /* Apple invented a new race of encoding on machines with
  786. * an HT APIC. They encode, among others, the index within
  787. * the HT APIC. We don't care about it here since thankfully,
  788. * it appears that they have the APIC already properly
  789. * configured, and thus our current fixup code that reads the
  790. * APIC config works fine. However, we still need to mask out
  791. * bits in the specifier to make sure we only get bit 0 which
  792. * is the level/edge bit (the only sense bit exposed by Apple),
  793. * as their bit 1 means something else.
  794. */
  795. if (machine_is(powermac))
  796. mask = 0x1;
  797. *out_flags = map_mpic_senses[intspec[1] & mask];
  798. } else
  799. *out_flags = IRQ_TYPE_NONE;
  800. DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
  801. intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
  802. return 0;
  803. }
  804. static struct irq_host_ops mpic_host_ops = {
  805. .match = mpic_host_match,
  806. .map = mpic_host_map,
  807. .xlate = mpic_host_xlate,
  808. };
  809. /*
  810. * Exported functions
  811. */
  812. struct mpic * __init mpic_alloc(struct device_node *node,
  813. phys_addr_t phys_addr,
  814. unsigned int flags,
  815. unsigned int isu_size,
  816. unsigned int irq_count,
  817. const char *name)
  818. {
  819. struct mpic *mpic;
  820. u32 reg;
  821. const char *vers;
  822. int i;
  823. int intvec_top;
  824. u64 paddr = phys_addr;
  825. mpic = alloc_bootmem(sizeof(struct mpic));
  826. if (mpic == NULL)
  827. return NULL;
  828. memset(mpic, 0, sizeof(struct mpic));
  829. mpic->name = name;
  830. mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
  831. isu_size, &mpic_host_ops,
  832. flags & MPIC_LARGE_VECTORS ? 2048 : 256);
  833. if (mpic->irqhost == NULL) {
  834. of_node_put(node);
  835. return NULL;
  836. }
  837. mpic->irqhost->host_data = mpic;
  838. mpic->hc_irq = mpic_irq_chip;
  839. mpic->hc_irq.typename = name;
  840. if (flags & MPIC_PRIMARY)
  841. mpic->hc_irq.set_affinity = mpic_set_affinity;
  842. #ifdef CONFIG_MPIC_U3_HT_IRQS
  843. mpic->hc_ht_irq = mpic_irq_ht_chip;
  844. mpic->hc_ht_irq.typename = name;
  845. if (flags & MPIC_PRIMARY)
  846. mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
  847. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  848. #ifdef CONFIG_SMP
  849. mpic->hc_ipi = mpic_ipi_chip;
  850. mpic->hc_ipi.typename = name;
  851. #endif /* CONFIG_SMP */
  852. mpic->flags = flags;
  853. mpic->isu_size = isu_size;
  854. mpic->irq_count = irq_count;
  855. mpic->num_sources = 0; /* so far */
  856. if (flags & MPIC_LARGE_VECTORS)
  857. intvec_top = 2047;
  858. else
  859. intvec_top = 255;
  860. mpic->timer_vecs[0] = intvec_top - 8;
  861. mpic->timer_vecs[1] = intvec_top - 7;
  862. mpic->timer_vecs[2] = intvec_top - 6;
  863. mpic->timer_vecs[3] = intvec_top - 5;
  864. mpic->ipi_vecs[0] = intvec_top - 4;
  865. mpic->ipi_vecs[1] = intvec_top - 3;
  866. mpic->ipi_vecs[2] = intvec_top - 2;
  867. mpic->ipi_vecs[3] = intvec_top - 1;
  868. mpic->spurious_vec = intvec_top;
  869. /* Check for "big-endian" in device-tree */
  870. if (node && of_get_property(node, "big-endian", NULL) != NULL)
  871. mpic->flags |= MPIC_BIG_ENDIAN;
  872. /* Look for protected sources */
  873. if (node) {
  874. unsigned int psize, bits, mapsize;
  875. const u32 *psrc =
  876. of_get_property(node, "protected-sources", &psize);
  877. if (psrc) {
  878. psize /= 4;
  879. bits = intvec_top + 1;
  880. mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
  881. mpic->protected = alloc_bootmem(mapsize);
  882. BUG_ON(mpic->protected == NULL);
  883. memset(mpic->protected, 0, mapsize);
  884. for (i = 0; i < psize; i++) {
  885. if (psrc[i] > intvec_top)
  886. continue;
  887. __set_bit(psrc[i], mpic->protected);
  888. }
  889. }
  890. }
  891. #ifdef CONFIG_MPIC_WEIRD
  892. mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
  893. #endif
  894. /* default register type */
  895. mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
  896. mpic_access_mmio_be : mpic_access_mmio_le;
  897. /* If no physical address is passed in, a device-node is mandatory */
  898. BUG_ON(paddr == 0 && node == NULL);
  899. /* If no physical address passed in, check if it's dcr based */
  900. if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
  901. #ifdef CONFIG_PPC_DCR
  902. mpic->flags |= MPIC_USES_DCR;
  903. mpic->reg_type = mpic_access_dcr;
  904. #else
  905. BUG();
  906. #endif /* CONFIG_PPC_DCR */
  907. }
  908. /* If the MPIC is not DCR based, and no physical address was passed
  909. * in, try to obtain one
  910. */
  911. if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
  912. const u32 *reg;
  913. reg = of_get_property(node, "reg", NULL);
  914. BUG_ON(reg == NULL);
  915. paddr = of_translate_address(node, reg);
  916. BUG_ON(paddr == OF_BAD_ADDR);
  917. }
  918. /* Map the global registers */
  919. mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
  920. mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
  921. /* Reset */
  922. if (flags & MPIC_WANTS_RESET) {
  923. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  924. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  925. | MPIC_GREG_GCONF_RESET);
  926. while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  927. & MPIC_GREG_GCONF_RESET)
  928. mb();
  929. }
  930. /* Read feature register, calculate num CPUs and, for non-ISU
  931. * MPICs, num sources as well. On ISU MPICs, sources are counted
  932. * as ISUs are added
  933. */
  934. reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
  935. mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
  936. >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
  937. if (isu_size == 0)
  938. mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
  939. >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
  940. /* Map the per-CPU registers */
  941. for (i = 0; i < mpic->num_cpus; i++) {
  942. mpic_map(mpic, paddr, &mpic->cpuregs[i],
  943. MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
  944. 0x1000);
  945. }
  946. /* Initialize main ISU if none provided */
  947. if (mpic->isu_size == 0) {
  948. mpic->isu_size = mpic->num_sources;
  949. mpic_map(mpic, paddr, &mpic->isus[0],
  950. MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
  951. }
  952. mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
  953. mpic->isu_mask = (1 << mpic->isu_shift) - 1;
  954. /* Display version */
  955. switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
  956. case 1:
  957. vers = "1.0";
  958. break;
  959. case 2:
  960. vers = "1.2";
  961. break;
  962. case 3:
  963. vers = "1.3";
  964. break;
  965. default:
  966. vers = "<unknown>";
  967. break;
  968. }
  969. printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
  970. " max %d CPUs\n",
  971. name, vers, (unsigned long long)paddr, mpic->num_cpus);
  972. printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
  973. mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
  974. mpic->next = mpics;
  975. mpics = mpic;
  976. if (flags & MPIC_PRIMARY) {
  977. mpic_primary = mpic;
  978. irq_set_default_host(mpic->irqhost);
  979. }
  980. return mpic;
  981. }
  982. void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
  983. phys_addr_t paddr)
  984. {
  985. unsigned int isu_first = isu_num * mpic->isu_size;
  986. BUG_ON(isu_num >= MPIC_MAX_ISU);
  987. mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
  988. MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
  989. if ((isu_first + mpic->isu_size) > mpic->num_sources)
  990. mpic->num_sources = isu_first + mpic->isu_size;
  991. }
  992. void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
  993. {
  994. mpic->senses = senses;
  995. mpic->senses_count = count;
  996. }
  997. void __init mpic_init(struct mpic *mpic)
  998. {
  999. int i;
  1000. BUG_ON(mpic->num_sources == 0);
  1001. printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
  1002. /* Set current processor priority to max */
  1003. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
  1004. /* Initialize timers: just disable them all */
  1005. for (i = 0; i < 4; i++) {
  1006. mpic_write(mpic->tmregs,
  1007. i * MPIC_INFO(TIMER_STRIDE) +
  1008. MPIC_INFO(TIMER_DESTINATION), 0);
  1009. mpic_write(mpic->tmregs,
  1010. i * MPIC_INFO(TIMER_STRIDE) +
  1011. MPIC_INFO(TIMER_VECTOR_PRI),
  1012. MPIC_VECPRI_MASK |
  1013. (mpic->timer_vecs[0] + i));
  1014. }
  1015. /* Initialize IPIs to our reserved vectors and mark them disabled for now */
  1016. mpic_test_broken_ipi(mpic);
  1017. for (i = 0; i < 4; i++) {
  1018. mpic_ipi_write(i,
  1019. MPIC_VECPRI_MASK |
  1020. (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
  1021. (mpic->ipi_vecs[0] + i));
  1022. }
  1023. /* Initialize interrupt sources */
  1024. if (mpic->irq_count == 0)
  1025. mpic->irq_count = mpic->num_sources;
  1026. /* Do the HT PIC fixups on U3 broken mpic */
  1027. DBG("MPIC flags: %x\n", mpic->flags);
  1028. if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
  1029. mpic_scan_ht_pics(mpic);
  1030. mpic_u3msi_init(mpic);
  1031. }
  1032. mpic_pasemi_msi_init(mpic);
  1033. for (i = 0; i < mpic->num_sources; i++) {
  1034. /* start with vector = source number, and masked */
  1035. u32 vecpri = MPIC_VECPRI_MASK | i |
  1036. (8 << MPIC_VECPRI_PRIORITY_SHIFT);
  1037. /* check if protected */
  1038. if (mpic->protected && test_bit(i, mpic->protected))
  1039. continue;
  1040. /* init hw */
  1041. mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
  1042. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1043. 1 << hard_smp_processor_id());
  1044. }
  1045. /* Init spurious vector */
  1046. mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
  1047. /* Disable 8259 passthrough, if supported */
  1048. if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
  1049. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  1050. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1051. | MPIC_GREG_GCONF_8259_PTHROU_DIS);
  1052. /* Set current processor priority to 0 */
  1053. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
  1054. #ifdef CONFIG_PM
  1055. /* allocate memory to save mpic state */
  1056. mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
  1057. BUG_ON(mpic->save_data == NULL);
  1058. #endif
  1059. }
  1060. void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
  1061. {
  1062. u32 v;
  1063. v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
  1064. v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
  1065. v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
  1066. mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
  1067. }
  1068. void __init mpic_set_serial_int(struct mpic *mpic, int enable)
  1069. {
  1070. unsigned long flags;
  1071. u32 v;
  1072. spin_lock_irqsave(&mpic_lock, flags);
  1073. v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
  1074. if (enable)
  1075. v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
  1076. else
  1077. v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
  1078. mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
  1079. spin_unlock_irqrestore(&mpic_lock, flags);
  1080. }
  1081. void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
  1082. {
  1083. int is_ipi;
  1084. struct mpic *mpic = mpic_find(irq, &is_ipi);
  1085. unsigned int src = mpic_irq_to_hw(irq);
  1086. unsigned long flags;
  1087. u32 reg;
  1088. spin_lock_irqsave(&mpic_lock, flags);
  1089. if (is_ipi) {
  1090. reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
  1091. ~MPIC_VECPRI_PRIORITY_MASK;
  1092. mpic_ipi_write(src - mpic->ipi_vecs[0],
  1093. reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
  1094. } else {
  1095. reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
  1096. & ~MPIC_VECPRI_PRIORITY_MASK;
  1097. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
  1098. reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
  1099. }
  1100. spin_unlock_irqrestore(&mpic_lock, flags);
  1101. }
  1102. unsigned int mpic_irq_get_priority(unsigned int irq)
  1103. {
  1104. int is_ipi;
  1105. struct mpic *mpic = mpic_find(irq, &is_ipi);
  1106. unsigned int src = mpic_irq_to_hw(irq);
  1107. unsigned long flags;
  1108. u32 reg;
  1109. spin_lock_irqsave(&mpic_lock, flags);
  1110. if (is_ipi)
  1111. reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
  1112. else
  1113. reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
  1114. spin_unlock_irqrestore(&mpic_lock, flags);
  1115. return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
  1116. }
  1117. void mpic_setup_this_cpu(void)
  1118. {
  1119. #ifdef CONFIG_SMP
  1120. struct mpic *mpic = mpic_primary;
  1121. unsigned long flags;
  1122. u32 msk = 1 << hard_smp_processor_id();
  1123. unsigned int i;
  1124. BUG_ON(mpic == NULL);
  1125. DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
  1126. spin_lock_irqsave(&mpic_lock, flags);
  1127. /* let the mpic know we want intrs. default affinity is 0xffffffff
  1128. * until changed via /proc. That's how it's done on x86. If we want
  1129. * it differently, then we should make sure we also change the default
  1130. * values of irq_desc[].affinity in irq.c.
  1131. */
  1132. if (distribute_irqs) {
  1133. for (i = 0; i < mpic->num_sources ; i++)
  1134. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1135. mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
  1136. }
  1137. /* Set current processor priority to 0 */
  1138. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
  1139. spin_unlock_irqrestore(&mpic_lock, flags);
  1140. #endif /* CONFIG_SMP */
  1141. }
  1142. int mpic_cpu_get_priority(void)
  1143. {
  1144. struct mpic *mpic = mpic_primary;
  1145. return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
  1146. }
  1147. void mpic_cpu_set_priority(int prio)
  1148. {
  1149. struct mpic *mpic = mpic_primary;
  1150. prio &= MPIC_CPU_TASKPRI_MASK;
  1151. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
  1152. }
  1153. /*
  1154. * XXX: someone who knows mpic should check this.
  1155. * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
  1156. * or can we reset the mpic in the new kernel?
  1157. */
  1158. void mpic_teardown_this_cpu(int secondary)
  1159. {
  1160. struct mpic *mpic = mpic_primary;
  1161. unsigned long flags;
  1162. u32 msk = 1 << hard_smp_processor_id();
  1163. unsigned int i;
  1164. BUG_ON(mpic == NULL);
  1165. DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
  1166. spin_lock_irqsave(&mpic_lock, flags);
  1167. /* let the mpic know we don't want intrs. */
  1168. for (i = 0; i < mpic->num_sources ; i++)
  1169. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1170. mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
  1171. /* Set current processor priority to max */
  1172. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
  1173. spin_unlock_irqrestore(&mpic_lock, flags);
  1174. }
  1175. void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
  1176. {
  1177. struct mpic *mpic = mpic_primary;
  1178. BUG_ON(mpic == NULL);
  1179. #ifdef DEBUG_IPI
  1180. DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
  1181. #endif
  1182. mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
  1183. ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
  1184. mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
  1185. }
  1186. unsigned int mpic_get_one_irq(struct mpic *mpic)
  1187. {
  1188. u32 src;
  1189. src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
  1190. #ifdef DEBUG_LOW
  1191. DBG("%s: get_one_irq(): %d\n", mpic->name, src);
  1192. #endif
  1193. if (unlikely(src == mpic->spurious_vec)) {
  1194. if (mpic->flags & MPIC_SPV_EOI)
  1195. mpic_eoi(mpic);
  1196. return NO_IRQ;
  1197. }
  1198. if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
  1199. if (printk_ratelimit())
  1200. printk(KERN_WARNING "%s: Got protected source %d !\n",
  1201. mpic->name, (int)src);
  1202. mpic_eoi(mpic);
  1203. return NO_IRQ;
  1204. }
  1205. return irq_linear_revmap(mpic->irqhost, src);
  1206. }
  1207. unsigned int mpic_get_irq(void)
  1208. {
  1209. struct mpic *mpic = mpic_primary;
  1210. BUG_ON(mpic == NULL);
  1211. return mpic_get_one_irq(mpic);
  1212. }
  1213. #ifdef CONFIG_SMP
  1214. void mpic_request_ipis(void)
  1215. {
  1216. struct mpic *mpic = mpic_primary;
  1217. long i, err;
  1218. static char *ipi_names[] = {
  1219. "IPI0 (call function)",
  1220. "IPI1 (reschedule)",
  1221. "IPI2 (unused)",
  1222. "IPI3 (debugger break)",
  1223. };
  1224. BUG_ON(mpic == NULL);
  1225. printk(KERN_INFO "mpic: requesting IPIs ... \n");
  1226. for (i = 0; i < 4; i++) {
  1227. unsigned int vipi = irq_create_mapping(mpic->irqhost,
  1228. mpic->ipi_vecs[0] + i);
  1229. if (vipi == NO_IRQ) {
  1230. printk(KERN_ERR "Failed to map IPI %ld\n", i);
  1231. break;
  1232. }
  1233. err = request_irq(vipi, mpic_ipi_action,
  1234. IRQF_DISABLED|IRQF_PERCPU,
  1235. ipi_names[i], (void *)i);
  1236. if (err) {
  1237. printk(KERN_ERR "Request of irq %d for IPI %ld failed\n",
  1238. vipi, i);
  1239. break;
  1240. }
  1241. }
  1242. }
  1243. void smp_mpic_message_pass(int target, int msg)
  1244. {
  1245. /* make sure we're sending something that translates to an IPI */
  1246. if ((unsigned int)msg > 3) {
  1247. printk("SMP %d: smp_message_pass: unknown msg %d\n",
  1248. smp_processor_id(), msg);
  1249. return;
  1250. }
  1251. switch (target) {
  1252. case MSG_ALL:
  1253. mpic_send_ipi(msg, 0xffffffff);
  1254. break;
  1255. case MSG_ALL_BUT_SELF:
  1256. mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
  1257. break;
  1258. default:
  1259. mpic_send_ipi(msg, 1 << target);
  1260. break;
  1261. }
  1262. }
  1263. int __init smp_mpic_probe(void)
  1264. {
  1265. int nr_cpus;
  1266. DBG("smp_mpic_probe()...\n");
  1267. nr_cpus = cpus_weight(cpu_possible_map);
  1268. DBG("nr_cpus: %d\n", nr_cpus);
  1269. if (nr_cpus > 1)
  1270. mpic_request_ipis();
  1271. return nr_cpus;
  1272. }
  1273. void __devinit smp_mpic_setup_cpu(int cpu)
  1274. {
  1275. mpic_setup_this_cpu();
  1276. }
  1277. #endif /* CONFIG_SMP */
  1278. #ifdef CONFIG_PM
  1279. static int mpic_suspend(struct sys_device *dev, pm_message_t state)
  1280. {
  1281. struct mpic *mpic = container_of(dev, struct mpic, sysdev);
  1282. int i;
  1283. for (i = 0; i < mpic->num_sources; i++) {
  1284. mpic->save_data[i].vecprio =
  1285. mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
  1286. mpic->save_data[i].dest =
  1287. mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
  1288. }
  1289. return 0;
  1290. }
  1291. static int mpic_resume(struct sys_device *dev)
  1292. {
  1293. struct mpic *mpic = container_of(dev, struct mpic, sysdev);
  1294. int i;
  1295. for (i = 0; i < mpic->num_sources; i++) {
  1296. mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
  1297. mpic->save_data[i].vecprio);
  1298. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1299. mpic->save_data[i].dest);
  1300. #ifdef CONFIG_MPIC_U3_HT_IRQS
  1301. {
  1302. struct mpic_irq_fixup *fixup = &mpic->fixups[i];
  1303. if (fixup->base) {
  1304. /* we use the lowest bit in an inverted meaning */
  1305. if ((mpic->save_data[i].fixup_data & 1) == 0)
  1306. continue;
  1307. /* Enable and configure */
  1308. writeb(0x10 + 2 * fixup->index, fixup->base + 2);
  1309. writel(mpic->save_data[i].fixup_data & ~1,
  1310. fixup->base + 4);
  1311. }
  1312. }
  1313. #endif
  1314. } /* end for loop */
  1315. return 0;
  1316. }
  1317. #endif
  1318. static struct sysdev_class mpic_sysclass = {
  1319. #ifdef CONFIG_PM
  1320. .resume = mpic_resume,
  1321. .suspend = mpic_suspend,
  1322. #endif
  1323. set_kset_name("mpic"),
  1324. };
  1325. static int mpic_init_sys(void)
  1326. {
  1327. struct mpic *mpic = mpics;
  1328. int error, id = 0;
  1329. error = sysdev_class_register(&mpic_sysclass);
  1330. while (mpic && !error) {
  1331. mpic->sysdev.cls = &mpic_sysclass;
  1332. mpic->sysdev.id = id++;
  1333. error = sysdev_register(&mpic->sysdev);
  1334. mpic = mpic->next;
  1335. }
  1336. return error;
  1337. }
  1338. device_initcall(mpic_init_sys);