qla_mr.c 90 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t __iomem *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. uint32_t __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state > pci_channel_io_frozen) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "error_state is greater than pci_channel_io_frozen, "
  53. "exiting.\n");
  54. return QLA_FUNCTION_TIMEOUT;
  55. }
  56. if (vha->device_flags & DFLG_DEV_FAILED) {
  57. ql_log(ql_log_warn, vha, 0x115f,
  58. "Device in failed state, exiting.\n");
  59. return QLA_FUNCTION_TIMEOUT;
  60. }
  61. reg = ha->iobase;
  62. io_lock_on = base_vha->flags.init_done;
  63. rval = QLA_SUCCESS;
  64. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  65. if (ha->flags.pci_channel_io_perm_failure) {
  66. ql_log(ql_log_warn, vha, 0x1175,
  67. "Perm failure on EEH timeout MBX, exiting.\n");
  68. return QLA_FUNCTION_TIMEOUT;
  69. }
  70. if (ha->flags.isp82xx_fw_hung) {
  71. /* Setting Link-Down error */
  72. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  73. ql_log(ql_log_warn, vha, 0x1176,
  74. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  75. rval = QLA_FUNCTION_FAILED;
  76. goto premature_exit;
  77. }
  78. /*
  79. * Wait for active mailbox commands to finish by waiting at most tov
  80. * seconds. This is to serialize actual issuing of mailbox cmds during
  81. * non ISP abort time.
  82. */
  83. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  84. /* Timeout occurred. Return error. */
  85. ql_log(ql_log_warn, vha, 0x1177,
  86. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  87. mcp->mb[0]);
  88. return QLA_FUNCTION_TIMEOUT;
  89. }
  90. ha->flags.mbox_busy = 1;
  91. /* Save mailbox command for debug */
  92. ha->mcp32 = mcp;
  93. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  94. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. /* Load mailbox registers. */
  97. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (mboxes & BIT_0)
  103. WRT_REG_DWORD(optr, *iptr);
  104. mboxes >>= 1;
  105. optr++;
  106. iptr++;
  107. }
  108. /* Issue set host interrupt command to send cmd out. */
  109. ha->flags.mbox_int = 0;
  110. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  111. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  112. (uint8_t *)mcp->mb, 16);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  114. ((uint8_t *)mcp->mb + 0x10), 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  116. ((uint8_t *)mcp->mb + 0x20), 8);
  117. /* Unlock mbx registers and wait for interrupt */
  118. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  119. "Going to unlock irq & waiting for interrupts. "
  120. "jiffies=%lx.\n", jiffies);
  121. /* Wait for mbx cmd completion until timeout */
  122. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  123. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  124. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  125. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  127. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  128. } else {
  129. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  130. "Cmd=%x Polling Mode.\n", command);
  131. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  132. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  133. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  134. while (!ha->flags.mbox_int) {
  135. if (time_after(jiffies, wait_time))
  136. break;
  137. /* Check for pending interrupts. */
  138. qla2x00_poll(ha->rsp_q_map[0]);
  139. if (!ha->flags.mbox_int &&
  140. !(IS_QLA2200(ha) &&
  141. command == MBC_LOAD_RISC_RAM_EXTENDED))
  142. usleep_range(10000, 11000);
  143. } /* while */
  144. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  145. "Waited %d sec.\n",
  146. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  147. }
  148. /* Check whether we timed out */
  149. if (ha->flags.mbox_int) {
  150. uint32_t *iptr2;
  151. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  152. "Cmd=%x completed.\n", command);
  153. /* Got interrupt. Clear the flag. */
  154. ha->flags.mbox_int = 0;
  155. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  156. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  157. rval = QLA_FUNCTION_FAILED;
  158. /* Load return mailbox registers. */
  159. iptr2 = mcp->mb;
  160. iptr = (uint32_t *)&ha->mailbox_out32[0];
  161. mboxes = mcp->in_mb;
  162. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  163. if (mboxes & BIT_0)
  164. *iptr2 = *iptr;
  165. mboxes >>= 1;
  166. iptr2++;
  167. iptr++;
  168. }
  169. } else {
  170. rval = QLA_FUNCTION_TIMEOUT;
  171. }
  172. ha->flags.mbox_busy = 0;
  173. /* Clean up */
  174. ha->mcp32 = NULL;
  175. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  176. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  177. "checking for additional resp interrupt.\n");
  178. /* polling mode for non isp_abort commands. */
  179. qla2x00_poll(ha->rsp_q_map[0]);
  180. }
  181. if (rval == QLA_FUNCTION_TIMEOUT &&
  182. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  183. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  184. ha->flags.eeh_busy) {
  185. /* not in dpc. schedule it for dpc to take over. */
  186. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  187. "Timeout, schedule isp_abort_needed.\n");
  188. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  189. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  190. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  191. ql_log(ql_log_info, base_vha, 0x115e,
  192. "Mailbox cmd timeout occurred, cmd=0x%x, "
  193. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  194. "abort.\n", command, mcp->mb[0],
  195. ha->flags.eeh_busy);
  196. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  197. qla2xxx_wake_dpc(vha);
  198. }
  199. } else if (!abort_active) {
  200. /* call abort directly since we are in the DPC thread */
  201. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  202. "Timeout, calling abort_isp.\n");
  203. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  204. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  205. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  206. ql_log(ql_log_info, base_vha, 0x1161,
  207. "Mailbox cmd timeout occurred, cmd=0x%x, "
  208. "mb[0]=0x%x. Scheduling ISP abort ",
  209. command, mcp->mb[0]);
  210. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  211. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  212. if (ha->isp_ops->abort_isp(vha)) {
  213. /* Failed. retry later. */
  214. set_bit(ISP_ABORT_NEEDED,
  215. &vha->dpc_flags);
  216. }
  217. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  218. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  219. "Finished abort_isp.\n");
  220. }
  221. }
  222. }
  223. premature_exit:
  224. /* Allow next mbx cmd to come in. */
  225. complete(&ha->mbx_cmd_comp);
  226. if (rval) {
  227. ql_log(ql_log_warn, base_vha, 0x1163,
  228. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  229. "mb[3]=%x, cmd=%x ****.\n",
  230. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  231. } else {
  232. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  233. }
  234. return rval;
  235. }
  236. /*
  237. * qlafx00_driver_shutdown
  238. * Indicate a driver shutdown to firmware.
  239. *
  240. * Input:
  241. * ha = adapter block pointer.
  242. *
  243. * Returns:
  244. * local function return status code.
  245. *
  246. * Context:
  247. * Kernel context.
  248. */
  249. static int
  250. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  251. {
  252. int rval;
  253. struct mbx_cmd_32 mc;
  254. struct mbx_cmd_32 *mcp = &mc;
  255. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  256. "Entered %s.\n", __func__);
  257. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  258. mcp->out_mb = MBX_0;
  259. mcp->in_mb = MBX_0;
  260. if (tmo)
  261. mcp->tov = tmo;
  262. else
  263. mcp->tov = MBX_TOV_SECONDS;
  264. mcp->flags = 0;
  265. rval = qlafx00_mailbox_command(vha, mcp);
  266. if (rval != QLA_SUCCESS) {
  267. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  268. "Failed=%x.\n", rval);
  269. } else {
  270. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  271. "Done %s.\n", __func__);
  272. }
  273. return rval;
  274. }
  275. /*
  276. * qlafx00_get_firmware_state
  277. * Get adapter firmware state.
  278. *
  279. * Input:
  280. * ha = adapter block pointer.
  281. * TARGET_QUEUE_LOCK must be released.
  282. * ADAPTER_STATE_LOCK must be released.
  283. *
  284. * Returns:
  285. * qla7xxx local function return status code.
  286. *
  287. * Context:
  288. * Kernel context.
  289. */
  290. static int
  291. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  292. {
  293. int rval;
  294. struct mbx_cmd_32 mc;
  295. struct mbx_cmd_32 *mcp = &mc;
  296. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  297. "Entered %s.\n", __func__);
  298. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  299. mcp->out_mb = MBX_0;
  300. mcp->in_mb = MBX_1|MBX_0;
  301. mcp->tov = MBX_TOV_SECONDS;
  302. mcp->flags = 0;
  303. rval = qlafx00_mailbox_command(vha, mcp);
  304. /* Return firmware states. */
  305. states[0] = mcp->mb[1];
  306. if (rval != QLA_SUCCESS) {
  307. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  308. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  309. } else {
  310. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  311. "Done %s.\n", __func__);
  312. }
  313. return rval;
  314. }
  315. /*
  316. * qlafx00_init_firmware
  317. * Initialize adapter firmware.
  318. *
  319. * Input:
  320. * ha = adapter block pointer.
  321. * dptr = Initialization control block pointer.
  322. * size = size of initialization control block.
  323. * TARGET_QUEUE_LOCK must be released.
  324. * ADAPTER_STATE_LOCK must be released.
  325. *
  326. * Returns:
  327. * qlafx00 local function return status code.
  328. *
  329. * Context:
  330. * Kernel context.
  331. */
  332. int
  333. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  334. {
  335. int rval;
  336. struct mbx_cmd_32 mc;
  337. struct mbx_cmd_32 *mcp = &mc;
  338. struct qla_hw_data *ha = vha->hw;
  339. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  340. "Entered %s.\n", __func__);
  341. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  342. mcp->mb[1] = 0;
  343. mcp->mb[2] = MSD(ha->init_cb_dma);
  344. mcp->mb[3] = LSD(ha->init_cb_dma);
  345. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  346. mcp->in_mb = MBX_0;
  347. mcp->buf_size = size;
  348. mcp->flags = MBX_DMA_OUT;
  349. mcp->tov = MBX_TOV_SECONDS;
  350. rval = qlafx00_mailbox_command(vha, mcp);
  351. if (rval != QLA_SUCCESS) {
  352. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  353. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  354. } else {
  355. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  356. "Done %s.\n", __func__);
  357. }
  358. return rval;
  359. }
  360. /*
  361. * qlafx00_mbx_reg_test
  362. */
  363. static int
  364. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  365. {
  366. int rval;
  367. struct mbx_cmd_32 mc;
  368. struct mbx_cmd_32 *mcp = &mc;
  369. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  370. "Entered %s.\n", __func__);
  371. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  372. mcp->mb[1] = 0xAAAA;
  373. mcp->mb[2] = 0x5555;
  374. mcp->mb[3] = 0xAA55;
  375. mcp->mb[4] = 0x55AA;
  376. mcp->mb[5] = 0xA5A5;
  377. mcp->mb[6] = 0x5A5A;
  378. mcp->mb[7] = 0x2525;
  379. mcp->mb[8] = 0xBBBB;
  380. mcp->mb[9] = 0x6666;
  381. mcp->mb[10] = 0xBB66;
  382. mcp->mb[11] = 0x66BB;
  383. mcp->mb[12] = 0xB6B6;
  384. mcp->mb[13] = 0x6B6B;
  385. mcp->mb[14] = 0x3636;
  386. mcp->mb[15] = 0xCCCC;
  387. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  388. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  389. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  390. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  391. mcp->buf_size = 0;
  392. mcp->flags = MBX_DMA_OUT;
  393. mcp->tov = MBX_TOV_SECONDS;
  394. rval = qlafx00_mailbox_command(vha, mcp);
  395. if (rval == QLA_SUCCESS) {
  396. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  397. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  398. rval = QLA_FUNCTION_FAILED;
  399. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  400. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  401. rval = QLA_FUNCTION_FAILED;
  402. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  403. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  404. rval = QLA_FUNCTION_FAILED;
  405. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  406. mcp->mb[31] != 0xCCCC)
  407. rval = QLA_FUNCTION_FAILED;
  408. }
  409. if (rval != QLA_SUCCESS) {
  410. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  411. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  412. } else {
  413. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  414. "Done %s.\n", __func__);
  415. }
  416. return rval;
  417. }
  418. /**
  419. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  420. * @ha: HA context
  421. *
  422. * Returns 0 on success.
  423. */
  424. int
  425. qlafx00_pci_config(scsi_qla_host_t *vha)
  426. {
  427. uint16_t w;
  428. struct qla_hw_data *ha = vha->hw;
  429. pci_set_master(ha->pdev);
  430. pci_try_set_mwi(ha->pdev);
  431. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  432. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  433. w &= ~PCI_COMMAND_INTX_DISABLE;
  434. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  435. /* PCIe -- adjust Maximum Read Request Size (2048). */
  436. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  437. pcie_set_readrq(ha->pdev, 2048);
  438. ha->chip_revision = ha->pdev->revision;
  439. return QLA_SUCCESS;
  440. }
  441. /**
  442. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  443. * @ha: HA context
  444. *
  445. */
  446. static inline void
  447. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  448. {
  449. unsigned long flags = 0;
  450. struct qla_hw_data *ha = vha->hw;
  451. int i, core;
  452. uint32_t cnt;
  453. /* Set all 4 cores in reset */
  454. for (i = 0; i < 4; i++) {
  455. QLAFX00_SET_HBA_SOC_REG(ha,
  456. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  457. }
  458. /* Set all 4 core Clock gating control */
  459. for (i = 0; i < 4; i++) {
  460. QLAFX00_SET_HBA_SOC_REG(ha,
  461. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  462. }
  463. /* Reset all units in Fabric */
  464. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x11F0101));
  465. /* Reset all interrupt control registers */
  466. for (i = 0; i < 115; i++) {
  467. QLAFX00_SET_HBA_SOC_REG(ha,
  468. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  469. }
  470. /* Reset Timers control registers. per core */
  471. for (core = 0; core < 4; core++)
  472. for (i = 0; i < 8; i++)
  473. QLAFX00_SET_HBA_SOC_REG(ha,
  474. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  475. /* Reset per core IRQ ack register */
  476. for (core = 0; core < 4; core++)
  477. QLAFX00_SET_HBA_SOC_REG(ha,
  478. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  479. /* Set Fabric control and config to defaults */
  480. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  481. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  482. spin_lock_irqsave(&ha->hardware_lock, flags);
  483. /* Kick in Fabric units */
  484. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  485. /* Kick in Core0 to start boot process */
  486. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  487. /* Wait 10secs for soft-reset to complete. */
  488. for (cnt = 10; cnt; cnt--) {
  489. msleep(1000);
  490. barrier();
  491. }
  492. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  493. }
  494. /**
  495. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  496. * @ha: HA context
  497. *
  498. * Returns 0 on success.
  499. */
  500. void
  501. qlafx00_soft_reset(scsi_qla_host_t *vha)
  502. {
  503. struct qla_hw_data *ha = vha->hw;
  504. if (unlikely(pci_channel_offline(ha->pdev) &&
  505. ha->flags.pci_channel_io_perm_failure))
  506. return;
  507. ha->isp_ops->disable_intrs(ha);
  508. qlafx00_soc_cpu_reset(vha);
  509. ha->isp_ops->enable_intrs(ha);
  510. }
  511. /**
  512. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  513. * @ha: HA context
  514. *
  515. * Returns 0 on success.
  516. */
  517. int
  518. qlafx00_chip_diag(scsi_qla_host_t *vha)
  519. {
  520. int rval = 0;
  521. struct qla_hw_data *ha = vha->hw;
  522. struct req_que *req = ha->req_q_map[0];
  523. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  524. rval = qlafx00_mbx_reg_test(vha);
  525. if (rval) {
  526. ql_log(ql_log_warn, vha, 0x1165,
  527. "Failed mailbox send register test\n");
  528. } else {
  529. /* Flag a successful rval */
  530. rval = QLA_SUCCESS;
  531. }
  532. return rval;
  533. }
  534. void
  535. qlafx00_config_rings(struct scsi_qla_host *vha)
  536. {
  537. struct qla_hw_data *ha = vha->hw;
  538. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  539. struct init_cb_fx *icb;
  540. struct req_que *req = ha->req_q_map[0];
  541. struct rsp_que *rsp = ha->rsp_q_map[0];
  542. /* Setup ring parameters in initialization control block. */
  543. icb = (struct init_cb_fx *)ha->init_cb;
  544. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  545. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  546. icb->request_q_length = cpu_to_le16(req->length);
  547. icb->response_q_length = cpu_to_le16(rsp->length);
  548. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  549. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  550. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  551. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  552. WRT_REG_DWORD(&reg->req_q_in, 0);
  553. WRT_REG_DWORD(&reg->req_q_out, 0);
  554. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  555. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  556. /* PCI posting */
  557. RD_REG_DWORD(&reg->rsp_q_out);
  558. }
  559. char *
  560. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  561. {
  562. struct qla_hw_data *ha = vha->hw;
  563. int pcie_reg;
  564. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  565. if (pcie_reg) {
  566. strcpy(str, "PCIe iSA");
  567. return str;
  568. }
  569. return str;
  570. }
  571. char *
  572. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str)
  573. {
  574. struct qla_hw_data *ha = vha->hw;
  575. sprintf(str, "%s", ha->mr.fw_version);
  576. return str;
  577. }
  578. void
  579. qlafx00_enable_intrs(struct qla_hw_data *ha)
  580. {
  581. unsigned long flags = 0;
  582. spin_lock_irqsave(&ha->hardware_lock, flags);
  583. ha->interrupts_on = 1;
  584. QLAFX00_ENABLE_ICNTRL_REG(ha);
  585. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  586. }
  587. void
  588. qlafx00_disable_intrs(struct qla_hw_data *ha)
  589. {
  590. unsigned long flags = 0;
  591. spin_lock_irqsave(&ha->hardware_lock, flags);
  592. ha->interrupts_on = 0;
  593. QLAFX00_DISABLE_ICNTRL_REG(ha);
  594. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  595. }
  596. static void
  597. qlafx00_tmf_iocb_timeout(void *data)
  598. {
  599. srb_t *sp = (srb_t *)data;
  600. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  601. tmf->u.tmf.comp_status = CS_TIMEOUT;
  602. complete(&tmf->u.tmf.comp);
  603. }
  604. static void
  605. qlafx00_tmf_sp_done(void *data, void *ptr, int res)
  606. {
  607. srb_t *sp = (srb_t *)ptr;
  608. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  609. complete(&tmf->u.tmf.comp);
  610. }
  611. static int
  612. qlafx00_async_tm_cmd(fc_port_t *fcport, uint32_t flags,
  613. uint32_t lun, uint32_t tag)
  614. {
  615. scsi_qla_host_t *vha = fcport->vha;
  616. struct srb_iocb *tm_iocb;
  617. srb_t *sp;
  618. int rval = QLA_FUNCTION_FAILED;
  619. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  620. if (!sp)
  621. goto done;
  622. tm_iocb = &sp->u.iocb_cmd;
  623. sp->type = SRB_TM_CMD;
  624. sp->name = "tmf";
  625. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
  626. tm_iocb->u.tmf.flags = flags;
  627. tm_iocb->u.tmf.lun = lun;
  628. tm_iocb->u.tmf.data = tag;
  629. sp->done = qlafx00_tmf_sp_done;
  630. tm_iocb->timeout = qlafx00_tmf_iocb_timeout;
  631. init_completion(&tm_iocb->u.tmf.comp);
  632. rval = qla2x00_start_sp(sp);
  633. if (rval != QLA_SUCCESS)
  634. goto done_free_sp;
  635. ql_dbg(ql_dbg_async, vha, 0x507b,
  636. "Task management command issued target_id=%x\n",
  637. fcport->tgt_id);
  638. wait_for_completion(&tm_iocb->u.tmf.comp);
  639. rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
  640. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  641. done_free_sp:
  642. sp->free(vha, sp);
  643. done:
  644. return rval;
  645. }
  646. int
  647. qlafx00_abort_target(fc_port_t *fcport, unsigned int l, int tag)
  648. {
  649. return qlafx00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  650. }
  651. int
  652. qlafx00_lun_reset(fc_port_t *fcport, unsigned int l, int tag)
  653. {
  654. return qlafx00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  655. }
  656. int
  657. qlafx00_iospace_config(struct qla_hw_data *ha)
  658. {
  659. if (pci_request_selected_regions(ha->pdev, ha->bars,
  660. QLA2XXX_DRIVER_NAME)) {
  661. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  662. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  663. pci_name(ha->pdev));
  664. goto iospace_error_exit;
  665. }
  666. /* Use MMIO operations for all accesses. */
  667. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  668. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  669. "Invalid pci I/O region size (%s).\n",
  670. pci_name(ha->pdev));
  671. goto iospace_error_exit;
  672. }
  673. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  674. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  675. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  676. pci_name(ha->pdev));
  677. goto iospace_error_exit;
  678. }
  679. ha->cregbase =
  680. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  681. if (!ha->cregbase) {
  682. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  683. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  684. goto iospace_error_exit;
  685. }
  686. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  687. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  688. "region #2 not an MMIO resource (%s), aborting\n",
  689. pci_name(ha->pdev));
  690. goto iospace_error_exit;
  691. }
  692. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  693. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  694. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  695. pci_name(ha->pdev));
  696. goto iospace_error_exit;
  697. }
  698. ha->iobase =
  699. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  700. if (!ha->iobase) {
  701. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  702. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  703. goto iospace_error_exit;
  704. }
  705. /* Determine queue resources */
  706. ha->max_req_queues = ha->max_rsp_queues = 1;
  707. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  708. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  709. ha->bars, ha->cregbase, ha->iobase);
  710. return 0;
  711. iospace_error_exit:
  712. return -ENOMEM;
  713. }
  714. static void
  715. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  716. {
  717. struct qla_hw_data *ha = vha->hw;
  718. struct req_que *req = ha->req_q_map[0];
  719. struct rsp_que *rsp = ha->rsp_q_map[0];
  720. req->length_fx00 = req->length;
  721. req->ring_fx00 = req->ring;
  722. req->dma_fx00 = req->dma;
  723. rsp->length_fx00 = rsp->length;
  724. rsp->ring_fx00 = rsp->ring;
  725. rsp->dma_fx00 = rsp->dma;
  726. ql_dbg(ql_dbg_init, vha, 0x012d,
  727. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  728. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  729. req->length_fx00, (u64)req->dma_fx00);
  730. ql_dbg(ql_dbg_init, vha, 0x012e,
  731. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  732. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  733. rsp->length_fx00, (u64)rsp->dma_fx00);
  734. }
  735. static int
  736. qlafx00_config_queues(struct scsi_qla_host *vha)
  737. {
  738. struct qla_hw_data *ha = vha->hw;
  739. struct req_que *req = ha->req_q_map[0];
  740. struct rsp_que *rsp = ha->rsp_q_map[0];
  741. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  742. req->length = ha->req_que_len;
  743. req->ring = (void *)ha->iobase + ha->req_que_off;
  744. req->dma = bar2_hdl + ha->req_que_off;
  745. if ((!req->ring) || (req->length == 0)) {
  746. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  747. "Unable to allocate memory for req_ring\n");
  748. return QLA_FUNCTION_FAILED;
  749. }
  750. ql_dbg(ql_dbg_init, vha, 0x0130,
  751. "req: %p req_ring pointer %p req len 0x%x "
  752. "req off 0x%x\n, req->dma: 0x%llx",
  753. req, req->ring, req->length,
  754. ha->req_que_off, (u64)req->dma);
  755. rsp->length = ha->rsp_que_len;
  756. rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
  757. rsp->dma = bar2_hdl + ha->rsp_que_off;
  758. if ((!rsp->ring) || (rsp->length == 0)) {
  759. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  760. "Unable to allocate memory for rsp_ring\n");
  761. return QLA_FUNCTION_FAILED;
  762. }
  763. ql_dbg(ql_dbg_init, vha, 0x0132,
  764. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  765. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  766. rsp, rsp->ring, rsp->length,
  767. ha->rsp_que_off, (u64)rsp->dma);
  768. return QLA_SUCCESS;
  769. }
  770. static int
  771. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  772. {
  773. int rval = 0;
  774. unsigned long wtime;
  775. uint16_t wait_time; /* Wait time */
  776. struct qla_hw_data *ha = vha->hw;
  777. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  778. uint32_t aenmbx, aenmbx7 = 0;
  779. uint32_t state[5];
  780. bool done = false;
  781. /* 30 seconds wait - Adjust if required */
  782. wait_time = 30;
  783. /* wait time before firmware ready */
  784. wtime = jiffies + (wait_time * HZ);
  785. do {
  786. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  787. barrier();
  788. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  789. "aenmbx: 0x%x\n", aenmbx);
  790. switch (aenmbx) {
  791. case MBA_FW_NOT_STARTED:
  792. case MBA_FW_STARTING:
  793. break;
  794. case MBA_SYSTEM_ERR:
  795. case MBA_REQ_TRANSFER_ERR:
  796. case MBA_RSP_TRANSFER_ERR:
  797. case MBA_FW_INIT_FAILURE:
  798. qlafx00_soft_reset(vha);
  799. break;
  800. case MBA_FW_RESTART_CMPLT:
  801. /* Set the mbx and rqstq intr code */
  802. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  803. ha->mbx_intr_code = MSW(aenmbx7);
  804. ha->rqstq_intr_code = LSW(aenmbx7);
  805. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  806. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  807. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  808. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  809. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  810. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  811. ql_dbg(ql_dbg_init, vha, 0x0134,
  812. "f/w returned mbx_intr_code: 0x%x, "
  813. "rqstq_intr_code: 0x%x\n",
  814. ha->mbx_intr_code, ha->rqstq_intr_code);
  815. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  816. rval = QLA_SUCCESS;
  817. done = true;
  818. break;
  819. default:
  820. /* If fw is apparently not ready. In order to continue,
  821. * we might need to issue Mbox cmd, but the problem is
  822. * that the DoorBell vector values that come with the
  823. * 8060 AEN are most likely gone by now (and thus no
  824. * bell would be rung on the fw side when mbox cmd is
  825. * issued). We have to therefore grab the 8060 AEN
  826. * shadow regs (filled in by FW when the last 8060
  827. * AEN was being posted).
  828. * Do the following to determine what is needed in
  829. * order to get the FW ready:
  830. * 1. reload the 8060 AEN values from the shadow regs
  831. * 2. clear int status to get rid of possible pending
  832. * interrupts
  833. * 3. issue Get FW State Mbox cmd to determine fw state
  834. * Set the mbx and rqstq intr code from Shadow Regs
  835. */
  836. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  837. ha->mbx_intr_code = MSW(aenmbx7);
  838. ha->rqstq_intr_code = LSW(aenmbx7);
  839. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  840. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  841. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  842. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  843. ql_dbg(ql_dbg_init, vha, 0x0135,
  844. "f/w returned mbx_intr_code: 0x%x, "
  845. "rqstq_intr_code: 0x%x\n",
  846. ha->mbx_intr_code, ha->rqstq_intr_code);
  847. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  848. /* Get the FW state */
  849. rval = qlafx00_get_firmware_state(vha, state);
  850. if (rval != QLA_SUCCESS) {
  851. /* Retry if timer has not expired */
  852. break;
  853. }
  854. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  855. /* Firmware is waiting to be
  856. * initialized by driver
  857. */
  858. rval = QLA_SUCCESS;
  859. done = true;
  860. break;
  861. }
  862. /* Issue driver shutdown and wait until f/w recovers.
  863. * Driver should continue to poll until 8060 AEN is
  864. * received indicating firmware recovery.
  865. */
  866. ql_dbg(ql_dbg_init, vha, 0x0136,
  867. "Sending Driver shutdown fw_state 0x%x\n",
  868. state[0]);
  869. rval = qlafx00_driver_shutdown(vha, 10);
  870. if (rval != QLA_SUCCESS) {
  871. rval = QLA_FUNCTION_FAILED;
  872. break;
  873. }
  874. msleep(500);
  875. wtime = jiffies + (wait_time * HZ);
  876. break;
  877. }
  878. if (!done) {
  879. if (time_after_eq(jiffies, wtime)) {
  880. ql_dbg(ql_dbg_init, vha, 0x0137,
  881. "Init f/w failed: aen[7]: 0x%x\n",
  882. RD_REG_DWORD(&reg->aenmailbox7));
  883. rval = QLA_FUNCTION_FAILED;
  884. done = true;
  885. break;
  886. }
  887. /* Delay for a while */
  888. msleep(500);
  889. }
  890. } while (!done);
  891. if (rval)
  892. ql_dbg(ql_dbg_init, vha, 0x0138,
  893. "%s **** FAILED ****.\n", __func__);
  894. else
  895. ql_dbg(ql_dbg_init, vha, 0x0139,
  896. "%s **** SUCCESS ****.\n", __func__);
  897. return rval;
  898. }
  899. /*
  900. * qlafx00_fw_ready() - Waits for firmware ready.
  901. * @ha: HA context
  902. *
  903. * Returns 0 on success.
  904. */
  905. int
  906. qlafx00_fw_ready(scsi_qla_host_t *vha)
  907. {
  908. int rval;
  909. unsigned long wtime;
  910. uint16_t wait_time; /* Wait time if loop is coming ready */
  911. uint32_t state[5];
  912. rval = QLA_SUCCESS;
  913. wait_time = 10;
  914. /* wait time before firmware ready */
  915. wtime = jiffies + (wait_time * HZ);
  916. /* Wait for ISP to finish init */
  917. if (!vha->flags.init_done)
  918. ql_dbg(ql_dbg_init, vha, 0x013a,
  919. "Waiting for init to complete...\n");
  920. do {
  921. rval = qlafx00_get_firmware_state(vha, state);
  922. if (rval == QLA_SUCCESS) {
  923. if (state[0] == FSTATE_FX00_INITIALIZED) {
  924. ql_dbg(ql_dbg_init, vha, 0x013b,
  925. "fw_state=%x\n", state[0]);
  926. rval = QLA_SUCCESS;
  927. break;
  928. }
  929. }
  930. rval = QLA_FUNCTION_FAILED;
  931. if (time_after_eq(jiffies, wtime))
  932. break;
  933. /* Delay for a while */
  934. msleep(500);
  935. ql_dbg(ql_dbg_init, vha, 0x013c,
  936. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  937. } while (1);
  938. if (rval)
  939. ql_dbg(ql_dbg_init, vha, 0x013d,
  940. "Firmware ready **** FAILED ****.\n");
  941. else
  942. ql_dbg(ql_dbg_init, vha, 0x013e,
  943. "Firmware ready **** SUCCESS ****.\n");
  944. return rval;
  945. }
  946. static int
  947. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  948. struct list_head *new_fcports)
  949. {
  950. int rval;
  951. uint16_t tgt_id;
  952. fc_port_t *fcport, *new_fcport;
  953. int found;
  954. struct qla_hw_data *ha = vha->hw;
  955. rval = QLA_SUCCESS;
  956. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  957. return QLA_FUNCTION_FAILED;
  958. if ((atomic_read(&vha->loop_down_timer) ||
  959. STATE_TRANSITION(vha))) {
  960. atomic_set(&vha->loop_down_timer, 0);
  961. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  962. return QLA_FUNCTION_FAILED;
  963. }
  964. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  965. "Listing Target bit map...\n");
  966. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  967. 0x2089, (uint8_t *)ha->gid_list, 32);
  968. /* Allocate temporary rmtport for any new rmtports discovered. */
  969. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  970. if (new_fcport == NULL)
  971. return QLA_MEMORY_ALLOC_FAILED;
  972. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  973. QLAFX00_TGT_NODE_LIST_SIZE) {
  974. /* Send get target node info */
  975. new_fcport->tgt_id = tgt_id;
  976. rval = qlafx00_fx_disc(vha, new_fcport,
  977. FXDISC_GET_TGT_NODE_INFO);
  978. if (rval != QLA_SUCCESS) {
  979. ql_log(ql_log_warn, vha, 0x208a,
  980. "Target info scan failed -- assuming zero-entry "
  981. "result...\n");
  982. continue;
  983. }
  984. /* Locate matching device in database. */
  985. found = 0;
  986. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  987. if (memcmp(new_fcport->port_name,
  988. fcport->port_name, WWN_SIZE))
  989. continue;
  990. found++;
  991. /*
  992. * If tgt_id is same and state FCS_ONLINE, nothing
  993. * changed.
  994. */
  995. if (fcport->tgt_id == new_fcport->tgt_id &&
  996. atomic_read(&fcport->state) == FCS_ONLINE)
  997. break;
  998. /*
  999. * Tgt ID changed or device was marked to be updated.
  1000. */
  1001. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1002. "TGT-ID Change(%s): Present tgt id: "
  1003. "0x%x state: 0x%x "
  1004. "wwnn = %llx wwpn = %llx.\n",
  1005. __func__, fcport->tgt_id,
  1006. atomic_read(&fcport->state),
  1007. (unsigned long long)wwn_to_u64(fcport->node_name),
  1008. (unsigned long long)wwn_to_u64(fcport->port_name));
  1009. ql_log(ql_log_info, vha, 0x208c,
  1010. "TGT-ID Announce(%s): Discovered tgt "
  1011. "id 0x%x wwnn = %llx "
  1012. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1013. (unsigned long long)
  1014. wwn_to_u64(new_fcport->node_name),
  1015. (unsigned long long)
  1016. wwn_to_u64(new_fcport->port_name));
  1017. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1018. fcport->old_tgt_id = fcport->tgt_id;
  1019. fcport->tgt_id = new_fcport->tgt_id;
  1020. ql_log(ql_log_info, vha, 0x208d,
  1021. "TGT-ID: New fcport Added: %p\n", fcport);
  1022. qla2x00_update_fcport(vha, fcport);
  1023. } else {
  1024. ql_log(ql_log_info, vha, 0x208e,
  1025. " Existing TGT-ID %x did not get "
  1026. " offline event from firmware.\n",
  1027. fcport->old_tgt_id);
  1028. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1029. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1030. kfree(new_fcport);
  1031. return rval;
  1032. }
  1033. break;
  1034. }
  1035. if (found)
  1036. continue;
  1037. /* If device was not in our fcports list, then add it. */
  1038. list_add_tail(&new_fcport->list, new_fcports);
  1039. /* Allocate a new replacement fcport. */
  1040. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1041. if (new_fcport == NULL)
  1042. return QLA_MEMORY_ALLOC_FAILED;
  1043. }
  1044. kfree(new_fcport);
  1045. return rval;
  1046. }
  1047. /*
  1048. * qlafx00_configure_all_targets
  1049. * Setup target devices with node ID's.
  1050. *
  1051. * Input:
  1052. * ha = adapter block pointer.
  1053. *
  1054. * Returns:
  1055. * 0 = success.
  1056. * BIT_0 = error
  1057. */
  1058. static int
  1059. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1060. {
  1061. int rval;
  1062. fc_port_t *fcport, *rmptemp;
  1063. LIST_HEAD(new_fcports);
  1064. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1065. FXDISC_GET_TGT_NODE_LIST);
  1066. if (rval != QLA_SUCCESS) {
  1067. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1068. return rval;
  1069. }
  1070. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1071. if (rval != QLA_SUCCESS) {
  1072. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1073. return rval;
  1074. }
  1075. /*
  1076. * Delete all previous devices marked lost.
  1077. */
  1078. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1079. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1080. break;
  1081. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1082. if (fcport->port_type != FCT_INITIATOR)
  1083. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1084. }
  1085. }
  1086. /*
  1087. * Add the new devices to our devices list.
  1088. */
  1089. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1090. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1091. break;
  1092. qla2x00_update_fcport(vha, fcport);
  1093. list_move_tail(&fcport->list, &vha->vp_fcports);
  1094. ql_log(ql_log_info, vha, 0x208f,
  1095. "Attach new target id 0x%x wwnn = %llx "
  1096. "wwpn = %llx.\n",
  1097. fcport->tgt_id,
  1098. (unsigned long long)wwn_to_u64(fcport->node_name),
  1099. (unsigned long long)wwn_to_u64(fcport->port_name));
  1100. }
  1101. /* Free all new device structures not processed. */
  1102. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1103. list_del(&fcport->list);
  1104. kfree(fcport);
  1105. }
  1106. return rval;
  1107. }
  1108. /*
  1109. * qlafx00_configure_devices
  1110. * Updates Fibre Channel Device Database with what is actually on loop.
  1111. *
  1112. * Input:
  1113. * ha = adapter block pointer.
  1114. *
  1115. * Returns:
  1116. * 0 = success.
  1117. * 1 = error.
  1118. * 2 = database was full and device was not configured.
  1119. */
  1120. int
  1121. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1122. {
  1123. int rval;
  1124. unsigned long flags, save_flags;
  1125. rval = QLA_SUCCESS;
  1126. save_flags = flags = vha->dpc_flags;
  1127. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1128. "Configure devices -- dpc flags =0x%lx\n", flags);
  1129. rval = qlafx00_configure_all_targets(vha);
  1130. if (rval == QLA_SUCCESS) {
  1131. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1132. rval = QLA_FUNCTION_FAILED;
  1133. } else {
  1134. atomic_set(&vha->loop_state, LOOP_READY);
  1135. ql_log(ql_log_info, vha, 0x2091,
  1136. "Device Ready\n");
  1137. }
  1138. }
  1139. if (rval) {
  1140. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1141. "%s *** FAILED ***.\n", __func__);
  1142. } else {
  1143. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1144. "%s: exiting normally.\n", __func__);
  1145. }
  1146. return rval;
  1147. }
  1148. static void
  1149. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha)
  1150. {
  1151. struct qla_hw_data *ha = vha->hw;
  1152. fc_port_t *fcport;
  1153. vha->flags.online = 0;
  1154. ha->flags.chip_reset_done = 0;
  1155. ha->mr.fw_hbt_en = 0;
  1156. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1157. vha->qla_stats.total_isp_aborts++;
  1158. ql_log(ql_log_info, vha, 0x013f,
  1159. "Performing ISP error recovery - ha = %p.\n", ha);
  1160. ha->isp_ops->reset_chip(vha);
  1161. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1162. atomic_set(&vha->loop_state, LOOP_DOWN);
  1163. atomic_set(&vha->loop_down_timer,
  1164. QLAFX00_LOOP_DOWN_TIME);
  1165. } else {
  1166. if (!atomic_read(&vha->loop_down_timer))
  1167. atomic_set(&vha->loop_down_timer,
  1168. QLAFX00_LOOP_DOWN_TIME);
  1169. }
  1170. /* Clear all async request states across all VPs. */
  1171. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1172. fcport->flags = 0;
  1173. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1174. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1175. }
  1176. if (!ha->flags.eeh_busy) {
  1177. /* Requeue all commands in outstanding command list. */
  1178. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1179. }
  1180. qla2x00_free_irqs(vha);
  1181. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1182. /* Clear the Interrupts */
  1183. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1184. ql_log(ql_log_info, vha, 0x0140,
  1185. "%s Done done - ha=%p.\n", __func__, ha);
  1186. }
  1187. /**
  1188. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1189. * @ha: HA context
  1190. *
  1191. * Beginning of request ring has initialization control block already built
  1192. * by nvram config routine.
  1193. *
  1194. * Returns 0 on success.
  1195. */
  1196. void
  1197. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1198. {
  1199. uint16_t cnt;
  1200. response_t *pkt;
  1201. rsp->ring_ptr = rsp->ring;
  1202. rsp->ring_index = 0;
  1203. rsp->status_srb = NULL;
  1204. pkt = rsp->ring_ptr;
  1205. for (cnt = 0; cnt < rsp->length; cnt++) {
  1206. pkt->signature = RESPONSE_PROCESSED;
  1207. WRT_REG_DWORD(&pkt->signature, RESPONSE_PROCESSED);
  1208. pkt++;
  1209. }
  1210. }
  1211. int
  1212. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1213. {
  1214. uint32_t status = QLA_FUNCTION_FAILED;
  1215. struct qla_hw_data *ha = vha->hw;
  1216. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1217. uint32_t aenmbx7;
  1218. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1219. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1220. ha->mbx_intr_code = MSW(aenmbx7);
  1221. ha->rqstq_intr_code = LSW(aenmbx7);
  1222. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1223. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1224. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1225. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1226. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1227. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1228. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1229. ha->mbx_intr_code, ha->rqstq_intr_code,
  1230. ha->req_que_off, ha->rsp_que_len);
  1231. /* Clear the Interrupts */
  1232. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1233. status = qla2x00_init_rings(vha);
  1234. if (!status) {
  1235. vha->flags.online = 1;
  1236. /* if no cable then assume it's good */
  1237. if ((vha->device_flags & DFLG_NO_CABLE))
  1238. status = 0;
  1239. /* Register system information */
  1240. if (qlafx00_fx_disc(vha,
  1241. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1242. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1243. "failed to register host info\n");
  1244. }
  1245. scsi_unblock_requests(vha->host);
  1246. return status;
  1247. }
  1248. void
  1249. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1250. {
  1251. struct qla_hw_data *ha = vha->hw;
  1252. uint32_t fw_heart_beat;
  1253. uint32_t aenmbx0;
  1254. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1255. /* Check firmware health */
  1256. if (ha->mr.fw_hbt_cnt)
  1257. ha->mr.fw_hbt_cnt--;
  1258. else {
  1259. if ((!ha->flags.mr_reset_hdlr_active) &&
  1260. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1261. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1262. (ha->mr.fw_hbt_en)) {
  1263. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1264. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1265. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1266. ha->mr.fw_hbt_miss_cnt = 0;
  1267. } else {
  1268. ha->mr.fw_hbt_miss_cnt++;
  1269. if (ha->mr.fw_hbt_miss_cnt ==
  1270. QLAFX00_HEARTBEAT_MISS_CNT) {
  1271. set_bit(ISP_ABORT_NEEDED,
  1272. &vha->dpc_flags);
  1273. qla2xxx_wake_dpc(vha);
  1274. ha->mr.fw_hbt_miss_cnt = 0;
  1275. }
  1276. }
  1277. }
  1278. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1279. }
  1280. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1281. /* Reset recovery to be performed in timer routine */
  1282. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1283. if (ha->mr.fw_reset_timer_exp) {
  1284. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1285. qla2xxx_wake_dpc(vha);
  1286. ha->mr.fw_reset_timer_exp = 0;
  1287. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1288. /* Wake up DPC to rescan the targets */
  1289. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1290. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1291. qla2xxx_wake_dpc(vha);
  1292. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1293. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1294. (!ha->mr.fw_hbt_en)) {
  1295. ha->mr.fw_hbt_en = 1;
  1296. } else if (!ha->mr.fw_reset_timer_tick) {
  1297. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1298. ha->mr.fw_reset_timer_exp = 1;
  1299. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1300. } else if (aenmbx0 == 0xFFFFFFFF) {
  1301. uint32_t data0, data1;
  1302. data0 = QLAFX00_RD_REG(ha,
  1303. QLAFX00_BAR1_BASE_ADDR_REG);
  1304. data1 = QLAFX00_RD_REG(ha,
  1305. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1306. data0 &= 0xffff0000;
  1307. data1 &= 0x0000ffff;
  1308. QLAFX00_WR_REG(ha,
  1309. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1310. (data0 | data1));
  1311. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1312. ha->mr.fw_reset_timer_tick =
  1313. QLAFX00_MAX_RESET_INTERVAL;
  1314. }
  1315. ha->mr.old_aenmbx0_state = aenmbx0;
  1316. ha->mr.fw_reset_timer_tick--;
  1317. }
  1318. }
  1319. /*
  1320. * qlfx00a_reset_initialize
  1321. * Re-initialize after a iSA device reset.
  1322. *
  1323. * Input:
  1324. * ha = adapter block pointer.
  1325. *
  1326. * Returns:
  1327. * 0 = success
  1328. */
  1329. int
  1330. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1331. {
  1332. struct qla_hw_data *ha = vha->hw;
  1333. if (vha->device_flags & DFLG_DEV_FAILED) {
  1334. ql_dbg(ql_dbg_init, vha, 0x0142,
  1335. "Device in failed state\n");
  1336. return QLA_SUCCESS;
  1337. }
  1338. ha->flags.mr_reset_hdlr_active = 1;
  1339. if (vha->flags.online) {
  1340. scsi_block_requests(vha->host);
  1341. qlafx00_abort_isp_cleanup(vha);
  1342. }
  1343. ql_log(ql_log_info, vha, 0x0143,
  1344. "(%s): succeeded.\n", __func__);
  1345. ha->flags.mr_reset_hdlr_active = 0;
  1346. return QLA_SUCCESS;
  1347. }
  1348. /*
  1349. * qlafx00_abort_isp
  1350. * Resets ISP and aborts all outstanding commands.
  1351. *
  1352. * Input:
  1353. * ha = adapter block pointer.
  1354. *
  1355. * Returns:
  1356. * 0 = success
  1357. */
  1358. int
  1359. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1360. {
  1361. struct qla_hw_data *ha = vha->hw;
  1362. if (vha->flags.online) {
  1363. if (unlikely(pci_channel_offline(ha->pdev) &&
  1364. ha->flags.pci_channel_io_perm_failure)) {
  1365. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1366. return QLA_SUCCESS;
  1367. }
  1368. scsi_block_requests(vha->host);
  1369. qlafx00_abort_isp_cleanup(vha);
  1370. }
  1371. ql_log(ql_log_info, vha, 0x0145,
  1372. "(%s): succeeded.\n", __func__);
  1373. return QLA_SUCCESS;
  1374. }
  1375. static inline fc_port_t*
  1376. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1377. {
  1378. fc_port_t *fcport;
  1379. /* Check for matching device in remote port list. */
  1380. fcport = NULL;
  1381. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1382. if (fcport->tgt_id == tgt_id) {
  1383. ql_dbg(ql_dbg_async, vha, 0x5072,
  1384. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1385. "and Remote TGT_ID: 0x%x\n",
  1386. fcport, fcport->tgt_id, tgt_id);
  1387. break;
  1388. }
  1389. }
  1390. return fcport;
  1391. }
  1392. static void
  1393. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1394. {
  1395. fc_port_t *fcport;
  1396. ql_log(ql_log_info, vha, 0x5073,
  1397. "Detach TGT-ID: 0x%x\n", tgt_id);
  1398. fcport = qlafx00_get_fcport(vha, tgt_id);
  1399. if (!fcport)
  1400. return;
  1401. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1402. return;
  1403. }
  1404. int
  1405. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1406. {
  1407. int rval = 0;
  1408. uint32_t aen_code, aen_data;
  1409. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1410. aen_data = evt->u.aenfx.evtcode;
  1411. switch (evt->u.aenfx.evtcode) {
  1412. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1413. if (evt->u.aenfx.mbx[1] == 0) {
  1414. if (evt->u.aenfx.mbx[2] == 1) {
  1415. if (!vha->flags.fw_tgt_reported)
  1416. vha->flags.fw_tgt_reported = 1;
  1417. atomic_set(&vha->loop_down_timer, 0);
  1418. atomic_set(&vha->loop_state, LOOP_UP);
  1419. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1420. qla2xxx_wake_dpc(vha);
  1421. } else if (evt->u.aenfx.mbx[2] == 2) {
  1422. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1423. }
  1424. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1425. if (evt->u.aenfx.mbx[2] == 1) {
  1426. if (!vha->flags.fw_tgt_reported)
  1427. vha->flags.fw_tgt_reported = 1;
  1428. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1429. } else if (evt->u.aenfx.mbx[2] == 2) {
  1430. vha->device_flags |= DFLG_NO_CABLE;
  1431. qla2x00_mark_all_devices_lost(vha, 1);
  1432. }
  1433. }
  1434. break;
  1435. case QLAFX00_MBA_LINK_UP:
  1436. aen_code = FCH_EVT_LINKUP;
  1437. aen_data = 0;
  1438. break;
  1439. case QLAFX00_MBA_LINK_DOWN:
  1440. aen_code = FCH_EVT_LINKDOWN;
  1441. aen_data = 0;
  1442. break;
  1443. }
  1444. fc_host_post_event(vha->host, fc_get_event_number(),
  1445. aen_code, aen_data);
  1446. return rval;
  1447. }
  1448. static void
  1449. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1450. {
  1451. u64 port_name = 0, node_name = 0;
  1452. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1453. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1454. fc_host_node_name(vha->host) = node_name;
  1455. fc_host_port_name(vha->host) = port_name;
  1456. if (!pinfo->port_type)
  1457. vha->hw->current_topology = ISP_CFG_F;
  1458. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1459. atomic_set(&vha->loop_state, LOOP_READY);
  1460. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1461. atomic_set(&vha->loop_state, LOOP_DOWN);
  1462. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1463. }
  1464. static void
  1465. qla2x00_fxdisc_iocb_timeout(void *data)
  1466. {
  1467. srb_t *sp = (srb_t *)data;
  1468. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1469. complete(&lio->u.fxiocb.fxiocb_comp);
  1470. }
  1471. static void
  1472. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1473. {
  1474. srb_t *sp = (srb_t *)ptr;
  1475. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1476. complete(&lio->u.fxiocb.fxiocb_comp);
  1477. }
  1478. int
  1479. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t fx_type)
  1480. {
  1481. srb_t *sp;
  1482. struct srb_iocb *fdisc;
  1483. int rval = QLA_FUNCTION_FAILED;
  1484. struct qla_hw_data *ha = vha->hw;
  1485. struct host_system_info *phost_info;
  1486. struct register_host_info *preg_hsi;
  1487. struct new_utsname *p_sysid = NULL;
  1488. struct timeval tv;
  1489. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1490. if (!sp)
  1491. goto done;
  1492. fdisc = &sp->u.iocb_cmd;
  1493. switch (fx_type) {
  1494. case FXDISC_GET_CONFIG_INFO:
  1495. fdisc->u.fxiocb.flags =
  1496. SRB_FXDISC_RESP_DMA_VALID;
  1497. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1498. break;
  1499. case FXDISC_GET_PORT_INFO:
  1500. fdisc->u.fxiocb.flags =
  1501. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1502. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1503. fdisc->u.fxiocb.req_data = fcport->port_id;
  1504. break;
  1505. case FXDISC_GET_TGT_NODE_INFO:
  1506. fdisc->u.fxiocb.flags =
  1507. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1508. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1509. fdisc->u.fxiocb.req_data = fcport->tgt_id;
  1510. break;
  1511. case FXDISC_GET_TGT_NODE_LIST:
  1512. fdisc->u.fxiocb.flags =
  1513. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1514. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1515. break;
  1516. case FXDISC_REG_HOST_INFO:
  1517. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1518. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1519. p_sysid = utsname();
  1520. if (!p_sysid) {
  1521. ql_log(ql_log_warn, vha, 0x303c,
  1522. "Not able to get the system informtion\n");
  1523. goto done_free_sp;
  1524. }
  1525. break;
  1526. default:
  1527. break;
  1528. }
  1529. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1530. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1531. fdisc->u.fxiocb.req_len,
  1532. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1533. if (!fdisc->u.fxiocb.req_addr)
  1534. goto done_free_sp;
  1535. if (fx_type == FXDISC_REG_HOST_INFO) {
  1536. preg_hsi = (struct register_host_info *)
  1537. fdisc->u.fxiocb.req_addr;
  1538. phost_info = &preg_hsi->hsi;
  1539. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1540. phost_info->os_type = OS_TYPE_LINUX;
  1541. strncpy(phost_info->sysname,
  1542. p_sysid->sysname, SYSNAME_LENGTH);
  1543. strncpy(phost_info->nodename,
  1544. p_sysid->nodename, NODENAME_LENGTH);
  1545. strncpy(phost_info->release,
  1546. p_sysid->release, RELEASE_LENGTH);
  1547. strncpy(phost_info->version,
  1548. p_sysid->version, VERSION_LENGTH);
  1549. strncpy(phost_info->machine,
  1550. p_sysid->machine, MACHINE_LENGTH);
  1551. strncpy(phost_info->domainname,
  1552. p_sysid->domainname, DOMNAME_LENGTH);
  1553. strncpy(phost_info->hostdriver,
  1554. QLA2XXX_VERSION, VERSION_LENGTH);
  1555. do_gettimeofday(&tv);
  1556. preg_hsi->utc = (uint64_t)tv.tv_sec;
  1557. ql_dbg(ql_dbg_init, vha, 0x0149,
  1558. "ISP%04X: Host registration with firmware\n",
  1559. ha->pdev->device);
  1560. ql_dbg(ql_dbg_init, vha, 0x014a,
  1561. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1562. phost_info->os_type,
  1563. phost_info->sysname,
  1564. phost_info->nodename);
  1565. ql_dbg(ql_dbg_init, vha, 0x014b,
  1566. "release = '%s', version = '%s'\n",
  1567. phost_info->release,
  1568. phost_info->version);
  1569. ql_dbg(ql_dbg_init, vha, 0x014c,
  1570. "machine = '%s' "
  1571. "domainname = '%s', hostdriver = '%s'\n",
  1572. phost_info->machine,
  1573. phost_info->domainname,
  1574. phost_info->hostdriver);
  1575. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1576. (uint8_t *)phost_info,
  1577. sizeof(struct host_system_info));
  1578. }
  1579. }
  1580. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1581. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1582. fdisc->u.fxiocb.rsp_len,
  1583. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1584. if (!fdisc->u.fxiocb.rsp_addr)
  1585. goto done_unmap_req;
  1586. }
  1587. sp->type = SRB_FXIOCB_DCMD;
  1588. sp->name = "fxdisc";
  1589. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1590. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1591. fdisc->u.fxiocb.req_func_type = fx_type;
  1592. sp->done = qla2x00_fxdisc_sp_done;
  1593. rval = qla2x00_start_sp(sp);
  1594. if (rval != QLA_SUCCESS)
  1595. goto done_unmap_dma;
  1596. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1597. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1598. struct config_info_data *pinfo =
  1599. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1600. memcpy(&vha->hw->mr.product_name, pinfo->product_name,
  1601. sizeof(vha->hw->mr.product_name));
  1602. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1603. sizeof(vha->hw->mr.symbolic_name));
  1604. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1605. sizeof(vha->hw->mr.serial_num));
  1606. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1607. sizeof(vha->hw->mr.hw_version));
  1608. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1609. sizeof(vha->hw->mr.fw_version));
  1610. strim(vha->hw->mr.fw_version);
  1611. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1612. sizeof(vha->hw->mr.uboot_version));
  1613. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1614. sizeof(vha->hw->mr.fru_serial_num));
  1615. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1616. struct port_info_data *pinfo =
  1617. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1618. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1619. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1620. vha->d_id.b.domain = pinfo->port_id[0];
  1621. vha->d_id.b.area = pinfo->port_id[1];
  1622. vha->d_id.b.al_pa = pinfo->port_id[2];
  1623. qlafx00_update_host_attr(vha, pinfo);
  1624. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1625. (uint8_t *)pinfo, 16);
  1626. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1627. struct qlafx00_tgt_node_info *pinfo =
  1628. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1629. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1630. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1631. fcport->port_type = FCT_TARGET;
  1632. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1633. (uint8_t *)pinfo, 16);
  1634. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1635. struct qlafx00_tgt_node_info *pinfo =
  1636. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1637. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1638. (uint8_t *)pinfo, 16);
  1639. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1640. }
  1641. rval = fdisc->u.fxiocb.result;
  1642. done_unmap_dma:
  1643. if (fdisc->u.fxiocb.rsp_addr)
  1644. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1645. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1646. done_unmap_req:
  1647. if (fdisc->u.fxiocb.req_addr)
  1648. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1649. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1650. done_free_sp:
  1651. sp->free(vha, sp);
  1652. done:
  1653. return rval;
  1654. }
  1655. static void
  1656. qlafx00_abort_iocb_timeout(void *data)
  1657. {
  1658. srb_t *sp = (srb_t *)data;
  1659. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1660. abt->u.abt.comp_status = CS_TIMEOUT;
  1661. complete(&abt->u.abt.comp);
  1662. }
  1663. static void
  1664. qlafx00_abort_sp_done(void *data, void *ptr, int res)
  1665. {
  1666. srb_t *sp = (srb_t *)ptr;
  1667. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1668. complete(&abt->u.abt.comp);
  1669. }
  1670. static int
  1671. qlafx00_async_abt_cmd(srb_t *cmd_sp)
  1672. {
  1673. scsi_qla_host_t *vha = cmd_sp->fcport->vha;
  1674. fc_port_t *fcport = cmd_sp->fcport;
  1675. struct srb_iocb *abt_iocb;
  1676. srb_t *sp;
  1677. int rval = QLA_FUNCTION_FAILED;
  1678. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1679. if (!sp)
  1680. goto done;
  1681. abt_iocb = &sp->u.iocb_cmd;
  1682. sp->type = SRB_ABT_CMD;
  1683. sp->name = "abort";
  1684. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1685. abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
  1686. sp->done = qlafx00_abort_sp_done;
  1687. abt_iocb->timeout = qlafx00_abort_iocb_timeout;
  1688. init_completion(&abt_iocb->u.abt.comp);
  1689. rval = qla2x00_start_sp(sp);
  1690. if (rval != QLA_SUCCESS)
  1691. goto done_free_sp;
  1692. ql_dbg(ql_dbg_async, vha, 0x507c,
  1693. "Abort command issued - hdl=%x, target_id=%x\n",
  1694. cmd_sp->handle, fcport->tgt_id);
  1695. wait_for_completion(&abt_iocb->u.abt.comp);
  1696. rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
  1697. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  1698. done_free_sp:
  1699. sp->free(vha, sp);
  1700. done:
  1701. return rval;
  1702. }
  1703. int
  1704. qlafx00_abort_command(srb_t *sp)
  1705. {
  1706. unsigned long flags = 0;
  1707. uint32_t handle;
  1708. fc_port_t *fcport = sp->fcport;
  1709. struct scsi_qla_host *vha = fcport->vha;
  1710. struct qla_hw_data *ha = vha->hw;
  1711. struct req_que *req = vha->req;
  1712. spin_lock_irqsave(&ha->hardware_lock, flags);
  1713. for (handle = 1; handle < DEFAULT_OUTSTANDING_COMMANDS; handle++) {
  1714. if (req->outstanding_cmds[handle] == sp)
  1715. break;
  1716. }
  1717. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1718. if (handle == DEFAULT_OUTSTANDING_COMMANDS) {
  1719. /* Command not found. */
  1720. return QLA_FUNCTION_FAILED;
  1721. }
  1722. return qlafx00_async_abt_cmd(sp);
  1723. }
  1724. /*
  1725. * qlafx00_initialize_adapter
  1726. * Initialize board.
  1727. *
  1728. * Input:
  1729. * ha = adapter block pointer.
  1730. *
  1731. * Returns:
  1732. * 0 = success
  1733. */
  1734. int
  1735. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1736. {
  1737. int rval;
  1738. struct qla_hw_data *ha = vha->hw;
  1739. /* Clear adapter flags. */
  1740. vha->flags.online = 0;
  1741. ha->flags.chip_reset_done = 0;
  1742. vha->flags.reset_active = 0;
  1743. ha->flags.pci_channel_io_perm_failure = 0;
  1744. ha->flags.eeh_busy = 0;
  1745. ha->thermal_support = 0;
  1746. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1747. atomic_set(&vha->loop_state, LOOP_DOWN);
  1748. vha->device_flags = DFLG_NO_CABLE;
  1749. vha->dpc_flags = 0;
  1750. vha->flags.management_server_logged_in = 0;
  1751. vha->marker_needed = 0;
  1752. ha->isp_abort_cnt = 0;
  1753. ha->beacon_blink_led = 0;
  1754. set_bit(0, ha->req_qid_map);
  1755. set_bit(0, ha->rsp_qid_map);
  1756. ql_dbg(ql_dbg_init, vha, 0x0147,
  1757. "Configuring PCI space...\n");
  1758. rval = ha->isp_ops->pci_config(vha);
  1759. if (rval) {
  1760. ql_log(ql_log_warn, vha, 0x0148,
  1761. "Unable to configure PCI space.\n");
  1762. return rval;
  1763. }
  1764. rval = qlafx00_init_fw_ready(vha);
  1765. if (rval != QLA_SUCCESS)
  1766. return rval;
  1767. qlafx00_save_queue_ptrs(vha);
  1768. rval = qlafx00_config_queues(vha);
  1769. if (rval != QLA_SUCCESS)
  1770. return rval;
  1771. /*
  1772. * Allocate the array of outstanding commands
  1773. * now that we know the firmware resources.
  1774. */
  1775. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1776. if (rval != QLA_SUCCESS)
  1777. return rval;
  1778. rval = qla2x00_init_rings(vha);
  1779. ha->flags.chip_reset_done = 1;
  1780. return rval;
  1781. }
  1782. uint32_t
  1783. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1784. char *buf)
  1785. {
  1786. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1787. int rval = QLA_FUNCTION_FAILED;
  1788. uint32_t state[1];
  1789. if (qla2x00_reset_active(vha))
  1790. ql_log(ql_log_warn, vha, 0x70ce,
  1791. "ISP reset active.\n");
  1792. else if (!vha->hw->flags.eeh_busy) {
  1793. rval = qlafx00_get_firmware_state(vha, state);
  1794. }
  1795. if (rval != QLA_SUCCESS)
  1796. memset(state, -1, sizeof(state));
  1797. return state[0];
  1798. }
  1799. void
  1800. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1801. {
  1802. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1803. (shost_priv(shost)))->hw;
  1804. u32 speed = FC_PORTSPEED_UNKNOWN;
  1805. switch (ha->link_data_rate) {
  1806. case QLAFX00_PORT_SPEED_2G:
  1807. speed = FC_PORTSPEED_2GBIT;
  1808. break;
  1809. case QLAFX00_PORT_SPEED_4G:
  1810. speed = FC_PORTSPEED_4GBIT;
  1811. break;
  1812. case QLAFX00_PORT_SPEED_8G:
  1813. speed = FC_PORTSPEED_8GBIT;
  1814. break;
  1815. case QLAFX00_PORT_SPEED_10G:
  1816. speed = FC_PORTSPEED_10GBIT;
  1817. break;
  1818. }
  1819. fc_host_speed(shost) = speed;
  1820. }
  1821. /** QLAFX00 specific ISR implementation functions */
  1822. static inline void
  1823. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1824. uint32_t sense_len, struct rsp_que *rsp, int res)
  1825. {
  1826. struct scsi_qla_host *vha = sp->fcport->vha;
  1827. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1828. uint32_t track_sense_len;
  1829. SET_FW_SENSE_LEN(sp, sense_len);
  1830. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1831. sense_len = SCSI_SENSE_BUFFERSIZE;
  1832. SET_CMD_SENSE_LEN(sp, sense_len);
  1833. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1834. track_sense_len = sense_len;
  1835. if (sense_len > par_sense_len)
  1836. sense_len = par_sense_len;
  1837. memcpy(cp->sense_buffer, sense_data, sense_len);
  1838. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1839. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1840. track_sense_len -= sense_len;
  1841. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1842. ql_dbg(ql_dbg_io, vha, 0x304d,
  1843. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1844. sense_len, par_sense_len, track_sense_len);
  1845. if (GET_FW_SENSE_LEN(sp) > 0) {
  1846. rsp->status_srb = sp;
  1847. cp->result = res;
  1848. }
  1849. if (sense_len) {
  1850. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1851. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1852. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1853. cp);
  1854. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1855. cp->sense_buffer, sense_len);
  1856. }
  1857. }
  1858. static void
  1859. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1860. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1861. uint16_t sstatus, uint16_t cpstatus)
  1862. {
  1863. struct srb_iocb *tmf;
  1864. tmf = &sp->u.iocb_cmd;
  1865. if (cpstatus != CS_COMPLETE ||
  1866. (sstatus & SS_RESPONSE_INFO_LEN_VALID))
  1867. cpstatus = CS_INCOMPLETE;
  1868. tmf->u.tmf.comp_status = cpstatus;
  1869. sp->done(vha, sp, 0);
  1870. }
  1871. static void
  1872. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1873. struct abort_iocb_entry_fx00 *pkt)
  1874. {
  1875. const char func[] = "ABT_IOCB";
  1876. srb_t *sp;
  1877. struct srb_iocb *abt;
  1878. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1879. if (!sp)
  1880. return;
  1881. abt = &sp->u.iocb_cmd;
  1882. abt->u.abt.comp_status = le32_to_cpu(pkt->tgt_id_sts);
  1883. sp->done(vha, sp, 0);
  1884. }
  1885. static void
  1886. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1887. struct ioctl_iocb_entry_fx00 *pkt)
  1888. {
  1889. const char func[] = "IOSB_IOCB";
  1890. srb_t *sp;
  1891. struct fc_bsg_job *bsg_job;
  1892. struct srb_iocb *iocb_job;
  1893. int res;
  1894. struct qla_mt_iocb_rsp_fx00 fstatus;
  1895. uint8_t *fw_sts_ptr;
  1896. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1897. if (!sp)
  1898. return;
  1899. if (sp->type == SRB_FXIOCB_DCMD) {
  1900. iocb_job = &sp->u.iocb_cmd;
  1901. iocb_job->u.fxiocb.seq_number = le32_to_cpu(pkt->seq_no);
  1902. iocb_job->u.fxiocb.fw_flags = le32_to_cpu(pkt->fw_iotcl_flags);
  1903. iocb_job->u.fxiocb.result = le32_to_cpu(pkt->status);
  1904. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1905. iocb_job->u.fxiocb.req_data =
  1906. le32_to_cpu(pkt->dataword_r);
  1907. } else {
  1908. bsg_job = sp->u.bsg_job;
  1909. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1910. fstatus.reserved_1 = pkt->reserved_0;
  1911. fstatus.func_type = pkt->comp_func_num;
  1912. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1913. fstatus.ioctl_data = pkt->dataword_r;
  1914. fstatus.adapid = pkt->adapid;
  1915. fstatus.adapid_hi = pkt->adapid_hi;
  1916. fstatus.reserved_2 = pkt->reserved_1;
  1917. fstatus.res_count = pkt->residuallen;
  1918. fstatus.status = pkt->status;
  1919. fstatus.seq_number = pkt->seq_no;
  1920. memcpy(fstatus.reserved_3,
  1921. pkt->reserved_2, 20 * sizeof(uint8_t));
  1922. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  1923. sizeof(struct fc_bsg_reply);
  1924. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  1925. sizeof(struct qla_mt_iocb_rsp_fx00));
  1926. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1927. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1928. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1929. sp->fcport->vha, 0x5080,
  1930. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  1931. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1932. sp->fcport->vha, 0x5074,
  1933. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  1934. res = bsg_job->reply->result = DID_OK << 16;
  1935. bsg_job->reply->reply_payload_rcv_len =
  1936. bsg_job->reply_payload.payload_len;
  1937. }
  1938. sp->done(vha, sp, res);
  1939. }
  1940. /**
  1941. * qlafx00_status_entry() - Process a Status IOCB entry.
  1942. * @ha: SCSI driver HA context
  1943. * @pkt: Entry pointer
  1944. */
  1945. static void
  1946. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1947. {
  1948. srb_t *sp;
  1949. fc_port_t *fcport;
  1950. struct scsi_cmnd *cp;
  1951. struct sts_entry_fx00 *sts;
  1952. uint16_t comp_status;
  1953. uint16_t scsi_status;
  1954. uint16_t ox_id;
  1955. uint8_t lscsi_status;
  1956. int32_t resid;
  1957. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1958. fw_resid_len;
  1959. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1960. struct qla_hw_data *ha = vha->hw;
  1961. uint32_t hindex, handle;
  1962. uint16_t que;
  1963. struct req_que *req;
  1964. int logit = 1;
  1965. int res = 0;
  1966. sts = (struct sts_entry_fx00 *) pkt;
  1967. comp_status = le16_to_cpu(sts->comp_status);
  1968. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1969. hindex = sts->handle;
  1970. handle = LSW(hindex);
  1971. que = MSW(hindex);
  1972. req = ha->req_q_map[que];
  1973. /* Validate handle. */
  1974. if (handle < req->num_outstanding_cmds)
  1975. sp = req->outstanding_cmds[handle];
  1976. else
  1977. sp = NULL;
  1978. if (sp == NULL) {
  1979. ql_dbg(ql_dbg_io, vha, 0x3034,
  1980. "Invalid status handle (0x%x).\n", handle);
  1981. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1982. qla2xxx_wake_dpc(vha);
  1983. return;
  1984. }
  1985. if (sp->type == SRB_TM_CMD) {
  1986. req->outstanding_cmds[handle] = NULL;
  1987. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  1988. scsi_status, comp_status);
  1989. return;
  1990. }
  1991. /* Fast path completion. */
  1992. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1993. qla2x00_do_host_ramp_up(vha);
  1994. qla2x00_process_completed_request(vha, req, handle);
  1995. return;
  1996. }
  1997. req->outstanding_cmds[handle] = NULL;
  1998. cp = GET_CMD_SP(sp);
  1999. if (cp == NULL) {
  2000. ql_dbg(ql_dbg_io, vha, 0x3048,
  2001. "Command already returned (0x%x/%p).\n",
  2002. handle, sp);
  2003. return;
  2004. }
  2005. lscsi_status = scsi_status & STATUS_MASK;
  2006. fcport = sp->fcport;
  2007. ox_id = 0;
  2008. sense_len = par_sense_len = rsp_info_len = resid_len =
  2009. fw_resid_len = 0;
  2010. if (scsi_status & SS_SENSE_LEN_VALID)
  2011. sense_len = le32_to_cpu(sts->sense_len);
  2012. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  2013. resid_len = le32_to_cpu(sts->residual_len);
  2014. if (comp_status == CS_DATA_UNDERRUN)
  2015. fw_resid_len = le32_to_cpu(sts->residual_len);
  2016. rsp_info = sense_data = sts->data;
  2017. par_sense_len = sizeof(sts->data);
  2018. /* Check for overrun. */
  2019. if (comp_status == CS_COMPLETE &&
  2020. scsi_status & SS_RESIDUAL_OVER)
  2021. comp_status = CS_DATA_OVERRUN;
  2022. /*
  2023. * Based on Host and scsi status generate status code for Linux
  2024. */
  2025. switch (comp_status) {
  2026. case CS_COMPLETE:
  2027. case CS_QUEUE_FULL:
  2028. if (scsi_status == 0) {
  2029. res = DID_OK << 16;
  2030. break;
  2031. }
  2032. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  2033. resid = resid_len;
  2034. scsi_set_resid(cp, resid);
  2035. if (!lscsi_status &&
  2036. ((unsigned)(scsi_bufflen(cp) - resid) <
  2037. cp->underflow)) {
  2038. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2039. "Mid-layer underflow "
  2040. "detected (0x%x of 0x%x bytes).\n",
  2041. resid, scsi_bufflen(cp));
  2042. res = DID_ERROR << 16;
  2043. break;
  2044. }
  2045. }
  2046. res = DID_OK << 16 | lscsi_status;
  2047. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  2048. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2049. "QUEUE FULL detected.\n");
  2050. break;
  2051. }
  2052. logit = 0;
  2053. if (lscsi_status != SS_CHECK_CONDITION)
  2054. break;
  2055. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2056. if (!(scsi_status & SS_SENSE_LEN_VALID))
  2057. break;
  2058. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2059. rsp, res);
  2060. break;
  2061. case CS_DATA_UNDERRUN:
  2062. /* Use F/W calculated residual length. */
  2063. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2064. resid = fw_resid_len;
  2065. else
  2066. resid = resid_len;
  2067. scsi_set_resid(cp, resid);
  2068. if (scsi_status & SS_RESIDUAL_UNDER) {
  2069. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2070. && fw_resid_len != resid_len) {
  2071. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2072. "Dropped frame(s) detected "
  2073. "(0x%x of 0x%x bytes).\n",
  2074. resid, scsi_bufflen(cp));
  2075. res = DID_ERROR << 16 | lscsi_status;
  2076. goto check_scsi_status;
  2077. }
  2078. if (!lscsi_status &&
  2079. ((unsigned)(scsi_bufflen(cp) - resid) <
  2080. cp->underflow)) {
  2081. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2082. "Mid-layer underflow "
  2083. "detected (0x%x of 0x%x bytes, "
  2084. "cp->underflow: 0x%x).\n",
  2085. resid, scsi_bufflen(cp), cp->underflow);
  2086. res = DID_ERROR << 16;
  2087. break;
  2088. }
  2089. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  2090. lscsi_status != SAM_STAT_BUSY) {
  2091. /*
  2092. * scsi status of task set and busy are considered
  2093. * to be task not completed.
  2094. */
  2095. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2096. "Dropped frame(s) detected (0x%x "
  2097. "of 0x%x bytes).\n", resid,
  2098. scsi_bufflen(cp));
  2099. res = DID_ERROR << 16 | lscsi_status;
  2100. goto check_scsi_status;
  2101. } else {
  2102. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2103. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2104. scsi_status, lscsi_status);
  2105. }
  2106. res = DID_OK << 16 | lscsi_status;
  2107. logit = 0;
  2108. check_scsi_status:
  2109. /*
  2110. * Check to see if SCSI Status is non zero. If so report SCSI
  2111. * Status.
  2112. */
  2113. if (lscsi_status != 0) {
  2114. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  2115. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2116. "QUEUE FULL detected.\n");
  2117. logit = 1;
  2118. break;
  2119. }
  2120. if (lscsi_status != SS_CHECK_CONDITION)
  2121. break;
  2122. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2123. if (!(scsi_status & SS_SENSE_LEN_VALID))
  2124. break;
  2125. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2126. sense_len, rsp, res);
  2127. }
  2128. break;
  2129. case CS_PORT_LOGGED_OUT:
  2130. case CS_PORT_CONFIG_CHG:
  2131. case CS_PORT_BUSY:
  2132. case CS_INCOMPLETE:
  2133. case CS_PORT_UNAVAILABLE:
  2134. case CS_TIMEOUT:
  2135. case CS_RESET:
  2136. /*
  2137. * We are going to have the fc class block the rport
  2138. * while we try to recover so instruct the mid layer
  2139. * to requeue until the class decides how to handle this.
  2140. */
  2141. res = DID_TRANSPORT_DISRUPTED << 16;
  2142. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2143. "Port down status: port-state=0x%x.\n",
  2144. atomic_read(&fcport->state));
  2145. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2146. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2147. break;
  2148. case CS_ABORTED:
  2149. res = DID_RESET << 16;
  2150. break;
  2151. default:
  2152. res = DID_ERROR << 16;
  2153. break;
  2154. }
  2155. if (logit)
  2156. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2157. "FCP command status: 0x%x-0x%x (0x%x) "
  2158. "nexus=%ld:%d:%d tgt_id: 0x%x lscsi_status: 0x%x"
  2159. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  2160. "rsp_info=0x%x resid=0x%x fw_resid=0x%x "
  2161. "sense_len=0x%x, par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2162. comp_status, scsi_status, res, vha->host_no,
  2163. cp->device->id, cp->device->lun, fcport->tgt_id,
  2164. lscsi_status, cp->cmnd[0], cp->cmnd[1], cp->cmnd[2],
  2165. cp->cmnd[3], cp->cmnd[4], cp->cmnd[5], cp->cmnd[6],
  2166. cp->cmnd[7], cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp),
  2167. rsp_info_len, resid_len, fw_resid_len, sense_len,
  2168. par_sense_len, rsp_info_len);
  2169. if (!res)
  2170. qla2x00_do_host_ramp_up(vha);
  2171. if (rsp->status_srb == NULL)
  2172. sp->done(ha, sp, res);
  2173. }
  2174. /**
  2175. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2176. * @ha: SCSI driver HA context
  2177. * @pkt: Entry pointer
  2178. *
  2179. * Extended sense data.
  2180. */
  2181. static void
  2182. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2183. {
  2184. uint8_t sense_sz = 0;
  2185. struct qla_hw_data *ha = rsp->hw;
  2186. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2187. srb_t *sp = rsp->status_srb;
  2188. struct scsi_cmnd *cp;
  2189. uint32_t sense_len;
  2190. uint8_t *sense_ptr;
  2191. if (!sp) {
  2192. ql_dbg(ql_dbg_io, vha, 0x3037,
  2193. "no SP, sp = %p\n", sp);
  2194. return;
  2195. }
  2196. if (!GET_FW_SENSE_LEN(sp)) {
  2197. ql_dbg(ql_dbg_io, vha, 0x304b,
  2198. "no fw sense data, sp = %p\n", sp);
  2199. return;
  2200. }
  2201. cp = GET_CMD_SP(sp);
  2202. if (cp == NULL) {
  2203. ql_log(ql_log_warn, vha, 0x303b,
  2204. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2205. rsp->status_srb = NULL;
  2206. return;
  2207. }
  2208. if (!GET_CMD_SENSE_LEN(sp)) {
  2209. ql_dbg(ql_dbg_io, vha, 0x304c,
  2210. "no sense data, sp = %p\n", sp);
  2211. } else {
  2212. sense_len = GET_CMD_SENSE_LEN(sp);
  2213. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2214. ql_dbg(ql_dbg_io, vha, 0x304f,
  2215. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2216. sp, sense_len, sense_ptr);
  2217. if (sense_len > sizeof(pkt->data))
  2218. sense_sz = sizeof(pkt->data);
  2219. else
  2220. sense_sz = sense_len;
  2221. /* Move sense data. */
  2222. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2223. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2224. memcpy(sense_ptr, pkt->data, sense_sz);
  2225. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2226. sense_ptr, sense_sz);
  2227. sense_len -= sense_sz;
  2228. sense_ptr += sense_sz;
  2229. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2230. SET_CMD_SENSE_LEN(sp, sense_len);
  2231. }
  2232. sense_len = GET_FW_SENSE_LEN(sp);
  2233. sense_len = (sense_len > sizeof(pkt->data)) ?
  2234. (sense_len - sizeof(pkt->data)) : 0;
  2235. SET_FW_SENSE_LEN(sp, sense_len);
  2236. /* Place command on done queue. */
  2237. if (sense_len == 0) {
  2238. rsp->status_srb = NULL;
  2239. sp->done(ha, sp, cp->result);
  2240. }
  2241. }
  2242. /**
  2243. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2244. * @ha: SCSI driver HA context
  2245. */
  2246. static void
  2247. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2248. struct rsp_que *rsp, void *pkt)
  2249. {
  2250. srb_t *sp;
  2251. struct multi_sts_entry_fx00 *stsmfx;
  2252. struct qla_hw_data *ha = vha->hw;
  2253. uint32_t handle, hindex, handle_count, i;
  2254. uint16_t que;
  2255. struct req_que *req;
  2256. uint32_t *handle_ptr;
  2257. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2258. handle_count = stsmfx->handle_count;
  2259. if (handle_count > MAX_HANDLE_COUNT) {
  2260. ql_dbg(ql_dbg_io, vha, 0x3035,
  2261. "Invalid handle count (0x%x).\n", handle_count);
  2262. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2263. qla2xxx_wake_dpc(vha);
  2264. return;
  2265. }
  2266. handle_ptr = (uint32_t *) &stsmfx->handles[0];
  2267. for (i = 0; i < handle_count; i++) {
  2268. hindex = le32_to_cpu(*handle_ptr);
  2269. handle = LSW(hindex);
  2270. que = MSW(hindex);
  2271. req = ha->req_q_map[que];
  2272. /* Validate handle. */
  2273. if (handle < req->num_outstanding_cmds)
  2274. sp = req->outstanding_cmds[handle];
  2275. else
  2276. sp = NULL;
  2277. if (sp == NULL) {
  2278. ql_dbg(ql_dbg_io, vha, 0x3044,
  2279. "Invalid status handle (0x%x).\n", handle);
  2280. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2281. qla2xxx_wake_dpc(vha);
  2282. return;
  2283. }
  2284. qla2x00_process_completed_request(vha, req, handle);
  2285. handle_ptr++;
  2286. }
  2287. }
  2288. /**
  2289. * qlafx00_error_entry() - Process an error entry.
  2290. * @ha: SCSI driver HA context
  2291. * @pkt: Entry pointer
  2292. */
  2293. static void
  2294. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2295. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2296. {
  2297. srb_t *sp;
  2298. struct qla_hw_data *ha = vha->hw;
  2299. const char func[] = "ERROR-IOCB";
  2300. uint16_t que = MSW(pkt->handle);
  2301. struct req_que *req = NULL;
  2302. int res = DID_ERROR << 16;
  2303. ql_dbg(ql_dbg_async, vha, 0x507f,
  2304. "type of error status in response: 0x%x\n", estatus);
  2305. req = ha->req_q_map[que];
  2306. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2307. if (sp) {
  2308. sp->done(ha, sp, res);
  2309. return;
  2310. }
  2311. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2312. qla2xxx_wake_dpc(vha);
  2313. }
  2314. /**
  2315. * qlafx00_process_response_queue() - Process response queue entries.
  2316. * @ha: SCSI driver HA context
  2317. */
  2318. static void
  2319. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2320. struct rsp_que *rsp)
  2321. {
  2322. struct sts_entry_fx00 *pkt;
  2323. response_t *lptr;
  2324. if (!vha->flags.online)
  2325. return;
  2326. while (RD_REG_DWORD(&(rsp->ring_ptr->signature)) !=
  2327. RESPONSE_PROCESSED) {
  2328. lptr = rsp->ring_ptr;
  2329. memcpy_fromio(rsp->rsp_pkt, lptr, sizeof(rsp->rsp_pkt));
  2330. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2331. rsp->ring_index++;
  2332. if (rsp->ring_index == rsp->length) {
  2333. rsp->ring_index = 0;
  2334. rsp->ring_ptr = rsp->ring;
  2335. } else {
  2336. rsp->ring_ptr++;
  2337. }
  2338. if (pkt->entry_status != 0 &&
  2339. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2340. qlafx00_error_entry(vha, rsp,
  2341. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2342. pkt->entry_type);
  2343. goto next_iter;
  2344. continue;
  2345. }
  2346. switch (pkt->entry_type) {
  2347. case STATUS_TYPE_FX00:
  2348. qlafx00_status_entry(vha, rsp, pkt);
  2349. break;
  2350. case STATUS_CONT_TYPE_FX00:
  2351. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2352. break;
  2353. case MULTI_STATUS_TYPE_FX00:
  2354. qlafx00_multistatus_entry(vha, rsp, pkt);
  2355. break;
  2356. case ABORT_IOCB_TYPE_FX00:
  2357. qlafx00_abort_iocb_entry(vha, rsp->req,
  2358. (struct abort_iocb_entry_fx00 *)pkt);
  2359. break;
  2360. case IOCTL_IOSB_TYPE_FX00:
  2361. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2362. (struct ioctl_iocb_entry_fx00 *)pkt);
  2363. break;
  2364. default:
  2365. /* Type Not Supported. */
  2366. ql_dbg(ql_dbg_async, vha, 0x5081,
  2367. "Received unknown response pkt type %x "
  2368. "entry status=%x.\n",
  2369. pkt->entry_type, pkt->entry_status);
  2370. break;
  2371. }
  2372. next_iter:
  2373. WRT_REG_DWORD(&lptr->signature, RESPONSE_PROCESSED);
  2374. wmb();
  2375. }
  2376. /* Adjust ring index */
  2377. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2378. }
  2379. /**
  2380. * qlafx00_async_event() - Process aynchronous events.
  2381. * @ha: SCSI driver HA context
  2382. */
  2383. static void
  2384. qlafx00_async_event(scsi_qla_host_t *vha)
  2385. {
  2386. struct qla_hw_data *ha = vha->hw;
  2387. struct device_reg_fx00 __iomem *reg;
  2388. int data_size = 1;
  2389. reg = &ha->iobase->ispfx00;
  2390. /* Setup to process RIO completion. */
  2391. switch (ha->aenmb[0]) {
  2392. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2393. ql_log(ql_log_warn, vha, 0x5079,
  2394. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2395. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2396. break;
  2397. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2398. ql_dbg(ql_dbg_async, vha, 0x5076,
  2399. "Asynchronous FW shutdown requested.\n");
  2400. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2401. qla2xxx_wake_dpc(vha);
  2402. break;
  2403. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2404. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2405. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2406. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2407. ql_dbg(ql_dbg_async, vha, 0x5077,
  2408. "Asynchronous port Update received "
  2409. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2410. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2411. data_size = 4;
  2412. break;
  2413. default:
  2414. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2415. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2416. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2417. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2418. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2419. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2420. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2421. ql_dbg(ql_dbg_async, vha, 0x5078,
  2422. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2423. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2424. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2425. break;
  2426. }
  2427. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2428. (uint32_t *)ha->aenmb, data_size);
  2429. }
  2430. /**
  2431. *
  2432. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2433. * @ha: SCSI driver HA context
  2434. * @mb16: Mailbox16 register
  2435. */
  2436. static void
  2437. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2438. {
  2439. uint16_t cnt;
  2440. uint16_t __iomem *wptr;
  2441. struct qla_hw_data *ha = vha->hw;
  2442. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2443. if (!ha->mcp32)
  2444. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2445. /* Load return mailbox registers. */
  2446. ha->flags.mbox_int = 1;
  2447. ha->mailbox_out32[0] = mb0;
  2448. wptr = (uint16_t __iomem *)&reg->mailbox17;
  2449. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2450. ha->mailbox_out32[cnt] = RD_REG_WORD(wptr);
  2451. wptr++;
  2452. }
  2453. }
  2454. /**
  2455. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2456. * @irq:
  2457. * @dev_id: SCSI driver HA context
  2458. *
  2459. * Called by system whenever the host adapter generates an interrupt.
  2460. *
  2461. * Returns handled flag.
  2462. */
  2463. irqreturn_t
  2464. qlafx00_intr_handler(int irq, void *dev_id)
  2465. {
  2466. scsi_qla_host_t *vha;
  2467. struct qla_hw_data *ha;
  2468. struct device_reg_fx00 __iomem *reg;
  2469. int status;
  2470. unsigned long iter;
  2471. uint32_t stat;
  2472. uint32_t mb[8];
  2473. struct rsp_que *rsp;
  2474. unsigned long flags;
  2475. uint32_t clr_intr = 0;
  2476. rsp = (struct rsp_que *) dev_id;
  2477. if (!rsp) {
  2478. ql_log(ql_log_info, NULL, 0x507d,
  2479. "%s: NULL response queue pointer.\n", __func__);
  2480. return IRQ_NONE;
  2481. }
  2482. ha = rsp->hw;
  2483. reg = &ha->iobase->ispfx00;
  2484. status = 0;
  2485. if (unlikely(pci_channel_offline(ha->pdev)))
  2486. return IRQ_HANDLED;
  2487. spin_lock_irqsave(&ha->hardware_lock, flags);
  2488. vha = pci_get_drvdata(ha->pdev);
  2489. for (iter = 50; iter--; clr_intr = 0) {
  2490. stat = QLAFX00_RD_INTR_REG(ha);
  2491. if ((stat & QLAFX00_HST_INT_STS_BITS) == 0)
  2492. break;
  2493. switch (stat & QLAFX00_HST_INT_STS_BITS) {
  2494. case QLAFX00_INTR_MB_CMPLT:
  2495. case QLAFX00_INTR_MB_RSP_CMPLT:
  2496. case QLAFX00_INTR_MB_ASYNC_CMPLT:
  2497. case QLAFX00_INTR_ALL_CMPLT:
  2498. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2499. qlafx00_mbx_completion(vha, mb[0]);
  2500. status |= MBX_INTERRUPT;
  2501. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2502. break;
  2503. case QLAFX00_INTR_ASYNC_CMPLT:
  2504. case QLAFX00_INTR_RSP_ASYNC_CMPLT:
  2505. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2506. qlafx00_async_event(vha);
  2507. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2508. break;
  2509. case QLAFX00_INTR_RSP_CMPLT:
  2510. qlafx00_process_response_queue(vha, rsp);
  2511. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2512. break;
  2513. default:
  2514. ql_dbg(ql_dbg_async, vha, 0x507a,
  2515. "Unrecognized interrupt type (%d).\n", stat);
  2516. break;
  2517. }
  2518. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2519. QLAFX00_RD_INTR_REG(ha);
  2520. }
  2521. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2522. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2523. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2524. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2525. complete(&ha->mbx_intr_comp);
  2526. }
  2527. return IRQ_HANDLED;
  2528. }
  2529. /** QLAFX00 specific IOCB implementation functions */
  2530. static inline cont_a64_entry_t *
  2531. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2532. cont_a64_entry_t *lcont_pkt)
  2533. {
  2534. cont_a64_entry_t *cont_pkt;
  2535. /* Adjust ring index. */
  2536. req->ring_index++;
  2537. if (req->ring_index == req->length) {
  2538. req->ring_index = 0;
  2539. req->ring_ptr = req->ring;
  2540. } else {
  2541. req->ring_ptr++;
  2542. }
  2543. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2544. /* Load packet defaults. */
  2545. *((uint32_t *)(&lcont_pkt->entry_type)) =
  2546. __constant_cpu_to_le32(CONTINUE_A64_TYPE_FX00);
  2547. return cont_pkt;
  2548. }
  2549. static inline void
  2550. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2551. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2552. {
  2553. uint16_t avail_dsds;
  2554. uint32_t *cur_dsd;
  2555. scsi_qla_host_t *vha;
  2556. struct scsi_cmnd *cmd;
  2557. struct scatterlist *sg;
  2558. int i, cont;
  2559. struct req_que *req;
  2560. cont_a64_entry_t lcont_pkt;
  2561. cont_a64_entry_t *cont_pkt;
  2562. vha = sp->fcport->vha;
  2563. req = vha->req;
  2564. cmd = GET_CMD_SP(sp);
  2565. cont = 0;
  2566. cont_pkt = NULL;
  2567. /* Update entry type to indicate Command Type 3 IOCB */
  2568. *((uint32_t *)(&lcmd_pkt->entry_type)) =
  2569. __constant_cpu_to_le32(FX00_COMMAND_TYPE_7);
  2570. /* No data transfer */
  2571. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2572. lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
  2573. return;
  2574. }
  2575. /* Set transfer direction */
  2576. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2577. lcmd_pkt->cntrl_flags =
  2578. __constant_cpu_to_le16(TMF_WRITE_DATA);
  2579. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2580. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2581. lcmd_pkt->cntrl_flags =
  2582. __constant_cpu_to_le16(TMF_READ_DATA);
  2583. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2584. }
  2585. /* One DSD is available in the Command Type 3 IOCB */
  2586. avail_dsds = 1;
  2587. cur_dsd = (uint32_t *)&lcmd_pkt->dseg_0_address;
  2588. /* Load data segments */
  2589. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2590. dma_addr_t sle_dma;
  2591. /* Allocate additional continuation packets? */
  2592. if (avail_dsds == 0) {
  2593. /*
  2594. * Five DSDs are available in the Continuation
  2595. * Type 1 IOCB.
  2596. */
  2597. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2598. cont_pkt =
  2599. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2600. cur_dsd = (uint32_t *)lcont_pkt.dseg_0_address;
  2601. avail_dsds = 5;
  2602. cont = 1;
  2603. }
  2604. sle_dma = sg_dma_address(sg);
  2605. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2606. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2607. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2608. avail_dsds--;
  2609. if (avail_dsds == 0 && cont == 1) {
  2610. cont = 0;
  2611. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2612. REQUEST_ENTRY_SIZE);
  2613. }
  2614. }
  2615. if (avail_dsds != 0 && cont == 1) {
  2616. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2617. REQUEST_ENTRY_SIZE);
  2618. }
  2619. }
  2620. /**
  2621. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2622. * @sp: command to send to the ISP
  2623. *
  2624. * Returns non-zero if a failure occurred, else zero.
  2625. */
  2626. int
  2627. qlafx00_start_scsi(srb_t *sp)
  2628. {
  2629. int ret, nseg;
  2630. unsigned long flags;
  2631. uint32_t index;
  2632. uint32_t handle;
  2633. uint16_t cnt;
  2634. uint16_t req_cnt;
  2635. uint16_t tot_dsds;
  2636. struct req_que *req = NULL;
  2637. struct rsp_que *rsp = NULL;
  2638. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2639. struct scsi_qla_host *vha = sp->fcport->vha;
  2640. struct qla_hw_data *ha = vha->hw;
  2641. struct cmd_type_7_fx00 *cmd_pkt;
  2642. struct cmd_type_7_fx00 lcmd_pkt;
  2643. struct scsi_lun llun;
  2644. char tag[2];
  2645. /* Setup device pointers. */
  2646. ret = 0;
  2647. rsp = ha->rsp_q_map[0];
  2648. req = vha->req;
  2649. /* So we know we haven't pci_map'ed anything yet */
  2650. tot_dsds = 0;
  2651. /* Forcing marker needed for now */
  2652. vha->marker_needed = 0;
  2653. /* Send marker if required */
  2654. if (vha->marker_needed != 0) {
  2655. if (qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL) !=
  2656. QLA_SUCCESS)
  2657. return QLA_FUNCTION_FAILED;
  2658. vha->marker_needed = 0;
  2659. }
  2660. /* Acquire ring specific lock */
  2661. spin_lock_irqsave(&ha->hardware_lock, flags);
  2662. /* Check for room in outstanding command list. */
  2663. handle = req->current_outstanding_cmd;
  2664. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2665. handle++;
  2666. if (handle == req->num_outstanding_cmds)
  2667. handle = 1;
  2668. if (!req->outstanding_cmds[handle])
  2669. break;
  2670. }
  2671. if (index == req->num_outstanding_cmds)
  2672. goto queuing_error;
  2673. /* Map the sg table so we have an accurate count of sg entries needed */
  2674. if (scsi_sg_count(cmd)) {
  2675. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2676. scsi_sg_count(cmd), cmd->sc_data_direction);
  2677. if (unlikely(!nseg))
  2678. goto queuing_error;
  2679. } else
  2680. nseg = 0;
  2681. tot_dsds = nseg;
  2682. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2683. if (req->cnt < (req_cnt + 2)) {
  2684. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2685. if (req->ring_index < cnt)
  2686. req->cnt = cnt - req->ring_index;
  2687. else
  2688. req->cnt = req->length -
  2689. (req->ring_index - cnt);
  2690. if (req->cnt < (req_cnt + 2))
  2691. goto queuing_error;
  2692. }
  2693. /* Build command packet. */
  2694. req->current_outstanding_cmd = handle;
  2695. req->outstanding_cmds[handle] = sp;
  2696. sp->handle = handle;
  2697. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2698. req->cnt -= req_cnt;
  2699. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2700. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2701. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2702. lcmd_pkt.handle_hi = 0;
  2703. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2704. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2705. int_to_scsilun(cmd->device->lun, &llun);
  2706. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2707. sizeof(lcmd_pkt.lun));
  2708. /* Update tagged queuing modifier -- default is TSK_SIMPLE (0). */
  2709. if (scsi_populate_tag_msg(cmd, tag)) {
  2710. switch (tag[0]) {
  2711. case HEAD_OF_QUEUE_TAG:
  2712. lcmd_pkt.task = TSK_HEAD_OF_QUEUE;
  2713. break;
  2714. case ORDERED_QUEUE_TAG:
  2715. lcmd_pkt.task = TSK_ORDERED;
  2716. break;
  2717. }
  2718. }
  2719. /* Load SCSI command packet. */
  2720. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2721. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2722. /* Build IOCB segments */
  2723. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2724. /* Set total data segment count. */
  2725. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2726. /* Specify response queue number where completion should happen */
  2727. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2728. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2729. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2730. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2731. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2732. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2733. wmb();
  2734. /* Adjust ring index. */
  2735. req->ring_index++;
  2736. if (req->ring_index == req->length) {
  2737. req->ring_index = 0;
  2738. req->ring_ptr = req->ring;
  2739. } else
  2740. req->ring_ptr++;
  2741. sp->flags |= SRB_DMA_VALID;
  2742. /* Set chip new ring index. */
  2743. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2744. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2745. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2746. return QLA_SUCCESS;
  2747. queuing_error:
  2748. if (tot_dsds)
  2749. scsi_dma_unmap(cmd);
  2750. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2751. return QLA_FUNCTION_FAILED;
  2752. }
  2753. void
  2754. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2755. {
  2756. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2757. scsi_qla_host_t *vha = sp->fcport->vha;
  2758. struct req_que *req = vha->req;
  2759. struct tsk_mgmt_entry_fx00 tm_iocb;
  2760. struct scsi_lun llun;
  2761. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2762. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2763. tm_iocb.entry_count = 1;
  2764. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2765. tm_iocb.handle_hi = 0;
  2766. tm_iocb.timeout = cpu_to_le16(qla2x00_get_async_timeout(vha) + 2);
  2767. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2768. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2769. if (tm_iocb.control_flags == TCF_LUN_RESET) {
  2770. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2771. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2772. sizeof(struct scsi_lun));
  2773. }
  2774. memcpy((void __iomem *)ptm_iocb, &tm_iocb,
  2775. sizeof(struct tsk_mgmt_entry_fx00));
  2776. wmb();
  2777. }
  2778. void
  2779. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2780. {
  2781. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2782. scsi_qla_host_t *vha = sp->fcport->vha;
  2783. struct req_que *req = vha->req;
  2784. struct abort_iocb_entry_fx00 abt_iocb;
  2785. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2786. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2787. abt_iocb.entry_count = 1;
  2788. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2789. abt_iocb.abort_handle =
  2790. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2791. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2792. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2793. memcpy((void __iomem *)pabt_iocb, &abt_iocb,
  2794. sizeof(struct abort_iocb_entry_fx00));
  2795. wmb();
  2796. }
  2797. void
  2798. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2799. {
  2800. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2801. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2802. struct fc_bsg_job *bsg_job;
  2803. struct fxdisc_entry_fx00 fx_iocb;
  2804. uint8_t entry_cnt = 1;
  2805. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2806. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2807. fx_iocb.handle = cpu_to_le32(sp->handle);
  2808. fx_iocb.entry_count = entry_cnt;
  2809. if (sp->type == SRB_FXIOCB_DCMD) {
  2810. fx_iocb.func_num =
  2811. cpu_to_le16(sp->u.iocb_cmd.u.fxiocb.req_func_type);
  2812. fx_iocb.adapid = cpu_to_le32(fxio->u.fxiocb.adapter_id);
  2813. fx_iocb.adapid_hi = cpu_to_le32(fxio->u.fxiocb.adapter_id_hi);
  2814. fx_iocb.reserved_0 = cpu_to_le32(fxio->u.fxiocb.reserved_0);
  2815. fx_iocb.reserved_1 = cpu_to_le32(fxio->u.fxiocb.reserved_1);
  2816. fx_iocb.dataword_extra =
  2817. cpu_to_le32(fxio->u.fxiocb.req_data_extra);
  2818. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2819. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2820. fx_iocb.req_xfrcnt =
  2821. cpu_to_le16(fxio->u.fxiocb.req_len);
  2822. fx_iocb.dseg_rq_address[0] =
  2823. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2824. fx_iocb.dseg_rq_address[1] =
  2825. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2826. fx_iocb.dseg_rq_len =
  2827. cpu_to_le32(fxio->u.fxiocb.req_len);
  2828. }
  2829. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2830. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2831. fx_iocb.rsp_xfrcnt =
  2832. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2833. fx_iocb.dseg_rsp_address[0] =
  2834. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2835. fx_iocb.dseg_rsp_address[1] =
  2836. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2837. fx_iocb.dseg_rsp_len =
  2838. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2839. }
  2840. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2841. fx_iocb.dataword =
  2842. cpu_to_le32(fxio->u.fxiocb.req_data);
  2843. }
  2844. fx_iocb.flags = fxio->u.fxiocb.flags;
  2845. } else {
  2846. struct scatterlist *sg;
  2847. bsg_job = sp->u.bsg_job;
  2848. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2849. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2850. fx_iocb.func_num = piocb_rqst->func_type;
  2851. fx_iocb.adapid = piocb_rqst->adapid;
  2852. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2853. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2854. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2855. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2856. fx_iocb.dataword = piocb_rqst->dataword;
  2857. fx_iocb.req_xfrcnt = cpu_to_le16(piocb_rqst->req_len);
  2858. fx_iocb.rsp_xfrcnt = cpu_to_le16(piocb_rqst->rsp_len);
  2859. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2860. int avail_dsds, tot_dsds;
  2861. cont_a64_entry_t lcont_pkt;
  2862. cont_a64_entry_t *cont_pkt = NULL;
  2863. uint32_t *cur_dsd;
  2864. int index = 0, cont = 0;
  2865. fx_iocb.req_dsdcnt =
  2866. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2867. tot_dsds =
  2868. cpu_to_le32(bsg_job->request_payload.sg_cnt);
  2869. cur_dsd = (uint32_t *)&fx_iocb.dseg_rq_address[0];
  2870. avail_dsds = 1;
  2871. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2872. tot_dsds, index) {
  2873. dma_addr_t sle_dma;
  2874. /* Allocate additional continuation packets? */
  2875. if (avail_dsds == 0) {
  2876. /*
  2877. * Five DSDs are available in the Cont.
  2878. * Type 1 IOCB.
  2879. */
  2880. memset(&lcont_pkt, 0,
  2881. REQUEST_ENTRY_SIZE);
  2882. cont_pkt =
  2883. qlafx00_prep_cont_type1_iocb(
  2884. sp->fcport->vha->req,
  2885. &lcont_pkt);
  2886. cur_dsd = (uint32_t *)
  2887. lcont_pkt.dseg_0_address;
  2888. avail_dsds = 5;
  2889. cont = 1;
  2890. entry_cnt++;
  2891. }
  2892. sle_dma = sg_dma_address(sg);
  2893. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2894. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2895. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2896. avail_dsds--;
  2897. if (avail_dsds == 0 && cont == 1) {
  2898. cont = 0;
  2899. memcpy_toio(
  2900. (void __iomem *)cont_pkt,
  2901. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2902. ql_dump_buffer(
  2903. ql_dbg_user + ql_dbg_verbose,
  2904. sp->fcport->vha, 0x3042,
  2905. (uint8_t *)&lcont_pkt,
  2906. REQUEST_ENTRY_SIZE);
  2907. }
  2908. }
  2909. if (avail_dsds != 0 && cont == 1) {
  2910. memcpy_toio((void __iomem *)cont_pkt,
  2911. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2912. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2913. sp->fcport->vha, 0x3043,
  2914. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2915. }
  2916. }
  2917. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2918. int avail_dsds, tot_dsds;
  2919. cont_a64_entry_t lcont_pkt;
  2920. cont_a64_entry_t *cont_pkt = NULL;
  2921. uint32_t *cur_dsd;
  2922. int index = 0, cont = 0;
  2923. fx_iocb.rsp_dsdcnt =
  2924. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2925. tot_dsds = cpu_to_le32(bsg_job->reply_payload.sg_cnt);
  2926. cur_dsd = (uint32_t *)&fx_iocb.dseg_rsp_address[0];
  2927. avail_dsds = 1;
  2928. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2929. tot_dsds, index) {
  2930. dma_addr_t sle_dma;
  2931. /* Allocate additional continuation packets? */
  2932. if (avail_dsds == 0) {
  2933. /*
  2934. * Five DSDs are available in the Cont.
  2935. * Type 1 IOCB.
  2936. */
  2937. memset(&lcont_pkt, 0,
  2938. REQUEST_ENTRY_SIZE);
  2939. cont_pkt =
  2940. qlafx00_prep_cont_type1_iocb(
  2941. sp->fcport->vha->req,
  2942. &lcont_pkt);
  2943. cur_dsd = (uint32_t *)
  2944. lcont_pkt.dseg_0_address;
  2945. avail_dsds = 5;
  2946. cont = 1;
  2947. entry_cnt++;
  2948. }
  2949. sle_dma = sg_dma_address(sg);
  2950. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2951. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2952. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2953. avail_dsds--;
  2954. if (avail_dsds == 0 && cont == 1) {
  2955. cont = 0;
  2956. memcpy_toio((void __iomem *)cont_pkt,
  2957. &lcont_pkt,
  2958. REQUEST_ENTRY_SIZE);
  2959. ql_dump_buffer(
  2960. ql_dbg_user + ql_dbg_verbose,
  2961. sp->fcport->vha, 0x3045,
  2962. (uint8_t *)&lcont_pkt,
  2963. REQUEST_ENTRY_SIZE);
  2964. }
  2965. }
  2966. if (avail_dsds != 0 && cont == 1) {
  2967. memcpy_toio((void __iomem *)cont_pkt,
  2968. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2969. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2970. sp->fcport->vha, 0x3046,
  2971. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2972. }
  2973. }
  2974. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  2975. fx_iocb.dataword = cpu_to_le32(piocb_rqst->dataword);
  2976. fx_iocb.flags = piocb_rqst->flags;
  2977. fx_iocb.entry_count = entry_cnt;
  2978. }
  2979. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2980. sp->fcport->vha, 0x3047,
  2981. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  2982. memcpy((void __iomem *)pfxiocb, &fx_iocb,
  2983. sizeof(struct fxdisc_entry_fx00));
  2984. wmb();
  2985. }