resource_tracker.c 108 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct vlan_res {
  54. struct list_head list;
  55. u16 vlan;
  56. int ref_count;
  57. int vlan_index;
  58. u8 port;
  59. };
  60. struct res_common {
  61. struct list_head list;
  62. struct rb_node node;
  63. u64 res_id;
  64. int owner;
  65. int state;
  66. int from_state;
  67. int to_state;
  68. int removing;
  69. };
  70. enum {
  71. RES_ANY_BUSY = 1
  72. };
  73. struct res_gid {
  74. struct list_head list;
  75. u8 gid[16];
  76. enum mlx4_protocol prot;
  77. enum mlx4_steer_type steer;
  78. u64 reg_id;
  79. };
  80. enum res_qp_states {
  81. RES_QP_BUSY = RES_ANY_BUSY,
  82. /* QP number was allocated */
  83. RES_QP_RESERVED,
  84. /* ICM memory for QP context was mapped */
  85. RES_QP_MAPPED,
  86. /* QP is in hw ownership */
  87. RES_QP_HW
  88. };
  89. struct res_qp {
  90. struct res_common com;
  91. struct res_mtt *mtt;
  92. struct res_cq *rcq;
  93. struct res_cq *scq;
  94. struct res_srq *srq;
  95. struct list_head mcg_list;
  96. spinlock_t mcg_spl;
  97. int local_qpn;
  98. atomic_t ref_count;
  99. u32 qpc_flags;
  100. u8 sched_queue;
  101. };
  102. enum res_mtt_states {
  103. RES_MTT_BUSY = RES_ANY_BUSY,
  104. RES_MTT_ALLOCATED,
  105. };
  106. static inline const char *mtt_states_str(enum res_mtt_states state)
  107. {
  108. switch (state) {
  109. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  110. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  111. default: return "Unknown";
  112. }
  113. }
  114. struct res_mtt {
  115. struct res_common com;
  116. int order;
  117. atomic_t ref_count;
  118. };
  119. enum res_mpt_states {
  120. RES_MPT_BUSY = RES_ANY_BUSY,
  121. RES_MPT_RESERVED,
  122. RES_MPT_MAPPED,
  123. RES_MPT_HW,
  124. };
  125. struct res_mpt {
  126. struct res_common com;
  127. struct res_mtt *mtt;
  128. int key;
  129. };
  130. enum res_eq_states {
  131. RES_EQ_BUSY = RES_ANY_BUSY,
  132. RES_EQ_RESERVED,
  133. RES_EQ_HW,
  134. };
  135. struct res_eq {
  136. struct res_common com;
  137. struct res_mtt *mtt;
  138. };
  139. enum res_cq_states {
  140. RES_CQ_BUSY = RES_ANY_BUSY,
  141. RES_CQ_ALLOCATED,
  142. RES_CQ_HW,
  143. };
  144. struct res_cq {
  145. struct res_common com;
  146. struct res_mtt *mtt;
  147. atomic_t ref_count;
  148. };
  149. enum res_srq_states {
  150. RES_SRQ_BUSY = RES_ANY_BUSY,
  151. RES_SRQ_ALLOCATED,
  152. RES_SRQ_HW,
  153. };
  154. struct res_srq {
  155. struct res_common com;
  156. struct res_mtt *mtt;
  157. struct res_cq *cq;
  158. atomic_t ref_count;
  159. };
  160. enum res_counter_states {
  161. RES_COUNTER_BUSY = RES_ANY_BUSY,
  162. RES_COUNTER_ALLOCATED,
  163. };
  164. struct res_counter {
  165. struct res_common com;
  166. int port;
  167. };
  168. enum res_xrcdn_states {
  169. RES_XRCD_BUSY = RES_ANY_BUSY,
  170. RES_XRCD_ALLOCATED,
  171. };
  172. struct res_xrcdn {
  173. struct res_common com;
  174. int port;
  175. };
  176. enum res_fs_rule_states {
  177. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  178. RES_FS_RULE_ALLOCATED,
  179. };
  180. struct res_fs_rule {
  181. struct res_common com;
  182. int qpn;
  183. };
  184. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  185. {
  186. struct rb_node *node = root->rb_node;
  187. while (node) {
  188. struct res_common *res = container_of(node, struct res_common,
  189. node);
  190. if (res_id < res->res_id)
  191. node = node->rb_left;
  192. else if (res_id > res->res_id)
  193. node = node->rb_right;
  194. else
  195. return res;
  196. }
  197. return NULL;
  198. }
  199. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  200. {
  201. struct rb_node **new = &(root->rb_node), *parent = NULL;
  202. /* Figure out where to put new node */
  203. while (*new) {
  204. struct res_common *this = container_of(*new, struct res_common,
  205. node);
  206. parent = *new;
  207. if (res->res_id < this->res_id)
  208. new = &((*new)->rb_left);
  209. else if (res->res_id > this->res_id)
  210. new = &((*new)->rb_right);
  211. else
  212. return -EEXIST;
  213. }
  214. /* Add new node and rebalance tree. */
  215. rb_link_node(&res->node, parent, new);
  216. rb_insert_color(&res->node, root);
  217. return 0;
  218. }
  219. enum qp_transition {
  220. QP_TRANS_INIT2RTR,
  221. QP_TRANS_RTR2RTS,
  222. QP_TRANS_RTS2RTS,
  223. QP_TRANS_SQERR2RTS,
  224. QP_TRANS_SQD2SQD,
  225. QP_TRANS_SQD2RTS
  226. };
  227. /* For Debug uses */
  228. static const char *ResourceType(enum mlx4_resource rt)
  229. {
  230. switch (rt) {
  231. case RES_QP: return "RES_QP";
  232. case RES_CQ: return "RES_CQ";
  233. case RES_SRQ: return "RES_SRQ";
  234. case RES_MPT: return "RES_MPT";
  235. case RES_MTT: return "RES_MTT";
  236. case RES_MAC: return "RES_MAC";
  237. case RES_VLAN: return "RES_VLAN";
  238. case RES_EQ: return "RES_EQ";
  239. case RES_COUNTER: return "RES_COUNTER";
  240. case RES_FS_RULE: return "RES_FS_RULE";
  241. case RES_XRCD: return "RES_XRCD";
  242. default: return "Unknown resource type !!!";
  243. };
  244. }
  245. static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
  246. static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
  247. enum mlx4_resource res_type, int count,
  248. int port)
  249. {
  250. struct mlx4_priv *priv = mlx4_priv(dev);
  251. struct resource_allocator *res_alloc =
  252. &priv->mfunc.master.res_tracker.res_alloc[res_type];
  253. int err = -EINVAL;
  254. int allocated, free, reserved, guaranteed, from_free;
  255. if (slave > dev->num_vfs)
  256. return -EINVAL;
  257. spin_lock(&res_alloc->alloc_lock);
  258. allocated = (port > 0) ?
  259. res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] :
  260. res_alloc->allocated[slave];
  261. free = (port > 0) ? res_alloc->res_port_free[port - 1] :
  262. res_alloc->res_free;
  263. reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
  264. res_alloc->res_reserved;
  265. guaranteed = res_alloc->guaranteed[slave];
  266. if (allocated + count > res_alloc->quota[slave])
  267. goto out;
  268. if (allocated + count <= guaranteed) {
  269. err = 0;
  270. } else {
  271. /* portion may need to be obtained from free area */
  272. if (guaranteed - allocated > 0)
  273. from_free = count - (guaranteed - allocated);
  274. else
  275. from_free = count;
  276. if (free - from_free > reserved)
  277. err = 0;
  278. }
  279. if (!err) {
  280. /* grant the request */
  281. if (port > 0) {
  282. res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] += count;
  283. res_alloc->res_port_free[port - 1] -= count;
  284. } else {
  285. res_alloc->allocated[slave] += count;
  286. res_alloc->res_free -= count;
  287. }
  288. }
  289. out:
  290. spin_unlock(&res_alloc->alloc_lock);
  291. return err;
  292. }
  293. static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
  294. enum mlx4_resource res_type, int count,
  295. int port)
  296. {
  297. struct mlx4_priv *priv = mlx4_priv(dev);
  298. struct resource_allocator *res_alloc =
  299. &priv->mfunc.master.res_tracker.res_alloc[res_type];
  300. if (slave > dev->num_vfs)
  301. return;
  302. spin_lock(&res_alloc->alloc_lock);
  303. if (port > 0) {
  304. res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] -= count;
  305. res_alloc->res_port_free[port - 1] += count;
  306. } else {
  307. res_alloc->allocated[slave] -= count;
  308. res_alloc->res_free += count;
  309. }
  310. spin_unlock(&res_alloc->alloc_lock);
  311. return;
  312. }
  313. static inline void initialize_res_quotas(struct mlx4_dev *dev,
  314. struct resource_allocator *res_alloc,
  315. enum mlx4_resource res_type,
  316. int vf, int num_instances)
  317. {
  318. res_alloc->guaranteed[vf] = num_instances / (2 * (dev->num_vfs + 1));
  319. res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
  320. if (vf == mlx4_master_func_num(dev)) {
  321. res_alloc->res_free = num_instances;
  322. if (res_type == RES_MTT) {
  323. /* reserved mtts will be taken out of the PF allocation */
  324. res_alloc->res_free += dev->caps.reserved_mtts;
  325. res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
  326. res_alloc->quota[vf] += dev->caps.reserved_mtts;
  327. }
  328. }
  329. }
  330. void mlx4_init_quotas(struct mlx4_dev *dev)
  331. {
  332. struct mlx4_priv *priv = mlx4_priv(dev);
  333. int pf;
  334. /* quotas for VFs are initialized in mlx4_slave_cap */
  335. if (mlx4_is_slave(dev))
  336. return;
  337. if (!mlx4_is_mfunc(dev)) {
  338. dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
  339. mlx4_num_reserved_sqps(dev);
  340. dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
  341. dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
  342. dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
  343. dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
  344. return;
  345. }
  346. pf = mlx4_master_func_num(dev);
  347. dev->quotas.qp =
  348. priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
  349. dev->quotas.cq =
  350. priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
  351. dev->quotas.srq =
  352. priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
  353. dev->quotas.mtt =
  354. priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
  355. dev->quotas.mpt =
  356. priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
  357. }
  358. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  359. {
  360. struct mlx4_priv *priv = mlx4_priv(dev);
  361. int i, j;
  362. int t;
  363. priv->mfunc.master.res_tracker.slave_list =
  364. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  365. GFP_KERNEL);
  366. if (!priv->mfunc.master.res_tracker.slave_list)
  367. return -ENOMEM;
  368. for (i = 0 ; i < dev->num_slaves; i++) {
  369. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  370. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  371. slave_list[i].res_list[t]);
  372. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  373. }
  374. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  375. dev->num_slaves);
  376. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  377. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  378. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  379. struct resource_allocator *res_alloc =
  380. &priv->mfunc.master.res_tracker.res_alloc[i];
  381. res_alloc->quota = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  382. res_alloc->guaranteed = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  383. if (i == RES_MAC || i == RES_VLAN)
  384. res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
  385. (dev->num_vfs + 1) * sizeof(int),
  386. GFP_KERNEL);
  387. else
  388. res_alloc->allocated = kzalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  389. if (!res_alloc->quota || !res_alloc->guaranteed ||
  390. !res_alloc->allocated)
  391. goto no_mem_err;
  392. spin_lock_init(&res_alloc->alloc_lock);
  393. for (t = 0; t < dev->num_vfs + 1; t++) {
  394. switch (i) {
  395. case RES_QP:
  396. initialize_res_quotas(dev, res_alloc, RES_QP,
  397. t, dev->caps.num_qps -
  398. dev->caps.reserved_qps -
  399. mlx4_num_reserved_sqps(dev));
  400. break;
  401. case RES_CQ:
  402. initialize_res_quotas(dev, res_alloc, RES_CQ,
  403. t, dev->caps.num_cqs -
  404. dev->caps.reserved_cqs);
  405. break;
  406. case RES_SRQ:
  407. initialize_res_quotas(dev, res_alloc, RES_SRQ,
  408. t, dev->caps.num_srqs -
  409. dev->caps.reserved_srqs);
  410. break;
  411. case RES_MPT:
  412. initialize_res_quotas(dev, res_alloc, RES_MPT,
  413. t, dev->caps.num_mpts -
  414. dev->caps.reserved_mrws);
  415. break;
  416. case RES_MTT:
  417. initialize_res_quotas(dev, res_alloc, RES_MTT,
  418. t, dev->caps.num_mtts -
  419. dev->caps.reserved_mtts);
  420. break;
  421. case RES_MAC:
  422. if (t == mlx4_master_func_num(dev)) {
  423. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  424. res_alloc->guaranteed[t] = 2;
  425. for (j = 0; j < MLX4_MAX_PORTS; j++)
  426. res_alloc->res_port_free[j] = MLX4_MAX_MAC_NUM;
  427. } else {
  428. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  429. res_alloc->guaranteed[t] = 2;
  430. }
  431. break;
  432. case RES_VLAN:
  433. if (t == mlx4_master_func_num(dev)) {
  434. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
  435. res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
  436. for (j = 0; j < MLX4_MAX_PORTS; j++)
  437. res_alloc->res_port_free[j] =
  438. res_alloc->quota[t];
  439. } else {
  440. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
  441. res_alloc->guaranteed[t] = 0;
  442. }
  443. break;
  444. case RES_COUNTER:
  445. res_alloc->quota[t] = dev->caps.max_counters;
  446. res_alloc->guaranteed[t] = 0;
  447. if (t == mlx4_master_func_num(dev))
  448. res_alloc->res_free = res_alloc->quota[t];
  449. break;
  450. default:
  451. break;
  452. }
  453. if (i == RES_MAC || i == RES_VLAN) {
  454. for (j = 0; j < MLX4_MAX_PORTS; j++)
  455. res_alloc->res_port_rsvd[j] +=
  456. res_alloc->guaranteed[t];
  457. } else {
  458. res_alloc->res_reserved += res_alloc->guaranteed[t];
  459. }
  460. }
  461. }
  462. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  463. return 0;
  464. no_mem_err:
  465. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  466. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  467. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  468. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  469. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  470. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  471. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  472. }
  473. return -ENOMEM;
  474. }
  475. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  476. enum mlx4_res_tracker_free_type type)
  477. {
  478. struct mlx4_priv *priv = mlx4_priv(dev);
  479. int i;
  480. if (priv->mfunc.master.res_tracker.slave_list) {
  481. if (type != RES_TR_FREE_STRUCTS_ONLY) {
  482. for (i = 0; i < dev->num_slaves; i++) {
  483. if (type == RES_TR_FREE_ALL ||
  484. dev->caps.function != i)
  485. mlx4_delete_all_resources_for_slave(dev, i);
  486. }
  487. /* free master's vlans */
  488. i = dev->caps.function;
  489. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  490. rem_slave_vlans(dev, i);
  491. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  492. }
  493. if (type != RES_TR_FREE_SLAVES_ONLY) {
  494. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  495. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  496. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  497. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  498. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  499. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  500. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  501. }
  502. kfree(priv->mfunc.master.res_tracker.slave_list);
  503. priv->mfunc.master.res_tracker.slave_list = NULL;
  504. }
  505. }
  506. }
  507. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  508. struct mlx4_cmd_mailbox *inbox)
  509. {
  510. u8 sched = *(u8 *)(inbox->buf + 64);
  511. u8 orig_index = *(u8 *)(inbox->buf + 35);
  512. u8 new_index;
  513. struct mlx4_priv *priv = mlx4_priv(dev);
  514. int port;
  515. port = (sched >> 6 & 1) + 1;
  516. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  517. *(u8 *)(inbox->buf + 35) = new_index;
  518. }
  519. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  520. u8 slave)
  521. {
  522. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  523. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  524. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  525. if (MLX4_QP_ST_UD == ts)
  526. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  527. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  528. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  529. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  530. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  531. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  532. }
  533. }
  534. static int update_vport_qp_param(struct mlx4_dev *dev,
  535. struct mlx4_cmd_mailbox *inbox,
  536. u8 slave, u32 qpn)
  537. {
  538. struct mlx4_qp_context *qpc = inbox->buf + 8;
  539. struct mlx4_vport_oper_state *vp_oper;
  540. struct mlx4_priv *priv;
  541. u32 qp_type;
  542. int port;
  543. port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
  544. priv = mlx4_priv(dev);
  545. vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
  546. if (MLX4_VGT != vp_oper->state.default_vlan) {
  547. qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  548. if (MLX4_QP_ST_RC == qp_type ||
  549. (MLX4_QP_ST_UD == qp_type &&
  550. !mlx4_is_qp_reserved(dev, qpn)))
  551. return -EINVAL;
  552. /* the reserved QPs (special, proxy, tunnel)
  553. * do not operate over vlans
  554. */
  555. if (mlx4_is_qp_reserved(dev, qpn))
  556. return 0;
  557. /* force strip vlan by clear vsd */
  558. qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
  559. if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
  560. dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
  561. qpc->pri_path.vlan_control =
  562. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  563. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  564. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  565. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  566. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  567. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  568. } else if (0 != vp_oper->state.default_vlan) {
  569. qpc->pri_path.vlan_control =
  570. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  571. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  572. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  573. } else { /* priority tagged */
  574. qpc->pri_path.vlan_control =
  575. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  576. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  577. }
  578. qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
  579. qpc->pri_path.vlan_index = vp_oper->vlan_idx;
  580. qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
  581. qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  582. qpc->pri_path.sched_queue &= 0xC7;
  583. qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
  584. }
  585. if (vp_oper->state.spoofchk) {
  586. qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
  587. qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
  588. }
  589. return 0;
  590. }
  591. static int mpt_mask(struct mlx4_dev *dev)
  592. {
  593. return dev->caps.num_mpts - 1;
  594. }
  595. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  596. enum mlx4_resource type)
  597. {
  598. struct mlx4_priv *priv = mlx4_priv(dev);
  599. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  600. res_id);
  601. }
  602. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  603. enum mlx4_resource type,
  604. void *res)
  605. {
  606. struct res_common *r;
  607. int err = 0;
  608. spin_lock_irq(mlx4_tlock(dev));
  609. r = find_res(dev, res_id, type);
  610. if (!r) {
  611. err = -ENONET;
  612. goto exit;
  613. }
  614. if (r->state == RES_ANY_BUSY) {
  615. err = -EBUSY;
  616. goto exit;
  617. }
  618. if (r->owner != slave) {
  619. err = -EPERM;
  620. goto exit;
  621. }
  622. r->from_state = r->state;
  623. r->state = RES_ANY_BUSY;
  624. if (res)
  625. *((struct res_common **)res) = r;
  626. exit:
  627. spin_unlock_irq(mlx4_tlock(dev));
  628. return err;
  629. }
  630. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  631. enum mlx4_resource type,
  632. u64 res_id, int *slave)
  633. {
  634. struct res_common *r;
  635. int err = -ENOENT;
  636. int id = res_id;
  637. if (type == RES_QP)
  638. id &= 0x7fffff;
  639. spin_lock(mlx4_tlock(dev));
  640. r = find_res(dev, id, type);
  641. if (r) {
  642. *slave = r->owner;
  643. err = 0;
  644. }
  645. spin_unlock(mlx4_tlock(dev));
  646. return err;
  647. }
  648. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  649. enum mlx4_resource type)
  650. {
  651. struct res_common *r;
  652. spin_lock_irq(mlx4_tlock(dev));
  653. r = find_res(dev, res_id, type);
  654. if (r)
  655. r->state = r->from_state;
  656. spin_unlock_irq(mlx4_tlock(dev));
  657. }
  658. static struct res_common *alloc_qp_tr(int id)
  659. {
  660. struct res_qp *ret;
  661. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  662. if (!ret)
  663. return NULL;
  664. ret->com.res_id = id;
  665. ret->com.state = RES_QP_RESERVED;
  666. ret->local_qpn = id;
  667. INIT_LIST_HEAD(&ret->mcg_list);
  668. spin_lock_init(&ret->mcg_spl);
  669. atomic_set(&ret->ref_count, 0);
  670. return &ret->com;
  671. }
  672. static struct res_common *alloc_mtt_tr(int id, int order)
  673. {
  674. struct res_mtt *ret;
  675. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  676. if (!ret)
  677. return NULL;
  678. ret->com.res_id = id;
  679. ret->order = order;
  680. ret->com.state = RES_MTT_ALLOCATED;
  681. atomic_set(&ret->ref_count, 0);
  682. return &ret->com;
  683. }
  684. static struct res_common *alloc_mpt_tr(int id, int key)
  685. {
  686. struct res_mpt *ret;
  687. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  688. if (!ret)
  689. return NULL;
  690. ret->com.res_id = id;
  691. ret->com.state = RES_MPT_RESERVED;
  692. ret->key = key;
  693. return &ret->com;
  694. }
  695. static struct res_common *alloc_eq_tr(int id)
  696. {
  697. struct res_eq *ret;
  698. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  699. if (!ret)
  700. return NULL;
  701. ret->com.res_id = id;
  702. ret->com.state = RES_EQ_RESERVED;
  703. return &ret->com;
  704. }
  705. static struct res_common *alloc_cq_tr(int id)
  706. {
  707. struct res_cq *ret;
  708. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  709. if (!ret)
  710. return NULL;
  711. ret->com.res_id = id;
  712. ret->com.state = RES_CQ_ALLOCATED;
  713. atomic_set(&ret->ref_count, 0);
  714. return &ret->com;
  715. }
  716. static struct res_common *alloc_srq_tr(int id)
  717. {
  718. struct res_srq *ret;
  719. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  720. if (!ret)
  721. return NULL;
  722. ret->com.res_id = id;
  723. ret->com.state = RES_SRQ_ALLOCATED;
  724. atomic_set(&ret->ref_count, 0);
  725. return &ret->com;
  726. }
  727. static struct res_common *alloc_counter_tr(int id)
  728. {
  729. struct res_counter *ret;
  730. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  731. if (!ret)
  732. return NULL;
  733. ret->com.res_id = id;
  734. ret->com.state = RES_COUNTER_ALLOCATED;
  735. return &ret->com;
  736. }
  737. static struct res_common *alloc_xrcdn_tr(int id)
  738. {
  739. struct res_xrcdn *ret;
  740. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  741. if (!ret)
  742. return NULL;
  743. ret->com.res_id = id;
  744. ret->com.state = RES_XRCD_ALLOCATED;
  745. return &ret->com;
  746. }
  747. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  748. {
  749. struct res_fs_rule *ret;
  750. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  751. if (!ret)
  752. return NULL;
  753. ret->com.res_id = id;
  754. ret->com.state = RES_FS_RULE_ALLOCATED;
  755. ret->qpn = qpn;
  756. return &ret->com;
  757. }
  758. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  759. int extra)
  760. {
  761. struct res_common *ret;
  762. switch (type) {
  763. case RES_QP:
  764. ret = alloc_qp_tr(id);
  765. break;
  766. case RES_MPT:
  767. ret = alloc_mpt_tr(id, extra);
  768. break;
  769. case RES_MTT:
  770. ret = alloc_mtt_tr(id, extra);
  771. break;
  772. case RES_EQ:
  773. ret = alloc_eq_tr(id);
  774. break;
  775. case RES_CQ:
  776. ret = alloc_cq_tr(id);
  777. break;
  778. case RES_SRQ:
  779. ret = alloc_srq_tr(id);
  780. break;
  781. case RES_MAC:
  782. printk(KERN_ERR "implementation missing\n");
  783. return NULL;
  784. case RES_COUNTER:
  785. ret = alloc_counter_tr(id);
  786. break;
  787. case RES_XRCD:
  788. ret = alloc_xrcdn_tr(id);
  789. break;
  790. case RES_FS_RULE:
  791. ret = alloc_fs_rule_tr(id, extra);
  792. break;
  793. default:
  794. return NULL;
  795. }
  796. if (ret)
  797. ret->owner = slave;
  798. return ret;
  799. }
  800. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  801. enum mlx4_resource type, int extra)
  802. {
  803. int i;
  804. int err;
  805. struct mlx4_priv *priv = mlx4_priv(dev);
  806. struct res_common **res_arr;
  807. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  808. struct rb_root *root = &tracker->res_tree[type];
  809. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  810. if (!res_arr)
  811. return -ENOMEM;
  812. for (i = 0; i < count; ++i) {
  813. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  814. if (!res_arr[i]) {
  815. for (--i; i >= 0; --i)
  816. kfree(res_arr[i]);
  817. kfree(res_arr);
  818. return -ENOMEM;
  819. }
  820. }
  821. spin_lock_irq(mlx4_tlock(dev));
  822. for (i = 0; i < count; ++i) {
  823. if (find_res(dev, base + i, type)) {
  824. err = -EEXIST;
  825. goto undo;
  826. }
  827. err = res_tracker_insert(root, res_arr[i]);
  828. if (err)
  829. goto undo;
  830. list_add_tail(&res_arr[i]->list,
  831. &tracker->slave_list[slave].res_list[type]);
  832. }
  833. spin_unlock_irq(mlx4_tlock(dev));
  834. kfree(res_arr);
  835. return 0;
  836. undo:
  837. for (--i; i >= base; --i)
  838. rb_erase(&res_arr[i]->node, root);
  839. spin_unlock_irq(mlx4_tlock(dev));
  840. for (i = 0; i < count; ++i)
  841. kfree(res_arr[i]);
  842. kfree(res_arr);
  843. return err;
  844. }
  845. static int remove_qp_ok(struct res_qp *res)
  846. {
  847. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  848. !list_empty(&res->mcg_list)) {
  849. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  850. res->com.state, atomic_read(&res->ref_count));
  851. return -EBUSY;
  852. } else if (res->com.state != RES_QP_RESERVED) {
  853. return -EPERM;
  854. }
  855. return 0;
  856. }
  857. static int remove_mtt_ok(struct res_mtt *res, int order)
  858. {
  859. if (res->com.state == RES_MTT_BUSY ||
  860. atomic_read(&res->ref_count)) {
  861. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  862. __func__, __LINE__,
  863. mtt_states_str(res->com.state),
  864. atomic_read(&res->ref_count));
  865. return -EBUSY;
  866. } else if (res->com.state != RES_MTT_ALLOCATED)
  867. return -EPERM;
  868. else if (res->order != order)
  869. return -EINVAL;
  870. return 0;
  871. }
  872. static int remove_mpt_ok(struct res_mpt *res)
  873. {
  874. if (res->com.state == RES_MPT_BUSY)
  875. return -EBUSY;
  876. else if (res->com.state != RES_MPT_RESERVED)
  877. return -EPERM;
  878. return 0;
  879. }
  880. static int remove_eq_ok(struct res_eq *res)
  881. {
  882. if (res->com.state == RES_MPT_BUSY)
  883. return -EBUSY;
  884. else if (res->com.state != RES_MPT_RESERVED)
  885. return -EPERM;
  886. return 0;
  887. }
  888. static int remove_counter_ok(struct res_counter *res)
  889. {
  890. if (res->com.state == RES_COUNTER_BUSY)
  891. return -EBUSY;
  892. else if (res->com.state != RES_COUNTER_ALLOCATED)
  893. return -EPERM;
  894. return 0;
  895. }
  896. static int remove_xrcdn_ok(struct res_xrcdn *res)
  897. {
  898. if (res->com.state == RES_XRCD_BUSY)
  899. return -EBUSY;
  900. else if (res->com.state != RES_XRCD_ALLOCATED)
  901. return -EPERM;
  902. return 0;
  903. }
  904. static int remove_fs_rule_ok(struct res_fs_rule *res)
  905. {
  906. if (res->com.state == RES_FS_RULE_BUSY)
  907. return -EBUSY;
  908. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  909. return -EPERM;
  910. return 0;
  911. }
  912. static int remove_cq_ok(struct res_cq *res)
  913. {
  914. if (res->com.state == RES_CQ_BUSY)
  915. return -EBUSY;
  916. else if (res->com.state != RES_CQ_ALLOCATED)
  917. return -EPERM;
  918. return 0;
  919. }
  920. static int remove_srq_ok(struct res_srq *res)
  921. {
  922. if (res->com.state == RES_SRQ_BUSY)
  923. return -EBUSY;
  924. else if (res->com.state != RES_SRQ_ALLOCATED)
  925. return -EPERM;
  926. return 0;
  927. }
  928. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  929. {
  930. switch (type) {
  931. case RES_QP:
  932. return remove_qp_ok((struct res_qp *)res);
  933. case RES_CQ:
  934. return remove_cq_ok((struct res_cq *)res);
  935. case RES_SRQ:
  936. return remove_srq_ok((struct res_srq *)res);
  937. case RES_MPT:
  938. return remove_mpt_ok((struct res_mpt *)res);
  939. case RES_MTT:
  940. return remove_mtt_ok((struct res_mtt *)res, extra);
  941. case RES_MAC:
  942. return -ENOSYS;
  943. case RES_EQ:
  944. return remove_eq_ok((struct res_eq *)res);
  945. case RES_COUNTER:
  946. return remove_counter_ok((struct res_counter *)res);
  947. case RES_XRCD:
  948. return remove_xrcdn_ok((struct res_xrcdn *)res);
  949. case RES_FS_RULE:
  950. return remove_fs_rule_ok((struct res_fs_rule *)res);
  951. default:
  952. return -EINVAL;
  953. }
  954. }
  955. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  956. enum mlx4_resource type, int extra)
  957. {
  958. u64 i;
  959. int err;
  960. struct mlx4_priv *priv = mlx4_priv(dev);
  961. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  962. struct res_common *r;
  963. spin_lock_irq(mlx4_tlock(dev));
  964. for (i = base; i < base + count; ++i) {
  965. r = res_tracker_lookup(&tracker->res_tree[type], i);
  966. if (!r) {
  967. err = -ENOENT;
  968. goto out;
  969. }
  970. if (r->owner != slave) {
  971. err = -EPERM;
  972. goto out;
  973. }
  974. err = remove_ok(r, type, extra);
  975. if (err)
  976. goto out;
  977. }
  978. for (i = base; i < base + count; ++i) {
  979. r = res_tracker_lookup(&tracker->res_tree[type], i);
  980. rb_erase(&r->node, &tracker->res_tree[type]);
  981. list_del(&r->list);
  982. kfree(r);
  983. }
  984. err = 0;
  985. out:
  986. spin_unlock_irq(mlx4_tlock(dev));
  987. return err;
  988. }
  989. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  990. enum res_qp_states state, struct res_qp **qp,
  991. int alloc)
  992. {
  993. struct mlx4_priv *priv = mlx4_priv(dev);
  994. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  995. struct res_qp *r;
  996. int err = 0;
  997. spin_lock_irq(mlx4_tlock(dev));
  998. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  999. if (!r)
  1000. err = -ENOENT;
  1001. else if (r->com.owner != slave)
  1002. err = -EPERM;
  1003. else {
  1004. switch (state) {
  1005. case RES_QP_BUSY:
  1006. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  1007. __func__, r->com.res_id);
  1008. err = -EBUSY;
  1009. break;
  1010. case RES_QP_RESERVED:
  1011. if (r->com.state == RES_QP_MAPPED && !alloc)
  1012. break;
  1013. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  1014. err = -EINVAL;
  1015. break;
  1016. case RES_QP_MAPPED:
  1017. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  1018. r->com.state == RES_QP_HW)
  1019. break;
  1020. else {
  1021. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  1022. r->com.res_id);
  1023. err = -EINVAL;
  1024. }
  1025. break;
  1026. case RES_QP_HW:
  1027. if (r->com.state != RES_QP_MAPPED)
  1028. err = -EINVAL;
  1029. break;
  1030. default:
  1031. err = -EINVAL;
  1032. }
  1033. if (!err) {
  1034. r->com.from_state = r->com.state;
  1035. r->com.to_state = state;
  1036. r->com.state = RES_QP_BUSY;
  1037. if (qp)
  1038. *qp = r;
  1039. }
  1040. }
  1041. spin_unlock_irq(mlx4_tlock(dev));
  1042. return err;
  1043. }
  1044. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1045. enum res_mpt_states state, struct res_mpt **mpt)
  1046. {
  1047. struct mlx4_priv *priv = mlx4_priv(dev);
  1048. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1049. struct res_mpt *r;
  1050. int err = 0;
  1051. spin_lock_irq(mlx4_tlock(dev));
  1052. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  1053. if (!r)
  1054. err = -ENOENT;
  1055. else if (r->com.owner != slave)
  1056. err = -EPERM;
  1057. else {
  1058. switch (state) {
  1059. case RES_MPT_BUSY:
  1060. err = -EINVAL;
  1061. break;
  1062. case RES_MPT_RESERVED:
  1063. if (r->com.state != RES_MPT_MAPPED)
  1064. err = -EINVAL;
  1065. break;
  1066. case RES_MPT_MAPPED:
  1067. if (r->com.state != RES_MPT_RESERVED &&
  1068. r->com.state != RES_MPT_HW)
  1069. err = -EINVAL;
  1070. break;
  1071. case RES_MPT_HW:
  1072. if (r->com.state != RES_MPT_MAPPED)
  1073. err = -EINVAL;
  1074. break;
  1075. default:
  1076. err = -EINVAL;
  1077. }
  1078. if (!err) {
  1079. r->com.from_state = r->com.state;
  1080. r->com.to_state = state;
  1081. r->com.state = RES_MPT_BUSY;
  1082. if (mpt)
  1083. *mpt = r;
  1084. }
  1085. }
  1086. spin_unlock_irq(mlx4_tlock(dev));
  1087. return err;
  1088. }
  1089. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1090. enum res_eq_states state, struct res_eq **eq)
  1091. {
  1092. struct mlx4_priv *priv = mlx4_priv(dev);
  1093. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1094. struct res_eq *r;
  1095. int err = 0;
  1096. spin_lock_irq(mlx4_tlock(dev));
  1097. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  1098. if (!r)
  1099. err = -ENOENT;
  1100. else if (r->com.owner != slave)
  1101. err = -EPERM;
  1102. else {
  1103. switch (state) {
  1104. case RES_EQ_BUSY:
  1105. err = -EINVAL;
  1106. break;
  1107. case RES_EQ_RESERVED:
  1108. if (r->com.state != RES_EQ_HW)
  1109. err = -EINVAL;
  1110. break;
  1111. case RES_EQ_HW:
  1112. if (r->com.state != RES_EQ_RESERVED)
  1113. err = -EINVAL;
  1114. break;
  1115. default:
  1116. err = -EINVAL;
  1117. }
  1118. if (!err) {
  1119. r->com.from_state = r->com.state;
  1120. r->com.to_state = state;
  1121. r->com.state = RES_EQ_BUSY;
  1122. if (eq)
  1123. *eq = r;
  1124. }
  1125. }
  1126. spin_unlock_irq(mlx4_tlock(dev));
  1127. return err;
  1128. }
  1129. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  1130. enum res_cq_states state, struct res_cq **cq)
  1131. {
  1132. struct mlx4_priv *priv = mlx4_priv(dev);
  1133. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1134. struct res_cq *r;
  1135. int err;
  1136. spin_lock_irq(mlx4_tlock(dev));
  1137. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  1138. if (!r)
  1139. err = -ENOENT;
  1140. else if (r->com.owner != slave)
  1141. err = -EPERM;
  1142. else {
  1143. switch (state) {
  1144. case RES_CQ_BUSY:
  1145. err = -EBUSY;
  1146. break;
  1147. case RES_CQ_ALLOCATED:
  1148. if (r->com.state != RES_CQ_HW)
  1149. err = -EINVAL;
  1150. else if (atomic_read(&r->ref_count))
  1151. err = -EBUSY;
  1152. else
  1153. err = 0;
  1154. break;
  1155. case RES_CQ_HW:
  1156. if (r->com.state != RES_CQ_ALLOCATED)
  1157. err = -EINVAL;
  1158. else
  1159. err = 0;
  1160. break;
  1161. default:
  1162. err = -EINVAL;
  1163. }
  1164. if (!err) {
  1165. r->com.from_state = r->com.state;
  1166. r->com.to_state = state;
  1167. r->com.state = RES_CQ_BUSY;
  1168. if (cq)
  1169. *cq = r;
  1170. }
  1171. }
  1172. spin_unlock_irq(mlx4_tlock(dev));
  1173. return err;
  1174. }
  1175. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1176. enum res_cq_states state, struct res_srq **srq)
  1177. {
  1178. struct mlx4_priv *priv = mlx4_priv(dev);
  1179. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1180. struct res_srq *r;
  1181. int err = 0;
  1182. spin_lock_irq(mlx4_tlock(dev));
  1183. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  1184. if (!r)
  1185. err = -ENOENT;
  1186. else if (r->com.owner != slave)
  1187. err = -EPERM;
  1188. else {
  1189. switch (state) {
  1190. case RES_SRQ_BUSY:
  1191. err = -EINVAL;
  1192. break;
  1193. case RES_SRQ_ALLOCATED:
  1194. if (r->com.state != RES_SRQ_HW)
  1195. err = -EINVAL;
  1196. else if (atomic_read(&r->ref_count))
  1197. err = -EBUSY;
  1198. break;
  1199. case RES_SRQ_HW:
  1200. if (r->com.state != RES_SRQ_ALLOCATED)
  1201. err = -EINVAL;
  1202. break;
  1203. default:
  1204. err = -EINVAL;
  1205. }
  1206. if (!err) {
  1207. r->com.from_state = r->com.state;
  1208. r->com.to_state = state;
  1209. r->com.state = RES_SRQ_BUSY;
  1210. if (srq)
  1211. *srq = r;
  1212. }
  1213. }
  1214. spin_unlock_irq(mlx4_tlock(dev));
  1215. return err;
  1216. }
  1217. static void res_abort_move(struct mlx4_dev *dev, int slave,
  1218. enum mlx4_resource type, int id)
  1219. {
  1220. struct mlx4_priv *priv = mlx4_priv(dev);
  1221. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1222. struct res_common *r;
  1223. spin_lock_irq(mlx4_tlock(dev));
  1224. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1225. if (r && (r->owner == slave))
  1226. r->state = r->from_state;
  1227. spin_unlock_irq(mlx4_tlock(dev));
  1228. }
  1229. static void res_end_move(struct mlx4_dev *dev, int slave,
  1230. enum mlx4_resource type, int id)
  1231. {
  1232. struct mlx4_priv *priv = mlx4_priv(dev);
  1233. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1234. struct res_common *r;
  1235. spin_lock_irq(mlx4_tlock(dev));
  1236. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1237. if (r && (r->owner == slave))
  1238. r->state = r->to_state;
  1239. spin_unlock_irq(mlx4_tlock(dev));
  1240. }
  1241. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  1242. {
  1243. return mlx4_is_qp_reserved(dev, qpn) &&
  1244. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  1245. }
  1246. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  1247. {
  1248. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  1249. }
  1250. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1251. u64 in_param, u64 *out_param)
  1252. {
  1253. int err;
  1254. int count;
  1255. int align;
  1256. int base;
  1257. int qpn;
  1258. switch (op) {
  1259. case RES_OP_RESERVE:
  1260. count = get_param_l(&in_param);
  1261. align = get_param_h(&in_param);
  1262. err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
  1263. if (err)
  1264. return err;
  1265. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  1266. if (err) {
  1267. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1268. return err;
  1269. }
  1270. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  1271. if (err) {
  1272. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1273. __mlx4_qp_release_range(dev, base, count);
  1274. return err;
  1275. }
  1276. set_param_l(out_param, base);
  1277. break;
  1278. case RES_OP_MAP_ICM:
  1279. qpn = get_param_l(&in_param) & 0x7fffff;
  1280. if (valid_reserved(dev, slave, qpn)) {
  1281. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1282. if (err)
  1283. return err;
  1284. }
  1285. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  1286. NULL, 1);
  1287. if (err)
  1288. return err;
  1289. if (!fw_reserved(dev, qpn)) {
  1290. err = __mlx4_qp_alloc_icm(dev, qpn);
  1291. if (err) {
  1292. res_abort_move(dev, slave, RES_QP, qpn);
  1293. return err;
  1294. }
  1295. }
  1296. res_end_move(dev, slave, RES_QP, qpn);
  1297. break;
  1298. default:
  1299. err = -EINVAL;
  1300. break;
  1301. }
  1302. return err;
  1303. }
  1304. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1305. u64 in_param, u64 *out_param)
  1306. {
  1307. int err = -EINVAL;
  1308. int base;
  1309. int order;
  1310. if (op != RES_OP_RESERVE_AND_MAP)
  1311. return err;
  1312. order = get_param_l(&in_param);
  1313. err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
  1314. if (err)
  1315. return err;
  1316. base = __mlx4_alloc_mtt_range(dev, order);
  1317. if (base == -1) {
  1318. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1319. return -ENOMEM;
  1320. }
  1321. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1322. if (err) {
  1323. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1324. __mlx4_free_mtt_range(dev, base, order);
  1325. } else {
  1326. set_param_l(out_param, base);
  1327. }
  1328. return err;
  1329. }
  1330. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1331. u64 in_param, u64 *out_param)
  1332. {
  1333. int err = -EINVAL;
  1334. int index;
  1335. int id;
  1336. struct res_mpt *mpt;
  1337. switch (op) {
  1338. case RES_OP_RESERVE:
  1339. err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
  1340. if (err)
  1341. break;
  1342. index = __mlx4_mpt_reserve(dev);
  1343. if (index == -1) {
  1344. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1345. break;
  1346. }
  1347. id = index & mpt_mask(dev);
  1348. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1349. if (err) {
  1350. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1351. __mlx4_mpt_release(dev, index);
  1352. break;
  1353. }
  1354. set_param_l(out_param, index);
  1355. break;
  1356. case RES_OP_MAP_ICM:
  1357. index = get_param_l(&in_param);
  1358. id = index & mpt_mask(dev);
  1359. err = mr_res_start_move_to(dev, slave, id,
  1360. RES_MPT_MAPPED, &mpt);
  1361. if (err)
  1362. return err;
  1363. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1364. if (err) {
  1365. res_abort_move(dev, slave, RES_MPT, id);
  1366. return err;
  1367. }
  1368. res_end_move(dev, slave, RES_MPT, id);
  1369. break;
  1370. }
  1371. return err;
  1372. }
  1373. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1374. u64 in_param, u64 *out_param)
  1375. {
  1376. int cqn;
  1377. int err;
  1378. switch (op) {
  1379. case RES_OP_RESERVE_AND_MAP:
  1380. err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
  1381. if (err)
  1382. break;
  1383. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1384. if (err) {
  1385. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1386. break;
  1387. }
  1388. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1389. if (err) {
  1390. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1391. __mlx4_cq_free_icm(dev, cqn);
  1392. break;
  1393. }
  1394. set_param_l(out_param, cqn);
  1395. break;
  1396. default:
  1397. err = -EINVAL;
  1398. }
  1399. return err;
  1400. }
  1401. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1402. u64 in_param, u64 *out_param)
  1403. {
  1404. int srqn;
  1405. int err;
  1406. switch (op) {
  1407. case RES_OP_RESERVE_AND_MAP:
  1408. err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
  1409. if (err)
  1410. break;
  1411. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1412. if (err) {
  1413. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1414. break;
  1415. }
  1416. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1417. if (err) {
  1418. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1419. __mlx4_srq_free_icm(dev, srqn);
  1420. break;
  1421. }
  1422. set_param_l(out_param, srqn);
  1423. break;
  1424. default:
  1425. err = -EINVAL;
  1426. }
  1427. return err;
  1428. }
  1429. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1430. {
  1431. struct mlx4_priv *priv = mlx4_priv(dev);
  1432. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1433. struct mac_res *res;
  1434. if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
  1435. return -EINVAL;
  1436. res = kzalloc(sizeof *res, GFP_KERNEL);
  1437. if (!res) {
  1438. mlx4_release_resource(dev, slave, RES_MAC, 1, port);
  1439. return -ENOMEM;
  1440. }
  1441. res->mac = mac;
  1442. res->port = (u8) port;
  1443. list_add_tail(&res->list,
  1444. &tracker->slave_list[slave].res_list[RES_MAC]);
  1445. return 0;
  1446. }
  1447. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1448. int port)
  1449. {
  1450. struct mlx4_priv *priv = mlx4_priv(dev);
  1451. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1452. struct list_head *mac_list =
  1453. &tracker->slave_list[slave].res_list[RES_MAC];
  1454. struct mac_res *res, *tmp;
  1455. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1456. if (res->mac == mac && res->port == (u8) port) {
  1457. list_del(&res->list);
  1458. mlx4_release_resource(dev, slave, RES_MAC, 1, port);
  1459. kfree(res);
  1460. break;
  1461. }
  1462. }
  1463. }
  1464. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1465. {
  1466. struct mlx4_priv *priv = mlx4_priv(dev);
  1467. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1468. struct list_head *mac_list =
  1469. &tracker->slave_list[slave].res_list[RES_MAC];
  1470. struct mac_res *res, *tmp;
  1471. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1472. list_del(&res->list);
  1473. __mlx4_unregister_mac(dev, res->port, res->mac);
  1474. mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
  1475. kfree(res);
  1476. }
  1477. }
  1478. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1479. u64 in_param, u64 *out_param, int in_port)
  1480. {
  1481. int err = -EINVAL;
  1482. int port;
  1483. u64 mac;
  1484. if (op != RES_OP_RESERVE_AND_MAP)
  1485. return err;
  1486. port = !in_port ? get_param_l(out_param) : in_port;
  1487. mac = in_param;
  1488. err = __mlx4_register_mac(dev, port, mac);
  1489. if (err >= 0) {
  1490. set_param_l(out_param, err);
  1491. err = 0;
  1492. }
  1493. if (!err) {
  1494. err = mac_add_to_slave(dev, slave, mac, port);
  1495. if (err)
  1496. __mlx4_unregister_mac(dev, port, mac);
  1497. }
  1498. return err;
  1499. }
  1500. static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1501. int port, int vlan_index)
  1502. {
  1503. struct mlx4_priv *priv = mlx4_priv(dev);
  1504. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1505. struct list_head *vlan_list =
  1506. &tracker->slave_list[slave].res_list[RES_VLAN];
  1507. struct vlan_res *res, *tmp;
  1508. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1509. if (res->vlan == vlan && res->port == (u8) port) {
  1510. /* vlan found. update ref count */
  1511. ++res->ref_count;
  1512. return 0;
  1513. }
  1514. }
  1515. if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
  1516. return -EINVAL;
  1517. res = kzalloc(sizeof(*res), GFP_KERNEL);
  1518. if (!res) {
  1519. mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
  1520. return -ENOMEM;
  1521. }
  1522. res->vlan = vlan;
  1523. res->port = (u8) port;
  1524. res->vlan_index = vlan_index;
  1525. res->ref_count = 1;
  1526. list_add_tail(&res->list,
  1527. &tracker->slave_list[slave].res_list[RES_VLAN]);
  1528. return 0;
  1529. }
  1530. static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1531. int port)
  1532. {
  1533. struct mlx4_priv *priv = mlx4_priv(dev);
  1534. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1535. struct list_head *vlan_list =
  1536. &tracker->slave_list[slave].res_list[RES_VLAN];
  1537. struct vlan_res *res, *tmp;
  1538. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1539. if (res->vlan == vlan && res->port == (u8) port) {
  1540. if (!--res->ref_count) {
  1541. list_del(&res->list);
  1542. mlx4_release_resource(dev, slave, RES_VLAN,
  1543. 1, port);
  1544. kfree(res);
  1545. }
  1546. break;
  1547. }
  1548. }
  1549. }
  1550. static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
  1551. {
  1552. struct mlx4_priv *priv = mlx4_priv(dev);
  1553. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1554. struct list_head *vlan_list =
  1555. &tracker->slave_list[slave].res_list[RES_VLAN];
  1556. struct vlan_res *res, *tmp;
  1557. int i;
  1558. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1559. list_del(&res->list);
  1560. /* dereference the vlan the num times the slave referenced it */
  1561. for (i = 0; i < res->ref_count; i++)
  1562. __mlx4_unregister_vlan(dev, res->port, res->vlan);
  1563. mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
  1564. kfree(res);
  1565. }
  1566. }
  1567. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1568. u64 in_param, u64 *out_param, int in_port)
  1569. {
  1570. struct mlx4_priv *priv = mlx4_priv(dev);
  1571. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1572. int err;
  1573. u16 vlan;
  1574. int vlan_index;
  1575. int port;
  1576. port = !in_port ? get_param_l(out_param) : in_port;
  1577. if (!port || op != RES_OP_RESERVE_AND_MAP)
  1578. return -EINVAL;
  1579. /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
  1580. if (!in_port && port > 0 && port <= dev->caps.num_ports) {
  1581. slave_state[slave].old_vlan_api = true;
  1582. return 0;
  1583. }
  1584. vlan = (u16) in_param;
  1585. err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
  1586. if (!err) {
  1587. set_param_l(out_param, (u32) vlan_index);
  1588. err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
  1589. if (err)
  1590. __mlx4_unregister_vlan(dev, port, vlan);
  1591. }
  1592. return err;
  1593. }
  1594. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1595. u64 in_param, u64 *out_param)
  1596. {
  1597. u32 index;
  1598. int err;
  1599. if (op != RES_OP_RESERVE)
  1600. return -EINVAL;
  1601. err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
  1602. if (err)
  1603. return err;
  1604. err = __mlx4_counter_alloc(dev, &index);
  1605. if (err) {
  1606. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1607. return err;
  1608. }
  1609. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1610. if (err) {
  1611. __mlx4_counter_free(dev, index);
  1612. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1613. } else {
  1614. set_param_l(out_param, index);
  1615. }
  1616. return err;
  1617. }
  1618. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1619. u64 in_param, u64 *out_param)
  1620. {
  1621. u32 xrcdn;
  1622. int err;
  1623. if (op != RES_OP_RESERVE)
  1624. return -EINVAL;
  1625. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1626. if (err)
  1627. return err;
  1628. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1629. if (err)
  1630. __mlx4_xrcd_free(dev, xrcdn);
  1631. else
  1632. set_param_l(out_param, xrcdn);
  1633. return err;
  1634. }
  1635. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1636. struct mlx4_vhcr *vhcr,
  1637. struct mlx4_cmd_mailbox *inbox,
  1638. struct mlx4_cmd_mailbox *outbox,
  1639. struct mlx4_cmd_info *cmd)
  1640. {
  1641. int err;
  1642. int alop = vhcr->op_modifier;
  1643. switch (vhcr->in_modifier & 0xFF) {
  1644. case RES_QP:
  1645. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1646. vhcr->in_param, &vhcr->out_param);
  1647. break;
  1648. case RES_MTT:
  1649. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1650. vhcr->in_param, &vhcr->out_param);
  1651. break;
  1652. case RES_MPT:
  1653. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1654. vhcr->in_param, &vhcr->out_param);
  1655. break;
  1656. case RES_CQ:
  1657. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1658. vhcr->in_param, &vhcr->out_param);
  1659. break;
  1660. case RES_SRQ:
  1661. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1662. vhcr->in_param, &vhcr->out_param);
  1663. break;
  1664. case RES_MAC:
  1665. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1666. vhcr->in_param, &vhcr->out_param,
  1667. (vhcr->in_modifier >> 8) & 0xFF);
  1668. break;
  1669. case RES_VLAN:
  1670. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1671. vhcr->in_param, &vhcr->out_param,
  1672. (vhcr->in_modifier >> 8) & 0xFF);
  1673. break;
  1674. case RES_COUNTER:
  1675. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1676. vhcr->in_param, &vhcr->out_param);
  1677. break;
  1678. case RES_XRCD:
  1679. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1680. vhcr->in_param, &vhcr->out_param);
  1681. break;
  1682. default:
  1683. err = -EINVAL;
  1684. break;
  1685. }
  1686. return err;
  1687. }
  1688. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1689. u64 in_param)
  1690. {
  1691. int err;
  1692. int count;
  1693. int base;
  1694. int qpn;
  1695. switch (op) {
  1696. case RES_OP_RESERVE:
  1697. base = get_param_l(&in_param) & 0x7fffff;
  1698. count = get_param_h(&in_param);
  1699. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1700. if (err)
  1701. break;
  1702. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1703. __mlx4_qp_release_range(dev, base, count);
  1704. break;
  1705. case RES_OP_MAP_ICM:
  1706. qpn = get_param_l(&in_param) & 0x7fffff;
  1707. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1708. NULL, 0);
  1709. if (err)
  1710. return err;
  1711. if (!fw_reserved(dev, qpn))
  1712. __mlx4_qp_free_icm(dev, qpn);
  1713. res_end_move(dev, slave, RES_QP, qpn);
  1714. if (valid_reserved(dev, slave, qpn))
  1715. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1716. break;
  1717. default:
  1718. err = -EINVAL;
  1719. break;
  1720. }
  1721. return err;
  1722. }
  1723. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1724. u64 in_param, u64 *out_param)
  1725. {
  1726. int err = -EINVAL;
  1727. int base;
  1728. int order;
  1729. if (op != RES_OP_RESERVE_AND_MAP)
  1730. return err;
  1731. base = get_param_l(&in_param);
  1732. order = get_param_h(&in_param);
  1733. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1734. if (!err) {
  1735. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1736. __mlx4_free_mtt_range(dev, base, order);
  1737. }
  1738. return err;
  1739. }
  1740. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1741. u64 in_param)
  1742. {
  1743. int err = -EINVAL;
  1744. int index;
  1745. int id;
  1746. struct res_mpt *mpt;
  1747. switch (op) {
  1748. case RES_OP_RESERVE:
  1749. index = get_param_l(&in_param);
  1750. id = index & mpt_mask(dev);
  1751. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1752. if (err)
  1753. break;
  1754. index = mpt->key;
  1755. put_res(dev, slave, id, RES_MPT);
  1756. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1757. if (err)
  1758. break;
  1759. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1760. __mlx4_mpt_release(dev, index);
  1761. break;
  1762. case RES_OP_MAP_ICM:
  1763. index = get_param_l(&in_param);
  1764. id = index & mpt_mask(dev);
  1765. err = mr_res_start_move_to(dev, slave, id,
  1766. RES_MPT_RESERVED, &mpt);
  1767. if (err)
  1768. return err;
  1769. __mlx4_mpt_free_icm(dev, mpt->key);
  1770. res_end_move(dev, slave, RES_MPT, id);
  1771. return err;
  1772. break;
  1773. default:
  1774. err = -EINVAL;
  1775. break;
  1776. }
  1777. return err;
  1778. }
  1779. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1780. u64 in_param, u64 *out_param)
  1781. {
  1782. int cqn;
  1783. int err;
  1784. switch (op) {
  1785. case RES_OP_RESERVE_AND_MAP:
  1786. cqn = get_param_l(&in_param);
  1787. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1788. if (err)
  1789. break;
  1790. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1791. __mlx4_cq_free_icm(dev, cqn);
  1792. break;
  1793. default:
  1794. err = -EINVAL;
  1795. break;
  1796. }
  1797. return err;
  1798. }
  1799. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1800. u64 in_param, u64 *out_param)
  1801. {
  1802. int srqn;
  1803. int err;
  1804. switch (op) {
  1805. case RES_OP_RESERVE_AND_MAP:
  1806. srqn = get_param_l(&in_param);
  1807. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1808. if (err)
  1809. break;
  1810. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1811. __mlx4_srq_free_icm(dev, srqn);
  1812. break;
  1813. default:
  1814. err = -EINVAL;
  1815. break;
  1816. }
  1817. return err;
  1818. }
  1819. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1820. u64 in_param, u64 *out_param, int in_port)
  1821. {
  1822. int port;
  1823. int err = 0;
  1824. switch (op) {
  1825. case RES_OP_RESERVE_AND_MAP:
  1826. port = !in_port ? get_param_l(out_param) : in_port;
  1827. mac_del_from_slave(dev, slave, in_param, port);
  1828. __mlx4_unregister_mac(dev, port, in_param);
  1829. break;
  1830. default:
  1831. err = -EINVAL;
  1832. break;
  1833. }
  1834. return err;
  1835. }
  1836. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1837. u64 in_param, u64 *out_param, int port)
  1838. {
  1839. struct mlx4_priv *priv = mlx4_priv(dev);
  1840. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1841. int err = 0;
  1842. switch (op) {
  1843. case RES_OP_RESERVE_AND_MAP:
  1844. if (slave_state[slave].old_vlan_api)
  1845. return 0;
  1846. if (!port)
  1847. return -EINVAL;
  1848. vlan_del_from_slave(dev, slave, in_param, port);
  1849. __mlx4_unregister_vlan(dev, port, in_param);
  1850. break;
  1851. default:
  1852. err = -EINVAL;
  1853. break;
  1854. }
  1855. return err;
  1856. }
  1857. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1858. u64 in_param, u64 *out_param)
  1859. {
  1860. int index;
  1861. int err;
  1862. if (op != RES_OP_RESERVE)
  1863. return -EINVAL;
  1864. index = get_param_l(&in_param);
  1865. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1866. if (err)
  1867. return err;
  1868. __mlx4_counter_free(dev, index);
  1869. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1870. return err;
  1871. }
  1872. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1873. u64 in_param, u64 *out_param)
  1874. {
  1875. int xrcdn;
  1876. int err;
  1877. if (op != RES_OP_RESERVE)
  1878. return -EINVAL;
  1879. xrcdn = get_param_l(&in_param);
  1880. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1881. if (err)
  1882. return err;
  1883. __mlx4_xrcd_free(dev, xrcdn);
  1884. return err;
  1885. }
  1886. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1887. struct mlx4_vhcr *vhcr,
  1888. struct mlx4_cmd_mailbox *inbox,
  1889. struct mlx4_cmd_mailbox *outbox,
  1890. struct mlx4_cmd_info *cmd)
  1891. {
  1892. int err = -EINVAL;
  1893. int alop = vhcr->op_modifier;
  1894. switch (vhcr->in_modifier & 0xFF) {
  1895. case RES_QP:
  1896. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1897. vhcr->in_param);
  1898. break;
  1899. case RES_MTT:
  1900. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1901. vhcr->in_param, &vhcr->out_param);
  1902. break;
  1903. case RES_MPT:
  1904. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1905. vhcr->in_param);
  1906. break;
  1907. case RES_CQ:
  1908. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1909. vhcr->in_param, &vhcr->out_param);
  1910. break;
  1911. case RES_SRQ:
  1912. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1913. vhcr->in_param, &vhcr->out_param);
  1914. break;
  1915. case RES_MAC:
  1916. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1917. vhcr->in_param, &vhcr->out_param,
  1918. (vhcr->in_modifier >> 8) & 0xFF);
  1919. break;
  1920. case RES_VLAN:
  1921. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1922. vhcr->in_param, &vhcr->out_param,
  1923. (vhcr->in_modifier >> 8) & 0xFF);
  1924. break;
  1925. case RES_COUNTER:
  1926. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1927. vhcr->in_param, &vhcr->out_param);
  1928. break;
  1929. case RES_XRCD:
  1930. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1931. vhcr->in_param, &vhcr->out_param);
  1932. default:
  1933. break;
  1934. }
  1935. return err;
  1936. }
  1937. /* ugly but other choices are uglier */
  1938. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1939. {
  1940. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1941. }
  1942. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1943. {
  1944. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1945. }
  1946. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1947. {
  1948. return be32_to_cpu(mpt->mtt_sz);
  1949. }
  1950. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  1951. {
  1952. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  1953. }
  1954. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  1955. {
  1956. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  1957. }
  1958. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  1959. {
  1960. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  1961. }
  1962. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  1963. {
  1964. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  1965. }
  1966. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1967. {
  1968. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1969. }
  1970. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1971. {
  1972. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1973. }
  1974. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1975. {
  1976. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1977. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1978. int log_sq_sride = qpc->sq_size_stride & 7;
  1979. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1980. int log_rq_stride = qpc->rq_size_stride & 7;
  1981. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1982. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1983. u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  1984. int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
  1985. int sq_size;
  1986. int rq_size;
  1987. int total_pages;
  1988. int total_mem;
  1989. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1990. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1991. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1992. total_mem = sq_size + rq_size;
  1993. total_pages =
  1994. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1995. page_shift);
  1996. return total_pages;
  1997. }
  1998. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1999. int size, struct res_mtt *mtt)
  2000. {
  2001. int res_start = mtt->com.res_id;
  2002. int res_size = (1 << mtt->order);
  2003. if (start < res_start || start + size > res_start + res_size)
  2004. return -EPERM;
  2005. return 0;
  2006. }
  2007. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2008. struct mlx4_vhcr *vhcr,
  2009. struct mlx4_cmd_mailbox *inbox,
  2010. struct mlx4_cmd_mailbox *outbox,
  2011. struct mlx4_cmd_info *cmd)
  2012. {
  2013. int err;
  2014. int index = vhcr->in_modifier;
  2015. struct res_mtt *mtt;
  2016. struct res_mpt *mpt;
  2017. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  2018. int phys;
  2019. int id;
  2020. u32 pd;
  2021. int pd_slave;
  2022. id = index & mpt_mask(dev);
  2023. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  2024. if (err)
  2025. return err;
  2026. /* Disable memory windows for VFs. */
  2027. if (!mr_is_region(inbox->buf)) {
  2028. err = -EPERM;
  2029. goto ex_abort;
  2030. }
  2031. /* Make sure that the PD bits related to the slave id are zeros. */
  2032. pd = mr_get_pd(inbox->buf);
  2033. pd_slave = (pd >> 17) & 0x7f;
  2034. if (pd_slave != 0 && pd_slave != slave) {
  2035. err = -EPERM;
  2036. goto ex_abort;
  2037. }
  2038. if (mr_is_fmr(inbox->buf)) {
  2039. /* FMR and Bind Enable are forbidden in slave devices. */
  2040. if (mr_is_bind_enabled(inbox->buf)) {
  2041. err = -EPERM;
  2042. goto ex_abort;
  2043. }
  2044. /* FMR and Memory Windows are also forbidden. */
  2045. if (!mr_is_region(inbox->buf)) {
  2046. err = -EPERM;
  2047. goto ex_abort;
  2048. }
  2049. }
  2050. phys = mr_phys_mpt(inbox->buf);
  2051. if (!phys) {
  2052. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2053. if (err)
  2054. goto ex_abort;
  2055. err = check_mtt_range(dev, slave, mtt_base,
  2056. mr_get_mtt_size(inbox->buf), mtt);
  2057. if (err)
  2058. goto ex_put;
  2059. mpt->mtt = mtt;
  2060. }
  2061. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2062. if (err)
  2063. goto ex_put;
  2064. if (!phys) {
  2065. atomic_inc(&mtt->ref_count);
  2066. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2067. }
  2068. res_end_move(dev, slave, RES_MPT, id);
  2069. return 0;
  2070. ex_put:
  2071. if (!phys)
  2072. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2073. ex_abort:
  2074. res_abort_move(dev, slave, RES_MPT, id);
  2075. return err;
  2076. }
  2077. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2078. struct mlx4_vhcr *vhcr,
  2079. struct mlx4_cmd_mailbox *inbox,
  2080. struct mlx4_cmd_mailbox *outbox,
  2081. struct mlx4_cmd_info *cmd)
  2082. {
  2083. int err;
  2084. int index = vhcr->in_modifier;
  2085. struct res_mpt *mpt;
  2086. int id;
  2087. id = index & mpt_mask(dev);
  2088. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  2089. if (err)
  2090. return err;
  2091. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2092. if (err)
  2093. goto ex_abort;
  2094. if (mpt->mtt)
  2095. atomic_dec(&mpt->mtt->ref_count);
  2096. res_end_move(dev, slave, RES_MPT, id);
  2097. return 0;
  2098. ex_abort:
  2099. res_abort_move(dev, slave, RES_MPT, id);
  2100. return err;
  2101. }
  2102. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2103. struct mlx4_vhcr *vhcr,
  2104. struct mlx4_cmd_mailbox *inbox,
  2105. struct mlx4_cmd_mailbox *outbox,
  2106. struct mlx4_cmd_info *cmd)
  2107. {
  2108. int err;
  2109. int index = vhcr->in_modifier;
  2110. struct res_mpt *mpt;
  2111. int id;
  2112. id = index & mpt_mask(dev);
  2113. err = get_res(dev, slave, id, RES_MPT, &mpt);
  2114. if (err)
  2115. return err;
  2116. if (mpt->com.from_state != RES_MPT_HW) {
  2117. err = -EBUSY;
  2118. goto out;
  2119. }
  2120. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2121. out:
  2122. put_res(dev, slave, id, RES_MPT);
  2123. return err;
  2124. }
  2125. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  2126. {
  2127. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  2128. }
  2129. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  2130. {
  2131. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  2132. }
  2133. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  2134. {
  2135. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  2136. }
  2137. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  2138. struct mlx4_qp_context *context)
  2139. {
  2140. u32 qpn = vhcr->in_modifier & 0xffffff;
  2141. u32 qkey = 0;
  2142. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  2143. return;
  2144. /* adjust qkey in qp context */
  2145. context->qkey = cpu_to_be32(qkey);
  2146. }
  2147. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2148. struct mlx4_vhcr *vhcr,
  2149. struct mlx4_cmd_mailbox *inbox,
  2150. struct mlx4_cmd_mailbox *outbox,
  2151. struct mlx4_cmd_info *cmd)
  2152. {
  2153. int err;
  2154. int qpn = vhcr->in_modifier & 0x7fffff;
  2155. struct res_mtt *mtt;
  2156. struct res_qp *qp;
  2157. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2158. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  2159. int mtt_size = qp_get_mtt_size(qpc);
  2160. struct res_cq *rcq;
  2161. struct res_cq *scq;
  2162. int rcqn = qp_get_rcqn(qpc);
  2163. int scqn = qp_get_scqn(qpc);
  2164. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  2165. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  2166. struct res_srq *srq;
  2167. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  2168. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  2169. if (err)
  2170. return err;
  2171. qp->local_qpn = local_qpn;
  2172. qp->sched_queue = 0;
  2173. qp->qpc_flags = be32_to_cpu(qpc->flags);
  2174. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2175. if (err)
  2176. goto ex_abort;
  2177. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2178. if (err)
  2179. goto ex_put_mtt;
  2180. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  2181. if (err)
  2182. goto ex_put_mtt;
  2183. if (scqn != rcqn) {
  2184. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  2185. if (err)
  2186. goto ex_put_rcq;
  2187. } else
  2188. scq = rcq;
  2189. if (use_srq) {
  2190. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2191. if (err)
  2192. goto ex_put_scq;
  2193. }
  2194. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2195. update_pkey_index(dev, slave, inbox);
  2196. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2197. if (err)
  2198. goto ex_put_srq;
  2199. atomic_inc(&mtt->ref_count);
  2200. qp->mtt = mtt;
  2201. atomic_inc(&rcq->ref_count);
  2202. qp->rcq = rcq;
  2203. atomic_inc(&scq->ref_count);
  2204. qp->scq = scq;
  2205. if (scqn != rcqn)
  2206. put_res(dev, slave, scqn, RES_CQ);
  2207. if (use_srq) {
  2208. atomic_inc(&srq->ref_count);
  2209. put_res(dev, slave, srqn, RES_SRQ);
  2210. qp->srq = srq;
  2211. }
  2212. put_res(dev, slave, rcqn, RES_CQ);
  2213. put_res(dev, slave, mtt_base, RES_MTT);
  2214. res_end_move(dev, slave, RES_QP, qpn);
  2215. return 0;
  2216. ex_put_srq:
  2217. if (use_srq)
  2218. put_res(dev, slave, srqn, RES_SRQ);
  2219. ex_put_scq:
  2220. if (scqn != rcqn)
  2221. put_res(dev, slave, scqn, RES_CQ);
  2222. ex_put_rcq:
  2223. put_res(dev, slave, rcqn, RES_CQ);
  2224. ex_put_mtt:
  2225. put_res(dev, slave, mtt_base, RES_MTT);
  2226. ex_abort:
  2227. res_abort_move(dev, slave, RES_QP, qpn);
  2228. return err;
  2229. }
  2230. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  2231. {
  2232. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  2233. }
  2234. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  2235. {
  2236. int log_eq_size = eqc->log_eq_size & 0x1f;
  2237. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  2238. if (log_eq_size + 5 < page_shift)
  2239. return 1;
  2240. return 1 << (log_eq_size + 5 - page_shift);
  2241. }
  2242. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  2243. {
  2244. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  2245. }
  2246. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  2247. {
  2248. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  2249. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  2250. if (log_cq_size + 5 < page_shift)
  2251. return 1;
  2252. return 1 << (log_cq_size + 5 - page_shift);
  2253. }
  2254. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2255. struct mlx4_vhcr *vhcr,
  2256. struct mlx4_cmd_mailbox *inbox,
  2257. struct mlx4_cmd_mailbox *outbox,
  2258. struct mlx4_cmd_info *cmd)
  2259. {
  2260. int err;
  2261. int eqn = vhcr->in_modifier;
  2262. int res_id = (slave << 8) | eqn;
  2263. struct mlx4_eq_context *eqc = inbox->buf;
  2264. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  2265. int mtt_size = eq_get_mtt_size(eqc);
  2266. struct res_eq *eq;
  2267. struct res_mtt *mtt;
  2268. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2269. if (err)
  2270. return err;
  2271. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  2272. if (err)
  2273. goto out_add;
  2274. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2275. if (err)
  2276. goto out_move;
  2277. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2278. if (err)
  2279. goto out_put;
  2280. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2281. if (err)
  2282. goto out_put;
  2283. atomic_inc(&mtt->ref_count);
  2284. eq->mtt = mtt;
  2285. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2286. res_end_move(dev, slave, RES_EQ, res_id);
  2287. return 0;
  2288. out_put:
  2289. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2290. out_move:
  2291. res_abort_move(dev, slave, RES_EQ, res_id);
  2292. out_add:
  2293. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2294. return err;
  2295. }
  2296. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  2297. int len, struct res_mtt **res)
  2298. {
  2299. struct mlx4_priv *priv = mlx4_priv(dev);
  2300. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2301. struct res_mtt *mtt;
  2302. int err = -EINVAL;
  2303. spin_lock_irq(mlx4_tlock(dev));
  2304. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  2305. com.list) {
  2306. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  2307. *res = mtt;
  2308. mtt->com.from_state = mtt->com.state;
  2309. mtt->com.state = RES_MTT_BUSY;
  2310. err = 0;
  2311. break;
  2312. }
  2313. }
  2314. spin_unlock_irq(mlx4_tlock(dev));
  2315. return err;
  2316. }
  2317. static int verify_qp_parameters(struct mlx4_dev *dev,
  2318. struct mlx4_cmd_mailbox *inbox,
  2319. enum qp_transition transition, u8 slave)
  2320. {
  2321. u32 qp_type;
  2322. struct mlx4_qp_context *qp_ctx;
  2323. enum mlx4_qp_optpar optpar;
  2324. qp_ctx = inbox->buf + 8;
  2325. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  2326. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  2327. switch (qp_type) {
  2328. case MLX4_QP_ST_RC:
  2329. case MLX4_QP_ST_UC:
  2330. switch (transition) {
  2331. case QP_TRANS_INIT2RTR:
  2332. case QP_TRANS_RTR2RTS:
  2333. case QP_TRANS_RTS2RTS:
  2334. case QP_TRANS_SQD2SQD:
  2335. case QP_TRANS_SQD2RTS:
  2336. if (slave != mlx4_master_func_num(dev))
  2337. /* slaves have only gid index 0 */
  2338. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  2339. if (qp_ctx->pri_path.mgid_index)
  2340. return -EINVAL;
  2341. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  2342. if (qp_ctx->alt_path.mgid_index)
  2343. return -EINVAL;
  2344. break;
  2345. default:
  2346. break;
  2347. }
  2348. break;
  2349. default:
  2350. break;
  2351. }
  2352. return 0;
  2353. }
  2354. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  2355. struct mlx4_vhcr *vhcr,
  2356. struct mlx4_cmd_mailbox *inbox,
  2357. struct mlx4_cmd_mailbox *outbox,
  2358. struct mlx4_cmd_info *cmd)
  2359. {
  2360. struct mlx4_mtt mtt;
  2361. __be64 *page_list = inbox->buf;
  2362. u64 *pg_list = (u64 *)page_list;
  2363. int i;
  2364. struct res_mtt *rmtt = NULL;
  2365. int start = be64_to_cpu(page_list[0]);
  2366. int npages = vhcr->in_modifier;
  2367. int err;
  2368. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  2369. if (err)
  2370. return err;
  2371. /* Call the SW implementation of write_mtt:
  2372. * - Prepare a dummy mtt struct
  2373. * - Translate inbox contents to simple addresses in host endianess */
  2374. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  2375. we don't really use it */
  2376. mtt.order = 0;
  2377. mtt.page_shift = 0;
  2378. for (i = 0; i < npages; ++i)
  2379. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  2380. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  2381. ((u64 *)page_list + 2));
  2382. if (rmtt)
  2383. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  2384. return err;
  2385. }
  2386. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2387. struct mlx4_vhcr *vhcr,
  2388. struct mlx4_cmd_mailbox *inbox,
  2389. struct mlx4_cmd_mailbox *outbox,
  2390. struct mlx4_cmd_info *cmd)
  2391. {
  2392. int eqn = vhcr->in_modifier;
  2393. int res_id = eqn | (slave << 8);
  2394. struct res_eq *eq;
  2395. int err;
  2396. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  2397. if (err)
  2398. return err;
  2399. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  2400. if (err)
  2401. goto ex_abort;
  2402. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2403. if (err)
  2404. goto ex_put;
  2405. atomic_dec(&eq->mtt->ref_count);
  2406. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2407. res_end_move(dev, slave, RES_EQ, res_id);
  2408. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2409. return 0;
  2410. ex_put:
  2411. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2412. ex_abort:
  2413. res_abort_move(dev, slave, RES_EQ, res_id);
  2414. return err;
  2415. }
  2416. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  2417. {
  2418. struct mlx4_priv *priv = mlx4_priv(dev);
  2419. struct mlx4_slave_event_eq_info *event_eq;
  2420. struct mlx4_cmd_mailbox *mailbox;
  2421. u32 in_modifier = 0;
  2422. int err;
  2423. int res_id;
  2424. struct res_eq *req;
  2425. if (!priv->mfunc.master.slave_state)
  2426. return -EINVAL;
  2427. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  2428. /* Create the event only if the slave is registered */
  2429. if (event_eq->eqn < 0)
  2430. return 0;
  2431. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2432. res_id = (slave << 8) | event_eq->eqn;
  2433. err = get_res(dev, slave, res_id, RES_EQ, &req);
  2434. if (err)
  2435. goto unlock;
  2436. if (req->com.from_state != RES_EQ_HW) {
  2437. err = -EINVAL;
  2438. goto put;
  2439. }
  2440. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2441. if (IS_ERR(mailbox)) {
  2442. err = PTR_ERR(mailbox);
  2443. goto put;
  2444. }
  2445. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  2446. ++event_eq->token;
  2447. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  2448. }
  2449. memcpy(mailbox->buf, (u8 *) eqe, 28);
  2450. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  2451. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  2452. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2453. MLX4_CMD_NATIVE);
  2454. put_res(dev, slave, res_id, RES_EQ);
  2455. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2456. mlx4_free_cmd_mailbox(dev, mailbox);
  2457. return err;
  2458. put:
  2459. put_res(dev, slave, res_id, RES_EQ);
  2460. unlock:
  2461. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2462. return err;
  2463. }
  2464. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2465. struct mlx4_vhcr *vhcr,
  2466. struct mlx4_cmd_mailbox *inbox,
  2467. struct mlx4_cmd_mailbox *outbox,
  2468. struct mlx4_cmd_info *cmd)
  2469. {
  2470. int eqn = vhcr->in_modifier;
  2471. int res_id = eqn | (slave << 8);
  2472. struct res_eq *eq;
  2473. int err;
  2474. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2475. if (err)
  2476. return err;
  2477. if (eq->com.from_state != RES_EQ_HW) {
  2478. err = -EINVAL;
  2479. goto ex_put;
  2480. }
  2481. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2482. ex_put:
  2483. put_res(dev, slave, res_id, RES_EQ);
  2484. return err;
  2485. }
  2486. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2487. struct mlx4_vhcr *vhcr,
  2488. struct mlx4_cmd_mailbox *inbox,
  2489. struct mlx4_cmd_mailbox *outbox,
  2490. struct mlx4_cmd_info *cmd)
  2491. {
  2492. int err;
  2493. int cqn = vhcr->in_modifier;
  2494. struct mlx4_cq_context *cqc = inbox->buf;
  2495. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2496. struct res_cq *cq;
  2497. struct res_mtt *mtt;
  2498. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2499. if (err)
  2500. return err;
  2501. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2502. if (err)
  2503. goto out_move;
  2504. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2505. if (err)
  2506. goto out_put;
  2507. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2508. if (err)
  2509. goto out_put;
  2510. atomic_inc(&mtt->ref_count);
  2511. cq->mtt = mtt;
  2512. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2513. res_end_move(dev, slave, RES_CQ, cqn);
  2514. return 0;
  2515. out_put:
  2516. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2517. out_move:
  2518. res_abort_move(dev, slave, RES_CQ, cqn);
  2519. return err;
  2520. }
  2521. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2522. struct mlx4_vhcr *vhcr,
  2523. struct mlx4_cmd_mailbox *inbox,
  2524. struct mlx4_cmd_mailbox *outbox,
  2525. struct mlx4_cmd_info *cmd)
  2526. {
  2527. int err;
  2528. int cqn = vhcr->in_modifier;
  2529. struct res_cq *cq;
  2530. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2531. if (err)
  2532. return err;
  2533. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2534. if (err)
  2535. goto out_move;
  2536. atomic_dec(&cq->mtt->ref_count);
  2537. res_end_move(dev, slave, RES_CQ, cqn);
  2538. return 0;
  2539. out_move:
  2540. res_abort_move(dev, slave, RES_CQ, cqn);
  2541. return err;
  2542. }
  2543. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2544. struct mlx4_vhcr *vhcr,
  2545. struct mlx4_cmd_mailbox *inbox,
  2546. struct mlx4_cmd_mailbox *outbox,
  2547. struct mlx4_cmd_info *cmd)
  2548. {
  2549. int cqn = vhcr->in_modifier;
  2550. struct res_cq *cq;
  2551. int err;
  2552. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2553. if (err)
  2554. return err;
  2555. if (cq->com.from_state != RES_CQ_HW)
  2556. goto ex_put;
  2557. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2558. ex_put:
  2559. put_res(dev, slave, cqn, RES_CQ);
  2560. return err;
  2561. }
  2562. static int handle_resize(struct mlx4_dev *dev, int slave,
  2563. struct mlx4_vhcr *vhcr,
  2564. struct mlx4_cmd_mailbox *inbox,
  2565. struct mlx4_cmd_mailbox *outbox,
  2566. struct mlx4_cmd_info *cmd,
  2567. struct res_cq *cq)
  2568. {
  2569. int err;
  2570. struct res_mtt *orig_mtt;
  2571. struct res_mtt *mtt;
  2572. struct mlx4_cq_context *cqc = inbox->buf;
  2573. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2574. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2575. if (err)
  2576. return err;
  2577. if (orig_mtt != cq->mtt) {
  2578. err = -EINVAL;
  2579. goto ex_put;
  2580. }
  2581. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2582. if (err)
  2583. goto ex_put;
  2584. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2585. if (err)
  2586. goto ex_put1;
  2587. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2588. if (err)
  2589. goto ex_put1;
  2590. atomic_dec(&orig_mtt->ref_count);
  2591. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2592. atomic_inc(&mtt->ref_count);
  2593. cq->mtt = mtt;
  2594. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2595. return 0;
  2596. ex_put1:
  2597. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2598. ex_put:
  2599. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2600. return err;
  2601. }
  2602. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2603. struct mlx4_vhcr *vhcr,
  2604. struct mlx4_cmd_mailbox *inbox,
  2605. struct mlx4_cmd_mailbox *outbox,
  2606. struct mlx4_cmd_info *cmd)
  2607. {
  2608. int cqn = vhcr->in_modifier;
  2609. struct res_cq *cq;
  2610. int err;
  2611. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2612. if (err)
  2613. return err;
  2614. if (cq->com.from_state != RES_CQ_HW)
  2615. goto ex_put;
  2616. if (vhcr->op_modifier == 0) {
  2617. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2618. goto ex_put;
  2619. }
  2620. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2621. ex_put:
  2622. put_res(dev, slave, cqn, RES_CQ);
  2623. return err;
  2624. }
  2625. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2626. {
  2627. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2628. int log_rq_stride = srqc->logstride & 7;
  2629. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2630. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2631. return 1;
  2632. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2633. }
  2634. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2635. struct mlx4_vhcr *vhcr,
  2636. struct mlx4_cmd_mailbox *inbox,
  2637. struct mlx4_cmd_mailbox *outbox,
  2638. struct mlx4_cmd_info *cmd)
  2639. {
  2640. int err;
  2641. int srqn = vhcr->in_modifier;
  2642. struct res_mtt *mtt;
  2643. struct res_srq *srq;
  2644. struct mlx4_srq_context *srqc = inbox->buf;
  2645. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2646. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2647. return -EINVAL;
  2648. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2649. if (err)
  2650. return err;
  2651. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2652. if (err)
  2653. goto ex_abort;
  2654. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2655. mtt);
  2656. if (err)
  2657. goto ex_put_mtt;
  2658. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2659. if (err)
  2660. goto ex_put_mtt;
  2661. atomic_inc(&mtt->ref_count);
  2662. srq->mtt = mtt;
  2663. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2664. res_end_move(dev, slave, RES_SRQ, srqn);
  2665. return 0;
  2666. ex_put_mtt:
  2667. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2668. ex_abort:
  2669. res_abort_move(dev, slave, RES_SRQ, srqn);
  2670. return err;
  2671. }
  2672. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2673. struct mlx4_vhcr *vhcr,
  2674. struct mlx4_cmd_mailbox *inbox,
  2675. struct mlx4_cmd_mailbox *outbox,
  2676. struct mlx4_cmd_info *cmd)
  2677. {
  2678. int err;
  2679. int srqn = vhcr->in_modifier;
  2680. struct res_srq *srq;
  2681. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2682. if (err)
  2683. return err;
  2684. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2685. if (err)
  2686. goto ex_abort;
  2687. atomic_dec(&srq->mtt->ref_count);
  2688. if (srq->cq)
  2689. atomic_dec(&srq->cq->ref_count);
  2690. res_end_move(dev, slave, RES_SRQ, srqn);
  2691. return 0;
  2692. ex_abort:
  2693. res_abort_move(dev, slave, RES_SRQ, srqn);
  2694. return err;
  2695. }
  2696. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2697. struct mlx4_vhcr *vhcr,
  2698. struct mlx4_cmd_mailbox *inbox,
  2699. struct mlx4_cmd_mailbox *outbox,
  2700. struct mlx4_cmd_info *cmd)
  2701. {
  2702. int err;
  2703. int srqn = vhcr->in_modifier;
  2704. struct res_srq *srq;
  2705. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2706. if (err)
  2707. return err;
  2708. if (srq->com.from_state != RES_SRQ_HW) {
  2709. err = -EBUSY;
  2710. goto out;
  2711. }
  2712. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2713. out:
  2714. put_res(dev, slave, srqn, RES_SRQ);
  2715. return err;
  2716. }
  2717. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2718. struct mlx4_vhcr *vhcr,
  2719. struct mlx4_cmd_mailbox *inbox,
  2720. struct mlx4_cmd_mailbox *outbox,
  2721. struct mlx4_cmd_info *cmd)
  2722. {
  2723. int err;
  2724. int srqn = vhcr->in_modifier;
  2725. struct res_srq *srq;
  2726. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2727. if (err)
  2728. return err;
  2729. if (srq->com.from_state != RES_SRQ_HW) {
  2730. err = -EBUSY;
  2731. goto out;
  2732. }
  2733. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2734. out:
  2735. put_res(dev, slave, srqn, RES_SRQ);
  2736. return err;
  2737. }
  2738. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2739. struct mlx4_vhcr *vhcr,
  2740. struct mlx4_cmd_mailbox *inbox,
  2741. struct mlx4_cmd_mailbox *outbox,
  2742. struct mlx4_cmd_info *cmd)
  2743. {
  2744. int err;
  2745. int qpn = vhcr->in_modifier & 0x7fffff;
  2746. struct res_qp *qp;
  2747. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2748. if (err)
  2749. return err;
  2750. if (qp->com.from_state != RES_QP_HW) {
  2751. err = -EBUSY;
  2752. goto out;
  2753. }
  2754. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2755. out:
  2756. put_res(dev, slave, qpn, RES_QP);
  2757. return err;
  2758. }
  2759. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2760. struct mlx4_vhcr *vhcr,
  2761. struct mlx4_cmd_mailbox *inbox,
  2762. struct mlx4_cmd_mailbox *outbox,
  2763. struct mlx4_cmd_info *cmd)
  2764. {
  2765. struct mlx4_qp_context *context = inbox->buf + 8;
  2766. adjust_proxy_tun_qkey(dev, vhcr, context);
  2767. update_pkey_index(dev, slave, inbox);
  2768. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2769. }
  2770. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2771. struct mlx4_vhcr *vhcr,
  2772. struct mlx4_cmd_mailbox *inbox,
  2773. struct mlx4_cmd_mailbox *outbox,
  2774. struct mlx4_cmd_info *cmd)
  2775. {
  2776. int err;
  2777. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2778. int qpn = vhcr->in_modifier & 0x7fffff;
  2779. struct res_qp *qp;
  2780. u8 orig_sched_queue;
  2781. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2782. if (err)
  2783. return err;
  2784. update_pkey_index(dev, slave, inbox);
  2785. update_gid(dev, inbox, (u8)slave);
  2786. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2787. orig_sched_queue = qpc->pri_path.sched_queue;
  2788. err = update_vport_qp_param(dev, inbox, slave, qpn);
  2789. if (err)
  2790. return err;
  2791. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2792. if (err)
  2793. return err;
  2794. if (qp->com.from_state != RES_QP_HW) {
  2795. err = -EBUSY;
  2796. goto out;
  2797. }
  2798. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2799. out:
  2800. /* if no error, save sched queue value passed in by VF. This is
  2801. * essentially the QOS value provided by the VF. This will be useful
  2802. * if we allow dynamic changes from VST back to VGT
  2803. */
  2804. if (!err)
  2805. qp->sched_queue = orig_sched_queue;
  2806. put_res(dev, slave, qpn, RES_QP);
  2807. return err;
  2808. }
  2809. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2810. struct mlx4_vhcr *vhcr,
  2811. struct mlx4_cmd_mailbox *inbox,
  2812. struct mlx4_cmd_mailbox *outbox,
  2813. struct mlx4_cmd_info *cmd)
  2814. {
  2815. int err;
  2816. struct mlx4_qp_context *context = inbox->buf + 8;
  2817. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2818. if (err)
  2819. return err;
  2820. update_pkey_index(dev, slave, inbox);
  2821. update_gid(dev, inbox, (u8)slave);
  2822. adjust_proxy_tun_qkey(dev, vhcr, context);
  2823. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2824. }
  2825. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2826. struct mlx4_vhcr *vhcr,
  2827. struct mlx4_cmd_mailbox *inbox,
  2828. struct mlx4_cmd_mailbox *outbox,
  2829. struct mlx4_cmd_info *cmd)
  2830. {
  2831. int err;
  2832. struct mlx4_qp_context *context = inbox->buf + 8;
  2833. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2834. if (err)
  2835. return err;
  2836. update_pkey_index(dev, slave, inbox);
  2837. update_gid(dev, inbox, (u8)slave);
  2838. adjust_proxy_tun_qkey(dev, vhcr, context);
  2839. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2840. }
  2841. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2842. struct mlx4_vhcr *vhcr,
  2843. struct mlx4_cmd_mailbox *inbox,
  2844. struct mlx4_cmd_mailbox *outbox,
  2845. struct mlx4_cmd_info *cmd)
  2846. {
  2847. struct mlx4_qp_context *context = inbox->buf + 8;
  2848. adjust_proxy_tun_qkey(dev, vhcr, context);
  2849. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2850. }
  2851. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2852. struct mlx4_vhcr *vhcr,
  2853. struct mlx4_cmd_mailbox *inbox,
  2854. struct mlx4_cmd_mailbox *outbox,
  2855. struct mlx4_cmd_info *cmd)
  2856. {
  2857. int err;
  2858. struct mlx4_qp_context *context = inbox->buf + 8;
  2859. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2860. if (err)
  2861. return err;
  2862. adjust_proxy_tun_qkey(dev, vhcr, context);
  2863. update_gid(dev, inbox, (u8)slave);
  2864. update_pkey_index(dev, slave, inbox);
  2865. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2866. }
  2867. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2868. struct mlx4_vhcr *vhcr,
  2869. struct mlx4_cmd_mailbox *inbox,
  2870. struct mlx4_cmd_mailbox *outbox,
  2871. struct mlx4_cmd_info *cmd)
  2872. {
  2873. int err;
  2874. struct mlx4_qp_context *context = inbox->buf + 8;
  2875. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2876. if (err)
  2877. return err;
  2878. adjust_proxy_tun_qkey(dev, vhcr, context);
  2879. update_gid(dev, inbox, (u8)slave);
  2880. update_pkey_index(dev, slave, inbox);
  2881. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2882. }
  2883. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2884. struct mlx4_vhcr *vhcr,
  2885. struct mlx4_cmd_mailbox *inbox,
  2886. struct mlx4_cmd_mailbox *outbox,
  2887. struct mlx4_cmd_info *cmd)
  2888. {
  2889. int err;
  2890. int qpn = vhcr->in_modifier & 0x7fffff;
  2891. struct res_qp *qp;
  2892. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2893. if (err)
  2894. return err;
  2895. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2896. if (err)
  2897. goto ex_abort;
  2898. atomic_dec(&qp->mtt->ref_count);
  2899. atomic_dec(&qp->rcq->ref_count);
  2900. atomic_dec(&qp->scq->ref_count);
  2901. if (qp->srq)
  2902. atomic_dec(&qp->srq->ref_count);
  2903. res_end_move(dev, slave, RES_QP, qpn);
  2904. return 0;
  2905. ex_abort:
  2906. res_abort_move(dev, slave, RES_QP, qpn);
  2907. return err;
  2908. }
  2909. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2910. struct res_qp *rqp, u8 *gid)
  2911. {
  2912. struct res_gid *res;
  2913. list_for_each_entry(res, &rqp->mcg_list, list) {
  2914. if (!memcmp(res->gid, gid, 16))
  2915. return res;
  2916. }
  2917. return NULL;
  2918. }
  2919. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2920. u8 *gid, enum mlx4_protocol prot,
  2921. enum mlx4_steer_type steer, u64 reg_id)
  2922. {
  2923. struct res_gid *res;
  2924. int err;
  2925. res = kzalloc(sizeof *res, GFP_KERNEL);
  2926. if (!res)
  2927. return -ENOMEM;
  2928. spin_lock_irq(&rqp->mcg_spl);
  2929. if (find_gid(dev, slave, rqp, gid)) {
  2930. kfree(res);
  2931. err = -EEXIST;
  2932. } else {
  2933. memcpy(res->gid, gid, 16);
  2934. res->prot = prot;
  2935. res->steer = steer;
  2936. res->reg_id = reg_id;
  2937. list_add_tail(&res->list, &rqp->mcg_list);
  2938. err = 0;
  2939. }
  2940. spin_unlock_irq(&rqp->mcg_spl);
  2941. return err;
  2942. }
  2943. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2944. u8 *gid, enum mlx4_protocol prot,
  2945. enum mlx4_steer_type steer, u64 *reg_id)
  2946. {
  2947. struct res_gid *res;
  2948. int err;
  2949. spin_lock_irq(&rqp->mcg_spl);
  2950. res = find_gid(dev, slave, rqp, gid);
  2951. if (!res || res->prot != prot || res->steer != steer)
  2952. err = -EINVAL;
  2953. else {
  2954. *reg_id = res->reg_id;
  2955. list_del(&res->list);
  2956. kfree(res);
  2957. err = 0;
  2958. }
  2959. spin_unlock_irq(&rqp->mcg_spl);
  2960. return err;
  2961. }
  2962. static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2963. int block_loopback, enum mlx4_protocol prot,
  2964. enum mlx4_steer_type type, u64 *reg_id)
  2965. {
  2966. switch (dev->caps.steering_mode) {
  2967. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2968. return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
  2969. block_loopback, prot,
  2970. reg_id);
  2971. case MLX4_STEERING_MODE_B0:
  2972. return mlx4_qp_attach_common(dev, qp, gid,
  2973. block_loopback, prot, type);
  2974. default:
  2975. return -EINVAL;
  2976. }
  2977. }
  2978. static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2979. enum mlx4_protocol prot, enum mlx4_steer_type type,
  2980. u64 reg_id)
  2981. {
  2982. switch (dev->caps.steering_mode) {
  2983. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2984. return mlx4_flow_detach(dev, reg_id);
  2985. case MLX4_STEERING_MODE_B0:
  2986. return mlx4_qp_detach_common(dev, qp, gid, prot, type);
  2987. default:
  2988. return -EINVAL;
  2989. }
  2990. }
  2991. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2992. struct mlx4_vhcr *vhcr,
  2993. struct mlx4_cmd_mailbox *inbox,
  2994. struct mlx4_cmd_mailbox *outbox,
  2995. struct mlx4_cmd_info *cmd)
  2996. {
  2997. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2998. u8 *gid = inbox->buf;
  2999. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  3000. int err;
  3001. int qpn;
  3002. struct res_qp *rqp;
  3003. u64 reg_id = 0;
  3004. int attach = vhcr->op_modifier;
  3005. int block_loopback = vhcr->in_modifier >> 31;
  3006. u8 steer_type_mask = 2;
  3007. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  3008. qpn = vhcr->in_modifier & 0xffffff;
  3009. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3010. if (err)
  3011. return err;
  3012. qp.qpn = qpn;
  3013. if (attach) {
  3014. err = qp_attach(dev, &qp, gid, block_loopback, prot,
  3015. type, &reg_id);
  3016. if (err) {
  3017. pr_err("Fail to attach rule to qp 0x%x\n", qpn);
  3018. goto ex_put;
  3019. }
  3020. err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
  3021. if (err)
  3022. goto ex_detach;
  3023. } else {
  3024. err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
  3025. if (err)
  3026. goto ex_put;
  3027. err = qp_detach(dev, &qp, gid, prot, type, reg_id);
  3028. if (err)
  3029. pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
  3030. qpn, reg_id);
  3031. }
  3032. put_res(dev, slave, qpn, RES_QP);
  3033. return err;
  3034. ex_detach:
  3035. qp_detach(dev, &qp, gid, prot, type, reg_id);
  3036. ex_put:
  3037. put_res(dev, slave, qpn, RES_QP);
  3038. return err;
  3039. }
  3040. /*
  3041. * MAC validation for Flow Steering rules.
  3042. * VF can attach rules only with a mac address which is assigned to it.
  3043. */
  3044. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  3045. struct list_head *rlist)
  3046. {
  3047. struct mac_res *res, *tmp;
  3048. __be64 be_mac;
  3049. /* make sure it isn't multicast or broadcast mac*/
  3050. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  3051. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  3052. list_for_each_entry_safe(res, tmp, rlist, list) {
  3053. be_mac = cpu_to_be64(res->mac << 16);
  3054. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  3055. return 0;
  3056. }
  3057. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  3058. eth_header->eth.dst_mac, slave);
  3059. return -EINVAL;
  3060. }
  3061. return 0;
  3062. }
  3063. /*
  3064. * In case of missing eth header, append eth header with a MAC address
  3065. * assigned to the VF.
  3066. */
  3067. static int add_eth_header(struct mlx4_dev *dev, int slave,
  3068. struct mlx4_cmd_mailbox *inbox,
  3069. struct list_head *rlist, int header_id)
  3070. {
  3071. struct mac_res *res, *tmp;
  3072. u8 port;
  3073. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3074. struct mlx4_net_trans_rule_hw_eth *eth_header;
  3075. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  3076. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  3077. __be64 be_mac = 0;
  3078. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  3079. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3080. port = ctrl->port;
  3081. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  3082. /* Clear a space in the inbox for eth header */
  3083. switch (header_id) {
  3084. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3085. ip_header =
  3086. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  3087. memmove(ip_header, eth_header,
  3088. sizeof(*ip_header) + sizeof(*l4_header));
  3089. break;
  3090. case MLX4_NET_TRANS_RULE_ID_TCP:
  3091. case MLX4_NET_TRANS_RULE_ID_UDP:
  3092. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  3093. (eth_header + 1);
  3094. memmove(l4_header, eth_header, sizeof(*l4_header));
  3095. break;
  3096. default:
  3097. return -EINVAL;
  3098. }
  3099. list_for_each_entry_safe(res, tmp, rlist, list) {
  3100. if (port == res->port) {
  3101. be_mac = cpu_to_be64(res->mac << 16);
  3102. break;
  3103. }
  3104. }
  3105. if (!be_mac) {
  3106. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  3107. port);
  3108. return -EINVAL;
  3109. }
  3110. memset(eth_header, 0, sizeof(*eth_header));
  3111. eth_header->size = sizeof(*eth_header) >> 2;
  3112. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  3113. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  3114. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  3115. return 0;
  3116. }
  3117. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  3118. struct mlx4_vhcr *vhcr,
  3119. struct mlx4_cmd_mailbox *inbox,
  3120. struct mlx4_cmd_mailbox *outbox,
  3121. struct mlx4_cmd_info *cmd)
  3122. {
  3123. struct mlx4_priv *priv = mlx4_priv(dev);
  3124. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3125. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  3126. int err;
  3127. int qpn;
  3128. struct res_qp *rqp;
  3129. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3130. struct _rule_hw *rule_header;
  3131. int header_id;
  3132. if (dev->caps.steering_mode !=
  3133. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3134. return -EOPNOTSUPP;
  3135. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3136. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  3137. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3138. if (err) {
  3139. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  3140. return err;
  3141. }
  3142. rule_header = (struct _rule_hw *)(ctrl + 1);
  3143. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  3144. switch (header_id) {
  3145. case MLX4_NET_TRANS_RULE_ID_ETH:
  3146. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  3147. err = -EINVAL;
  3148. goto err_put;
  3149. }
  3150. break;
  3151. case MLX4_NET_TRANS_RULE_ID_IB:
  3152. break;
  3153. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3154. case MLX4_NET_TRANS_RULE_ID_TCP:
  3155. case MLX4_NET_TRANS_RULE_ID_UDP:
  3156. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  3157. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  3158. err = -EINVAL;
  3159. goto err_put;
  3160. }
  3161. vhcr->in_modifier +=
  3162. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  3163. break;
  3164. default:
  3165. pr_err("Corrupted mailbox.\n");
  3166. err = -EINVAL;
  3167. goto err_put;
  3168. }
  3169. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  3170. vhcr->in_modifier, 0,
  3171. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  3172. MLX4_CMD_NATIVE);
  3173. if (err)
  3174. goto err_put;
  3175. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  3176. if (err) {
  3177. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  3178. /* detach rule*/
  3179. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  3180. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3181. MLX4_CMD_NATIVE);
  3182. goto err_put;
  3183. }
  3184. atomic_inc(&rqp->ref_count);
  3185. err_put:
  3186. put_res(dev, slave, qpn, RES_QP);
  3187. return err;
  3188. }
  3189. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  3190. struct mlx4_vhcr *vhcr,
  3191. struct mlx4_cmd_mailbox *inbox,
  3192. struct mlx4_cmd_mailbox *outbox,
  3193. struct mlx4_cmd_info *cmd)
  3194. {
  3195. int err;
  3196. struct res_qp *rqp;
  3197. struct res_fs_rule *rrule;
  3198. if (dev->caps.steering_mode !=
  3199. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3200. return -EOPNOTSUPP;
  3201. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  3202. if (err)
  3203. return err;
  3204. /* Release the rule form busy state before removal */
  3205. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  3206. err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
  3207. if (err)
  3208. return err;
  3209. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  3210. if (err) {
  3211. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  3212. goto out;
  3213. }
  3214. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  3215. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3216. MLX4_CMD_NATIVE);
  3217. if (!err)
  3218. atomic_dec(&rqp->ref_count);
  3219. out:
  3220. put_res(dev, slave, rrule->qpn, RES_QP);
  3221. return err;
  3222. }
  3223. enum {
  3224. BUSY_MAX_RETRIES = 10
  3225. };
  3226. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  3227. struct mlx4_vhcr *vhcr,
  3228. struct mlx4_cmd_mailbox *inbox,
  3229. struct mlx4_cmd_mailbox *outbox,
  3230. struct mlx4_cmd_info *cmd)
  3231. {
  3232. int err;
  3233. int index = vhcr->in_modifier & 0xffff;
  3234. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  3235. if (err)
  3236. return err;
  3237. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3238. put_res(dev, slave, index, RES_COUNTER);
  3239. return err;
  3240. }
  3241. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  3242. {
  3243. struct res_gid *rgid;
  3244. struct res_gid *tmp;
  3245. struct mlx4_qp qp; /* dummy for calling attach/detach */
  3246. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  3247. switch (dev->caps.steering_mode) {
  3248. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  3249. mlx4_flow_detach(dev, rgid->reg_id);
  3250. break;
  3251. case MLX4_STEERING_MODE_B0:
  3252. qp.qpn = rqp->local_qpn;
  3253. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
  3254. rgid->prot, rgid->steer);
  3255. break;
  3256. }
  3257. list_del(&rgid->list);
  3258. kfree(rgid);
  3259. }
  3260. }
  3261. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  3262. enum mlx4_resource type, int print)
  3263. {
  3264. struct mlx4_priv *priv = mlx4_priv(dev);
  3265. struct mlx4_resource_tracker *tracker =
  3266. &priv->mfunc.master.res_tracker;
  3267. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  3268. struct res_common *r;
  3269. struct res_common *tmp;
  3270. int busy;
  3271. busy = 0;
  3272. spin_lock_irq(mlx4_tlock(dev));
  3273. list_for_each_entry_safe(r, tmp, rlist, list) {
  3274. if (r->owner == slave) {
  3275. if (!r->removing) {
  3276. if (r->state == RES_ANY_BUSY) {
  3277. if (print)
  3278. mlx4_dbg(dev,
  3279. "%s id 0x%llx is busy\n",
  3280. ResourceType(type),
  3281. r->res_id);
  3282. ++busy;
  3283. } else {
  3284. r->from_state = r->state;
  3285. r->state = RES_ANY_BUSY;
  3286. r->removing = 1;
  3287. }
  3288. }
  3289. }
  3290. }
  3291. spin_unlock_irq(mlx4_tlock(dev));
  3292. return busy;
  3293. }
  3294. static int move_all_busy(struct mlx4_dev *dev, int slave,
  3295. enum mlx4_resource type)
  3296. {
  3297. unsigned long begin;
  3298. int busy;
  3299. begin = jiffies;
  3300. do {
  3301. busy = _move_all_busy(dev, slave, type, 0);
  3302. if (time_after(jiffies, begin + 5 * HZ))
  3303. break;
  3304. if (busy)
  3305. cond_resched();
  3306. } while (busy);
  3307. if (busy)
  3308. busy = _move_all_busy(dev, slave, type, 1);
  3309. return busy;
  3310. }
  3311. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  3312. {
  3313. struct mlx4_priv *priv = mlx4_priv(dev);
  3314. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3315. struct list_head *qp_list =
  3316. &tracker->slave_list[slave].res_list[RES_QP];
  3317. struct res_qp *qp;
  3318. struct res_qp *tmp;
  3319. int state;
  3320. u64 in_param;
  3321. int qpn;
  3322. int err;
  3323. err = move_all_busy(dev, slave, RES_QP);
  3324. if (err)
  3325. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  3326. "for slave %d\n", slave);
  3327. spin_lock_irq(mlx4_tlock(dev));
  3328. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3329. spin_unlock_irq(mlx4_tlock(dev));
  3330. if (qp->com.owner == slave) {
  3331. qpn = qp->com.res_id;
  3332. detach_qp(dev, slave, qp);
  3333. state = qp->com.from_state;
  3334. while (state != 0) {
  3335. switch (state) {
  3336. case RES_QP_RESERVED:
  3337. spin_lock_irq(mlx4_tlock(dev));
  3338. rb_erase(&qp->com.node,
  3339. &tracker->res_tree[RES_QP]);
  3340. list_del(&qp->com.list);
  3341. spin_unlock_irq(mlx4_tlock(dev));
  3342. if (!valid_reserved(dev, slave, qpn)) {
  3343. __mlx4_qp_release_range(dev, qpn, 1);
  3344. mlx4_release_resource(dev, slave,
  3345. RES_QP, 1, 0);
  3346. }
  3347. kfree(qp);
  3348. state = 0;
  3349. break;
  3350. case RES_QP_MAPPED:
  3351. if (!valid_reserved(dev, slave, qpn))
  3352. __mlx4_qp_free_icm(dev, qpn);
  3353. state = RES_QP_RESERVED;
  3354. break;
  3355. case RES_QP_HW:
  3356. in_param = slave;
  3357. err = mlx4_cmd(dev, in_param,
  3358. qp->local_qpn, 2,
  3359. MLX4_CMD_2RST_QP,
  3360. MLX4_CMD_TIME_CLASS_A,
  3361. MLX4_CMD_NATIVE);
  3362. if (err)
  3363. mlx4_dbg(dev, "rem_slave_qps: failed"
  3364. " to move slave %d qpn %d to"
  3365. " reset\n", slave,
  3366. qp->local_qpn);
  3367. atomic_dec(&qp->rcq->ref_count);
  3368. atomic_dec(&qp->scq->ref_count);
  3369. atomic_dec(&qp->mtt->ref_count);
  3370. if (qp->srq)
  3371. atomic_dec(&qp->srq->ref_count);
  3372. state = RES_QP_MAPPED;
  3373. break;
  3374. default:
  3375. state = 0;
  3376. }
  3377. }
  3378. }
  3379. spin_lock_irq(mlx4_tlock(dev));
  3380. }
  3381. spin_unlock_irq(mlx4_tlock(dev));
  3382. }
  3383. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  3384. {
  3385. struct mlx4_priv *priv = mlx4_priv(dev);
  3386. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3387. struct list_head *srq_list =
  3388. &tracker->slave_list[slave].res_list[RES_SRQ];
  3389. struct res_srq *srq;
  3390. struct res_srq *tmp;
  3391. int state;
  3392. u64 in_param;
  3393. LIST_HEAD(tlist);
  3394. int srqn;
  3395. int err;
  3396. err = move_all_busy(dev, slave, RES_SRQ);
  3397. if (err)
  3398. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  3399. "busy for slave %d\n", slave);
  3400. spin_lock_irq(mlx4_tlock(dev));
  3401. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  3402. spin_unlock_irq(mlx4_tlock(dev));
  3403. if (srq->com.owner == slave) {
  3404. srqn = srq->com.res_id;
  3405. state = srq->com.from_state;
  3406. while (state != 0) {
  3407. switch (state) {
  3408. case RES_SRQ_ALLOCATED:
  3409. __mlx4_srq_free_icm(dev, srqn);
  3410. spin_lock_irq(mlx4_tlock(dev));
  3411. rb_erase(&srq->com.node,
  3412. &tracker->res_tree[RES_SRQ]);
  3413. list_del(&srq->com.list);
  3414. spin_unlock_irq(mlx4_tlock(dev));
  3415. mlx4_release_resource(dev, slave,
  3416. RES_SRQ, 1, 0);
  3417. kfree(srq);
  3418. state = 0;
  3419. break;
  3420. case RES_SRQ_HW:
  3421. in_param = slave;
  3422. err = mlx4_cmd(dev, in_param, srqn, 1,
  3423. MLX4_CMD_HW2SW_SRQ,
  3424. MLX4_CMD_TIME_CLASS_A,
  3425. MLX4_CMD_NATIVE);
  3426. if (err)
  3427. mlx4_dbg(dev, "rem_slave_srqs: failed"
  3428. " to move slave %d srq %d to"
  3429. " SW ownership\n",
  3430. slave, srqn);
  3431. atomic_dec(&srq->mtt->ref_count);
  3432. if (srq->cq)
  3433. atomic_dec(&srq->cq->ref_count);
  3434. state = RES_SRQ_ALLOCATED;
  3435. break;
  3436. default:
  3437. state = 0;
  3438. }
  3439. }
  3440. }
  3441. spin_lock_irq(mlx4_tlock(dev));
  3442. }
  3443. spin_unlock_irq(mlx4_tlock(dev));
  3444. }
  3445. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  3446. {
  3447. struct mlx4_priv *priv = mlx4_priv(dev);
  3448. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3449. struct list_head *cq_list =
  3450. &tracker->slave_list[slave].res_list[RES_CQ];
  3451. struct res_cq *cq;
  3452. struct res_cq *tmp;
  3453. int state;
  3454. u64 in_param;
  3455. LIST_HEAD(tlist);
  3456. int cqn;
  3457. int err;
  3458. err = move_all_busy(dev, slave, RES_CQ);
  3459. if (err)
  3460. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  3461. "busy for slave %d\n", slave);
  3462. spin_lock_irq(mlx4_tlock(dev));
  3463. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  3464. spin_unlock_irq(mlx4_tlock(dev));
  3465. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  3466. cqn = cq->com.res_id;
  3467. state = cq->com.from_state;
  3468. while (state != 0) {
  3469. switch (state) {
  3470. case RES_CQ_ALLOCATED:
  3471. __mlx4_cq_free_icm(dev, cqn);
  3472. spin_lock_irq(mlx4_tlock(dev));
  3473. rb_erase(&cq->com.node,
  3474. &tracker->res_tree[RES_CQ]);
  3475. list_del(&cq->com.list);
  3476. spin_unlock_irq(mlx4_tlock(dev));
  3477. mlx4_release_resource(dev, slave,
  3478. RES_CQ, 1, 0);
  3479. kfree(cq);
  3480. state = 0;
  3481. break;
  3482. case RES_CQ_HW:
  3483. in_param = slave;
  3484. err = mlx4_cmd(dev, in_param, cqn, 1,
  3485. MLX4_CMD_HW2SW_CQ,
  3486. MLX4_CMD_TIME_CLASS_A,
  3487. MLX4_CMD_NATIVE);
  3488. if (err)
  3489. mlx4_dbg(dev, "rem_slave_cqs: failed"
  3490. " to move slave %d cq %d to"
  3491. " SW ownership\n",
  3492. slave, cqn);
  3493. atomic_dec(&cq->mtt->ref_count);
  3494. state = RES_CQ_ALLOCATED;
  3495. break;
  3496. default:
  3497. state = 0;
  3498. }
  3499. }
  3500. }
  3501. spin_lock_irq(mlx4_tlock(dev));
  3502. }
  3503. spin_unlock_irq(mlx4_tlock(dev));
  3504. }
  3505. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  3506. {
  3507. struct mlx4_priv *priv = mlx4_priv(dev);
  3508. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3509. struct list_head *mpt_list =
  3510. &tracker->slave_list[slave].res_list[RES_MPT];
  3511. struct res_mpt *mpt;
  3512. struct res_mpt *tmp;
  3513. int state;
  3514. u64 in_param;
  3515. LIST_HEAD(tlist);
  3516. int mptn;
  3517. int err;
  3518. err = move_all_busy(dev, slave, RES_MPT);
  3519. if (err)
  3520. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  3521. "busy for slave %d\n", slave);
  3522. spin_lock_irq(mlx4_tlock(dev));
  3523. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  3524. spin_unlock_irq(mlx4_tlock(dev));
  3525. if (mpt->com.owner == slave) {
  3526. mptn = mpt->com.res_id;
  3527. state = mpt->com.from_state;
  3528. while (state != 0) {
  3529. switch (state) {
  3530. case RES_MPT_RESERVED:
  3531. __mlx4_mpt_release(dev, mpt->key);
  3532. spin_lock_irq(mlx4_tlock(dev));
  3533. rb_erase(&mpt->com.node,
  3534. &tracker->res_tree[RES_MPT]);
  3535. list_del(&mpt->com.list);
  3536. spin_unlock_irq(mlx4_tlock(dev));
  3537. mlx4_release_resource(dev, slave,
  3538. RES_MPT, 1, 0);
  3539. kfree(mpt);
  3540. state = 0;
  3541. break;
  3542. case RES_MPT_MAPPED:
  3543. __mlx4_mpt_free_icm(dev, mpt->key);
  3544. state = RES_MPT_RESERVED;
  3545. break;
  3546. case RES_MPT_HW:
  3547. in_param = slave;
  3548. err = mlx4_cmd(dev, in_param, mptn, 0,
  3549. MLX4_CMD_HW2SW_MPT,
  3550. MLX4_CMD_TIME_CLASS_A,
  3551. MLX4_CMD_NATIVE);
  3552. if (err)
  3553. mlx4_dbg(dev, "rem_slave_mrs: failed"
  3554. " to move slave %d mpt %d to"
  3555. " SW ownership\n",
  3556. slave, mptn);
  3557. if (mpt->mtt)
  3558. atomic_dec(&mpt->mtt->ref_count);
  3559. state = RES_MPT_MAPPED;
  3560. break;
  3561. default:
  3562. state = 0;
  3563. }
  3564. }
  3565. }
  3566. spin_lock_irq(mlx4_tlock(dev));
  3567. }
  3568. spin_unlock_irq(mlx4_tlock(dev));
  3569. }
  3570. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  3571. {
  3572. struct mlx4_priv *priv = mlx4_priv(dev);
  3573. struct mlx4_resource_tracker *tracker =
  3574. &priv->mfunc.master.res_tracker;
  3575. struct list_head *mtt_list =
  3576. &tracker->slave_list[slave].res_list[RES_MTT];
  3577. struct res_mtt *mtt;
  3578. struct res_mtt *tmp;
  3579. int state;
  3580. LIST_HEAD(tlist);
  3581. int base;
  3582. int err;
  3583. err = move_all_busy(dev, slave, RES_MTT);
  3584. if (err)
  3585. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  3586. "busy for slave %d\n", slave);
  3587. spin_lock_irq(mlx4_tlock(dev));
  3588. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  3589. spin_unlock_irq(mlx4_tlock(dev));
  3590. if (mtt->com.owner == slave) {
  3591. base = mtt->com.res_id;
  3592. state = mtt->com.from_state;
  3593. while (state != 0) {
  3594. switch (state) {
  3595. case RES_MTT_ALLOCATED:
  3596. __mlx4_free_mtt_range(dev, base,
  3597. mtt->order);
  3598. spin_lock_irq(mlx4_tlock(dev));
  3599. rb_erase(&mtt->com.node,
  3600. &tracker->res_tree[RES_MTT]);
  3601. list_del(&mtt->com.list);
  3602. spin_unlock_irq(mlx4_tlock(dev));
  3603. mlx4_release_resource(dev, slave, RES_MTT,
  3604. 1 << mtt->order, 0);
  3605. kfree(mtt);
  3606. state = 0;
  3607. break;
  3608. default:
  3609. state = 0;
  3610. }
  3611. }
  3612. }
  3613. spin_lock_irq(mlx4_tlock(dev));
  3614. }
  3615. spin_unlock_irq(mlx4_tlock(dev));
  3616. }
  3617. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3618. {
  3619. struct mlx4_priv *priv = mlx4_priv(dev);
  3620. struct mlx4_resource_tracker *tracker =
  3621. &priv->mfunc.master.res_tracker;
  3622. struct list_head *fs_rule_list =
  3623. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3624. struct res_fs_rule *fs_rule;
  3625. struct res_fs_rule *tmp;
  3626. int state;
  3627. u64 base;
  3628. int err;
  3629. err = move_all_busy(dev, slave, RES_FS_RULE);
  3630. if (err)
  3631. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3632. slave);
  3633. spin_lock_irq(mlx4_tlock(dev));
  3634. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3635. spin_unlock_irq(mlx4_tlock(dev));
  3636. if (fs_rule->com.owner == slave) {
  3637. base = fs_rule->com.res_id;
  3638. state = fs_rule->com.from_state;
  3639. while (state != 0) {
  3640. switch (state) {
  3641. case RES_FS_RULE_ALLOCATED:
  3642. /* detach rule */
  3643. err = mlx4_cmd(dev, base, 0, 0,
  3644. MLX4_QP_FLOW_STEERING_DETACH,
  3645. MLX4_CMD_TIME_CLASS_A,
  3646. MLX4_CMD_NATIVE);
  3647. spin_lock_irq(mlx4_tlock(dev));
  3648. rb_erase(&fs_rule->com.node,
  3649. &tracker->res_tree[RES_FS_RULE]);
  3650. list_del(&fs_rule->com.list);
  3651. spin_unlock_irq(mlx4_tlock(dev));
  3652. kfree(fs_rule);
  3653. state = 0;
  3654. break;
  3655. default:
  3656. state = 0;
  3657. }
  3658. }
  3659. }
  3660. spin_lock_irq(mlx4_tlock(dev));
  3661. }
  3662. spin_unlock_irq(mlx4_tlock(dev));
  3663. }
  3664. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3665. {
  3666. struct mlx4_priv *priv = mlx4_priv(dev);
  3667. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3668. struct list_head *eq_list =
  3669. &tracker->slave_list[slave].res_list[RES_EQ];
  3670. struct res_eq *eq;
  3671. struct res_eq *tmp;
  3672. int err;
  3673. int state;
  3674. LIST_HEAD(tlist);
  3675. int eqn;
  3676. struct mlx4_cmd_mailbox *mailbox;
  3677. err = move_all_busy(dev, slave, RES_EQ);
  3678. if (err)
  3679. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3680. "busy for slave %d\n", slave);
  3681. spin_lock_irq(mlx4_tlock(dev));
  3682. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3683. spin_unlock_irq(mlx4_tlock(dev));
  3684. if (eq->com.owner == slave) {
  3685. eqn = eq->com.res_id;
  3686. state = eq->com.from_state;
  3687. while (state != 0) {
  3688. switch (state) {
  3689. case RES_EQ_RESERVED:
  3690. spin_lock_irq(mlx4_tlock(dev));
  3691. rb_erase(&eq->com.node,
  3692. &tracker->res_tree[RES_EQ]);
  3693. list_del(&eq->com.list);
  3694. spin_unlock_irq(mlx4_tlock(dev));
  3695. kfree(eq);
  3696. state = 0;
  3697. break;
  3698. case RES_EQ_HW:
  3699. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3700. if (IS_ERR(mailbox)) {
  3701. cond_resched();
  3702. continue;
  3703. }
  3704. err = mlx4_cmd_box(dev, slave, 0,
  3705. eqn & 0xff, 0,
  3706. MLX4_CMD_HW2SW_EQ,
  3707. MLX4_CMD_TIME_CLASS_A,
  3708. MLX4_CMD_NATIVE);
  3709. if (err)
  3710. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3711. " to move slave %d eqs %d to"
  3712. " SW ownership\n", slave, eqn);
  3713. mlx4_free_cmd_mailbox(dev, mailbox);
  3714. atomic_dec(&eq->mtt->ref_count);
  3715. state = RES_EQ_RESERVED;
  3716. break;
  3717. default:
  3718. state = 0;
  3719. }
  3720. }
  3721. }
  3722. spin_lock_irq(mlx4_tlock(dev));
  3723. }
  3724. spin_unlock_irq(mlx4_tlock(dev));
  3725. }
  3726. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3727. {
  3728. struct mlx4_priv *priv = mlx4_priv(dev);
  3729. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3730. struct list_head *counter_list =
  3731. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3732. struct res_counter *counter;
  3733. struct res_counter *tmp;
  3734. int err;
  3735. int index;
  3736. err = move_all_busy(dev, slave, RES_COUNTER);
  3737. if (err)
  3738. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3739. "busy for slave %d\n", slave);
  3740. spin_lock_irq(mlx4_tlock(dev));
  3741. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3742. if (counter->com.owner == slave) {
  3743. index = counter->com.res_id;
  3744. rb_erase(&counter->com.node,
  3745. &tracker->res_tree[RES_COUNTER]);
  3746. list_del(&counter->com.list);
  3747. kfree(counter);
  3748. __mlx4_counter_free(dev, index);
  3749. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  3750. }
  3751. }
  3752. spin_unlock_irq(mlx4_tlock(dev));
  3753. }
  3754. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3755. {
  3756. struct mlx4_priv *priv = mlx4_priv(dev);
  3757. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3758. struct list_head *xrcdn_list =
  3759. &tracker->slave_list[slave].res_list[RES_XRCD];
  3760. struct res_xrcdn *xrcd;
  3761. struct res_xrcdn *tmp;
  3762. int err;
  3763. int xrcdn;
  3764. err = move_all_busy(dev, slave, RES_XRCD);
  3765. if (err)
  3766. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3767. "busy for slave %d\n", slave);
  3768. spin_lock_irq(mlx4_tlock(dev));
  3769. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3770. if (xrcd->com.owner == slave) {
  3771. xrcdn = xrcd->com.res_id;
  3772. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3773. list_del(&xrcd->com.list);
  3774. kfree(xrcd);
  3775. __mlx4_xrcd_free(dev, xrcdn);
  3776. }
  3777. }
  3778. spin_unlock_irq(mlx4_tlock(dev));
  3779. }
  3780. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3781. {
  3782. struct mlx4_priv *priv = mlx4_priv(dev);
  3783. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3784. rem_slave_vlans(dev, slave);
  3785. rem_slave_macs(dev, slave);
  3786. rem_slave_fs_rule(dev, slave);
  3787. rem_slave_qps(dev, slave);
  3788. rem_slave_srqs(dev, slave);
  3789. rem_slave_cqs(dev, slave);
  3790. rem_slave_mrs(dev, slave);
  3791. rem_slave_eqs(dev, slave);
  3792. rem_slave_mtts(dev, slave);
  3793. rem_slave_counters(dev, slave);
  3794. rem_slave_xrcdns(dev, slave);
  3795. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3796. }
  3797. void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
  3798. {
  3799. struct mlx4_vf_immed_vlan_work *work =
  3800. container_of(_work, struct mlx4_vf_immed_vlan_work, work);
  3801. struct mlx4_cmd_mailbox *mailbox;
  3802. struct mlx4_update_qp_context *upd_context;
  3803. struct mlx4_dev *dev = &work->priv->dev;
  3804. struct mlx4_resource_tracker *tracker =
  3805. &work->priv->mfunc.master.res_tracker;
  3806. struct list_head *qp_list =
  3807. &tracker->slave_list[work->slave].res_list[RES_QP];
  3808. struct res_qp *qp;
  3809. struct res_qp *tmp;
  3810. u64 qp_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
  3811. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
  3812. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
  3813. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
  3814. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
  3815. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED) |
  3816. (1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
  3817. (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
  3818. int err;
  3819. int port, errors = 0;
  3820. u8 vlan_control;
  3821. if (mlx4_is_slave(dev)) {
  3822. mlx4_warn(dev, "Trying to update-qp in slave %d\n",
  3823. work->slave);
  3824. goto out;
  3825. }
  3826. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3827. if (IS_ERR(mailbox))
  3828. goto out;
  3829. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
  3830. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3831. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  3832. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  3833. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  3834. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  3835. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  3836. else if (!work->vlan_id)
  3837. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3838. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  3839. else
  3840. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3841. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  3842. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  3843. upd_context = mailbox->buf;
  3844. upd_context->primary_addr_path_mask = cpu_to_be64(qp_mask);
  3845. upd_context->qp_context.pri_path.vlan_control = vlan_control;
  3846. upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
  3847. spin_lock_irq(mlx4_tlock(dev));
  3848. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3849. spin_unlock_irq(mlx4_tlock(dev));
  3850. if (qp->com.owner == work->slave) {
  3851. if (qp->com.from_state != RES_QP_HW ||
  3852. !qp->sched_queue || /* no INIT2RTR trans yet */
  3853. mlx4_is_qp_reserved(dev, qp->local_qpn) ||
  3854. qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
  3855. spin_lock_irq(mlx4_tlock(dev));
  3856. continue;
  3857. }
  3858. port = (qp->sched_queue >> 6 & 1) + 1;
  3859. if (port != work->port) {
  3860. spin_lock_irq(mlx4_tlock(dev));
  3861. continue;
  3862. }
  3863. upd_context->qp_context.pri_path.sched_queue =
  3864. qp->sched_queue & 0xC7;
  3865. upd_context->qp_context.pri_path.sched_queue |=
  3866. ((work->qos & 0x7) << 3);
  3867. err = mlx4_cmd(dev, mailbox->dma,
  3868. qp->local_qpn & 0xffffff,
  3869. 0, MLX4_CMD_UPDATE_QP,
  3870. MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
  3871. if (err) {
  3872. mlx4_info(dev, "UPDATE_QP failed for slave %d, "
  3873. "port %d, qpn %d (%d)\n",
  3874. work->slave, port, qp->local_qpn,
  3875. err);
  3876. errors++;
  3877. }
  3878. }
  3879. spin_lock_irq(mlx4_tlock(dev));
  3880. }
  3881. spin_unlock_irq(mlx4_tlock(dev));
  3882. mlx4_free_cmd_mailbox(dev, mailbox);
  3883. if (errors)
  3884. mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
  3885. errors, work->slave, work->port);
  3886. /* unregister previous vlan_id if needed and we had no errors
  3887. * while updating the QPs
  3888. */
  3889. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
  3890. NO_INDX != work->orig_vlan_ix)
  3891. __mlx4_unregister_vlan(&work->priv->dev, work->port,
  3892. work->orig_vlan_id);
  3893. out:
  3894. kfree(work);
  3895. return;
  3896. }