core.h 26 KB

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  1. /*
  2. * core.h -- Core Driver for Wolfson WM8350 PMIC
  3. *
  4. * Copyright 2007 Wolfson Microelectronics PLC
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #ifndef __LINUX_MFD_WM8350_CORE_H_
  13. #define __LINUX_MFD_WM8350_CORE_H_
  14. #include <linux/kernel.h>
  15. #include <linux/mutex.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/mfd/wm8350/audio.h>
  18. #include <linux/mfd/wm8350/gpio.h>
  19. #include <linux/mfd/wm8350/pmic.h>
  20. #include <linux/mfd/wm8350/rtc.h>
  21. #include <linux/mfd/wm8350/supply.h>
  22. #include <linux/mfd/wm8350/wdt.h>
  23. /*
  24. * Register values.
  25. */
  26. #define WM8350_RESET_ID 0x00
  27. #define WM8350_ID 0x01
  28. #define WM8350_REVISION 0x02
  29. #define WM8350_SYSTEM_CONTROL_1 0x03
  30. #define WM8350_SYSTEM_CONTROL_2 0x04
  31. #define WM8350_SYSTEM_HIBERNATE 0x05
  32. #define WM8350_INTERFACE_CONTROL 0x06
  33. #define WM8350_POWER_MGMT_1 0x08
  34. #define WM8350_POWER_MGMT_2 0x09
  35. #define WM8350_POWER_MGMT_3 0x0A
  36. #define WM8350_POWER_MGMT_4 0x0B
  37. #define WM8350_POWER_MGMT_5 0x0C
  38. #define WM8350_POWER_MGMT_6 0x0D
  39. #define WM8350_POWER_MGMT_7 0x0E
  40. #define WM8350_SYSTEM_INTERRUPTS 0x18
  41. #define WM8350_INT_STATUS_1 0x19
  42. #define WM8350_INT_STATUS_2 0x1A
  43. #define WM8350_POWER_UP_INT_STATUS 0x1B
  44. #define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C
  45. #define WM8350_OVER_CURRENT_INT_STATUS 0x1D
  46. #define WM8350_GPIO_INT_STATUS 0x1E
  47. #define WM8350_COMPARATOR_INT_STATUS 0x1F
  48. #define WM8350_SYSTEM_INTERRUPTS_MASK 0x20
  49. #define WM8350_INT_STATUS_1_MASK 0x21
  50. #define WM8350_INT_STATUS_2_MASK 0x22
  51. #define WM8350_POWER_UP_INT_STATUS_MASK 0x23
  52. #define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24
  53. #define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25
  54. #define WM8350_GPIO_INT_STATUS_MASK 0x26
  55. #define WM8350_COMPARATOR_INT_STATUS_MASK 0x27
  56. #define WM8350_CHARGER_OVERRIDES 0xE2
  57. #define WM8350_MISC_OVERRIDES 0xE3
  58. #define WM8350_COMPARATOR_OVERRIDES 0xE7
  59. #define WM8350_STATE_MACHINE_STATUS 0xE9
  60. #define WM8350_MAX_REGISTER 0xFF
  61. /*
  62. * Field Definitions.
  63. */
  64. /*
  65. * R0 (0x00) - Reset/ID
  66. */
  67. #define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF
  68. /*
  69. * R1 (0x01) - ID
  70. */
  71. #define WM8350_CHIP_REV_MASK 0x7000
  72. #define WM8350_CONF_STS_MASK 0x0C00
  73. #define WM8350_CUST_ID_MASK 0x00FF
  74. /*
  75. * R2 (0x02) - Revision
  76. */
  77. #define WM8350_MASK_REV_MASK 0x00FF
  78. /*
  79. * R3 (0x03) - System Control 1
  80. */
  81. #define WM8350_CHIP_ON 0x8000
  82. #define WM8350_POWERCYCLE 0x2000
  83. #define WM8350_VCC_FAULT_OV 0x1000
  84. #define WM8350_REG_RSTB_TIME_MASK 0x0C00
  85. #define WM8350_BG_SLEEP 0x0200
  86. #define WM8350_MEM_VALID 0x0020
  87. #define WM8350_CHIP_SET_UP 0x0010
  88. #define WM8350_ON_DEB_T 0x0008
  89. #define WM8350_ON_POL 0x0002
  90. #define WM8350_IRQ_POL 0x0001
  91. /*
  92. * R4 (0x04) - System Control 2
  93. */
  94. #define WM8350_USB_SUSPEND_8MA 0x8000
  95. #define WM8350_USB_SUSPEND 0x4000
  96. #define WM8350_USB_MSTR 0x2000
  97. #define WM8350_USB_MSTR_SRC 0x1000
  98. #define WM8350_USB_500MA 0x0800
  99. #define WM8350_USB_NOLIM 0x0400
  100. /*
  101. * R5 (0x05) - System Hibernate
  102. */
  103. #define WM8350_HIBERNATE 0x8000
  104. #define WM8350_WDOG_HIB_MODE 0x0080
  105. #define WM8350_REG_HIB_STARTUP_SEQ 0x0040
  106. #define WM8350_REG_RESET_HIB_MODE 0x0020
  107. #define WM8350_RST_HIB_MODE 0x0010
  108. #define WM8350_IRQ_HIB_MODE 0x0008
  109. #define WM8350_MEMRST_HIB_MODE 0x0004
  110. #define WM8350_PCCOMP_HIB_MODE 0x0002
  111. #define WM8350_TEMPMON_HIB_MODE 0x0001
  112. /*
  113. * R6 (0x06) - Interface Control
  114. */
  115. #define WM8350_USE_DEV_PINS 0x8000
  116. #define WM8350_USE_DEV_PINS_MASK 0x8000
  117. #define WM8350_USE_DEV_PINS_SHIFT 15
  118. #define WM8350_DEV_ADDR_MASK 0x6000
  119. #define WM8350_DEV_ADDR_SHIFT 13
  120. #define WM8350_CONFIG_DONE 0x1000
  121. #define WM8350_CONFIG_DONE_MASK 0x1000
  122. #define WM8350_CONFIG_DONE_SHIFT 12
  123. #define WM8350_RECONFIG_AT_ON 0x0800
  124. #define WM8350_RECONFIG_AT_ON_MASK 0x0800
  125. #define WM8350_RECONFIG_AT_ON_SHIFT 11
  126. #define WM8350_AUTOINC 0x0200
  127. #define WM8350_AUTOINC_MASK 0x0200
  128. #define WM8350_AUTOINC_SHIFT 9
  129. #define WM8350_ARA 0x0100
  130. #define WM8350_ARA_MASK 0x0100
  131. #define WM8350_ARA_SHIFT 8
  132. #define WM8350_SPI_CFG 0x0008
  133. #define WM8350_SPI_CFG_MASK 0x0008
  134. #define WM8350_SPI_CFG_SHIFT 3
  135. #define WM8350_SPI_4WIRE 0x0004
  136. #define WM8350_SPI_4WIRE_MASK 0x0004
  137. #define WM8350_SPI_4WIRE_SHIFT 2
  138. #define WM8350_SPI_3WIRE 0x0002
  139. #define WM8350_SPI_3WIRE_MASK 0x0002
  140. #define WM8350_SPI_3WIRE_SHIFT 1
  141. /* Bit values for R06 (0x06) */
  142. #define WM8350_USE_DEV_PINS_PRIMARY 0
  143. #define WM8350_USE_DEV_PINS_DEV 1
  144. #define WM8350_DEV_ADDR_34 0
  145. #define WM8350_DEV_ADDR_36 1
  146. #define WM8350_DEV_ADDR_3C 2
  147. #define WM8350_DEV_ADDR_3E 3
  148. #define WM8350_CONFIG_DONE_OFF 0
  149. #define WM8350_CONFIG_DONE_DONE 1
  150. #define WM8350_RECONFIG_AT_ON_OFF 0
  151. #define WM8350_RECONFIG_AT_ON_ON 1
  152. #define WM8350_AUTOINC_OFF 0
  153. #define WM8350_AUTOINC_ON 1
  154. #define WM8350_ARA_OFF 0
  155. #define WM8350_ARA_ON 1
  156. #define WM8350_SPI_CFG_CMOS 0
  157. #define WM8350_SPI_CFG_OD 1
  158. #define WM8350_SPI_4WIRE_3WIRE 0
  159. #define WM8350_SPI_4WIRE_4WIRE 1
  160. #define WM8350_SPI_3WIRE_I2C 0
  161. #define WM8350_SPI_3WIRE_SPI 1
  162. /*
  163. * R8 (0x08) - Power mgmt (1)
  164. */
  165. #define WM8350_CODEC_ISEL_MASK 0xC000
  166. #define WM8350_VBUFEN 0x2000
  167. #define WM8350_OUTPUT_DRAIN_EN 0x0400
  168. #define WM8350_MIC_DET_ENA 0x0100
  169. #define WM8350_BIASEN 0x0020
  170. #define WM8350_MICBEN 0x0010
  171. #define WM8350_VMIDEN 0x0004
  172. #define WM8350_VMID_MASK 0x0003
  173. #define WM8350_VMID_SHIFT 0
  174. /*
  175. * R9 (0x09) - Power mgmt (2)
  176. */
  177. #define WM8350_IN3R_ENA 0x0800
  178. #define WM8350_IN3L_ENA 0x0400
  179. #define WM8350_INR_ENA 0x0200
  180. #define WM8350_INL_ENA 0x0100
  181. #define WM8350_MIXINR_ENA 0x0080
  182. #define WM8350_MIXINL_ENA 0x0040
  183. #define WM8350_OUT4_ENA 0x0020
  184. #define WM8350_OUT3_ENA 0x0010
  185. #define WM8350_MIXOUTR_ENA 0x0002
  186. #define WM8350_MIXOUTL_ENA 0x0001
  187. /*
  188. * R10 (0x0A) - Power mgmt (3)
  189. */
  190. #define WM8350_IN3R_TO_OUT2R 0x0080
  191. #define WM8350_OUT2R_ENA 0x0008
  192. #define WM8350_OUT2L_ENA 0x0004
  193. #define WM8350_OUT1R_ENA 0x0002
  194. #define WM8350_OUT1L_ENA 0x0001
  195. /*
  196. * R11 (0x0B) - Power mgmt (4)
  197. */
  198. #define WM8350_SYSCLK_ENA 0x4000
  199. #define WM8350_ADC_HPF_ENA 0x2000
  200. #define WM8350_FLL_ENA 0x0800
  201. #define WM8350_FLL_OSC_ENA 0x0400
  202. #define WM8350_TOCLK_ENA 0x0100
  203. #define WM8350_DACR_ENA 0x0020
  204. #define WM8350_DACL_ENA 0x0010
  205. #define WM8350_ADCR_ENA 0x0008
  206. #define WM8350_ADCL_ENA 0x0004
  207. /*
  208. * R12 (0x0C) - Power mgmt (5)
  209. */
  210. #define WM8350_CODEC_ENA 0x1000
  211. #define WM8350_RTC_TICK_ENA 0x0800
  212. #define WM8350_OSC32K_ENA 0x0400
  213. #define WM8350_CHG_ENA 0x0200
  214. #define WM8350_ACC_DET_ENA 0x0100
  215. #define WM8350_AUXADC_ENA 0x0080
  216. #define WM8350_DCMP4_ENA 0x0008
  217. #define WM8350_DCMP3_ENA 0x0004
  218. #define WM8350_DCMP2_ENA 0x0002
  219. #define WM8350_DCMP1_ENA 0x0001
  220. /*
  221. * R13 (0x0D) - Power mgmt (6)
  222. */
  223. #define WM8350_LS_ENA 0x8000
  224. #define WM8350_LDO4_ENA 0x0800
  225. #define WM8350_LDO3_ENA 0x0400
  226. #define WM8350_LDO2_ENA 0x0200
  227. #define WM8350_LDO1_ENA 0x0100
  228. #define WM8350_DC6_ENA 0x0020
  229. #define WM8350_DC5_ENA 0x0010
  230. #define WM8350_DC4_ENA 0x0008
  231. #define WM8350_DC3_ENA 0x0004
  232. #define WM8350_DC2_ENA 0x0002
  233. #define WM8350_DC1_ENA 0x0001
  234. /*
  235. * R14 (0x0E) - Power mgmt (7)
  236. */
  237. #define WM8350_CS2_ENA 0x0002
  238. #define WM8350_CS1_ENA 0x0001
  239. /*
  240. * R24 (0x18) - System Interrupts
  241. */
  242. #define WM8350_OC_INT 0x2000
  243. #define WM8350_UV_INT 0x1000
  244. #define WM8350_PUTO_INT 0x0800
  245. #define WM8350_CS_INT 0x0200
  246. #define WM8350_EXT_INT 0x0100
  247. #define WM8350_CODEC_INT 0x0080
  248. #define WM8350_GP_INT 0x0040
  249. #define WM8350_AUXADC_INT 0x0020
  250. #define WM8350_RTC_INT 0x0010
  251. #define WM8350_SYS_INT 0x0008
  252. #define WM8350_CHG_INT 0x0004
  253. #define WM8350_USB_INT 0x0002
  254. #define WM8350_WKUP_INT 0x0001
  255. /*
  256. * R25 (0x19) - Interrupt Status 1
  257. */
  258. #define WM8350_CHG_BAT_HOT_EINT 0x8000
  259. #define WM8350_CHG_BAT_COLD_EINT 0x4000
  260. #define WM8350_CHG_BAT_FAIL_EINT 0x2000
  261. #define WM8350_CHG_TO_EINT 0x1000
  262. #define WM8350_CHG_END_EINT 0x0800
  263. #define WM8350_CHG_START_EINT 0x0400
  264. #define WM8350_CHG_FAST_RDY_EINT 0x0200
  265. #define WM8350_RTC_PER_EINT 0x0080
  266. #define WM8350_RTC_SEC_EINT 0x0040
  267. #define WM8350_RTC_ALM_EINT 0x0020
  268. #define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004
  269. #define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002
  270. #define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001
  271. /*
  272. * R26 (0x1A) - Interrupt Status 2
  273. */
  274. #define WM8350_CS1_EINT 0x2000
  275. #define WM8350_CS2_EINT 0x1000
  276. #define WM8350_USB_LIMIT_EINT 0x0400
  277. #define WM8350_AUXADC_DATARDY_EINT 0x0100
  278. #define WM8350_AUXADC_DCOMP4_EINT 0x0080
  279. #define WM8350_AUXADC_DCOMP3_EINT 0x0040
  280. #define WM8350_AUXADC_DCOMP2_EINT 0x0020
  281. #define WM8350_AUXADC_DCOMP1_EINT 0x0010
  282. #define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008
  283. #define WM8350_SYS_CHIP_GT115_EINT 0x0004
  284. #define WM8350_SYS_CHIP_GT140_EINT 0x0002
  285. #define WM8350_SYS_WDOG_TO_EINT 0x0001
  286. /*
  287. * R27 (0x1B) - Power Up Interrupt Status
  288. */
  289. #define WM8350_PUTO_LDO4_EINT 0x0800
  290. #define WM8350_PUTO_LDO3_EINT 0x0400
  291. #define WM8350_PUTO_LDO2_EINT 0x0200
  292. #define WM8350_PUTO_LDO1_EINT 0x0100
  293. #define WM8350_PUTO_DC6_EINT 0x0020
  294. #define WM8350_PUTO_DC5_EINT 0x0010
  295. #define WM8350_PUTO_DC4_EINT 0x0008
  296. #define WM8350_PUTO_DC3_EINT 0x0004
  297. #define WM8350_PUTO_DC2_EINT 0x0002
  298. #define WM8350_PUTO_DC1_EINT 0x0001
  299. /*
  300. * R28 (0x1C) - Under Voltage Interrupt status
  301. */
  302. #define WM8350_UV_LDO4_EINT 0x0800
  303. #define WM8350_UV_LDO3_EINT 0x0400
  304. #define WM8350_UV_LDO2_EINT 0x0200
  305. #define WM8350_UV_LDO1_EINT 0x0100
  306. #define WM8350_UV_DC6_EINT 0x0020
  307. #define WM8350_UV_DC5_EINT 0x0010
  308. #define WM8350_UV_DC4_EINT 0x0008
  309. #define WM8350_UV_DC3_EINT 0x0004
  310. #define WM8350_UV_DC2_EINT 0x0002
  311. #define WM8350_UV_DC1_EINT 0x0001
  312. /*
  313. * R29 (0x1D) - Over Current Interrupt status
  314. */
  315. #define WM8350_OC_LS_EINT 0x8000
  316. /*
  317. * R30 (0x1E) - GPIO Interrupt Status
  318. */
  319. #define WM8350_GP12_EINT 0x1000
  320. #define WM8350_GP11_EINT 0x0800
  321. #define WM8350_GP10_EINT 0x0400
  322. #define WM8350_GP9_EINT 0x0200
  323. #define WM8350_GP8_EINT 0x0100
  324. #define WM8350_GP7_EINT 0x0080
  325. #define WM8350_GP6_EINT 0x0040
  326. #define WM8350_GP5_EINT 0x0020
  327. #define WM8350_GP4_EINT 0x0010
  328. #define WM8350_GP3_EINT 0x0008
  329. #define WM8350_GP2_EINT 0x0004
  330. #define WM8350_GP1_EINT 0x0002
  331. #define WM8350_GP0_EINT 0x0001
  332. /*
  333. * R31 (0x1F) - Comparator Interrupt Status
  334. */
  335. #define WM8350_EXT_USB_FB_EINT 0x8000
  336. #define WM8350_EXT_WALL_FB_EINT 0x4000
  337. #define WM8350_EXT_BAT_FB_EINT 0x2000
  338. #define WM8350_CODEC_JCK_DET_L_EINT 0x0800
  339. #define WM8350_CODEC_JCK_DET_R_EINT 0x0400
  340. #define WM8350_CODEC_MICSCD_EINT 0x0200
  341. #define WM8350_CODEC_MICD_EINT 0x0100
  342. #define WM8350_WKUP_OFF_STATE_EINT 0x0040
  343. #define WM8350_WKUP_HIB_STATE_EINT 0x0020
  344. #define WM8350_WKUP_CONV_FAULT_EINT 0x0010
  345. #define WM8350_WKUP_WDOG_RST_EINT 0x0008
  346. #define WM8350_WKUP_GP_PWR_ON_EINT 0x0004
  347. #define WM8350_WKUP_ONKEY_EINT 0x0002
  348. #define WM8350_WKUP_GP_WAKEUP_EINT 0x0001
  349. /*
  350. * R32 (0x20) - System Interrupts Mask
  351. */
  352. #define WM8350_IM_OC_INT 0x2000
  353. #define WM8350_IM_UV_INT 0x1000
  354. #define WM8350_IM_PUTO_INT 0x0800
  355. #define WM8350_IM_SPARE_INT 0x0400
  356. #define WM8350_IM_CS_INT 0x0200
  357. #define WM8350_IM_EXT_INT 0x0100
  358. #define WM8350_IM_CODEC_INT 0x0080
  359. #define WM8350_IM_GP_INT 0x0040
  360. #define WM8350_IM_AUXADC_INT 0x0020
  361. #define WM8350_IM_RTC_INT 0x0010
  362. #define WM8350_IM_SYS_INT 0x0008
  363. #define WM8350_IM_CHG_INT 0x0004
  364. #define WM8350_IM_USB_INT 0x0002
  365. #define WM8350_IM_WKUP_INT 0x0001
  366. /*
  367. * R33 (0x21) - Interrupt Status 1 Mask
  368. */
  369. #define WM8350_IM_CHG_BAT_HOT_EINT 0x8000
  370. #define WM8350_IM_CHG_BAT_COLD_EINT 0x4000
  371. #define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000
  372. #define WM8350_IM_CHG_TO_EINT 0x1000
  373. #define WM8350_IM_CHG_END_EINT 0x0800
  374. #define WM8350_IM_CHG_START_EINT 0x0400
  375. #define WM8350_IM_CHG_FAST_RDY_EINT 0x0200
  376. #define WM8350_IM_RTC_PER_EINT 0x0080
  377. #define WM8350_IM_RTC_SEC_EINT 0x0040
  378. #define WM8350_IM_RTC_ALM_EINT 0x0020
  379. #define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004
  380. #define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002
  381. #define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001
  382. /*
  383. * R34 (0x22) - Interrupt Status 2 Mask
  384. */
  385. #define WM8350_IM_SPARE2_EINT 0x8000
  386. #define WM8350_IM_SPARE1_EINT 0x4000
  387. #define WM8350_IM_CS1_EINT 0x2000
  388. #define WM8350_IM_CS2_EINT 0x1000
  389. #define WM8350_IM_USB_LIMIT_EINT 0x0400
  390. #define WM8350_IM_AUXADC_DATARDY_EINT 0x0100
  391. #define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080
  392. #define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040
  393. #define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020
  394. #define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010
  395. #define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008
  396. #define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004
  397. #define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002
  398. #define WM8350_IM_SYS_WDOG_TO_EINT 0x0001
  399. /*
  400. * R35 (0x23) - Power Up Interrupt Status Mask
  401. */
  402. #define WM8350_IM_PUTO_LDO4_EINT 0x0800
  403. #define WM8350_IM_PUTO_LDO3_EINT 0x0400
  404. #define WM8350_IM_PUTO_LDO2_EINT 0x0200
  405. #define WM8350_IM_PUTO_LDO1_EINT 0x0100
  406. #define WM8350_IM_PUTO_DC6_EINT 0x0020
  407. #define WM8350_IM_PUTO_DC5_EINT 0x0010
  408. #define WM8350_IM_PUTO_DC4_EINT 0x0008
  409. #define WM8350_IM_PUTO_DC3_EINT 0x0004
  410. #define WM8350_IM_PUTO_DC2_EINT 0x0002
  411. #define WM8350_IM_PUTO_DC1_EINT 0x0001
  412. /*
  413. * R36 (0x24) - Under Voltage Interrupt status Mask
  414. */
  415. #define WM8350_IM_UV_LDO4_EINT 0x0800
  416. #define WM8350_IM_UV_LDO3_EINT 0x0400
  417. #define WM8350_IM_UV_LDO2_EINT 0x0200
  418. #define WM8350_IM_UV_LDO1_EINT 0x0100
  419. #define WM8350_IM_UV_DC6_EINT 0x0020
  420. #define WM8350_IM_UV_DC5_EINT 0x0010
  421. #define WM8350_IM_UV_DC4_EINT 0x0008
  422. #define WM8350_IM_UV_DC3_EINT 0x0004
  423. #define WM8350_IM_UV_DC2_EINT 0x0002
  424. #define WM8350_IM_UV_DC1_EINT 0x0001
  425. /*
  426. * R37 (0x25) - Over Current Interrupt status Mask
  427. */
  428. #define WM8350_IM_OC_LS_EINT 0x8000
  429. /*
  430. * R38 (0x26) - GPIO Interrupt Status Mask
  431. */
  432. #define WM8350_IM_GP12_EINT 0x1000
  433. #define WM8350_IM_GP11_EINT 0x0800
  434. #define WM8350_IM_GP10_EINT 0x0400
  435. #define WM8350_IM_GP9_EINT 0x0200
  436. #define WM8350_IM_GP8_EINT 0x0100
  437. #define WM8350_IM_GP7_EINT 0x0080
  438. #define WM8350_IM_GP6_EINT 0x0040
  439. #define WM8350_IM_GP5_EINT 0x0020
  440. #define WM8350_IM_GP4_EINT 0x0010
  441. #define WM8350_IM_GP3_EINT 0x0008
  442. #define WM8350_IM_GP2_EINT 0x0004
  443. #define WM8350_IM_GP1_EINT 0x0002
  444. #define WM8350_IM_GP0_EINT 0x0001
  445. /*
  446. * R39 (0x27) - Comparator Interrupt Status Mask
  447. */
  448. #define WM8350_IM_EXT_USB_FB_EINT 0x8000
  449. #define WM8350_IM_EXT_WALL_FB_EINT 0x4000
  450. #define WM8350_IM_EXT_BAT_FB_EINT 0x2000
  451. #define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800
  452. #define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400
  453. #define WM8350_IM_CODEC_MICSCD_EINT 0x0200
  454. #define WM8350_IM_CODEC_MICD_EINT 0x0100
  455. #define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040
  456. #define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020
  457. #define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010
  458. #define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008
  459. #define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004
  460. #define WM8350_IM_WKUP_ONKEY_EINT 0x0002
  461. #define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001
  462. /*
  463. * R220 (0xDC) - RAM BIST 1
  464. */
  465. #define WM8350_READ_STATUS 0x0800
  466. #define WM8350_TSTRAM_CLK 0x0100
  467. #define WM8350_TSTRAM_CLK_ENA 0x0080
  468. #define WM8350_STARTSEQ 0x0040
  469. #define WM8350_READ_SRC 0x0020
  470. #define WM8350_COUNT_DIR 0x0010
  471. #define WM8350_TSTRAM_MODE_MASK 0x000E
  472. #define WM8350_TSTRAM_ENA 0x0001
  473. /*
  474. * R225 (0xE1) - DCDC/LDO status
  475. */
  476. #define WM8350_LS_STS 0x8000
  477. #define WM8350_LDO4_STS 0x0800
  478. #define WM8350_LDO3_STS 0x0400
  479. #define WM8350_LDO2_STS 0x0200
  480. #define WM8350_LDO1_STS 0x0100
  481. #define WM8350_DC6_STS 0x0020
  482. #define WM8350_DC5_STS 0x0010
  483. #define WM8350_DC4_STS 0x0008
  484. #define WM8350_DC3_STS 0x0004
  485. #define WM8350_DC2_STS 0x0002
  486. #define WM8350_DC1_STS 0x0001
  487. /*
  488. * R226 (0xE2) - Charger status
  489. */
  490. #define WM8350_CHG_BATT_HOT_OVRDE 0x8000
  491. #define WM8350_CHG_BATT_COLD_OVRDE 0x4000
  492. /*
  493. * R227 (0xE3) - Misc Overrides
  494. */
  495. #define WM8350_USB_LIMIT_OVRDE 0x0400
  496. /*
  497. * R227 (0xE7) - Comparator Overrides
  498. */
  499. #define WM8350_USB_FB_OVRDE 0x8000
  500. #define WM8350_WALL_FB_OVRDE 0x4000
  501. #define WM8350_BATT_FB_OVRDE 0x2000
  502. /*
  503. * R233 (0xE9) - State Machinine Status
  504. */
  505. #define WM8350_USB_SM_MASK 0x0700
  506. #define WM8350_USB_SM_SHIFT 8
  507. #define WM8350_USB_SM_100_SLV 1
  508. #define WM8350_USB_SM_500_SLV 5
  509. #define WM8350_USB_SM_STDBY_SLV 7
  510. /* WM8350 wake up conditions */
  511. #define WM8350_IRQ_WKUP_OFF_STATE 43
  512. #define WM8350_IRQ_WKUP_HIB_STATE 44
  513. #define WM8350_IRQ_WKUP_CONV_FAULT 45
  514. #define WM8350_IRQ_WKUP_WDOG_RST 46
  515. #define WM8350_IRQ_WKUP_GP_PWR_ON 47
  516. #define WM8350_IRQ_WKUP_ONKEY 48
  517. #define WM8350_IRQ_WKUP_GP_WAKEUP 49
  518. /* wm8350 chip revisions */
  519. #define WM8350_REV_E 0x4
  520. #define WM8350_REV_F 0x5
  521. #define WM8350_REV_G 0x6
  522. #define WM8350_REV_H 0x7
  523. #define WM8350_NUM_IRQ 63
  524. struct wm8350_reg_access {
  525. u16 readable; /* Mask of readable bits */
  526. u16 writable; /* Mask of writable bits */
  527. u16 vol; /* Mask of volatile bits */
  528. };
  529. extern const struct wm8350_reg_access wm8350_reg_io_map[];
  530. extern const u16 wm8350_mode0_defaults[];
  531. extern const u16 wm8350_mode1_defaults[];
  532. extern const u16 wm8350_mode2_defaults[];
  533. extern const u16 wm8350_mode3_defaults[];
  534. extern const u16 wm8351_mode0_defaults[];
  535. extern const u16 wm8351_mode1_defaults[];
  536. extern const u16 wm8351_mode2_defaults[];
  537. extern const u16 wm8351_mode3_defaults[];
  538. extern const u16 wm8352_mode0_defaults[];
  539. extern const u16 wm8352_mode1_defaults[];
  540. extern const u16 wm8352_mode2_defaults[];
  541. extern const u16 wm8352_mode3_defaults[];
  542. struct wm8350;
  543. struct wm8350_irq {
  544. irq_handler_t handler;
  545. void *data;
  546. };
  547. struct wm8350_hwmon {
  548. struct platform_device *pdev;
  549. struct device *classdev;
  550. };
  551. struct wm8350 {
  552. struct device *dev;
  553. /* device IO */
  554. union {
  555. struct i2c_client *i2c_client;
  556. struct spi_device *spi_device;
  557. };
  558. int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
  559. int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
  560. void *src);
  561. u16 *reg_cache;
  562. struct mutex auxadc_mutex;
  563. /* Interrupt handling */
  564. struct mutex irq_mutex; /* IRQ table mutex */
  565. struct wm8350_irq irq[WM8350_NUM_IRQ];
  566. int chip_irq;
  567. /* Client devices */
  568. struct wm8350_codec codec;
  569. struct wm8350_gpio gpio;
  570. struct wm8350_hwmon hwmon;
  571. struct wm8350_pmic pmic;
  572. struct wm8350_power power;
  573. struct wm8350_rtc rtc;
  574. struct wm8350_wdt wdt;
  575. };
  576. /**
  577. * Data to be supplied by the platform to initialise the WM8350.
  578. *
  579. * @init: Function called during driver initialisation. Should be
  580. * used by the platform to configure GPIO functions and similar.
  581. * @irq_high: Set if WM8350 IRQ is active high.
  582. * @irq_base: Base IRQ for genirq (not currently used).
  583. */
  584. struct wm8350_platform_data {
  585. int (*init)(struct wm8350 *wm8350);
  586. int irq_high;
  587. int irq_base;
  588. };
  589. /*
  590. * WM8350 device initialisation and exit.
  591. */
  592. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  593. struct wm8350_platform_data *pdata);
  594. void wm8350_device_exit(struct wm8350 *wm8350);
  595. /*
  596. * WM8350 device IO
  597. */
  598. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
  599. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
  600. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
  601. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
  602. int wm8350_reg_lock(struct wm8350 *wm8350);
  603. int wm8350_reg_unlock(struct wm8350 *wm8350);
  604. int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
  605. int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
  606. /*
  607. * WM8350 internal interrupts
  608. */
  609. int wm8350_register_irq(struct wm8350 *wm8350, int irq,
  610. irq_handler_t handler, unsigned long flags,
  611. const char *name, void *data);
  612. int wm8350_free_irq(struct wm8350 *wm8350, int irq);
  613. int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
  614. int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
  615. int wm8350_irq_init(struct wm8350 *wm8350, int irq,
  616. struct wm8350_platform_data *pdata);
  617. int wm8350_irq_exit(struct wm8350 *wm8350);
  618. #endif