qla_mbx.c 129 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/gfp.h>
  11. /*
  12. * qla2x00_mailbox_command
  13. * Issue mailbox command and waits for completion.
  14. *
  15. * Input:
  16. * ha = adapter block pointer.
  17. * mcp = driver internal mbx struct pointer.
  18. *
  19. * Output:
  20. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  21. *
  22. * Returns:
  23. * 0 : QLA_SUCCESS = cmd performed success
  24. * 1 : QLA_FUNCTION_FAILED (error encountered)
  25. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  26. *
  27. * Context:
  28. * Kernel context.
  29. */
  30. static int
  31. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  32. {
  33. int rval;
  34. unsigned long flags = 0;
  35. device_reg_t __iomem *reg;
  36. uint8_t abort_active;
  37. uint8_t io_lock_on;
  38. uint16_t command = 0;
  39. uint16_t *iptr;
  40. uint16_t __iomem *optr;
  41. uint32_t cnt;
  42. uint32_t mboxes;
  43. unsigned long wait_time;
  44. struct qla_hw_data *ha = vha->hw;
  45. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  46. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  47. if (ha->pdev->error_state > pci_channel_io_frozen) {
  48. ql_log(ql_log_warn, vha, 0x1001,
  49. "error_state is greater than pci_channel_io_frozen, "
  50. "exiting.\n");
  51. return QLA_FUNCTION_TIMEOUT;
  52. }
  53. if (vha->device_flags & DFLG_DEV_FAILED) {
  54. ql_log(ql_log_warn, vha, 0x1002,
  55. "Device in failed state, exiting.\n");
  56. return QLA_FUNCTION_TIMEOUT;
  57. }
  58. reg = ha->iobase;
  59. io_lock_on = base_vha->flags.init_done;
  60. rval = QLA_SUCCESS;
  61. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  62. if (ha->flags.pci_channel_io_perm_failure) {
  63. ql_log(ql_log_warn, vha, 0x1003,
  64. "Perm failure on EEH timeout MBX, exiting.\n");
  65. return QLA_FUNCTION_TIMEOUT;
  66. }
  67. if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
  68. /* Setting Link-Down error */
  69. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  70. ql_log(ql_log_warn, vha, 0x1004,
  71. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  72. return QLA_FUNCTION_TIMEOUT;
  73. }
  74. /*
  75. * Wait for active mailbox commands to finish by waiting at most tov
  76. * seconds. This is to serialize actual issuing of mailbox cmds during
  77. * non ISP abort time.
  78. */
  79. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  80. /* Timeout occurred. Return error. */
  81. ql_log(ql_log_warn, vha, 0x1005,
  82. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  83. mcp->mb[0]);
  84. return QLA_FUNCTION_TIMEOUT;
  85. }
  86. ha->flags.mbox_busy = 1;
  87. /* Save mailbox command for debug */
  88. ha->mcp = mcp;
  89. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  90. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  91. spin_lock_irqsave(&ha->hardware_lock, flags);
  92. /* Load mailbox registers. */
  93. if (IS_P3P_TYPE(ha))
  94. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  95. else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
  96. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  97. else
  98. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  99. iptr = mcp->mb;
  100. command = mcp->mb[0];
  101. mboxes = mcp->out_mb;
  102. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  103. if (IS_QLA2200(ha) && cnt == 8)
  104. optr =
  105. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  106. if (mboxes & BIT_0)
  107. WRT_REG_WORD(optr, *iptr);
  108. mboxes >>= 1;
  109. optr++;
  110. iptr++;
  111. }
  112. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
  113. "Loaded MBX registers (displayed in bytes) =.\n");
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
  115. (uint8_t *)mcp->mb, 16);
  116. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
  117. ".\n");
  118. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
  119. ((uint8_t *)mcp->mb + 0x10), 16);
  120. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
  121. ".\n");
  122. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
  123. ((uint8_t *)mcp->mb + 0x20), 8);
  124. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  125. "I/O Address = %p.\n", optr);
  126. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
  127. /* Issue set host interrupt command to send cmd out. */
  128. ha->flags.mbox_int = 0;
  129. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  130. /* Unlock mbx registers and wait for interrupt */
  131. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  132. "Going to unlock irq & waiting for interrupts. "
  133. "jiffies=%lx.\n", jiffies);
  134. /* Wait for mbx cmd completion until timeout */
  135. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  136. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  137. if (IS_P3P_TYPE(ha)) {
  138. if (RD_REG_DWORD(&reg->isp82.hint) &
  139. HINT_MBX_INT_PENDING) {
  140. spin_unlock_irqrestore(&ha->hardware_lock,
  141. flags);
  142. ha->flags.mbox_busy = 0;
  143. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  144. "Pending mailbox timeout, exiting.\n");
  145. rval = QLA_FUNCTION_TIMEOUT;
  146. goto premature_exit;
  147. }
  148. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  149. } else if (IS_FWI2_CAPABLE(ha))
  150. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  151. else
  152. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  153. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  154. if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
  155. mcp->tov * HZ)) {
  156. ql_dbg(ql_dbg_mbx, vha, 0x117a,
  157. "cmd=%x Timeout.\n", command);
  158. spin_lock_irqsave(&ha->hardware_lock, flags);
  159. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  160. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  161. }
  162. } else {
  163. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  164. "Cmd=%x Polling Mode.\n", command);
  165. if (IS_P3P_TYPE(ha)) {
  166. if (RD_REG_DWORD(&reg->isp82.hint) &
  167. HINT_MBX_INT_PENDING) {
  168. spin_unlock_irqrestore(&ha->hardware_lock,
  169. flags);
  170. ha->flags.mbox_busy = 0;
  171. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  172. "Pending mailbox timeout, exiting.\n");
  173. rval = QLA_FUNCTION_TIMEOUT;
  174. goto premature_exit;
  175. }
  176. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  177. } else if (IS_FWI2_CAPABLE(ha))
  178. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  179. else
  180. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  181. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  182. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  183. while (!ha->flags.mbox_int) {
  184. if (time_after(jiffies, wait_time))
  185. break;
  186. /* Check for pending interrupts. */
  187. qla2x00_poll(ha->rsp_q_map[0]);
  188. if (!ha->flags.mbox_int &&
  189. !(IS_QLA2200(ha) &&
  190. command == MBC_LOAD_RISC_RAM_EXTENDED))
  191. msleep(10);
  192. } /* while */
  193. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  194. "Waited %d sec.\n",
  195. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  196. }
  197. /* Check whether we timed out */
  198. if (ha->flags.mbox_int) {
  199. uint16_t *iptr2;
  200. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  201. "Cmd=%x completed.\n", command);
  202. /* Got interrupt. Clear the flag. */
  203. ha->flags.mbox_int = 0;
  204. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  205. if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
  206. ha->flags.mbox_busy = 0;
  207. /* Setting Link-Down error */
  208. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  209. ha->mcp = NULL;
  210. rval = QLA_FUNCTION_FAILED;
  211. ql_log(ql_log_warn, vha, 0x1015,
  212. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  213. goto premature_exit;
  214. }
  215. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  216. rval = QLA_FUNCTION_FAILED;
  217. /* Load return mailbox registers. */
  218. iptr2 = mcp->mb;
  219. iptr = (uint16_t *)&ha->mailbox_out[0];
  220. mboxes = mcp->in_mb;
  221. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  222. if (mboxes & BIT_0)
  223. *iptr2 = *iptr;
  224. mboxes >>= 1;
  225. iptr2++;
  226. iptr++;
  227. }
  228. } else {
  229. uint16_t mb0;
  230. uint32_t ictrl;
  231. if (IS_FWI2_CAPABLE(ha)) {
  232. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  233. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  234. } else {
  235. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  236. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  237. }
  238. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  239. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  240. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  241. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  242. /*
  243. * Attempt to capture a firmware dump for further analysis
  244. * of the current firmware state. We do not need to do this
  245. * if we are intentionally generating a dump.
  246. */
  247. if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
  248. ha->isp_ops->fw_dump(vha, 0);
  249. rval = QLA_FUNCTION_TIMEOUT;
  250. }
  251. ha->flags.mbox_busy = 0;
  252. /* Clean up */
  253. ha->mcp = NULL;
  254. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  255. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  256. "Checking for additional resp interrupt.\n");
  257. /* polling mode for non isp_abort commands. */
  258. qla2x00_poll(ha->rsp_q_map[0]);
  259. }
  260. if (rval == QLA_FUNCTION_TIMEOUT &&
  261. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  262. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  263. ha->flags.eeh_busy) {
  264. /* not in dpc. schedule it for dpc to take over. */
  265. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  266. "Timeout, schedule isp_abort_needed.\n");
  267. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  268. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  269. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  270. if (IS_QLA82XX(ha)) {
  271. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  272. "disabling pause transmit on port "
  273. "0 & 1.\n");
  274. qla82xx_wr_32(ha,
  275. QLA82XX_CRB_NIU + 0x98,
  276. CRB_NIU_XG_PAUSE_CTL_P0|
  277. CRB_NIU_XG_PAUSE_CTL_P1);
  278. }
  279. ql_log(ql_log_info, base_vha, 0x101c,
  280. "Mailbox cmd timeout occurred, cmd=0x%x, "
  281. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  282. "abort.\n", command, mcp->mb[0],
  283. ha->flags.eeh_busy);
  284. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  285. qla2xxx_wake_dpc(vha);
  286. }
  287. } else if (!abort_active) {
  288. /* call abort directly since we are in the DPC thread */
  289. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  290. "Timeout, calling abort_isp.\n");
  291. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  292. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  293. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  294. if (IS_QLA82XX(ha)) {
  295. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  296. "disabling pause transmit on port "
  297. "0 & 1.\n");
  298. qla82xx_wr_32(ha,
  299. QLA82XX_CRB_NIU + 0x98,
  300. CRB_NIU_XG_PAUSE_CTL_P0|
  301. CRB_NIU_XG_PAUSE_CTL_P1);
  302. }
  303. ql_log(ql_log_info, base_vha, 0x101e,
  304. "Mailbox cmd timeout occurred, cmd=0x%x, "
  305. "mb[0]=0x%x. Scheduling ISP abort ",
  306. command, mcp->mb[0]);
  307. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  308. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  309. /* Allow next mbx cmd to come in. */
  310. complete(&ha->mbx_cmd_comp);
  311. if (ha->isp_ops->abort_isp(vha)) {
  312. /* Failed. retry later. */
  313. set_bit(ISP_ABORT_NEEDED,
  314. &vha->dpc_flags);
  315. }
  316. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  317. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  318. "Finished abort_isp.\n");
  319. goto mbx_done;
  320. }
  321. }
  322. }
  323. premature_exit:
  324. /* Allow next mbx cmd to come in. */
  325. complete(&ha->mbx_cmd_comp);
  326. mbx_done:
  327. if (rval) {
  328. ql_log(ql_log_warn, base_vha, 0x1020,
  329. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  330. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  331. } else {
  332. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  333. }
  334. return rval;
  335. }
  336. int
  337. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  338. uint32_t risc_code_size)
  339. {
  340. int rval;
  341. struct qla_hw_data *ha = vha->hw;
  342. mbx_cmd_t mc;
  343. mbx_cmd_t *mcp = &mc;
  344. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  345. "Entered %s.\n", __func__);
  346. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  347. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  348. mcp->mb[8] = MSW(risc_addr);
  349. mcp->out_mb = MBX_8|MBX_0;
  350. } else {
  351. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  352. mcp->out_mb = MBX_0;
  353. }
  354. mcp->mb[1] = LSW(risc_addr);
  355. mcp->mb[2] = MSW(req_dma);
  356. mcp->mb[3] = LSW(req_dma);
  357. mcp->mb[6] = MSW(MSD(req_dma));
  358. mcp->mb[7] = LSW(MSD(req_dma));
  359. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  360. if (IS_FWI2_CAPABLE(ha)) {
  361. mcp->mb[4] = MSW(risc_code_size);
  362. mcp->mb[5] = LSW(risc_code_size);
  363. mcp->out_mb |= MBX_5|MBX_4;
  364. } else {
  365. mcp->mb[4] = LSW(risc_code_size);
  366. mcp->out_mb |= MBX_4;
  367. }
  368. mcp->in_mb = MBX_0;
  369. mcp->tov = MBX_TOV_SECONDS;
  370. mcp->flags = 0;
  371. rval = qla2x00_mailbox_command(vha, mcp);
  372. if (rval != QLA_SUCCESS) {
  373. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  374. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  375. } else {
  376. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  377. "Done %s.\n", __func__);
  378. }
  379. return rval;
  380. }
  381. #define EXTENDED_BB_CREDITS BIT_0
  382. /*
  383. * qla2x00_execute_fw
  384. * Start adapter firmware.
  385. *
  386. * Input:
  387. * ha = adapter block pointer.
  388. * TARGET_QUEUE_LOCK must be released.
  389. * ADAPTER_STATE_LOCK must be released.
  390. *
  391. * Returns:
  392. * qla2x00 local function return status code.
  393. *
  394. * Context:
  395. * Kernel context.
  396. */
  397. int
  398. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  399. {
  400. int rval;
  401. struct qla_hw_data *ha = vha->hw;
  402. mbx_cmd_t mc;
  403. mbx_cmd_t *mcp = &mc;
  404. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  405. "Entered %s.\n", __func__);
  406. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  407. mcp->out_mb = MBX_0;
  408. mcp->in_mb = MBX_0;
  409. if (IS_FWI2_CAPABLE(ha)) {
  410. mcp->mb[1] = MSW(risc_addr);
  411. mcp->mb[2] = LSW(risc_addr);
  412. mcp->mb[3] = 0;
  413. if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
  414. struct nvram_81xx *nv = ha->nvram;
  415. mcp->mb[4] = (nv->enhanced_features &
  416. EXTENDED_BB_CREDITS);
  417. } else
  418. mcp->mb[4] = 0;
  419. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  420. mcp->in_mb |= MBX_1;
  421. } else {
  422. mcp->mb[1] = LSW(risc_addr);
  423. mcp->out_mb |= MBX_1;
  424. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  425. mcp->mb[2] = 0;
  426. mcp->out_mb |= MBX_2;
  427. }
  428. }
  429. mcp->tov = MBX_TOV_SECONDS;
  430. mcp->flags = 0;
  431. rval = qla2x00_mailbox_command(vha, mcp);
  432. if (rval != QLA_SUCCESS) {
  433. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  434. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  435. } else {
  436. if (IS_FWI2_CAPABLE(ha)) {
  437. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  438. "Done exchanges=%x.\n", mcp->mb[1]);
  439. } else {
  440. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  441. "Done %s.\n", __func__);
  442. }
  443. }
  444. return rval;
  445. }
  446. /*
  447. * qla2x00_get_fw_version
  448. * Get firmware version.
  449. *
  450. * Input:
  451. * ha: adapter state pointer.
  452. * major: pointer for major number.
  453. * minor: pointer for minor number.
  454. * subminor: pointer for subminor number.
  455. *
  456. * Returns:
  457. * qla2x00 local function return status code.
  458. *
  459. * Context:
  460. * Kernel context.
  461. */
  462. int
  463. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  464. {
  465. int rval;
  466. mbx_cmd_t mc;
  467. mbx_cmd_t *mcp = &mc;
  468. struct qla_hw_data *ha = vha->hw;
  469. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  470. "Entered %s.\n", __func__);
  471. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  472. mcp->out_mb = MBX_0;
  473. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  474. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
  475. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  476. if (IS_FWI2_CAPABLE(ha))
  477. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  478. mcp->flags = 0;
  479. mcp->tov = MBX_TOV_SECONDS;
  480. rval = qla2x00_mailbox_command(vha, mcp);
  481. if (rval != QLA_SUCCESS)
  482. goto failed;
  483. /* Return mailbox data. */
  484. ha->fw_major_version = mcp->mb[1];
  485. ha->fw_minor_version = mcp->mb[2];
  486. ha->fw_subminor_version = mcp->mb[3];
  487. ha->fw_attributes = mcp->mb[6];
  488. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  489. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  490. else
  491. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  492. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  493. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  494. ha->mpi_version[1] = mcp->mb[11] >> 8;
  495. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  496. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  497. ha->phy_version[0] = mcp->mb[8] & 0xff;
  498. ha->phy_version[1] = mcp->mb[9] >> 8;
  499. ha->phy_version[2] = mcp->mb[9] & 0xff;
  500. }
  501. if (IS_FWI2_CAPABLE(ha)) {
  502. ha->fw_attributes_h = mcp->mb[15];
  503. ha->fw_attributes_ext[0] = mcp->mb[16];
  504. ha->fw_attributes_ext[1] = mcp->mb[17];
  505. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  506. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  507. __func__, mcp->mb[15], mcp->mb[6]);
  508. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  509. "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
  510. __func__, mcp->mb[17], mcp->mb[16]);
  511. }
  512. failed:
  513. if (rval != QLA_SUCCESS) {
  514. /*EMPTY*/
  515. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  516. } else {
  517. /*EMPTY*/
  518. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  519. "Done %s.\n", __func__);
  520. }
  521. return rval;
  522. }
  523. /*
  524. * qla2x00_get_fw_options
  525. * Set firmware options.
  526. *
  527. * Input:
  528. * ha = adapter block pointer.
  529. * fwopt = pointer for firmware options.
  530. *
  531. * Returns:
  532. * qla2x00 local function return status code.
  533. *
  534. * Context:
  535. * Kernel context.
  536. */
  537. int
  538. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  539. {
  540. int rval;
  541. mbx_cmd_t mc;
  542. mbx_cmd_t *mcp = &mc;
  543. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  544. "Entered %s.\n", __func__);
  545. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  546. mcp->out_mb = MBX_0;
  547. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  548. mcp->tov = MBX_TOV_SECONDS;
  549. mcp->flags = 0;
  550. rval = qla2x00_mailbox_command(vha, mcp);
  551. if (rval != QLA_SUCCESS) {
  552. /*EMPTY*/
  553. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  554. } else {
  555. fwopts[0] = mcp->mb[0];
  556. fwopts[1] = mcp->mb[1];
  557. fwopts[2] = mcp->mb[2];
  558. fwopts[3] = mcp->mb[3];
  559. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  560. "Done %s.\n", __func__);
  561. }
  562. return rval;
  563. }
  564. /*
  565. * qla2x00_set_fw_options
  566. * Set firmware options.
  567. *
  568. * Input:
  569. * ha = adapter block pointer.
  570. * fwopt = pointer for firmware options.
  571. *
  572. * Returns:
  573. * qla2x00 local function return status code.
  574. *
  575. * Context:
  576. * Kernel context.
  577. */
  578. int
  579. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  580. {
  581. int rval;
  582. mbx_cmd_t mc;
  583. mbx_cmd_t *mcp = &mc;
  584. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  585. "Entered %s.\n", __func__);
  586. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  587. mcp->mb[1] = fwopts[1];
  588. mcp->mb[2] = fwopts[2];
  589. mcp->mb[3] = fwopts[3];
  590. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  591. mcp->in_mb = MBX_0;
  592. if (IS_FWI2_CAPABLE(vha->hw)) {
  593. mcp->in_mb |= MBX_1;
  594. } else {
  595. mcp->mb[10] = fwopts[10];
  596. mcp->mb[11] = fwopts[11];
  597. mcp->mb[12] = 0; /* Undocumented, but used */
  598. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  599. }
  600. mcp->tov = MBX_TOV_SECONDS;
  601. mcp->flags = 0;
  602. rval = qla2x00_mailbox_command(vha, mcp);
  603. fwopts[0] = mcp->mb[0];
  604. if (rval != QLA_SUCCESS) {
  605. /*EMPTY*/
  606. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  607. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  608. } else {
  609. /*EMPTY*/
  610. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  611. "Done %s.\n", __func__);
  612. }
  613. return rval;
  614. }
  615. /*
  616. * qla2x00_mbx_reg_test
  617. * Mailbox register wrap test.
  618. *
  619. * Input:
  620. * ha = adapter block pointer.
  621. * TARGET_QUEUE_LOCK must be released.
  622. * ADAPTER_STATE_LOCK must be released.
  623. *
  624. * Returns:
  625. * qla2x00 local function return status code.
  626. *
  627. * Context:
  628. * Kernel context.
  629. */
  630. int
  631. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  632. {
  633. int rval;
  634. mbx_cmd_t mc;
  635. mbx_cmd_t *mcp = &mc;
  636. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  637. "Entered %s.\n", __func__);
  638. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  639. mcp->mb[1] = 0xAAAA;
  640. mcp->mb[2] = 0x5555;
  641. mcp->mb[3] = 0xAA55;
  642. mcp->mb[4] = 0x55AA;
  643. mcp->mb[5] = 0xA5A5;
  644. mcp->mb[6] = 0x5A5A;
  645. mcp->mb[7] = 0x2525;
  646. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  647. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  648. mcp->tov = MBX_TOV_SECONDS;
  649. mcp->flags = 0;
  650. rval = qla2x00_mailbox_command(vha, mcp);
  651. if (rval == QLA_SUCCESS) {
  652. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  653. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  654. rval = QLA_FUNCTION_FAILED;
  655. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  656. mcp->mb[7] != 0x2525)
  657. rval = QLA_FUNCTION_FAILED;
  658. }
  659. if (rval != QLA_SUCCESS) {
  660. /*EMPTY*/
  661. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  662. } else {
  663. /*EMPTY*/
  664. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  665. "Done %s.\n", __func__);
  666. }
  667. return rval;
  668. }
  669. /*
  670. * qla2x00_verify_checksum
  671. * Verify firmware checksum.
  672. *
  673. * Input:
  674. * ha = adapter block pointer.
  675. * TARGET_QUEUE_LOCK must be released.
  676. * ADAPTER_STATE_LOCK must be released.
  677. *
  678. * Returns:
  679. * qla2x00 local function return status code.
  680. *
  681. * Context:
  682. * Kernel context.
  683. */
  684. int
  685. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  686. {
  687. int rval;
  688. mbx_cmd_t mc;
  689. mbx_cmd_t *mcp = &mc;
  690. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  691. "Entered %s.\n", __func__);
  692. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  693. mcp->out_mb = MBX_0;
  694. mcp->in_mb = MBX_0;
  695. if (IS_FWI2_CAPABLE(vha->hw)) {
  696. mcp->mb[1] = MSW(risc_addr);
  697. mcp->mb[2] = LSW(risc_addr);
  698. mcp->out_mb |= MBX_2|MBX_1;
  699. mcp->in_mb |= MBX_2|MBX_1;
  700. } else {
  701. mcp->mb[1] = LSW(risc_addr);
  702. mcp->out_mb |= MBX_1;
  703. mcp->in_mb |= MBX_1;
  704. }
  705. mcp->tov = MBX_TOV_SECONDS;
  706. mcp->flags = 0;
  707. rval = qla2x00_mailbox_command(vha, mcp);
  708. if (rval != QLA_SUCCESS) {
  709. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  710. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  711. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  712. } else {
  713. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  714. "Done %s.\n", __func__);
  715. }
  716. return rval;
  717. }
  718. /*
  719. * qla2x00_issue_iocb
  720. * Issue IOCB using mailbox command
  721. *
  722. * Input:
  723. * ha = adapter state pointer.
  724. * buffer = buffer pointer.
  725. * phys_addr = physical address of buffer.
  726. * size = size of buffer.
  727. * TARGET_QUEUE_LOCK must be released.
  728. * ADAPTER_STATE_LOCK must be released.
  729. *
  730. * Returns:
  731. * qla2x00 local function return status code.
  732. *
  733. * Context:
  734. * Kernel context.
  735. */
  736. int
  737. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  738. dma_addr_t phys_addr, size_t size, uint32_t tov)
  739. {
  740. int rval;
  741. mbx_cmd_t mc;
  742. mbx_cmd_t *mcp = &mc;
  743. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  744. "Entered %s.\n", __func__);
  745. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  746. mcp->mb[1] = 0;
  747. mcp->mb[2] = MSW(phys_addr);
  748. mcp->mb[3] = LSW(phys_addr);
  749. mcp->mb[6] = MSW(MSD(phys_addr));
  750. mcp->mb[7] = LSW(MSD(phys_addr));
  751. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  752. mcp->in_mb = MBX_2|MBX_0;
  753. mcp->tov = tov;
  754. mcp->flags = 0;
  755. rval = qla2x00_mailbox_command(vha, mcp);
  756. if (rval != QLA_SUCCESS) {
  757. /*EMPTY*/
  758. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  759. } else {
  760. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  761. /* Mask reserved bits. */
  762. sts_entry->entry_status &=
  763. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  764. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  765. "Done %s.\n", __func__);
  766. }
  767. return rval;
  768. }
  769. int
  770. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  771. size_t size)
  772. {
  773. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  774. MBX_TOV_SECONDS);
  775. }
  776. /*
  777. * qla2x00_abort_command
  778. * Abort command aborts a specified IOCB.
  779. *
  780. * Input:
  781. * ha = adapter block pointer.
  782. * sp = SB structure pointer.
  783. *
  784. * Returns:
  785. * qla2x00 local function return status code.
  786. *
  787. * Context:
  788. * Kernel context.
  789. */
  790. int
  791. qla2x00_abort_command(srb_t *sp)
  792. {
  793. unsigned long flags = 0;
  794. int rval;
  795. uint32_t handle = 0;
  796. mbx_cmd_t mc;
  797. mbx_cmd_t *mcp = &mc;
  798. fc_port_t *fcport = sp->fcport;
  799. scsi_qla_host_t *vha = fcport->vha;
  800. struct qla_hw_data *ha = vha->hw;
  801. struct req_que *req = vha->req;
  802. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  803. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  804. "Entered %s.\n", __func__);
  805. spin_lock_irqsave(&ha->hardware_lock, flags);
  806. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  807. if (req->outstanding_cmds[handle] == sp)
  808. break;
  809. }
  810. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  811. if (handle == req->num_outstanding_cmds) {
  812. /* command not found */
  813. return QLA_FUNCTION_FAILED;
  814. }
  815. mcp->mb[0] = MBC_ABORT_COMMAND;
  816. if (HAS_EXTENDED_IDS(ha))
  817. mcp->mb[1] = fcport->loop_id;
  818. else
  819. mcp->mb[1] = fcport->loop_id << 8;
  820. mcp->mb[2] = (uint16_t)handle;
  821. mcp->mb[3] = (uint16_t)(handle >> 16);
  822. mcp->mb[6] = (uint16_t)cmd->device->lun;
  823. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  824. mcp->in_mb = MBX_0;
  825. mcp->tov = MBX_TOV_SECONDS;
  826. mcp->flags = 0;
  827. rval = qla2x00_mailbox_command(vha, mcp);
  828. if (rval != QLA_SUCCESS) {
  829. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  830. } else {
  831. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  832. "Done %s.\n", __func__);
  833. }
  834. return rval;
  835. }
  836. int
  837. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  838. {
  839. int rval, rval2;
  840. mbx_cmd_t mc;
  841. mbx_cmd_t *mcp = &mc;
  842. scsi_qla_host_t *vha;
  843. struct req_que *req;
  844. struct rsp_que *rsp;
  845. l = l;
  846. vha = fcport->vha;
  847. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  848. "Entered %s.\n", __func__);
  849. req = vha->hw->req_q_map[0];
  850. rsp = req->rsp;
  851. mcp->mb[0] = MBC_ABORT_TARGET;
  852. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  853. if (HAS_EXTENDED_IDS(vha->hw)) {
  854. mcp->mb[1] = fcport->loop_id;
  855. mcp->mb[10] = 0;
  856. mcp->out_mb |= MBX_10;
  857. } else {
  858. mcp->mb[1] = fcport->loop_id << 8;
  859. }
  860. mcp->mb[2] = vha->hw->loop_reset_delay;
  861. mcp->mb[9] = vha->vp_idx;
  862. mcp->in_mb = MBX_0;
  863. mcp->tov = MBX_TOV_SECONDS;
  864. mcp->flags = 0;
  865. rval = qla2x00_mailbox_command(vha, mcp);
  866. if (rval != QLA_SUCCESS) {
  867. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  868. "Failed=%x.\n", rval);
  869. }
  870. /* Issue marker IOCB. */
  871. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  872. MK_SYNC_ID);
  873. if (rval2 != QLA_SUCCESS) {
  874. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  875. "Failed to issue marker IOCB (%x).\n", rval2);
  876. } else {
  877. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  878. "Done %s.\n", __func__);
  879. }
  880. return rval;
  881. }
  882. int
  883. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  884. {
  885. int rval, rval2;
  886. mbx_cmd_t mc;
  887. mbx_cmd_t *mcp = &mc;
  888. scsi_qla_host_t *vha;
  889. struct req_que *req;
  890. struct rsp_que *rsp;
  891. vha = fcport->vha;
  892. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  893. "Entered %s.\n", __func__);
  894. req = vha->hw->req_q_map[0];
  895. rsp = req->rsp;
  896. mcp->mb[0] = MBC_LUN_RESET;
  897. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  898. if (HAS_EXTENDED_IDS(vha->hw))
  899. mcp->mb[1] = fcport->loop_id;
  900. else
  901. mcp->mb[1] = fcport->loop_id << 8;
  902. mcp->mb[2] = l;
  903. mcp->mb[3] = 0;
  904. mcp->mb[9] = vha->vp_idx;
  905. mcp->in_mb = MBX_0;
  906. mcp->tov = MBX_TOV_SECONDS;
  907. mcp->flags = 0;
  908. rval = qla2x00_mailbox_command(vha, mcp);
  909. if (rval != QLA_SUCCESS) {
  910. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  911. }
  912. /* Issue marker IOCB. */
  913. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  914. MK_SYNC_ID_LUN);
  915. if (rval2 != QLA_SUCCESS) {
  916. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  917. "Failed to issue marker IOCB (%x).\n", rval2);
  918. } else {
  919. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  920. "Done %s.\n", __func__);
  921. }
  922. return rval;
  923. }
  924. /*
  925. * qla2x00_get_adapter_id
  926. * Get adapter ID and topology.
  927. *
  928. * Input:
  929. * ha = adapter block pointer.
  930. * id = pointer for loop ID.
  931. * al_pa = pointer for AL_PA.
  932. * area = pointer for area.
  933. * domain = pointer for domain.
  934. * top = pointer for topology.
  935. * TARGET_QUEUE_LOCK must be released.
  936. * ADAPTER_STATE_LOCK must be released.
  937. *
  938. * Returns:
  939. * qla2x00 local function return status code.
  940. *
  941. * Context:
  942. * Kernel context.
  943. */
  944. int
  945. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  946. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  947. {
  948. int rval;
  949. mbx_cmd_t mc;
  950. mbx_cmd_t *mcp = &mc;
  951. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  952. "Entered %s.\n", __func__);
  953. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  954. mcp->mb[9] = vha->vp_idx;
  955. mcp->out_mb = MBX_9|MBX_0;
  956. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  957. if (IS_CNA_CAPABLE(vha->hw))
  958. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  959. mcp->tov = MBX_TOV_SECONDS;
  960. mcp->flags = 0;
  961. rval = qla2x00_mailbox_command(vha, mcp);
  962. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  963. rval = QLA_COMMAND_ERROR;
  964. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  965. rval = QLA_INVALID_COMMAND;
  966. /* Return data. */
  967. *id = mcp->mb[1];
  968. *al_pa = LSB(mcp->mb[2]);
  969. *area = MSB(mcp->mb[2]);
  970. *domain = LSB(mcp->mb[3]);
  971. *top = mcp->mb[6];
  972. *sw_cap = mcp->mb[7];
  973. if (rval != QLA_SUCCESS) {
  974. /*EMPTY*/
  975. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  976. } else {
  977. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  978. "Done %s.\n", __func__);
  979. if (IS_CNA_CAPABLE(vha->hw)) {
  980. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  981. vha->fcoe_fcf_idx = mcp->mb[10];
  982. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  983. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  984. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  985. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  986. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  987. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  988. }
  989. }
  990. return rval;
  991. }
  992. /*
  993. * qla2x00_get_retry_cnt
  994. * Get current firmware login retry count and delay.
  995. *
  996. * Input:
  997. * ha = adapter block pointer.
  998. * retry_cnt = pointer to login retry count.
  999. * tov = pointer to login timeout value.
  1000. *
  1001. * Returns:
  1002. * qla2x00 local function return status code.
  1003. *
  1004. * Context:
  1005. * Kernel context.
  1006. */
  1007. int
  1008. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1009. uint16_t *r_a_tov)
  1010. {
  1011. int rval;
  1012. uint16_t ratov;
  1013. mbx_cmd_t mc;
  1014. mbx_cmd_t *mcp = &mc;
  1015. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1016. "Entered %s.\n", __func__);
  1017. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1018. mcp->out_mb = MBX_0;
  1019. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1020. mcp->tov = MBX_TOV_SECONDS;
  1021. mcp->flags = 0;
  1022. rval = qla2x00_mailbox_command(vha, mcp);
  1023. if (rval != QLA_SUCCESS) {
  1024. /*EMPTY*/
  1025. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1026. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1027. } else {
  1028. /* Convert returned data and check our values. */
  1029. *r_a_tov = mcp->mb[3] / 2;
  1030. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1031. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1032. /* Update to the larger values */
  1033. *retry_cnt = (uint8_t)mcp->mb[1];
  1034. *tov = ratov;
  1035. }
  1036. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1037. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1038. }
  1039. return rval;
  1040. }
  1041. /*
  1042. * qla2x00_init_firmware
  1043. * Initialize adapter firmware.
  1044. *
  1045. * Input:
  1046. * ha = adapter block pointer.
  1047. * dptr = Initialization control block pointer.
  1048. * size = size of initialization control block.
  1049. * TARGET_QUEUE_LOCK must be released.
  1050. * ADAPTER_STATE_LOCK must be released.
  1051. *
  1052. * Returns:
  1053. * qla2x00 local function return status code.
  1054. *
  1055. * Context:
  1056. * Kernel context.
  1057. */
  1058. int
  1059. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1060. {
  1061. int rval;
  1062. mbx_cmd_t mc;
  1063. mbx_cmd_t *mcp = &mc;
  1064. struct qla_hw_data *ha = vha->hw;
  1065. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1066. "Entered %s.\n", __func__);
  1067. if (IS_P3P_TYPE(ha) && ql2xdbwr)
  1068. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1069. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1070. if (ha->flags.npiv_supported)
  1071. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1072. else
  1073. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1074. mcp->mb[1] = 0;
  1075. mcp->mb[2] = MSW(ha->init_cb_dma);
  1076. mcp->mb[3] = LSW(ha->init_cb_dma);
  1077. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1078. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1079. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1080. if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
  1081. mcp->mb[1] = BIT_0;
  1082. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1083. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1084. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1085. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1086. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1087. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1088. }
  1089. /* 1 and 2 should normally be captured. */
  1090. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1091. if (IS_QLA83XX(ha))
  1092. /* mb3 is additional info about the installed SFP. */
  1093. mcp->in_mb |= MBX_3;
  1094. mcp->buf_size = size;
  1095. mcp->flags = MBX_DMA_OUT;
  1096. mcp->tov = MBX_TOV_SECONDS;
  1097. rval = qla2x00_mailbox_command(vha, mcp);
  1098. if (rval != QLA_SUCCESS) {
  1099. /*EMPTY*/
  1100. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1101. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1102. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1103. } else {
  1104. /*EMPTY*/
  1105. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1106. "Done %s.\n", __func__);
  1107. }
  1108. return rval;
  1109. }
  1110. /*
  1111. * qla2x00_get_node_name_list
  1112. * Issue get node name list mailbox command, kmalloc()
  1113. * and return the resulting list. Caller must kfree() it!
  1114. *
  1115. * Input:
  1116. * ha = adapter state pointer.
  1117. * out_data = resulting list
  1118. * out_len = length of the resulting list
  1119. *
  1120. * Returns:
  1121. * qla2x00 local function return status code.
  1122. *
  1123. * Context:
  1124. * Kernel context.
  1125. */
  1126. int
  1127. qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
  1128. {
  1129. struct qla_hw_data *ha = vha->hw;
  1130. struct qla_port_24xx_data *list = NULL;
  1131. void *pmap;
  1132. mbx_cmd_t mc;
  1133. dma_addr_t pmap_dma;
  1134. ulong dma_size;
  1135. int rval, left;
  1136. left = 1;
  1137. while (left > 0) {
  1138. dma_size = left * sizeof(*list);
  1139. pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
  1140. &pmap_dma, GFP_KERNEL);
  1141. if (!pmap) {
  1142. ql_log(ql_log_warn, vha, 0x113f,
  1143. "%s(%ld): DMA Alloc failed of %ld\n",
  1144. __func__, vha->host_no, dma_size);
  1145. rval = QLA_MEMORY_ALLOC_FAILED;
  1146. goto out;
  1147. }
  1148. mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
  1149. mc.mb[1] = BIT_1 | BIT_3;
  1150. mc.mb[2] = MSW(pmap_dma);
  1151. mc.mb[3] = LSW(pmap_dma);
  1152. mc.mb[6] = MSW(MSD(pmap_dma));
  1153. mc.mb[7] = LSW(MSD(pmap_dma));
  1154. mc.mb[8] = dma_size;
  1155. mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
  1156. mc.in_mb = MBX_0|MBX_1;
  1157. mc.tov = 30;
  1158. mc.flags = MBX_DMA_IN;
  1159. rval = qla2x00_mailbox_command(vha, &mc);
  1160. if (rval != QLA_SUCCESS) {
  1161. if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
  1162. (mc.mb[1] == 0xA)) {
  1163. left += le16_to_cpu(mc.mb[2]) /
  1164. sizeof(struct qla_port_24xx_data);
  1165. goto restart;
  1166. }
  1167. goto out_free;
  1168. }
  1169. left = 0;
  1170. list = kzalloc(dma_size, GFP_KERNEL);
  1171. if (!list) {
  1172. ql_log(ql_log_warn, vha, 0x1140,
  1173. "%s(%ld): failed to allocate node names list "
  1174. "structure.\n", __func__, vha->host_no);
  1175. rval = QLA_MEMORY_ALLOC_FAILED;
  1176. goto out_free;
  1177. }
  1178. memcpy(list, pmap, dma_size);
  1179. restart:
  1180. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1181. }
  1182. *out_data = list;
  1183. *out_len = dma_size;
  1184. out:
  1185. return rval;
  1186. out_free:
  1187. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1188. return rval;
  1189. }
  1190. /*
  1191. * qla2x00_get_port_database
  1192. * Issue normal/enhanced get port database mailbox command
  1193. * and copy device name as necessary.
  1194. *
  1195. * Input:
  1196. * ha = adapter state pointer.
  1197. * dev = structure pointer.
  1198. * opt = enhanced cmd option byte.
  1199. *
  1200. * Returns:
  1201. * qla2x00 local function return status code.
  1202. *
  1203. * Context:
  1204. * Kernel context.
  1205. */
  1206. int
  1207. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1208. {
  1209. int rval;
  1210. mbx_cmd_t mc;
  1211. mbx_cmd_t *mcp = &mc;
  1212. port_database_t *pd;
  1213. struct port_database_24xx *pd24;
  1214. dma_addr_t pd_dma;
  1215. struct qla_hw_data *ha = vha->hw;
  1216. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1217. "Entered %s.\n", __func__);
  1218. pd24 = NULL;
  1219. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1220. if (pd == NULL) {
  1221. ql_log(ql_log_warn, vha, 0x1050,
  1222. "Failed to allocate port database structure.\n");
  1223. return QLA_MEMORY_ALLOC_FAILED;
  1224. }
  1225. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1226. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1227. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1228. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1229. mcp->mb[2] = MSW(pd_dma);
  1230. mcp->mb[3] = LSW(pd_dma);
  1231. mcp->mb[6] = MSW(MSD(pd_dma));
  1232. mcp->mb[7] = LSW(MSD(pd_dma));
  1233. mcp->mb[9] = vha->vp_idx;
  1234. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1235. mcp->in_mb = MBX_0;
  1236. if (IS_FWI2_CAPABLE(ha)) {
  1237. mcp->mb[1] = fcport->loop_id;
  1238. mcp->mb[10] = opt;
  1239. mcp->out_mb |= MBX_10|MBX_1;
  1240. mcp->in_mb |= MBX_1;
  1241. } else if (HAS_EXTENDED_IDS(ha)) {
  1242. mcp->mb[1] = fcport->loop_id;
  1243. mcp->mb[10] = opt;
  1244. mcp->out_mb |= MBX_10|MBX_1;
  1245. } else {
  1246. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1247. mcp->out_mb |= MBX_1;
  1248. }
  1249. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1250. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1251. mcp->flags = MBX_DMA_IN;
  1252. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1253. rval = qla2x00_mailbox_command(vha, mcp);
  1254. if (rval != QLA_SUCCESS)
  1255. goto gpd_error_out;
  1256. if (IS_FWI2_CAPABLE(ha)) {
  1257. uint64_t zero = 0;
  1258. pd24 = (struct port_database_24xx *) pd;
  1259. /* Check for logged in state. */
  1260. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1261. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1262. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1263. "Unable to verify login-state (%x/%x) for "
  1264. "loop_id %x.\n", pd24->current_login_state,
  1265. pd24->last_login_state, fcport->loop_id);
  1266. rval = QLA_FUNCTION_FAILED;
  1267. goto gpd_error_out;
  1268. }
  1269. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1270. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1271. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1272. /* We lost the device mid way. */
  1273. rval = QLA_NOT_LOGGED_IN;
  1274. goto gpd_error_out;
  1275. }
  1276. /* Names are little-endian. */
  1277. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1278. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1279. /* Get port_id of device. */
  1280. fcport->d_id.b.domain = pd24->port_id[0];
  1281. fcport->d_id.b.area = pd24->port_id[1];
  1282. fcport->d_id.b.al_pa = pd24->port_id[2];
  1283. fcport->d_id.b.rsvd_1 = 0;
  1284. /* If not target must be initiator or unknown type. */
  1285. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1286. fcport->port_type = FCT_INITIATOR;
  1287. else
  1288. fcport->port_type = FCT_TARGET;
  1289. /* Passback COS information. */
  1290. fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
  1291. FC_COS_CLASS2 : FC_COS_CLASS3;
  1292. if (pd24->prli_svc_param_word_3[0] & BIT_7)
  1293. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1294. } else {
  1295. uint64_t zero = 0;
  1296. /* Check for logged in state. */
  1297. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1298. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1299. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1300. "Unable to verify login-state (%x/%x) - "
  1301. "portid=%02x%02x%02x.\n", pd->master_state,
  1302. pd->slave_state, fcport->d_id.b.domain,
  1303. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1304. rval = QLA_FUNCTION_FAILED;
  1305. goto gpd_error_out;
  1306. }
  1307. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1308. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1309. memcmp(fcport->port_name, pd->port_name, 8))) {
  1310. /* We lost the device mid way. */
  1311. rval = QLA_NOT_LOGGED_IN;
  1312. goto gpd_error_out;
  1313. }
  1314. /* Names are little-endian. */
  1315. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1316. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1317. /* Get port_id of device. */
  1318. fcport->d_id.b.domain = pd->port_id[0];
  1319. fcport->d_id.b.area = pd->port_id[3];
  1320. fcport->d_id.b.al_pa = pd->port_id[2];
  1321. fcport->d_id.b.rsvd_1 = 0;
  1322. /* If not target must be initiator or unknown type. */
  1323. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1324. fcport->port_type = FCT_INITIATOR;
  1325. else
  1326. fcport->port_type = FCT_TARGET;
  1327. /* Passback COS information. */
  1328. fcport->supported_classes = (pd->options & BIT_4) ?
  1329. FC_COS_CLASS2: FC_COS_CLASS3;
  1330. }
  1331. gpd_error_out:
  1332. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1333. if (rval != QLA_SUCCESS) {
  1334. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1335. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1336. mcp->mb[0], mcp->mb[1]);
  1337. } else {
  1338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1339. "Done %s.\n", __func__);
  1340. }
  1341. return rval;
  1342. }
  1343. /*
  1344. * qla2x00_get_firmware_state
  1345. * Get adapter firmware state.
  1346. *
  1347. * Input:
  1348. * ha = adapter block pointer.
  1349. * dptr = pointer for firmware state.
  1350. * TARGET_QUEUE_LOCK must be released.
  1351. * ADAPTER_STATE_LOCK must be released.
  1352. *
  1353. * Returns:
  1354. * qla2x00 local function return status code.
  1355. *
  1356. * Context:
  1357. * Kernel context.
  1358. */
  1359. int
  1360. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1361. {
  1362. int rval;
  1363. mbx_cmd_t mc;
  1364. mbx_cmd_t *mcp = &mc;
  1365. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1366. "Entered %s.\n", __func__);
  1367. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1368. mcp->out_mb = MBX_0;
  1369. if (IS_FWI2_CAPABLE(vha->hw))
  1370. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1371. else
  1372. mcp->in_mb = MBX_1|MBX_0;
  1373. mcp->tov = MBX_TOV_SECONDS;
  1374. mcp->flags = 0;
  1375. rval = qla2x00_mailbox_command(vha, mcp);
  1376. /* Return firmware states. */
  1377. states[0] = mcp->mb[1];
  1378. if (IS_FWI2_CAPABLE(vha->hw)) {
  1379. states[1] = mcp->mb[2];
  1380. states[2] = mcp->mb[3];
  1381. states[3] = mcp->mb[4];
  1382. states[4] = mcp->mb[5];
  1383. }
  1384. if (rval != QLA_SUCCESS) {
  1385. /*EMPTY*/
  1386. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1387. } else {
  1388. /*EMPTY*/
  1389. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1390. "Done %s.\n", __func__);
  1391. }
  1392. return rval;
  1393. }
  1394. /*
  1395. * qla2x00_get_port_name
  1396. * Issue get port name mailbox command.
  1397. * Returned name is in big endian format.
  1398. *
  1399. * Input:
  1400. * ha = adapter block pointer.
  1401. * loop_id = loop ID of device.
  1402. * name = pointer for name.
  1403. * TARGET_QUEUE_LOCK must be released.
  1404. * ADAPTER_STATE_LOCK must be released.
  1405. *
  1406. * Returns:
  1407. * qla2x00 local function return status code.
  1408. *
  1409. * Context:
  1410. * Kernel context.
  1411. */
  1412. int
  1413. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1414. uint8_t opt)
  1415. {
  1416. int rval;
  1417. mbx_cmd_t mc;
  1418. mbx_cmd_t *mcp = &mc;
  1419. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1420. "Entered %s.\n", __func__);
  1421. mcp->mb[0] = MBC_GET_PORT_NAME;
  1422. mcp->mb[9] = vha->vp_idx;
  1423. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1424. if (HAS_EXTENDED_IDS(vha->hw)) {
  1425. mcp->mb[1] = loop_id;
  1426. mcp->mb[10] = opt;
  1427. mcp->out_mb |= MBX_10;
  1428. } else {
  1429. mcp->mb[1] = loop_id << 8 | opt;
  1430. }
  1431. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1432. mcp->tov = MBX_TOV_SECONDS;
  1433. mcp->flags = 0;
  1434. rval = qla2x00_mailbox_command(vha, mcp);
  1435. if (rval != QLA_SUCCESS) {
  1436. /*EMPTY*/
  1437. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1438. } else {
  1439. if (name != NULL) {
  1440. /* This function returns name in big endian. */
  1441. name[0] = MSB(mcp->mb[2]);
  1442. name[1] = LSB(mcp->mb[2]);
  1443. name[2] = MSB(mcp->mb[3]);
  1444. name[3] = LSB(mcp->mb[3]);
  1445. name[4] = MSB(mcp->mb[6]);
  1446. name[5] = LSB(mcp->mb[6]);
  1447. name[6] = MSB(mcp->mb[7]);
  1448. name[7] = LSB(mcp->mb[7]);
  1449. }
  1450. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1451. "Done %s.\n", __func__);
  1452. }
  1453. return rval;
  1454. }
  1455. /*
  1456. * qla24xx_link_initialization
  1457. * Issue link initialization mailbox command.
  1458. *
  1459. * Input:
  1460. * ha = adapter block pointer.
  1461. * TARGET_QUEUE_LOCK must be released.
  1462. * ADAPTER_STATE_LOCK must be released.
  1463. *
  1464. * Returns:
  1465. * qla2x00 local function return status code.
  1466. *
  1467. * Context:
  1468. * Kernel context.
  1469. */
  1470. int
  1471. qla24xx_link_initialize(scsi_qla_host_t *vha)
  1472. {
  1473. int rval;
  1474. mbx_cmd_t mc;
  1475. mbx_cmd_t *mcp = &mc;
  1476. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
  1477. "Entered %s.\n", __func__);
  1478. if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
  1479. return QLA_FUNCTION_FAILED;
  1480. mcp->mb[0] = MBC_LINK_INITIALIZATION;
  1481. mcp->mb[1] = BIT_4;
  1482. if (vha->hw->operating_mode == LOOP)
  1483. mcp->mb[1] |= BIT_6;
  1484. else
  1485. mcp->mb[1] |= BIT_5;
  1486. mcp->mb[2] = 0;
  1487. mcp->mb[3] = 0;
  1488. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1489. mcp->in_mb = MBX_0;
  1490. mcp->tov = MBX_TOV_SECONDS;
  1491. mcp->flags = 0;
  1492. rval = qla2x00_mailbox_command(vha, mcp);
  1493. if (rval != QLA_SUCCESS) {
  1494. ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
  1495. } else {
  1496. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
  1497. "Done %s.\n", __func__);
  1498. }
  1499. return rval;
  1500. }
  1501. /*
  1502. * qla2x00_lip_reset
  1503. * Issue LIP reset mailbox command.
  1504. *
  1505. * Input:
  1506. * ha = adapter block pointer.
  1507. * TARGET_QUEUE_LOCK must be released.
  1508. * ADAPTER_STATE_LOCK must be released.
  1509. *
  1510. * Returns:
  1511. * qla2x00 local function return status code.
  1512. *
  1513. * Context:
  1514. * Kernel context.
  1515. */
  1516. int
  1517. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1518. {
  1519. int rval;
  1520. mbx_cmd_t mc;
  1521. mbx_cmd_t *mcp = &mc;
  1522. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1523. "Entered %s.\n", __func__);
  1524. if (IS_CNA_CAPABLE(vha->hw)) {
  1525. /* Logout across all FCFs. */
  1526. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1527. mcp->mb[1] = BIT_1;
  1528. mcp->mb[2] = 0;
  1529. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1530. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1531. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1532. mcp->mb[1] = BIT_6;
  1533. mcp->mb[2] = 0;
  1534. mcp->mb[3] = vha->hw->loop_reset_delay;
  1535. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1536. } else {
  1537. mcp->mb[0] = MBC_LIP_RESET;
  1538. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1539. if (HAS_EXTENDED_IDS(vha->hw)) {
  1540. mcp->mb[1] = 0x00ff;
  1541. mcp->mb[10] = 0;
  1542. mcp->out_mb |= MBX_10;
  1543. } else {
  1544. mcp->mb[1] = 0xff00;
  1545. }
  1546. mcp->mb[2] = vha->hw->loop_reset_delay;
  1547. mcp->mb[3] = 0;
  1548. }
  1549. mcp->in_mb = MBX_0;
  1550. mcp->tov = MBX_TOV_SECONDS;
  1551. mcp->flags = 0;
  1552. rval = qla2x00_mailbox_command(vha, mcp);
  1553. if (rval != QLA_SUCCESS) {
  1554. /*EMPTY*/
  1555. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1556. } else {
  1557. /*EMPTY*/
  1558. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1559. "Done %s.\n", __func__);
  1560. }
  1561. return rval;
  1562. }
  1563. /*
  1564. * qla2x00_send_sns
  1565. * Send SNS command.
  1566. *
  1567. * Input:
  1568. * ha = adapter block pointer.
  1569. * sns = pointer for command.
  1570. * cmd_size = command size.
  1571. * buf_size = response/command size.
  1572. * TARGET_QUEUE_LOCK must be released.
  1573. * ADAPTER_STATE_LOCK must be released.
  1574. *
  1575. * Returns:
  1576. * qla2x00 local function return status code.
  1577. *
  1578. * Context:
  1579. * Kernel context.
  1580. */
  1581. int
  1582. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1583. uint16_t cmd_size, size_t buf_size)
  1584. {
  1585. int rval;
  1586. mbx_cmd_t mc;
  1587. mbx_cmd_t *mcp = &mc;
  1588. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1589. "Entered %s.\n", __func__);
  1590. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1591. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1592. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1593. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1594. mcp->mb[1] = cmd_size;
  1595. mcp->mb[2] = MSW(sns_phys_address);
  1596. mcp->mb[3] = LSW(sns_phys_address);
  1597. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1598. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1599. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1600. mcp->in_mb = MBX_0|MBX_1;
  1601. mcp->buf_size = buf_size;
  1602. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1603. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1604. rval = qla2x00_mailbox_command(vha, mcp);
  1605. if (rval != QLA_SUCCESS) {
  1606. /*EMPTY*/
  1607. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1608. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1609. rval, mcp->mb[0], mcp->mb[1]);
  1610. } else {
  1611. /*EMPTY*/
  1612. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1613. "Done %s.\n", __func__);
  1614. }
  1615. return rval;
  1616. }
  1617. int
  1618. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1619. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1620. {
  1621. int rval;
  1622. struct logio_entry_24xx *lg;
  1623. dma_addr_t lg_dma;
  1624. uint32_t iop[2];
  1625. struct qla_hw_data *ha = vha->hw;
  1626. struct req_que *req;
  1627. struct rsp_que *rsp;
  1628. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1629. "Entered %s.\n", __func__);
  1630. if (ha->flags.cpu_affinity_enabled)
  1631. req = ha->req_q_map[0];
  1632. else
  1633. req = vha->req;
  1634. rsp = req->rsp;
  1635. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1636. if (lg == NULL) {
  1637. ql_log(ql_log_warn, vha, 0x1062,
  1638. "Failed to allocate login IOCB.\n");
  1639. return QLA_MEMORY_ALLOC_FAILED;
  1640. }
  1641. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1642. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1643. lg->entry_count = 1;
  1644. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1645. lg->nport_handle = cpu_to_le16(loop_id);
  1646. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1647. if (opt & BIT_0)
  1648. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1649. if (opt & BIT_1)
  1650. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1651. lg->port_id[0] = al_pa;
  1652. lg->port_id[1] = area;
  1653. lg->port_id[2] = domain;
  1654. lg->vp_index = vha->vp_idx;
  1655. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1656. (ha->r_a_tov / 10 * 2) + 2);
  1657. if (rval != QLA_SUCCESS) {
  1658. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1659. "Failed to issue login IOCB (%x).\n", rval);
  1660. } else if (lg->entry_status != 0) {
  1661. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1662. "Failed to complete IOCB -- error status (%x).\n",
  1663. lg->entry_status);
  1664. rval = QLA_FUNCTION_FAILED;
  1665. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1666. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1667. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1668. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1669. "Failed to complete IOCB -- completion status (%x) "
  1670. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1671. iop[0], iop[1]);
  1672. switch (iop[0]) {
  1673. case LSC_SCODE_PORTID_USED:
  1674. mb[0] = MBS_PORT_ID_USED;
  1675. mb[1] = LSW(iop[1]);
  1676. break;
  1677. case LSC_SCODE_NPORT_USED:
  1678. mb[0] = MBS_LOOP_ID_USED;
  1679. break;
  1680. case LSC_SCODE_NOLINK:
  1681. case LSC_SCODE_NOIOCB:
  1682. case LSC_SCODE_NOXCB:
  1683. case LSC_SCODE_CMD_FAILED:
  1684. case LSC_SCODE_NOFABRIC:
  1685. case LSC_SCODE_FW_NOT_READY:
  1686. case LSC_SCODE_NOT_LOGGED_IN:
  1687. case LSC_SCODE_NOPCB:
  1688. case LSC_SCODE_ELS_REJECT:
  1689. case LSC_SCODE_CMD_PARAM_ERR:
  1690. case LSC_SCODE_NONPORT:
  1691. case LSC_SCODE_LOGGED_IN:
  1692. case LSC_SCODE_NOFLOGI_ACC:
  1693. default:
  1694. mb[0] = MBS_COMMAND_ERROR;
  1695. break;
  1696. }
  1697. } else {
  1698. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1699. "Done %s.\n", __func__);
  1700. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1701. mb[0] = MBS_COMMAND_COMPLETE;
  1702. mb[1] = 0;
  1703. if (iop[0] & BIT_4) {
  1704. if (iop[0] & BIT_8)
  1705. mb[1] |= BIT_1;
  1706. } else
  1707. mb[1] = BIT_0;
  1708. /* Passback COS information. */
  1709. mb[10] = 0;
  1710. if (lg->io_parameter[7] || lg->io_parameter[8])
  1711. mb[10] |= BIT_0; /* Class 2. */
  1712. if (lg->io_parameter[9] || lg->io_parameter[10])
  1713. mb[10] |= BIT_1; /* Class 3. */
  1714. if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
  1715. mb[10] |= BIT_7; /* Confirmed Completion
  1716. * Allowed
  1717. */
  1718. }
  1719. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1720. return rval;
  1721. }
  1722. /*
  1723. * qla2x00_login_fabric
  1724. * Issue login fabric port mailbox command.
  1725. *
  1726. * Input:
  1727. * ha = adapter block pointer.
  1728. * loop_id = device loop ID.
  1729. * domain = device domain.
  1730. * area = device area.
  1731. * al_pa = device AL_PA.
  1732. * status = pointer for return status.
  1733. * opt = command options.
  1734. * TARGET_QUEUE_LOCK must be released.
  1735. * ADAPTER_STATE_LOCK must be released.
  1736. *
  1737. * Returns:
  1738. * qla2x00 local function return status code.
  1739. *
  1740. * Context:
  1741. * Kernel context.
  1742. */
  1743. int
  1744. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1745. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1746. {
  1747. int rval;
  1748. mbx_cmd_t mc;
  1749. mbx_cmd_t *mcp = &mc;
  1750. struct qla_hw_data *ha = vha->hw;
  1751. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1752. "Entered %s.\n", __func__);
  1753. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1754. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1755. if (HAS_EXTENDED_IDS(ha)) {
  1756. mcp->mb[1] = loop_id;
  1757. mcp->mb[10] = opt;
  1758. mcp->out_mb |= MBX_10;
  1759. } else {
  1760. mcp->mb[1] = (loop_id << 8) | opt;
  1761. }
  1762. mcp->mb[2] = domain;
  1763. mcp->mb[3] = area << 8 | al_pa;
  1764. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1765. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1766. mcp->flags = 0;
  1767. rval = qla2x00_mailbox_command(vha, mcp);
  1768. /* Return mailbox statuses. */
  1769. if (mb != NULL) {
  1770. mb[0] = mcp->mb[0];
  1771. mb[1] = mcp->mb[1];
  1772. mb[2] = mcp->mb[2];
  1773. mb[6] = mcp->mb[6];
  1774. mb[7] = mcp->mb[7];
  1775. /* COS retrieved from Get-Port-Database mailbox command. */
  1776. mb[10] = 0;
  1777. }
  1778. if (rval != QLA_SUCCESS) {
  1779. /* RLU tmp code: need to change main mailbox_command function to
  1780. * return ok even when the mailbox completion value is not
  1781. * SUCCESS. The caller needs to be responsible to interpret
  1782. * the return values of this mailbox command if we're not
  1783. * to change too much of the existing code.
  1784. */
  1785. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1786. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1787. mcp->mb[0] == 0x4006)
  1788. rval = QLA_SUCCESS;
  1789. /*EMPTY*/
  1790. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1791. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1792. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1793. } else {
  1794. /*EMPTY*/
  1795. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1796. "Done %s.\n", __func__);
  1797. }
  1798. return rval;
  1799. }
  1800. /*
  1801. * qla2x00_login_local_device
  1802. * Issue login loop port mailbox command.
  1803. *
  1804. * Input:
  1805. * ha = adapter block pointer.
  1806. * loop_id = device loop ID.
  1807. * opt = command options.
  1808. *
  1809. * Returns:
  1810. * Return status code.
  1811. *
  1812. * Context:
  1813. * Kernel context.
  1814. *
  1815. */
  1816. int
  1817. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1818. uint16_t *mb_ret, uint8_t opt)
  1819. {
  1820. int rval;
  1821. mbx_cmd_t mc;
  1822. mbx_cmd_t *mcp = &mc;
  1823. struct qla_hw_data *ha = vha->hw;
  1824. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1825. "Entered %s.\n", __func__);
  1826. if (IS_FWI2_CAPABLE(ha))
  1827. return qla24xx_login_fabric(vha, fcport->loop_id,
  1828. fcport->d_id.b.domain, fcport->d_id.b.area,
  1829. fcport->d_id.b.al_pa, mb_ret, opt);
  1830. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1831. if (HAS_EXTENDED_IDS(ha))
  1832. mcp->mb[1] = fcport->loop_id;
  1833. else
  1834. mcp->mb[1] = fcport->loop_id << 8;
  1835. mcp->mb[2] = opt;
  1836. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1837. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1838. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1839. mcp->flags = 0;
  1840. rval = qla2x00_mailbox_command(vha, mcp);
  1841. /* Return mailbox statuses. */
  1842. if (mb_ret != NULL) {
  1843. mb_ret[0] = mcp->mb[0];
  1844. mb_ret[1] = mcp->mb[1];
  1845. mb_ret[6] = mcp->mb[6];
  1846. mb_ret[7] = mcp->mb[7];
  1847. }
  1848. if (rval != QLA_SUCCESS) {
  1849. /* AV tmp code: need to change main mailbox_command function to
  1850. * return ok even when the mailbox completion value is not
  1851. * SUCCESS. The caller needs to be responsible to interpret
  1852. * the return values of this mailbox command if we're not
  1853. * to change too much of the existing code.
  1854. */
  1855. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1856. rval = QLA_SUCCESS;
  1857. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1858. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1859. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1860. } else {
  1861. /*EMPTY*/
  1862. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1863. "Done %s.\n", __func__);
  1864. }
  1865. return (rval);
  1866. }
  1867. int
  1868. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1869. uint8_t area, uint8_t al_pa)
  1870. {
  1871. int rval;
  1872. struct logio_entry_24xx *lg;
  1873. dma_addr_t lg_dma;
  1874. struct qla_hw_data *ha = vha->hw;
  1875. struct req_que *req;
  1876. struct rsp_que *rsp;
  1877. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1878. "Entered %s.\n", __func__);
  1879. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1880. if (lg == NULL) {
  1881. ql_log(ql_log_warn, vha, 0x106e,
  1882. "Failed to allocate logout IOCB.\n");
  1883. return QLA_MEMORY_ALLOC_FAILED;
  1884. }
  1885. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1886. if (ql2xmaxqueues > 1)
  1887. req = ha->req_q_map[0];
  1888. else
  1889. req = vha->req;
  1890. rsp = req->rsp;
  1891. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1892. lg->entry_count = 1;
  1893. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1894. lg->nport_handle = cpu_to_le16(loop_id);
  1895. lg->control_flags =
  1896. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1897. LCF_FREE_NPORT);
  1898. lg->port_id[0] = al_pa;
  1899. lg->port_id[1] = area;
  1900. lg->port_id[2] = domain;
  1901. lg->vp_index = vha->vp_idx;
  1902. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1903. (ha->r_a_tov / 10 * 2) + 2);
  1904. if (rval != QLA_SUCCESS) {
  1905. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1906. "Failed to issue logout IOCB (%x).\n", rval);
  1907. } else if (lg->entry_status != 0) {
  1908. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1909. "Failed to complete IOCB -- error status (%x).\n",
  1910. lg->entry_status);
  1911. rval = QLA_FUNCTION_FAILED;
  1912. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1913. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1914. "Failed to complete IOCB -- completion status (%x) "
  1915. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1916. le32_to_cpu(lg->io_parameter[0]),
  1917. le32_to_cpu(lg->io_parameter[1]));
  1918. } else {
  1919. /*EMPTY*/
  1920. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1921. "Done %s.\n", __func__);
  1922. }
  1923. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1924. return rval;
  1925. }
  1926. /*
  1927. * qla2x00_fabric_logout
  1928. * Issue logout fabric port mailbox command.
  1929. *
  1930. * Input:
  1931. * ha = adapter block pointer.
  1932. * loop_id = device loop ID.
  1933. * TARGET_QUEUE_LOCK must be released.
  1934. * ADAPTER_STATE_LOCK must be released.
  1935. *
  1936. * Returns:
  1937. * qla2x00 local function return status code.
  1938. *
  1939. * Context:
  1940. * Kernel context.
  1941. */
  1942. int
  1943. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1944. uint8_t area, uint8_t al_pa)
  1945. {
  1946. int rval;
  1947. mbx_cmd_t mc;
  1948. mbx_cmd_t *mcp = &mc;
  1949. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1950. "Entered %s.\n", __func__);
  1951. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1952. mcp->out_mb = MBX_1|MBX_0;
  1953. if (HAS_EXTENDED_IDS(vha->hw)) {
  1954. mcp->mb[1] = loop_id;
  1955. mcp->mb[10] = 0;
  1956. mcp->out_mb |= MBX_10;
  1957. } else {
  1958. mcp->mb[1] = loop_id << 8;
  1959. }
  1960. mcp->in_mb = MBX_1|MBX_0;
  1961. mcp->tov = MBX_TOV_SECONDS;
  1962. mcp->flags = 0;
  1963. rval = qla2x00_mailbox_command(vha, mcp);
  1964. if (rval != QLA_SUCCESS) {
  1965. /*EMPTY*/
  1966. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1967. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1968. } else {
  1969. /*EMPTY*/
  1970. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  1971. "Done %s.\n", __func__);
  1972. }
  1973. return rval;
  1974. }
  1975. /*
  1976. * qla2x00_full_login_lip
  1977. * Issue full login LIP mailbox command.
  1978. *
  1979. * Input:
  1980. * ha = adapter block pointer.
  1981. * TARGET_QUEUE_LOCK must be released.
  1982. * ADAPTER_STATE_LOCK must be released.
  1983. *
  1984. * Returns:
  1985. * qla2x00 local function return status code.
  1986. *
  1987. * Context:
  1988. * Kernel context.
  1989. */
  1990. int
  1991. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1992. {
  1993. int rval;
  1994. mbx_cmd_t mc;
  1995. mbx_cmd_t *mcp = &mc;
  1996. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  1997. "Entered %s.\n", __func__);
  1998. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1999. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  2000. mcp->mb[2] = 0;
  2001. mcp->mb[3] = 0;
  2002. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  2003. mcp->in_mb = MBX_0;
  2004. mcp->tov = MBX_TOV_SECONDS;
  2005. mcp->flags = 0;
  2006. rval = qla2x00_mailbox_command(vha, mcp);
  2007. if (rval != QLA_SUCCESS) {
  2008. /*EMPTY*/
  2009. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  2010. } else {
  2011. /*EMPTY*/
  2012. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  2013. "Done %s.\n", __func__);
  2014. }
  2015. return rval;
  2016. }
  2017. /*
  2018. * qla2x00_get_id_list
  2019. *
  2020. * Input:
  2021. * ha = adapter block pointer.
  2022. *
  2023. * Returns:
  2024. * qla2x00 local function return status code.
  2025. *
  2026. * Context:
  2027. * Kernel context.
  2028. */
  2029. int
  2030. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  2031. uint16_t *entries)
  2032. {
  2033. int rval;
  2034. mbx_cmd_t mc;
  2035. mbx_cmd_t *mcp = &mc;
  2036. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  2037. "Entered %s.\n", __func__);
  2038. if (id_list == NULL)
  2039. return QLA_FUNCTION_FAILED;
  2040. mcp->mb[0] = MBC_GET_ID_LIST;
  2041. mcp->out_mb = MBX_0;
  2042. if (IS_FWI2_CAPABLE(vha->hw)) {
  2043. mcp->mb[2] = MSW(id_list_dma);
  2044. mcp->mb[3] = LSW(id_list_dma);
  2045. mcp->mb[6] = MSW(MSD(id_list_dma));
  2046. mcp->mb[7] = LSW(MSD(id_list_dma));
  2047. mcp->mb[8] = 0;
  2048. mcp->mb[9] = vha->vp_idx;
  2049. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  2050. } else {
  2051. mcp->mb[1] = MSW(id_list_dma);
  2052. mcp->mb[2] = LSW(id_list_dma);
  2053. mcp->mb[3] = MSW(MSD(id_list_dma));
  2054. mcp->mb[6] = LSW(MSD(id_list_dma));
  2055. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  2056. }
  2057. mcp->in_mb = MBX_1|MBX_0;
  2058. mcp->tov = MBX_TOV_SECONDS;
  2059. mcp->flags = 0;
  2060. rval = qla2x00_mailbox_command(vha, mcp);
  2061. if (rval != QLA_SUCCESS) {
  2062. /*EMPTY*/
  2063. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  2064. } else {
  2065. *entries = mcp->mb[1];
  2066. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  2067. "Done %s.\n", __func__);
  2068. }
  2069. return rval;
  2070. }
  2071. /*
  2072. * qla2x00_get_resource_cnts
  2073. * Get current firmware resource counts.
  2074. *
  2075. * Input:
  2076. * ha = adapter block pointer.
  2077. *
  2078. * Returns:
  2079. * qla2x00 local function return status code.
  2080. *
  2081. * Context:
  2082. * Kernel context.
  2083. */
  2084. int
  2085. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  2086. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  2087. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  2088. {
  2089. int rval;
  2090. mbx_cmd_t mc;
  2091. mbx_cmd_t *mcp = &mc;
  2092. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  2093. "Entered %s.\n", __func__);
  2094. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  2095. mcp->out_mb = MBX_0;
  2096. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  2097. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  2098. mcp->in_mb |= MBX_12;
  2099. mcp->tov = MBX_TOV_SECONDS;
  2100. mcp->flags = 0;
  2101. rval = qla2x00_mailbox_command(vha, mcp);
  2102. if (rval != QLA_SUCCESS) {
  2103. /*EMPTY*/
  2104. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  2105. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2106. } else {
  2107. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  2108. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  2109. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  2110. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  2111. mcp->mb[11], mcp->mb[12]);
  2112. if (cur_xchg_cnt)
  2113. *cur_xchg_cnt = mcp->mb[3];
  2114. if (orig_xchg_cnt)
  2115. *orig_xchg_cnt = mcp->mb[6];
  2116. if (cur_iocb_cnt)
  2117. *cur_iocb_cnt = mcp->mb[7];
  2118. if (orig_iocb_cnt)
  2119. *orig_iocb_cnt = mcp->mb[10];
  2120. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  2121. *max_npiv_vports = mcp->mb[11];
  2122. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
  2123. *max_fcfs = mcp->mb[12];
  2124. }
  2125. return (rval);
  2126. }
  2127. /*
  2128. * qla2x00_get_fcal_position_map
  2129. * Get FCAL (LILP) position map using mailbox command
  2130. *
  2131. * Input:
  2132. * ha = adapter state pointer.
  2133. * pos_map = buffer pointer (can be NULL).
  2134. *
  2135. * Returns:
  2136. * qla2x00 local function return status code.
  2137. *
  2138. * Context:
  2139. * Kernel context.
  2140. */
  2141. int
  2142. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2143. {
  2144. int rval;
  2145. mbx_cmd_t mc;
  2146. mbx_cmd_t *mcp = &mc;
  2147. char *pmap;
  2148. dma_addr_t pmap_dma;
  2149. struct qla_hw_data *ha = vha->hw;
  2150. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2151. "Entered %s.\n", __func__);
  2152. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2153. if (pmap == NULL) {
  2154. ql_log(ql_log_warn, vha, 0x1080,
  2155. "Memory alloc failed.\n");
  2156. return QLA_MEMORY_ALLOC_FAILED;
  2157. }
  2158. memset(pmap, 0, FCAL_MAP_SIZE);
  2159. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2160. mcp->mb[2] = MSW(pmap_dma);
  2161. mcp->mb[3] = LSW(pmap_dma);
  2162. mcp->mb[6] = MSW(MSD(pmap_dma));
  2163. mcp->mb[7] = LSW(MSD(pmap_dma));
  2164. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2165. mcp->in_mb = MBX_1|MBX_0;
  2166. mcp->buf_size = FCAL_MAP_SIZE;
  2167. mcp->flags = MBX_DMA_IN;
  2168. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2169. rval = qla2x00_mailbox_command(vha, mcp);
  2170. if (rval == QLA_SUCCESS) {
  2171. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2172. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2173. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2174. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2175. pmap, pmap[0] + 1);
  2176. if (pos_map)
  2177. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2178. }
  2179. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2180. if (rval != QLA_SUCCESS) {
  2181. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2182. } else {
  2183. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2184. "Done %s.\n", __func__);
  2185. }
  2186. return rval;
  2187. }
  2188. /*
  2189. * qla2x00_get_link_status
  2190. *
  2191. * Input:
  2192. * ha = adapter block pointer.
  2193. * loop_id = device loop ID.
  2194. * ret_buf = pointer to link status return buffer.
  2195. *
  2196. * Returns:
  2197. * 0 = success.
  2198. * BIT_0 = mem alloc error.
  2199. * BIT_1 = mailbox error.
  2200. */
  2201. int
  2202. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2203. struct link_statistics *stats, dma_addr_t stats_dma)
  2204. {
  2205. int rval;
  2206. mbx_cmd_t mc;
  2207. mbx_cmd_t *mcp = &mc;
  2208. uint32_t *siter, *diter, dwords;
  2209. struct qla_hw_data *ha = vha->hw;
  2210. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2211. "Entered %s.\n", __func__);
  2212. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2213. mcp->mb[2] = MSW(stats_dma);
  2214. mcp->mb[3] = LSW(stats_dma);
  2215. mcp->mb[6] = MSW(MSD(stats_dma));
  2216. mcp->mb[7] = LSW(MSD(stats_dma));
  2217. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2218. mcp->in_mb = MBX_0;
  2219. if (IS_FWI2_CAPABLE(ha)) {
  2220. mcp->mb[1] = loop_id;
  2221. mcp->mb[4] = 0;
  2222. mcp->mb[10] = 0;
  2223. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2224. mcp->in_mb |= MBX_1;
  2225. } else if (HAS_EXTENDED_IDS(ha)) {
  2226. mcp->mb[1] = loop_id;
  2227. mcp->mb[10] = 0;
  2228. mcp->out_mb |= MBX_10|MBX_1;
  2229. } else {
  2230. mcp->mb[1] = loop_id << 8;
  2231. mcp->out_mb |= MBX_1;
  2232. }
  2233. mcp->tov = MBX_TOV_SECONDS;
  2234. mcp->flags = IOCTL_CMD;
  2235. rval = qla2x00_mailbox_command(vha, mcp);
  2236. if (rval == QLA_SUCCESS) {
  2237. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2238. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2239. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2240. rval = QLA_FUNCTION_FAILED;
  2241. } else {
  2242. /* Copy over data -- firmware data is LE. */
  2243. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2244. "Done %s.\n", __func__);
  2245. dwords = offsetof(struct link_statistics, unused1) / 4;
  2246. siter = diter = &stats->link_fail_cnt;
  2247. while (dwords--)
  2248. *diter++ = le32_to_cpu(*siter++);
  2249. }
  2250. } else {
  2251. /* Failed. */
  2252. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2253. }
  2254. return rval;
  2255. }
  2256. int
  2257. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2258. dma_addr_t stats_dma)
  2259. {
  2260. int rval;
  2261. mbx_cmd_t mc;
  2262. mbx_cmd_t *mcp = &mc;
  2263. uint32_t *siter, *diter, dwords;
  2264. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2265. "Entered %s.\n", __func__);
  2266. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2267. mcp->mb[2] = MSW(stats_dma);
  2268. mcp->mb[3] = LSW(stats_dma);
  2269. mcp->mb[6] = MSW(MSD(stats_dma));
  2270. mcp->mb[7] = LSW(MSD(stats_dma));
  2271. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2272. mcp->mb[9] = vha->vp_idx;
  2273. mcp->mb[10] = 0;
  2274. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2275. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2276. mcp->tov = MBX_TOV_SECONDS;
  2277. mcp->flags = IOCTL_CMD;
  2278. rval = qla2x00_mailbox_command(vha, mcp);
  2279. if (rval == QLA_SUCCESS) {
  2280. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2281. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2282. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2283. rval = QLA_FUNCTION_FAILED;
  2284. } else {
  2285. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2286. "Done %s.\n", __func__);
  2287. /* Copy over data -- firmware data is LE. */
  2288. dwords = sizeof(struct link_statistics) / 4;
  2289. siter = diter = &stats->link_fail_cnt;
  2290. while (dwords--)
  2291. *diter++ = le32_to_cpu(*siter++);
  2292. }
  2293. } else {
  2294. /* Failed. */
  2295. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2296. }
  2297. return rval;
  2298. }
  2299. int
  2300. qla24xx_abort_command(srb_t *sp)
  2301. {
  2302. int rval;
  2303. unsigned long flags = 0;
  2304. struct abort_entry_24xx *abt;
  2305. dma_addr_t abt_dma;
  2306. uint32_t handle;
  2307. fc_port_t *fcport = sp->fcport;
  2308. struct scsi_qla_host *vha = fcport->vha;
  2309. struct qla_hw_data *ha = vha->hw;
  2310. struct req_que *req = vha->req;
  2311. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2312. "Entered %s.\n", __func__);
  2313. spin_lock_irqsave(&ha->hardware_lock, flags);
  2314. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  2315. if (req->outstanding_cmds[handle] == sp)
  2316. break;
  2317. }
  2318. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2319. if (handle == req->num_outstanding_cmds) {
  2320. /* Command not found. */
  2321. return QLA_FUNCTION_FAILED;
  2322. }
  2323. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2324. if (abt == NULL) {
  2325. ql_log(ql_log_warn, vha, 0x108d,
  2326. "Failed to allocate abort IOCB.\n");
  2327. return QLA_MEMORY_ALLOC_FAILED;
  2328. }
  2329. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2330. abt->entry_type = ABORT_IOCB_TYPE;
  2331. abt->entry_count = 1;
  2332. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2333. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2334. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2335. abt->port_id[0] = fcport->d_id.b.al_pa;
  2336. abt->port_id[1] = fcport->d_id.b.area;
  2337. abt->port_id[2] = fcport->d_id.b.domain;
  2338. abt->vp_index = fcport->vha->vp_idx;
  2339. abt->req_que_no = cpu_to_le16(req->id);
  2340. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2341. if (rval != QLA_SUCCESS) {
  2342. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2343. "Failed to issue IOCB (%x).\n", rval);
  2344. } else if (abt->entry_status != 0) {
  2345. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2346. "Failed to complete IOCB -- error status (%x).\n",
  2347. abt->entry_status);
  2348. rval = QLA_FUNCTION_FAILED;
  2349. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2350. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2351. "Failed to complete IOCB -- completion status (%x).\n",
  2352. le16_to_cpu(abt->nport_handle));
  2353. rval = QLA_FUNCTION_FAILED;
  2354. } else {
  2355. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2356. "Done %s.\n", __func__);
  2357. }
  2358. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2359. return rval;
  2360. }
  2361. struct tsk_mgmt_cmd {
  2362. union {
  2363. struct tsk_mgmt_entry tsk;
  2364. struct sts_entry_24xx sts;
  2365. } p;
  2366. };
  2367. static int
  2368. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2369. unsigned int l, int tag)
  2370. {
  2371. int rval, rval2;
  2372. struct tsk_mgmt_cmd *tsk;
  2373. struct sts_entry_24xx *sts;
  2374. dma_addr_t tsk_dma;
  2375. scsi_qla_host_t *vha;
  2376. struct qla_hw_data *ha;
  2377. struct req_que *req;
  2378. struct rsp_que *rsp;
  2379. vha = fcport->vha;
  2380. ha = vha->hw;
  2381. req = vha->req;
  2382. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2383. "Entered %s.\n", __func__);
  2384. if (ha->flags.cpu_affinity_enabled)
  2385. rsp = ha->rsp_q_map[tag + 1];
  2386. else
  2387. rsp = req->rsp;
  2388. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2389. if (tsk == NULL) {
  2390. ql_log(ql_log_warn, vha, 0x1093,
  2391. "Failed to allocate task management IOCB.\n");
  2392. return QLA_MEMORY_ALLOC_FAILED;
  2393. }
  2394. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2395. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2396. tsk->p.tsk.entry_count = 1;
  2397. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2398. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2399. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2400. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2401. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2402. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2403. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2404. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2405. if (type == TCF_LUN_RESET) {
  2406. int_to_scsilun(l, &tsk->p.tsk.lun);
  2407. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2408. sizeof(tsk->p.tsk.lun));
  2409. }
  2410. sts = &tsk->p.sts;
  2411. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2412. if (rval != QLA_SUCCESS) {
  2413. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2414. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2415. } else if (sts->entry_status != 0) {
  2416. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2417. "Failed to complete IOCB -- error status (%x).\n",
  2418. sts->entry_status);
  2419. rval = QLA_FUNCTION_FAILED;
  2420. } else if (sts->comp_status !=
  2421. __constant_cpu_to_le16(CS_COMPLETE)) {
  2422. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2423. "Failed to complete IOCB -- completion status (%x).\n",
  2424. le16_to_cpu(sts->comp_status));
  2425. rval = QLA_FUNCTION_FAILED;
  2426. } else if (le16_to_cpu(sts->scsi_status) &
  2427. SS_RESPONSE_INFO_LEN_VALID) {
  2428. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2429. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2430. "Ignoring inconsistent data length -- not enough "
  2431. "response info (%d).\n",
  2432. le32_to_cpu(sts->rsp_data_len));
  2433. } else if (sts->data[3]) {
  2434. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2435. "Failed to complete IOCB -- response (%x).\n",
  2436. sts->data[3]);
  2437. rval = QLA_FUNCTION_FAILED;
  2438. }
  2439. }
  2440. /* Issue marker IOCB. */
  2441. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2442. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2443. if (rval2 != QLA_SUCCESS) {
  2444. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2445. "Failed to issue marker IOCB (%x).\n", rval2);
  2446. } else {
  2447. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2448. "Done %s.\n", __func__);
  2449. }
  2450. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2451. return rval;
  2452. }
  2453. int
  2454. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2455. {
  2456. struct qla_hw_data *ha = fcport->vha->hw;
  2457. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2458. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2459. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2460. }
  2461. int
  2462. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2463. {
  2464. struct qla_hw_data *ha = fcport->vha->hw;
  2465. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2466. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2467. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2468. }
  2469. int
  2470. qla2x00_system_error(scsi_qla_host_t *vha)
  2471. {
  2472. int rval;
  2473. mbx_cmd_t mc;
  2474. mbx_cmd_t *mcp = &mc;
  2475. struct qla_hw_data *ha = vha->hw;
  2476. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2477. return QLA_FUNCTION_FAILED;
  2478. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2479. "Entered %s.\n", __func__);
  2480. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2481. mcp->out_mb = MBX_0;
  2482. mcp->in_mb = MBX_0;
  2483. mcp->tov = 5;
  2484. mcp->flags = 0;
  2485. rval = qla2x00_mailbox_command(vha, mcp);
  2486. if (rval != QLA_SUCCESS) {
  2487. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2488. } else {
  2489. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2490. "Done %s.\n", __func__);
  2491. }
  2492. return rval;
  2493. }
  2494. /**
  2495. * qla2x00_set_serdes_params() -
  2496. * @ha: HA context
  2497. *
  2498. * Returns
  2499. */
  2500. int
  2501. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2502. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2503. {
  2504. int rval;
  2505. mbx_cmd_t mc;
  2506. mbx_cmd_t *mcp = &mc;
  2507. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2508. "Entered %s.\n", __func__);
  2509. mcp->mb[0] = MBC_SERDES_PARAMS;
  2510. mcp->mb[1] = BIT_0;
  2511. mcp->mb[2] = sw_em_1g | BIT_15;
  2512. mcp->mb[3] = sw_em_2g | BIT_15;
  2513. mcp->mb[4] = sw_em_4g | BIT_15;
  2514. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2515. mcp->in_mb = MBX_0;
  2516. mcp->tov = MBX_TOV_SECONDS;
  2517. mcp->flags = 0;
  2518. rval = qla2x00_mailbox_command(vha, mcp);
  2519. if (rval != QLA_SUCCESS) {
  2520. /*EMPTY*/
  2521. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2522. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2523. } else {
  2524. /*EMPTY*/
  2525. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2526. "Done %s.\n", __func__);
  2527. }
  2528. return rval;
  2529. }
  2530. int
  2531. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2532. {
  2533. int rval;
  2534. mbx_cmd_t mc;
  2535. mbx_cmd_t *mcp = &mc;
  2536. if (!IS_FWI2_CAPABLE(vha->hw))
  2537. return QLA_FUNCTION_FAILED;
  2538. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2539. "Entered %s.\n", __func__);
  2540. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2541. mcp->mb[1] = 0;
  2542. mcp->out_mb = MBX_1|MBX_0;
  2543. mcp->in_mb = MBX_0;
  2544. mcp->tov = 5;
  2545. mcp->flags = 0;
  2546. rval = qla2x00_mailbox_command(vha, mcp);
  2547. if (rval != QLA_SUCCESS) {
  2548. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2549. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2550. rval = QLA_INVALID_COMMAND;
  2551. } else {
  2552. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2553. "Done %s.\n", __func__);
  2554. }
  2555. return rval;
  2556. }
  2557. int
  2558. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2559. uint16_t buffers)
  2560. {
  2561. int rval;
  2562. mbx_cmd_t mc;
  2563. mbx_cmd_t *mcp = &mc;
  2564. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2565. "Entered %s.\n", __func__);
  2566. if (!IS_FWI2_CAPABLE(vha->hw))
  2567. return QLA_FUNCTION_FAILED;
  2568. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2569. return QLA_FUNCTION_FAILED;
  2570. mcp->mb[0] = MBC_TRACE_CONTROL;
  2571. mcp->mb[1] = TC_EFT_ENABLE;
  2572. mcp->mb[2] = LSW(eft_dma);
  2573. mcp->mb[3] = MSW(eft_dma);
  2574. mcp->mb[4] = LSW(MSD(eft_dma));
  2575. mcp->mb[5] = MSW(MSD(eft_dma));
  2576. mcp->mb[6] = buffers;
  2577. mcp->mb[7] = TC_AEN_DISABLE;
  2578. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2579. mcp->in_mb = MBX_1|MBX_0;
  2580. mcp->tov = MBX_TOV_SECONDS;
  2581. mcp->flags = 0;
  2582. rval = qla2x00_mailbox_command(vha, mcp);
  2583. if (rval != QLA_SUCCESS) {
  2584. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2585. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2586. rval, mcp->mb[0], mcp->mb[1]);
  2587. } else {
  2588. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2589. "Done %s.\n", __func__);
  2590. }
  2591. return rval;
  2592. }
  2593. int
  2594. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2595. {
  2596. int rval;
  2597. mbx_cmd_t mc;
  2598. mbx_cmd_t *mcp = &mc;
  2599. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2600. "Entered %s.\n", __func__);
  2601. if (!IS_FWI2_CAPABLE(vha->hw))
  2602. return QLA_FUNCTION_FAILED;
  2603. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2604. return QLA_FUNCTION_FAILED;
  2605. mcp->mb[0] = MBC_TRACE_CONTROL;
  2606. mcp->mb[1] = TC_EFT_DISABLE;
  2607. mcp->out_mb = MBX_1|MBX_0;
  2608. mcp->in_mb = MBX_1|MBX_0;
  2609. mcp->tov = MBX_TOV_SECONDS;
  2610. mcp->flags = 0;
  2611. rval = qla2x00_mailbox_command(vha, mcp);
  2612. if (rval != QLA_SUCCESS) {
  2613. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2614. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2615. rval, mcp->mb[0], mcp->mb[1]);
  2616. } else {
  2617. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2618. "Done %s.\n", __func__);
  2619. }
  2620. return rval;
  2621. }
  2622. int
  2623. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2624. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2625. {
  2626. int rval;
  2627. mbx_cmd_t mc;
  2628. mbx_cmd_t *mcp = &mc;
  2629. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2630. "Entered %s.\n", __func__);
  2631. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2632. !IS_QLA83XX(vha->hw))
  2633. return QLA_FUNCTION_FAILED;
  2634. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2635. return QLA_FUNCTION_FAILED;
  2636. mcp->mb[0] = MBC_TRACE_CONTROL;
  2637. mcp->mb[1] = TC_FCE_ENABLE;
  2638. mcp->mb[2] = LSW(fce_dma);
  2639. mcp->mb[3] = MSW(fce_dma);
  2640. mcp->mb[4] = LSW(MSD(fce_dma));
  2641. mcp->mb[5] = MSW(MSD(fce_dma));
  2642. mcp->mb[6] = buffers;
  2643. mcp->mb[7] = TC_AEN_DISABLE;
  2644. mcp->mb[8] = 0;
  2645. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2646. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2647. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2648. MBX_1|MBX_0;
  2649. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2650. mcp->tov = MBX_TOV_SECONDS;
  2651. mcp->flags = 0;
  2652. rval = qla2x00_mailbox_command(vha, mcp);
  2653. if (rval != QLA_SUCCESS) {
  2654. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2655. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2656. rval, mcp->mb[0], mcp->mb[1]);
  2657. } else {
  2658. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2659. "Done %s.\n", __func__);
  2660. if (mb)
  2661. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2662. if (dwords)
  2663. *dwords = buffers;
  2664. }
  2665. return rval;
  2666. }
  2667. int
  2668. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2669. {
  2670. int rval;
  2671. mbx_cmd_t mc;
  2672. mbx_cmd_t *mcp = &mc;
  2673. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2674. "Entered %s.\n", __func__);
  2675. if (!IS_FWI2_CAPABLE(vha->hw))
  2676. return QLA_FUNCTION_FAILED;
  2677. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2678. return QLA_FUNCTION_FAILED;
  2679. mcp->mb[0] = MBC_TRACE_CONTROL;
  2680. mcp->mb[1] = TC_FCE_DISABLE;
  2681. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2682. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2683. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2684. MBX_1|MBX_0;
  2685. mcp->tov = MBX_TOV_SECONDS;
  2686. mcp->flags = 0;
  2687. rval = qla2x00_mailbox_command(vha, mcp);
  2688. if (rval != QLA_SUCCESS) {
  2689. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2690. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2691. rval, mcp->mb[0], mcp->mb[1]);
  2692. } else {
  2693. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2694. "Done %s.\n", __func__);
  2695. if (wr)
  2696. *wr = (uint64_t) mcp->mb[5] << 48 |
  2697. (uint64_t) mcp->mb[4] << 32 |
  2698. (uint64_t) mcp->mb[3] << 16 |
  2699. (uint64_t) mcp->mb[2];
  2700. if (rd)
  2701. *rd = (uint64_t) mcp->mb[9] << 48 |
  2702. (uint64_t) mcp->mb[8] << 32 |
  2703. (uint64_t) mcp->mb[7] << 16 |
  2704. (uint64_t) mcp->mb[6];
  2705. }
  2706. return rval;
  2707. }
  2708. int
  2709. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2710. uint16_t *port_speed, uint16_t *mb)
  2711. {
  2712. int rval;
  2713. mbx_cmd_t mc;
  2714. mbx_cmd_t *mcp = &mc;
  2715. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2716. "Entered %s.\n", __func__);
  2717. if (!IS_IIDMA_CAPABLE(vha->hw))
  2718. return QLA_FUNCTION_FAILED;
  2719. mcp->mb[0] = MBC_PORT_PARAMS;
  2720. mcp->mb[1] = loop_id;
  2721. mcp->mb[2] = mcp->mb[3] = 0;
  2722. mcp->mb[9] = vha->vp_idx;
  2723. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2724. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2725. mcp->tov = MBX_TOV_SECONDS;
  2726. mcp->flags = 0;
  2727. rval = qla2x00_mailbox_command(vha, mcp);
  2728. /* Return mailbox statuses. */
  2729. if (mb != NULL) {
  2730. mb[0] = mcp->mb[0];
  2731. mb[1] = mcp->mb[1];
  2732. mb[3] = mcp->mb[3];
  2733. }
  2734. if (rval != QLA_SUCCESS) {
  2735. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2736. } else {
  2737. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2738. "Done %s.\n", __func__);
  2739. if (port_speed)
  2740. *port_speed = mcp->mb[3];
  2741. }
  2742. return rval;
  2743. }
  2744. int
  2745. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2746. uint16_t port_speed, uint16_t *mb)
  2747. {
  2748. int rval;
  2749. mbx_cmd_t mc;
  2750. mbx_cmd_t *mcp = &mc;
  2751. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2752. "Entered %s.\n", __func__);
  2753. if (!IS_IIDMA_CAPABLE(vha->hw))
  2754. return QLA_FUNCTION_FAILED;
  2755. mcp->mb[0] = MBC_PORT_PARAMS;
  2756. mcp->mb[1] = loop_id;
  2757. mcp->mb[2] = BIT_0;
  2758. if (IS_CNA_CAPABLE(vha->hw))
  2759. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2760. else
  2761. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2762. mcp->mb[9] = vha->vp_idx;
  2763. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2764. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2765. mcp->tov = MBX_TOV_SECONDS;
  2766. mcp->flags = 0;
  2767. rval = qla2x00_mailbox_command(vha, mcp);
  2768. /* Return mailbox statuses. */
  2769. if (mb != NULL) {
  2770. mb[0] = mcp->mb[0];
  2771. mb[1] = mcp->mb[1];
  2772. mb[3] = mcp->mb[3];
  2773. }
  2774. if (rval != QLA_SUCCESS) {
  2775. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2776. "Failed=%x.\n", rval);
  2777. } else {
  2778. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2779. "Done %s.\n", __func__);
  2780. }
  2781. return rval;
  2782. }
  2783. void
  2784. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2785. struct vp_rpt_id_entry_24xx *rptid_entry)
  2786. {
  2787. uint8_t vp_idx;
  2788. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2789. struct qla_hw_data *ha = vha->hw;
  2790. scsi_qla_host_t *vp;
  2791. unsigned long flags;
  2792. int found;
  2793. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2794. "Entered %s.\n", __func__);
  2795. if (rptid_entry->entry_status != 0)
  2796. return;
  2797. if (rptid_entry->format == 0) {
  2798. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2799. "Format 0 : Number of VPs setup %d, number of "
  2800. "VPs acquired %d.\n",
  2801. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2802. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2803. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2804. "Primary port id %02x%02x%02x.\n",
  2805. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2806. rptid_entry->port_id[0]);
  2807. } else if (rptid_entry->format == 1) {
  2808. vp_idx = LSB(stat);
  2809. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2810. "Format 1: VP[%d] enabled - status %d - with "
  2811. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2812. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2813. rptid_entry->port_id[0]);
  2814. vp = vha;
  2815. if (vp_idx == 0 && (MSB(stat) != 1))
  2816. goto reg_needed;
  2817. if (MSB(stat) != 0 && MSB(stat) != 2) {
  2818. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2819. "Could not acquire ID for VP[%d].\n", vp_idx);
  2820. return;
  2821. }
  2822. found = 0;
  2823. spin_lock_irqsave(&ha->vport_slock, flags);
  2824. list_for_each_entry(vp, &ha->vp_list, list) {
  2825. if (vp_idx == vp->vp_idx) {
  2826. found = 1;
  2827. break;
  2828. }
  2829. }
  2830. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2831. if (!found)
  2832. return;
  2833. vp->d_id.b.domain = rptid_entry->port_id[2];
  2834. vp->d_id.b.area = rptid_entry->port_id[1];
  2835. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2836. /*
  2837. * Cannot configure here as we are still sitting on the
  2838. * response queue. Handle it in dpc context.
  2839. */
  2840. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2841. reg_needed:
  2842. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2843. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2844. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2845. qla2xxx_wake_dpc(vha);
  2846. }
  2847. }
  2848. /*
  2849. * qla24xx_modify_vp_config
  2850. * Change VP configuration for vha
  2851. *
  2852. * Input:
  2853. * vha = adapter block pointer.
  2854. *
  2855. * Returns:
  2856. * qla2xxx local function return status code.
  2857. *
  2858. * Context:
  2859. * Kernel context.
  2860. */
  2861. int
  2862. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2863. {
  2864. int rval;
  2865. struct vp_config_entry_24xx *vpmod;
  2866. dma_addr_t vpmod_dma;
  2867. struct qla_hw_data *ha = vha->hw;
  2868. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2869. /* This can be called by the parent */
  2870. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  2871. "Entered %s.\n", __func__);
  2872. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2873. if (!vpmod) {
  2874. ql_log(ql_log_warn, vha, 0x10bc,
  2875. "Failed to allocate modify VP IOCB.\n");
  2876. return QLA_MEMORY_ALLOC_FAILED;
  2877. }
  2878. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2879. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2880. vpmod->entry_count = 1;
  2881. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2882. vpmod->vp_count = 1;
  2883. vpmod->vp_index1 = vha->vp_idx;
  2884. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2885. qlt_modify_vp_config(vha, vpmod);
  2886. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2887. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2888. vpmod->entry_count = 1;
  2889. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2890. if (rval != QLA_SUCCESS) {
  2891. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2892. "Failed to issue VP config IOCB (%x).\n", rval);
  2893. } else if (vpmod->comp_status != 0) {
  2894. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2895. "Failed to complete IOCB -- error status (%x).\n",
  2896. vpmod->comp_status);
  2897. rval = QLA_FUNCTION_FAILED;
  2898. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2899. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2900. "Failed to complete IOCB -- completion status (%x).\n",
  2901. le16_to_cpu(vpmod->comp_status));
  2902. rval = QLA_FUNCTION_FAILED;
  2903. } else {
  2904. /* EMPTY */
  2905. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  2906. "Done %s.\n", __func__);
  2907. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2908. }
  2909. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2910. return rval;
  2911. }
  2912. /*
  2913. * qla24xx_control_vp
  2914. * Enable a virtual port for given host
  2915. *
  2916. * Input:
  2917. * ha = adapter block pointer.
  2918. * vhba = virtual adapter (unused)
  2919. * index = index number for enabled VP
  2920. *
  2921. * Returns:
  2922. * qla2xxx local function return status code.
  2923. *
  2924. * Context:
  2925. * Kernel context.
  2926. */
  2927. int
  2928. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2929. {
  2930. int rval;
  2931. int map, pos;
  2932. struct vp_ctrl_entry_24xx *vce;
  2933. dma_addr_t vce_dma;
  2934. struct qla_hw_data *ha = vha->hw;
  2935. int vp_index = vha->vp_idx;
  2936. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2937. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  2938. "Entered %s enabling index %d.\n", __func__, vp_index);
  2939. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2940. return QLA_PARAMETER_ERROR;
  2941. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2942. if (!vce) {
  2943. ql_log(ql_log_warn, vha, 0x10c2,
  2944. "Failed to allocate VP control IOCB.\n");
  2945. return QLA_MEMORY_ALLOC_FAILED;
  2946. }
  2947. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2948. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2949. vce->entry_count = 1;
  2950. vce->command = cpu_to_le16(cmd);
  2951. vce->vp_count = __constant_cpu_to_le16(1);
  2952. /* index map in firmware starts with 1; decrement index
  2953. * this is ok as we never use index 0
  2954. */
  2955. map = (vp_index - 1) / 8;
  2956. pos = (vp_index - 1) & 7;
  2957. mutex_lock(&ha->vport_lock);
  2958. vce->vp_idx_map[map] |= 1 << pos;
  2959. mutex_unlock(&ha->vport_lock);
  2960. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2961. if (rval != QLA_SUCCESS) {
  2962. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2963. "Failed to issue VP control IOCB (%x).\n", rval);
  2964. } else if (vce->entry_status != 0) {
  2965. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2966. "Failed to complete IOCB -- error status (%x).\n",
  2967. vce->entry_status);
  2968. rval = QLA_FUNCTION_FAILED;
  2969. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2970. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2971. "Failed to complet IOCB -- completion status (%x).\n",
  2972. le16_to_cpu(vce->comp_status));
  2973. rval = QLA_FUNCTION_FAILED;
  2974. } else {
  2975. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  2976. "Done %s.\n", __func__);
  2977. }
  2978. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2979. return rval;
  2980. }
  2981. /*
  2982. * qla2x00_send_change_request
  2983. * Receive or disable RSCN request from fabric controller
  2984. *
  2985. * Input:
  2986. * ha = adapter block pointer
  2987. * format = registration format:
  2988. * 0 - Reserved
  2989. * 1 - Fabric detected registration
  2990. * 2 - N_port detected registration
  2991. * 3 - Full registration
  2992. * FF - clear registration
  2993. * vp_idx = Virtual port index
  2994. *
  2995. * Returns:
  2996. * qla2x00 local function return status code.
  2997. *
  2998. * Context:
  2999. * Kernel Context
  3000. */
  3001. int
  3002. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  3003. uint16_t vp_idx)
  3004. {
  3005. int rval;
  3006. mbx_cmd_t mc;
  3007. mbx_cmd_t *mcp = &mc;
  3008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  3009. "Entered %s.\n", __func__);
  3010. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  3011. mcp->mb[1] = format;
  3012. mcp->mb[9] = vp_idx;
  3013. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  3014. mcp->in_mb = MBX_0|MBX_1;
  3015. mcp->tov = MBX_TOV_SECONDS;
  3016. mcp->flags = 0;
  3017. rval = qla2x00_mailbox_command(vha, mcp);
  3018. if (rval == QLA_SUCCESS) {
  3019. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  3020. rval = BIT_1;
  3021. }
  3022. } else
  3023. rval = BIT_1;
  3024. return rval;
  3025. }
  3026. int
  3027. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  3028. uint32_t size)
  3029. {
  3030. int rval;
  3031. mbx_cmd_t mc;
  3032. mbx_cmd_t *mcp = &mc;
  3033. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  3034. "Entered %s.\n", __func__);
  3035. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  3036. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  3037. mcp->mb[8] = MSW(addr);
  3038. mcp->out_mb = MBX_8|MBX_0;
  3039. } else {
  3040. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  3041. mcp->out_mb = MBX_0;
  3042. }
  3043. mcp->mb[1] = LSW(addr);
  3044. mcp->mb[2] = MSW(req_dma);
  3045. mcp->mb[3] = LSW(req_dma);
  3046. mcp->mb[6] = MSW(MSD(req_dma));
  3047. mcp->mb[7] = LSW(MSD(req_dma));
  3048. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  3049. if (IS_FWI2_CAPABLE(vha->hw)) {
  3050. mcp->mb[4] = MSW(size);
  3051. mcp->mb[5] = LSW(size);
  3052. mcp->out_mb |= MBX_5|MBX_4;
  3053. } else {
  3054. mcp->mb[4] = LSW(size);
  3055. mcp->out_mb |= MBX_4;
  3056. }
  3057. mcp->in_mb = MBX_0;
  3058. mcp->tov = MBX_TOV_SECONDS;
  3059. mcp->flags = 0;
  3060. rval = qla2x00_mailbox_command(vha, mcp);
  3061. if (rval != QLA_SUCCESS) {
  3062. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  3063. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3064. } else {
  3065. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  3066. "Done %s.\n", __func__);
  3067. }
  3068. return rval;
  3069. }
  3070. /* 84XX Support **************************************************************/
  3071. struct cs84xx_mgmt_cmd {
  3072. union {
  3073. struct verify_chip_entry_84xx req;
  3074. struct verify_chip_rsp_84xx rsp;
  3075. } p;
  3076. };
  3077. int
  3078. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  3079. {
  3080. int rval, retry;
  3081. struct cs84xx_mgmt_cmd *mn;
  3082. dma_addr_t mn_dma;
  3083. uint16_t options;
  3084. unsigned long flags;
  3085. struct qla_hw_data *ha = vha->hw;
  3086. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  3087. "Entered %s.\n", __func__);
  3088. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  3089. if (mn == NULL) {
  3090. return QLA_MEMORY_ALLOC_FAILED;
  3091. }
  3092. /* Force Update? */
  3093. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  3094. /* Diagnostic firmware? */
  3095. /* options |= MENLO_DIAG_FW; */
  3096. /* We update the firmware with only one data sequence. */
  3097. options |= VCO_END_OF_DATA;
  3098. do {
  3099. retry = 0;
  3100. memset(mn, 0, sizeof(*mn));
  3101. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  3102. mn->p.req.entry_count = 1;
  3103. mn->p.req.options = cpu_to_le16(options);
  3104. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  3105. "Dump of Verify Request.\n");
  3106. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  3107. (uint8_t *)mn, sizeof(*mn));
  3108. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  3109. if (rval != QLA_SUCCESS) {
  3110. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  3111. "Failed to issue verify IOCB (%x).\n", rval);
  3112. goto verify_done;
  3113. }
  3114. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  3115. "Dump of Verify Response.\n");
  3116. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  3117. (uint8_t *)mn, sizeof(*mn));
  3118. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  3119. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  3120. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  3121. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  3122. "cs=%x fc=%x.\n", status[0], status[1]);
  3123. if (status[0] != CS_COMPLETE) {
  3124. rval = QLA_FUNCTION_FAILED;
  3125. if (!(options & VCO_DONT_UPDATE_FW)) {
  3126. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  3127. "Firmware update failed. Retrying "
  3128. "without update firmware.\n");
  3129. options |= VCO_DONT_UPDATE_FW;
  3130. options &= ~VCO_FORCE_UPDATE;
  3131. retry = 1;
  3132. }
  3133. } else {
  3134. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  3135. "Firmware updated to %x.\n",
  3136. le32_to_cpu(mn->p.rsp.fw_ver));
  3137. /* NOTE: we only update OP firmware. */
  3138. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  3139. ha->cs84xx->op_fw_version =
  3140. le32_to_cpu(mn->p.rsp.fw_ver);
  3141. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3142. flags);
  3143. }
  3144. } while (retry);
  3145. verify_done:
  3146. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3147. if (rval != QLA_SUCCESS) {
  3148. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3149. "Failed=%x.\n", rval);
  3150. } else {
  3151. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3152. "Done %s.\n", __func__);
  3153. }
  3154. return rval;
  3155. }
  3156. int
  3157. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3158. {
  3159. int rval;
  3160. unsigned long flags;
  3161. mbx_cmd_t mc;
  3162. mbx_cmd_t *mcp = &mc;
  3163. struct qla_hw_data *ha = vha->hw;
  3164. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3165. "Entered %s.\n", __func__);
  3166. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3167. mcp->mb[1] = req->options;
  3168. mcp->mb[2] = MSW(LSD(req->dma));
  3169. mcp->mb[3] = LSW(LSD(req->dma));
  3170. mcp->mb[6] = MSW(MSD(req->dma));
  3171. mcp->mb[7] = LSW(MSD(req->dma));
  3172. mcp->mb[5] = req->length;
  3173. if (req->rsp)
  3174. mcp->mb[10] = req->rsp->id;
  3175. mcp->mb[12] = req->qos;
  3176. mcp->mb[11] = req->vp_idx;
  3177. mcp->mb[13] = req->rid;
  3178. if (IS_QLA83XX(ha))
  3179. mcp->mb[15] = 0;
  3180. mcp->mb[4] = req->id;
  3181. /* que in ptr index */
  3182. mcp->mb[8] = 0;
  3183. /* que out ptr index */
  3184. mcp->mb[9] = 0;
  3185. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3186. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3187. mcp->in_mb = MBX_0;
  3188. mcp->flags = MBX_DMA_OUT;
  3189. mcp->tov = MBX_TOV_SECONDS * 2;
  3190. if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  3191. mcp->in_mb |= MBX_1;
  3192. if (IS_QLA83XX(ha)) {
  3193. mcp->out_mb |= MBX_15;
  3194. /* debug q create issue in SR-IOV */
  3195. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3196. }
  3197. spin_lock_irqsave(&ha->hardware_lock, flags);
  3198. if (!(req->options & BIT_0)) {
  3199. WRT_REG_DWORD(req->req_q_in, 0);
  3200. if (!IS_QLA83XX(ha))
  3201. WRT_REG_DWORD(req->req_q_out, 0);
  3202. }
  3203. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3204. rval = qla2x00_mailbox_command(vha, mcp);
  3205. if (rval != QLA_SUCCESS) {
  3206. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3207. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3208. } else {
  3209. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3210. "Done %s.\n", __func__);
  3211. }
  3212. return rval;
  3213. }
  3214. int
  3215. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3216. {
  3217. int rval;
  3218. unsigned long flags;
  3219. mbx_cmd_t mc;
  3220. mbx_cmd_t *mcp = &mc;
  3221. struct qla_hw_data *ha = vha->hw;
  3222. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3223. "Entered %s.\n", __func__);
  3224. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3225. mcp->mb[1] = rsp->options;
  3226. mcp->mb[2] = MSW(LSD(rsp->dma));
  3227. mcp->mb[3] = LSW(LSD(rsp->dma));
  3228. mcp->mb[6] = MSW(MSD(rsp->dma));
  3229. mcp->mb[7] = LSW(MSD(rsp->dma));
  3230. mcp->mb[5] = rsp->length;
  3231. mcp->mb[14] = rsp->msix->entry;
  3232. mcp->mb[13] = rsp->rid;
  3233. if (IS_QLA83XX(ha))
  3234. mcp->mb[15] = 0;
  3235. mcp->mb[4] = rsp->id;
  3236. /* que in ptr index */
  3237. mcp->mb[8] = 0;
  3238. /* que out ptr index */
  3239. mcp->mb[9] = 0;
  3240. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3241. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3242. mcp->in_mb = MBX_0;
  3243. mcp->flags = MBX_DMA_OUT;
  3244. mcp->tov = MBX_TOV_SECONDS * 2;
  3245. if (IS_QLA81XX(ha)) {
  3246. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3247. mcp->in_mb |= MBX_1;
  3248. } else if (IS_QLA83XX(ha)) {
  3249. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3250. mcp->in_mb |= MBX_1;
  3251. /* debug q create issue in SR-IOV */
  3252. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3253. }
  3254. spin_lock_irqsave(&ha->hardware_lock, flags);
  3255. if (!(rsp->options & BIT_0)) {
  3256. WRT_REG_DWORD(rsp->rsp_q_out, 0);
  3257. if (!IS_QLA83XX(ha))
  3258. WRT_REG_DWORD(rsp->rsp_q_in, 0);
  3259. }
  3260. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3261. rval = qla2x00_mailbox_command(vha, mcp);
  3262. if (rval != QLA_SUCCESS) {
  3263. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3264. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3265. } else {
  3266. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3267. "Done %s.\n", __func__);
  3268. }
  3269. return rval;
  3270. }
  3271. int
  3272. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3273. {
  3274. int rval;
  3275. mbx_cmd_t mc;
  3276. mbx_cmd_t *mcp = &mc;
  3277. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3278. "Entered %s.\n", __func__);
  3279. mcp->mb[0] = MBC_IDC_ACK;
  3280. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3281. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3282. mcp->in_mb = MBX_0;
  3283. mcp->tov = MBX_TOV_SECONDS;
  3284. mcp->flags = 0;
  3285. rval = qla2x00_mailbox_command(vha, mcp);
  3286. if (rval != QLA_SUCCESS) {
  3287. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3288. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3289. } else {
  3290. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3291. "Done %s.\n", __func__);
  3292. }
  3293. return rval;
  3294. }
  3295. int
  3296. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3297. {
  3298. int rval;
  3299. mbx_cmd_t mc;
  3300. mbx_cmd_t *mcp = &mc;
  3301. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3302. "Entered %s.\n", __func__);
  3303. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3304. return QLA_FUNCTION_FAILED;
  3305. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3306. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3307. mcp->out_mb = MBX_1|MBX_0;
  3308. mcp->in_mb = MBX_1|MBX_0;
  3309. mcp->tov = MBX_TOV_SECONDS;
  3310. mcp->flags = 0;
  3311. rval = qla2x00_mailbox_command(vha, mcp);
  3312. if (rval != QLA_SUCCESS) {
  3313. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3314. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3315. rval, mcp->mb[0], mcp->mb[1]);
  3316. } else {
  3317. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3318. "Done %s.\n", __func__);
  3319. *sector_size = mcp->mb[1];
  3320. }
  3321. return rval;
  3322. }
  3323. int
  3324. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3325. {
  3326. int rval;
  3327. mbx_cmd_t mc;
  3328. mbx_cmd_t *mcp = &mc;
  3329. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3330. return QLA_FUNCTION_FAILED;
  3331. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3332. "Entered %s.\n", __func__);
  3333. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3334. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3335. FAC_OPT_CMD_WRITE_PROTECT;
  3336. mcp->out_mb = MBX_1|MBX_0;
  3337. mcp->in_mb = MBX_1|MBX_0;
  3338. mcp->tov = MBX_TOV_SECONDS;
  3339. mcp->flags = 0;
  3340. rval = qla2x00_mailbox_command(vha, mcp);
  3341. if (rval != QLA_SUCCESS) {
  3342. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3343. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3344. rval, mcp->mb[0], mcp->mb[1]);
  3345. } else {
  3346. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3347. "Done %s.\n", __func__);
  3348. }
  3349. return rval;
  3350. }
  3351. int
  3352. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3353. {
  3354. int rval;
  3355. mbx_cmd_t mc;
  3356. mbx_cmd_t *mcp = &mc;
  3357. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3358. return QLA_FUNCTION_FAILED;
  3359. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3360. "Entered %s.\n", __func__);
  3361. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3362. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3363. mcp->mb[2] = LSW(start);
  3364. mcp->mb[3] = MSW(start);
  3365. mcp->mb[4] = LSW(finish);
  3366. mcp->mb[5] = MSW(finish);
  3367. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3368. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3369. mcp->tov = MBX_TOV_SECONDS;
  3370. mcp->flags = 0;
  3371. rval = qla2x00_mailbox_command(vha, mcp);
  3372. if (rval != QLA_SUCCESS) {
  3373. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3374. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3375. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3376. } else {
  3377. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3378. "Done %s.\n", __func__);
  3379. }
  3380. return rval;
  3381. }
  3382. int
  3383. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3384. {
  3385. int rval = 0;
  3386. mbx_cmd_t mc;
  3387. mbx_cmd_t *mcp = &mc;
  3388. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3389. "Entered %s.\n", __func__);
  3390. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3391. mcp->out_mb = MBX_0;
  3392. mcp->in_mb = MBX_0|MBX_1;
  3393. mcp->tov = MBX_TOV_SECONDS;
  3394. mcp->flags = 0;
  3395. rval = qla2x00_mailbox_command(vha, mcp);
  3396. if (rval != QLA_SUCCESS) {
  3397. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3398. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3399. rval, mcp->mb[0], mcp->mb[1]);
  3400. } else {
  3401. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3402. "Done %s.\n", __func__);
  3403. }
  3404. return rval;
  3405. }
  3406. int
  3407. qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
  3408. {
  3409. int rval;
  3410. mbx_cmd_t mc;
  3411. mbx_cmd_t *mcp = &mc;
  3412. int i;
  3413. int len;
  3414. uint16_t *str;
  3415. struct qla_hw_data *ha = vha->hw;
  3416. if (!IS_P3P_TYPE(ha))
  3417. return QLA_FUNCTION_FAILED;
  3418. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
  3419. "Entered %s.\n", __func__);
  3420. str = (void *)version;
  3421. len = strlen(version);
  3422. mcp->mb[0] = MBC_SET_RNID_PARAMS;
  3423. mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
  3424. mcp->out_mb = MBX_1|MBX_0;
  3425. for (i = 4; i < 16 && len; i++, str++, len -= 2) {
  3426. mcp->mb[i] = cpu_to_le16p(str);
  3427. mcp->out_mb |= 1<<i;
  3428. }
  3429. for (; i < 16; i++) {
  3430. mcp->mb[i] = 0;
  3431. mcp->out_mb |= 1<<i;
  3432. }
  3433. mcp->in_mb = MBX_1|MBX_0;
  3434. mcp->tov = MBX_TOV_SECONDS;
  3435. mcp->flags = 0;
  3436. rval = qla2x00_mailbox_command(vha, mcp);
  3437. if (rval != QLA_SUCCESS) {
  3438. ql_dbg(ql_dbg_mbx, vha, 0x117c,
  3439. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3440. } else {
  3441. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
  3442. "Done %s.\n", __func__);
  3443. }
  3444. return rval;
  3445. }
  3446. int
  3447. qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
  3448. {
  3449. int rval;
  3450. mbx_cmd_t mc;
  3451. mbx_cmd_t *mcp = &mc;
  3452. int len;
  3453. uint16_t dwlen;
  3454. uint8_t *str;
  3455. dma_addr_t str_dma;
  3456. struct qla_hw_data *ha = vha->hw;
  3457. if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
  3458. IS_P3P_TYPE(ha))
  3459. return QLA_FUNCTION_FAILED;
  3460. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
  3461. "Entered %s.\n", __func__);
  3462. str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
  3463. if (!str) {
  3464. ql_log(ql_log_warn, vha, 0x117f,
  3465. "Failed to allocate driver version param.\n");
  3466. return QLA_MEMORY_ALLOC_FAILED;
  3467. }
  3468. memcpy(str, "\x7\x3\x11\x0", 4);
  3469. dwlen = str[0];
  3470. len = dwlen * 4 - 4;
  3471. memset(str + 4, 0, len);
  3472. if (len > strlen(version))
  3473. len = strlen(version);
  3474. memcpy(str + 4, version, len);
  3475. mcp->mb[0] = MBC_SET_RNID_PARAMS;
  3476. mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
  3477. mcp->mb[2] = MSW(LSD(str_dma));
  3478. mcp->mb[3] = LSW(LSD(str_dma));
  3479. mcp->mb[6] = MSW(MSD(str_dma));
  3480. mcp->mb[7] = LSW(MSD(str_dma));
  3481. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3482. mcp->in_mb = MBX_1|MBX_0;
  3483. mcp->tov = MBX_TOV_SECONDS;
  3484. mcp->flags = 0;
  3485. rval = qla2x00_mailbox_command(vha, mcp);
  3486. if (rval != QLA_SUCCESS) {
  3487. ql_dbg(ql_dbg_mbx, vha, 0x1180,
  3488. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3489. } else {
  3490. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
  3491. "Done %s.\n", __func__);
  3492. }
  3493. dma_pool_free(ha->s_dma_pool, str, str_dma);
  3494. return rval;
  3495. }
  3496. static int
  3497. qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
  3498. {
  3499. int rval;
  3500. mbx_cmd_t mc;
  3501. mbx_cmd_t *mcp = &mc;
  3502. if (!IS_FWI2_CAPABLE(vha->hw))
  3503. return QLA_FUNCTION_FAILED;
  3504. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
  3505. "Entered %s.\n", __func__);
  3506. mcp->mb[0] = MBC_GET_RNID_PARAMS;
  3507. mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
  3508. mcp->out_mb = MBX_1|MBX_0;
  3509. mcp->in_mb = MBX_1|MBX_0;
  3510. mcp->tov = MBX_TOV_SECONDS;
  3511. mcp->flags = 0;
  3512. rval = qla2x00_mailbox_command(vha, mcp);
  3513. *temp = mcp->mb[1];
  3514. if (rval != QLA_SUCCESS) {
  3515. ql_dbg(ql_dbg_mbx, vha, 0x115a,
  3516. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3517. } else {
  3518. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
  3519. "Done %s.\n", __func__);
  3520. }
  3521. return rval;
  3522. }
  3523. int
  3524. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3525. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3526. {
  3527. int rval;
  3528. mbx_cmd_t mc;
  3529. mbx_cmd_t *mcp = &mc;
  3530. struct qla_hw_data *ha = vha->hw;
  3531. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3532. "Entered %s.\n", __func__);
  3533. if (!IS_FWI2_CAPABLE(ha))
  3534. return QLA_FUNCTION_FAILED;
  3535. if (len == 1)
  3536. opt |= BIT_0;
  3537. mcp->mb[0] = MBC_READ_SFP;
  3538. mcp->mb[1] = dev;
  3539. mcp->mb[2] = MSW(sfp_dma);
  3540. mcp->mb[3] = LSW(sfp_dma);
  3541. mcp->mb[6] = MSW(MSD(sfp_dma));
  3542. mcp->mb[7] = LSW(MSD(sfp_dma));
  3543. mcp->mb[8] = len;
  3544. mcp->mb[9] = off;
  3545. mcp->mb[10] = opt;
  3546. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3547. mcp->in_mb = MBX_1|MBX_0;
  3548. mcp->tov = MBX_TOV_SECONDS;
  3549. mcp->flags = 0;
  3550. rval = qla2x00_mailbox_command(vha, mcp);
  3551. if (opt & BIT_0)
  3552. *sfp = mcp->mb[1];
  3553. if (rval != QLA_SUCCESS) {
  3554. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3555. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3556. } else {
  3557. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3558. "Done %s.\n", __func__);
  3559. }
  3560. return rval;
  3561. }
  3562. int
  3563. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3564. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3565. {
  3566. int rval;
  3567. mbx_cmd_t mc;
  3568. mbx_cmd_t *mcp = &mc;
  3569. struct qla_hw_data *ha = vha->hw;
  3570. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3571. "Entered %s.\n", __func__);
  3572. if (!IS_FWI2_CAPABLE(ha))
  3573. return QLA_FUNCTION_FAILED;
  3574. if (len == 1)
  3575. opt |= BIT_0;
  3576. if (opt & BIT_0)
  3577. len = *sfp;
  3578. mcp->mb[0] = MBC_WRITE_SFP;
  3579. mcp->mb[1] = dev;
  3580. mcp->mb[2] = MSW(sfp_dma);
  3581. mcp->mb[3] = LSW(sfp_dma);
  3582. mcp->mb[6] = MSW(MSD(sfp_dma));
  3583. mcp->mb[7] = LSW(MSD(sfp_dma));
  3584. mcp->mb[8] = len;
  3585. mcp->mb[9] = off;
  3586. mcp->mb[10] = opt;
  3587. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3588. mcp->in_mb = MBX_1|MBX_0;
  3589. mcp->tov = MBX_TOV_SECONDS;
  3590. mcp->flags = 0;
  3591. rval = qla2x00_mailbox_command(vha, mcp);
  3592. if (rval != QLA_SUCCESS) {
  3593. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3594. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3595. } else {
  3596. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3597. "Done %s.\n", __func__);
  3598. }
  3599. return rval;
  3600. }
  3601. int
  3602. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3603. uint16_t size_in_bytes, uint16_t *actual_size)
  3604. {
  3605. int rval;
  3606. mbx_cmd_t mc;
  3607. mbx_cmd_t *mcp = &mc;
  3608. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3609. "Entered %s.\n", __func__);
  3610. if (!IS_CNA_CAPABLE(vha->hw))
  3611. return QLA_FUNCTION_FAILED;
  3612. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3613. mcp->mb[2] = MSW(stats_dma);
  3614. mcp->mb[3] = LSW(stats_dma);
  3615. mcp->mb[6] = MSW(MSD(stats_dma));
  3616. mcp->mb[7] = LSW(MSD(stats_dma));
  3617. mcp->mb[8] = size_in_bytes >> 2;
  3618. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3619. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3620. mcp->tov = MBX_TOV_SECONDS;
  3621. mcp->flags = 0;
  3622. rval = qla2x00_mailbox_command(vha, mcp);
  3623. if (rval != QLA_SUCCESS) {
  3624. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3625. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3626. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3627. } else {
  3628. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3629. "Done %s.\n", __func__);
  3630. *actual_size = mcp->mb[2] << 2;
  3631. }
  3632. return rval;
  3633. }
  3634. int
  3635. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3636. uint16_t size)
  3637. {
  3638. int rval;
  3639. mbx_cmd_t mc;
  3640. mbx_cmd_t *mcp = &mc;
  3641. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3642. "Entered %s.\n", __func__);
  3643. if (!IS_CNA_CAPABLE(vha->hw))
  3644. return QLA_FUNCTION_FAILED;
  3645. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3646. mcp->mb[1] = 0;
  3647. mcp->mb[2] = MSW(tlv_dma);
  3648. mcp->mb[3] = LSW(tlv_dma);
  3649. mcp->mb[6] = MSW(MSD(tlv_dma));
  3650. mcp->mb[7] = LSW(MSD(tlv_dma));
  3651. mcp->mb[8] = size;
  3652. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3653. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3654. mcp->tov = MBX_TOV_SECONDS;
  3655. mcp->flags = 0;
  3656. rval = qla2x00_mailbox_command(vha, mcp);
  3657. if (rval != QLA_SUCCESS) {
  3658. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3659. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3660. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3661. } else {
  3662. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3663. "Done %s.\n", __func__);
  3664. }
  3665. return rval;
  3666. }
  3667. int
  3668. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3669. {
  3670. int rval;
  3671. mbx_cmd_t mc;
  3672. mbx_cmd_t *mcp = &mc;
  3673. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3674. "Entered %s.\n", __func__);
  3675. if (!IS_FWI2_CAPABLE(vha->hw))
  3676. return QLA_FUNCTION_FAILED;
  3677. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3678. mcp->mb[1] = LSW(risc_addr);
  3679. mcp->mb[8] = MSW(risc_addr);
  3680. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3681. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3682. mcp->tov = 30;
  3683. mcp->flags = 0;
  3684. rval = qla2x00_mailbox_command(vha, mcp);
  3685. if (rval != QLA_SUCCESS) {
  3686. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3687. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3688. } else {
  3689. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3690. "Done %s.\n", __func__);
  3691. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3692. }
  3693. return rval;
  3694. }
  3695. int
  3696. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3697. uint16_t *mresp)
  3698. {
  3699. int rval;
  3700. mbx_cmd_t mc;
  3701. mbx_cmd_t *mcp = &mc;
  3702. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3703. "Entered %s.\n", __func__);
  3704. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3705. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3706. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3707. /* transfer count */
  3708. mcp->mb[10] = LSW(mreq->transfer_size);
  3709. mcp->mb[11] = MSW(mreq->transfer_size);
  3710. /* send data address */
  3711. mcp->mb[14] = LSW(mreq->send_dma);
  3712. mcp->mb[15] = MSW(mreq->send_dma);
  3713. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3714. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3715. /* receive data address */
  3716. mcp->mb[16] = LSW(mreq->rcv_dma);
  3717. mcp->mb[17] = MSW(mreq->rcv_dma);
  3718. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3719. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3720. /* Iteration count */
  3721. mcp->mb[18] = LSW(mreq->iteration_count);
  3722. mcp->mb[19] = MSW(mreq->iteration_count);
  3723. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3724. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3725. if (IS_CNA_CAPABLE(vha->hw))
  3726. mcp->out_mb |= MBX_2;
  3727. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3728. mcp->buf_size = mreq->transfer_size;
  3729. mcp->tov = MBX_TOV_SECONDS;
  3730. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3731. rval = qla2x00_mailbox_command(vha, mcp);
  3732. if (rval != QLA_SUCCESS) {
  3733. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3734. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3735. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3736. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3737. } else {
  3738. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3739. "Done %s.\n", __func__);
  3740. }
  3741. /* Copy mailbox information */
  3742. memcpy( mresp, mcp->mb, 64);
  3743. return rval;
  3744. }
  3745. int
  3746. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3747. uint16_t *mresp)
  3748. {
  3749. int rval;
  3750. mbx_cmd_t mc;
  3751. mbx_cmd_t *mcp = &mc;
  3752. struct qla_hw_data *ha = vha->hw;
  3753. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3754. "Entered %s.\n", __func__);
  3755. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3756. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3757. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3758. if (IS_CNA_CAPABLE(ha)) {
  3759. mcp->mb[1] |= BIT_15;
  3760. mcp->mb[2] = vha->fcoe_fcf_idx;
  3761. }
  3762. mcp->mb[16] = LSW(mreq->rcv_dma);
  3763. mcp->mb[17] = MSW(mreq->rcv_dma);
  3764. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3765. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3766. mcp->mb[10] = LSW(mreq->transfer_size);
  3767. mcp->mb[14] = LSW(mreq->send_dma);
  3768. mcp->mb[15] = MSW(mreq->send_dma);
  3769. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3770. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3771. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3772. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3773. if (IS_CNA_CAPABLE(ha))
  3774. mcp->out_mb |= MBX_2;
  3775. mcp->in_mb = MBX_0;
  3776. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3777. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3778. mcp->in_mb |= MBX_1;
  3779. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3780. mcp->in_mb |= MBX_3;
  3781. mcp->tov = MBX_TOV_SECONDS;
  3782. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3783. mcp->buf_size = mreq->transfer_size;
  3784. rval = qla2x00_mailbox_command(vha, mcp);
  3785. if (rval != QLA_SUCCESS) {
  3786. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3787. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3788. rval, mcp->mb[0], mcp->mb[1]);
  3789. } else {
  3790. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3791. "Done %s.\n", __func__);
  3792. }
  3793. /* Copy mailbox information */
  3794. memcpy(mresp, mcp->mb, 64);
  3795. return rval;
  3796. }
  3797. int
  3798. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3799. {
  3800. int rval;
  3801. mbx_cmd_t mc;
  3802. mbx_cmd_t *mcp = &mc;
  3803. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3804. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3805. mcp->mb[0] = MBC_ISP84XX_RESET;
  3806. mcp->mb[1] = enable_diagnostic;
  3807. mcp->out_mb = MBX_1|MBX_0;
  3808. mcp->in_mb = MBX_1|MBX_0;
  3809. mcp->tov = MBX_TOV_SECONDS;
  3810. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3811. rval = qla2x00_mailbox_command(vha, mcp);
  3812. if (rval != QLA_SUCCESS)
  3813. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3814. else
  3815. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  3816. "Done %s.\n", __func__);
  3817. return rval;
  3818. }
  3819. int
  3820. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3821. {
  3822. int rval;
  3823. mbx_cmd_t mc;
  3824. mbx_cmd_t *mcp = &mc;
  3825. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  3826. "Entered %s.\n", __func__);
  3827. if (!IS_FWI2_CAPABLE(vha->hw))
  3828. return QLA_FUNCTION_FAILED;
  3829. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3830. mcp->mb[1] = LSW(risc_addr);
  3831. mcp->mb[2] = LSW(data);
  3832. mcp->mb[3] = MSW(data);
  3833. mcp->mb[8] = MSW(risc_addr);
  3834. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3835. mcp->in_mb = MBX_0;
  3836. mcp->tov = 30;
  3837. mcp->flags = 0;
  3838. rval = qla2x00_mailbox_command(vha, mcp);
  3839. if (rval != QLA_SUCCESS) {
  3840. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3841. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3842. } else {
  3843. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  3844. "Done %s.\n", __func__);
  3845. }
  3846. return rval;
  3847. }
  3848. int
  3849. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3850. {
  3851. int rval;
  3852. uint32_t stat, timer;
  3853. uint16_t mb0 = 0;
  3854. struct qla_hw_data *ha = vha->hw;
  3855. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3856. rval = QLA_SUCCESS;
  3857. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  3858. "Entered %s.\n", __func__);
  3859. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3860. /* Write the MBC data to the registers */
  3861. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3862. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3863. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3864. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3865. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3866. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3867. /* Poll for MBC interrupt */
  3868. for (timer = 6000000; timer; timer--) {
  3869. /* Check for pending interrupts. */
  3870. stat = RD_REG_DWORD(&reg->host_status);
  3871. if (stat & HSRX_RISC_INT) {
  3872. stat &= 0xff;
  3873. if (stat == 0x1 || stat == 0x2 ||
  3874. stat == 0x10 || stat == 0x11) {
  3875. set_bit(MBX_INTERRUPT,
  3876. &ha->mbx_cmd_flags);
  3877. mb0 = RD_REG_WORD(&reg->mailbox0);
  3878. WRT_REG_DWORD(&reg->hccr,
  3879. HCCRX_CLR_RISC_INT);
  3880. RD_REG_DWORD(&reg->hccr);
  3881. break;
  3882. }
  3883. }
  3884. udelay(5);
  3885. }
  3886. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3887. rval = mb0 & MBS_MASK;
  3888. else
  3889. rval = QLA_FUNCTION_FAILED;
  3890. if (rval != QLA_SUCCESS) {
  3891. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3892. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3893. } else {
  3894. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  3895. "Done %s.\n", __func__);
  3896. }
  3897. return rval;
  3898. }
  3899. int
  3900. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3901. {
  3902. int rval;
  3903. mbx_cmd_t mc;
  3904. mbx_cmd_t *mcp = &mc;
  3905. struct qla_hw_data *ha = vha->hw;
  3906. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  3907. "Entered %s.\n", __func__);
  3908. if (!IS_FWI2_CAPABLE(ha))
  3909. return QLA_FUNCTION_FAILED;
  3910. mcp->mb[0] = MBC_DATA_RATE;
  3911. mcp->mb[1] = 0;
  3912. mcp->out_mb = MBX_1|MBX_0;
  3913. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3914. if (IS_QLA83XX(ha))
  3915. mcp->in_mb |= MBX_3;
  3916. mcp->tov = MBX_TOV_SECONDS;
  3917. mcp->flags = 0;
  3918. rval = qla2x00_mailbox_command(vha, mcp);
  3919. if (rval != QLA_SUCCESS) {
  3920. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3921. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3922. } else {
  3923. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  3924. "Done %s.\n", __func__);
  3925. if (mcp->mb[1] != 0x7)
  3926. ha->link_data_rate = mcp->mb[1];
  3927. }
  3928. return rval;
  3929. }
  3930. int
  3931. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3932. {
  3933. int rval;
  3934. mbx_cmd_t mc;
  3935. mbx_cmd_t *mcp = &mc;
  3936. struct qla_hw_data *ha = vha->hw;
  3937. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  3938. "Entered %s.\n", __func__);
  3939. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha))
  3940. return QLA_FUNCTION_FAILED;
  3941. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3942. mcp->out_mb = MBX_0;
  3943. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3944. mcp->tov = MBX_TOV_SECONDS;
  3945. mcp->flags = 0;
  3946. rval = qla2x00_mailbox_command(vha, mcp);
  3947. if (rval != QLA_SUCCESS) {
  3948. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3949. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3950. } else {
  3951. /* Copy all bits to preserve original value */
  3952. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3953. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  3954. "Done %s.\n", __func__);
  3955. }
  3956. return rval;
  3957. }
  3958. int
  3959. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3960. {
  3961. int rval;
  3962. mbx_cmd_t mc;
  3963. mbx_cmd_t *mcp = &mc;
  3964. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  3965. "Entered %s.\n", __func__);
  3966. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3967. /* Copy all bits to preserve original setting */
  3968. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3969. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3970. mcp->in_mb = MBX_0;
  3971. mcp->tov = MBX_TOV_SECONDS;
  3972. mcp->flags = 0;
  3973. rval = qla2x00_mailbox_command(vha, mcp);
  3974. if (rval != QLA_SUCCESS) {
  3975. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3976. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3977. } else
  3978. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  3979. "Done %s.\n", __func__);
  3980. return rval;
  3981. }
  3982. int
  3983. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3984. uint16_t *mb)
  3985. {
  3986. int rval;
  3987. mbx_cmd_t mc;
  3988. mbx_cmd_t *mcp = &mc;
  3989. struct qla_hw_data *ha = vha->hw;
  3990. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  3991. "Entered %s.\n", __func__);
  3992. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3993. return QLA_FUNCTION_FAILED;
  3994. mcp->mb[0] = MBC_PORT_PARAMS;
  3995. mcp->mb[1] = loop_id;
  3996. if (ha->flags.fcp_prio_enabled)
  3997. mcp->mb[2] = BIT_1;
  3998. else
  3999. mcp->mb[2] = BIT_2;
  4000. mcp->mb[4] = priority & 0xf;
  4001. mcp->mb[9] = vha->vp_idx;
  4002. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4003. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4004. mcp->tov = 30;
  4005. mcp->flags = 0;
  4006. rval = qla2x00_mailbox_command(vha, mcp);
  4007. if (mb != NULL) {
  4008. mb[0] = mcp->mb[0];
  4009. mb[1] = mcp->mb[1];
  4010. mb[3] = mcp->mb[3];
  4011. mb[4] = mcp->mb[4];
  4012. }
  4013. if (rval != QLA_SUCCESS) {
  4014. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  4015. } else {
  4016. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  4017. "Done %s.\n", __func__);
  4018. }
  4019. return rval;
  4020. }
  4021. int
  4022. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
  4023. {
  4024. int rval = QLA_FUNCTION_FAILED;
  4025. struct qla_hw_data *ha = vha->hw;
  4026. uint8_t byte;
  4027. if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
  4028. ql_dbg(ql_dbg_mbx, vha, 0x1150,
  4029. "Thermal not supported by this card.\n");
  4030. return rval;
  4031. }
  4032. if (IS_QLA25XX(ha)) {
  4033. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  4034. ha->pdev->subsystem_device == 0x0175) {
  4035. rval = qla2x00_read_sfp(vha, 0, &byte,
  4036. 0x98, 0x1, 1, BIT_13|BIT_0);
  4037. *temp = byte;
  4038. return rval;
  4039. }
  4040. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  4041. ha->pdev->subsystem_device == 0x338e) {
  4042. rval = qla2x00_read_sfp(vha, 0, &byte,
  4043. 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
  4044. *temp = byte;
  4045. return rval;
  4046. }
  4047. ql_dbg(ql_dbg_mbx, vha, 0x10c9,
  4048. "Thermal not supported by this card.\n");
  4049. return rval;
  4050. }
  4051. if (IS_QLA82XX(ha)) {
  4052. *temp = qla82xx_read_temperature(vha);
  4053. rval = QLA_SUCCESS;
  4054. return rval;
  4055. } else if (IS_QLA8044(ha)) {
  4056. *temp = qla8044_read_temperature(vha);
  4057. rval = QLA_SUCCESS;
  4058. return rval;
  4059. }
  4060. rval = qla2x00_read_asic_temperature(vha, temp);
  4061. return rval;
  4062. }
  4063. int
  4064. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  4065. {
  4066. int rval;
  4067. struct qla_hw_data *ha = vha->hw;
  4068. mbx_cmd_t mc;
  4069. mbx_cmd_t *mcp = &mc;
  4070. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  4071. "Entered %s.\n", __func__);
  4072. if (!IS_FWI2_CAPABLE(ha))
  4073. return QLA_FUNCTION_FAILED;
  4074. memset(mcp, 0, sizeof(mbx_cmd_t));
  4075. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4076. mcp->mb[1] = 1;
  4077. mcp->out_mb = MBX_1|MBX_0;
  4078. mcp->in_mb = MBX_0;
  4079. mcp->tov = 30;
  4080. mcp->flags = 0;
  4081. rval = qla2x00_mailbox_command(vha, mcp);
  4082. if (rval != QLA_SUCCESS) {
  4083. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  4084. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4085. } else {
  4086. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  4087. "Done %s.\n", __func__);
  4088. }
  4089. return rval;
  4090. }
  4091. int
  4092. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  4093. {
  4094. int rval;
  4095. struct qla_hw_data *ha = vha->hw;
  4096. mbx_cmd_t mc;
  4097. mbx_cmd_t *mcp = &mc;
  4098. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  4099. "Entered %s.\n", __func__);
  4100. if (!IS_P3P_TYPE(ha))
  4101. return QLA_FUNCTION_FAILED;
  4102. memset(mcp, 0, sizeof(mbx_cmd_t));
  4103. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4104. mcp->mb[1] = 0;
  4105. mcp->out_mb = MBX_1|MBX_0;
  4106. mcp->in_mb = MBX_0;
  4107. mcp->tov = 30;
  4108. mcp->flags = 0;
  4109. rval = qla2x00_mailbox_command(vha, mcp);
  4110. if (rval != QLA_SUCCESS) {
  4111. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  4112. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4113. } else {
  4114. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  4115. "Done %s.\n", __func__);
  4116. }
  4117. return rval;
  4118. }
  4119. int
  4120. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  4121. {
  4122. struct qla_hw_data *ha = vha->hw;
  4123. mbx_cmd_t mc;
  4124. mbx_cmd_t *mcp = &mc;
  4125. int rval = QLA_FUNCTION_FAILED;
  4126. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  4127. "Entered %s.\n", __func__);
  4128. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4129. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4130. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4131. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  4132. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  4133. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4134. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  4135. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4136. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4137. mcp->tov = MBX_TOV_SECONDS;
  4138. rval = qla2x00_mailbox_command(vha, mcp);
  4139. /* Always copy back return mailbox values. */
  4140. if (rval != QLA_SUCCESS) {
  4141. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  4142. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4143. (mcp->mb[1] << 16) | mcp->mb[0],
  4144. (mcp->mb[3] << 16) | mcp->mb[2]);
  4145. } else {
  4146. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  4147. "Done %s.\n", __func__);
  4148. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  4149. if (!ha->md_template_size) {
  4150. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  4151. "Null template size obtained.\n");
  4152. rval = QLA_FUNCTION_FAILED;
  4153. }
  4154. }
  4155. return rval;
  4156. }
  4157. int
  4158. qla82xx_md_get_template(scsi_qla_host_t *vha)
  4159. {
  4160. struct qla_hw_data *ha = vha->hw;
  4161. mbx_cmd_t mc;
  4162. mbx_cmd_t *mcp = &mc;
  4163. int rval = QLA_FUNCTION_FAILED;
  4164. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  4165. "Entered %s.\n", __func__);
  4166. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4167. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4168. if (!ha->md_tmplt_hdr) {
  4169. ql_log(ql_log_warn, vha, 0x1124,
  4170. "Unable to allocate memory for Minidump template.\n");
  4171. return rval;
  4172. }
  4173. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4174. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4175. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4176. mcp->mb[2] = LSW(RQST_TMPLT);
  4177. mcp->mb[3] = MSW(RQST_TMPLT);
  4178. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  4179. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  4180. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  4181. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  4182. mcp->mb[8] = LSW(ha->md_template_size);
  4183. mcp->mb[9] = MSW(ha->md_template_size);
  4184. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4185. mcp->tov = MBX_TOV_SECONDS;
  4186. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4187. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4188. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4189. rval = qla2x00_mailbox_command(vha, mcp);
  4190. if (rval != QLA_SUCCESS) {
  4191. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  4192. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4193. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4194. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4195. } else
  4196. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  4197. "Done %s.\n", __func__);
  4198. return rval;
  4199. }
  4200. int
  4201. qla8044_md_get_template(scsi_qla_host_t *vha)
  4202. {
  4203. struct qla_hw_data *ha = vha->hw;
  4204. mbx_cmd_t mc;
  4205. mbx_cmd_t *mcp = &mc;
  4206. int rval = QLA_FUNCTION_FAILED;
  4207. int offset = 0, size = MINIDUMP_SIZE_36K;
  4208. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
  4209. "Entered %s.\n", __func__);
  4210. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4211. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4212. if (!ha->md_tmplt_hdr) {
  4213. ql_log(ql_log_warn, vha, 0xb11b,
  4214. "Unable to allocate memory for Minidump template.\n");
  4215. return rval;
  4216. }
  4217. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4218. while (offset < ha->md_template_size) {
  4219. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4220. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4221. mcp->mb[2] = LSW(RQST_TMPLT);
  4222. mcp->mb[3] = MSW(RQST_TMPLT);
  4223. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
  4224. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
  4225. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
  4226. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
  4227. mcp->mb[8] = LSW(size);
  4228. mcp->mb[9] = MSW(size);
  4229. mcp->mb[10] = offset & 0x0000FFFF;
  4230. mcp->mb[11] = offset & 0xFFFF0000;
  4231. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4232. mcp->tov = MBX_TOV_SECONDS;
  4233. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4234. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4235. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4236. rval = qla2x00_mailbox_command(vha, mcp);
  4237. if (rval != QLA_SUCCESS) {
  4238. ql_dbg(ql_dbg_mbx, vha, 0xb11c,
  4239. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4240. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4241. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4242. return rval;
  4243. } else
  4244. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
  4245. "Done %s.\n", __func__);
  4246. offset = offset + size;
  4247. }
  4248. return rval;
  4249. }
  4250. int
  4251. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4252. {
  4253. int rval;
  4254. struct qla_hw_data *ha = vha->hw;
  4255. mbx_cmd_t mc;
  4256. mbx_cmd_t *mcp = &mc;
  4257. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4258. return QLA_FUNCTION_FAILED;
  4259. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  4260. "Entered %s.\n", __func__);
  4261. memset(mcp, 0, sizeof(mbx_cmd_t));
  4262. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4263. mcp->mb[1] = led_cfg[0];
  4264. mcp->mb[2] = led_cfg[1];
  4265. if (IS_QLA8031(ha)) {
  4266. mcp->mb[3] = led_cfg[2];
  4267. mcp->mb[4] = led_cfg[3];
  4268. mcp->mb[5] = led_cfg[4];
  4269. mcp->mb[6] = led_cfg[5];
  4270. }
  4271. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4272. if (IS_QLA8031(ha))
  4273. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4274. mcp->in_mb = MBX_0;
  4275. mcp->tov = 30;
  4276. mcp->flags = 0;
  4277. rval = qla2x00_mailbox_command(vha, mcp);
  4278. if (rval != QLA_SUCCESS) {
  4279. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  4280. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4281. } else {
  4282. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  4283. "Done %s.\n", __func__);
  4284. }
  4285. return rval;
  4286. }
  4287. int
  4288. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4289. {
  4290. int rval;
  4291. struct qla_hw_data *ha = vha->hw;
  4292. mbx_cmd_t mc;
  4293. mbx_cmd_t *mcp = &mc;
  4294. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4295. return QLA_FUNCTION_FAILED;
  4296. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  4297. "Entered %s.\n", __func__);
  4298. memset(mcp, 0, sizeof(mbx_cmd_t));
  4299. mcp->mb[0] = MBC_GET_LED_CONFIG;
  4300. mcp->out_mb = MBX_0;
  4301. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4302. if (IS_QLA8031(ha))
  4303. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4304. mcp->tov = 30;
  4305. mcp->flags = 0;
  4306. rval = qla2x00_mailbox_command(vha, mcp);
  4307. if (rval != QLA_SUCCESS) {
  4308. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  4309. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4310. } else {
  4311. led_cfg[0] = mcp->mb[1];
  4312. led_cfg[1] = mcp->mb[2];
  4313. if (IS_QLA8031(ha)) {
  4314. led_cfg[2] = mcp->mb[3];
  4315. led_cfg[3] = mcp->mb[4];
  4316. led_cfg[4] = mcp->mb[5];
  4317. led_cfg[5] = mcp->mb[6];
  4318. }
  4319. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4320. "Done %s.\n", __func__);
  4321. }
  4322. return rval;
  4323. }
  4324. int
  4325. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4326. {
  4327. int rval;
  4328. struct qla_hw_data *ha = vha->hw;
  4329. mbx_cmd_t mc;
  4330. mbx_cmd_t *mcp = &mc;
  4331. if (!IS_P3P_TYPE(ha))
  4332. return QLA_FUNCTION_FAILED;
  4333. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4334. "Entered %s.\n", __func__);
  4335. memset(mcp, 0, sizeof(mbx_cmd_t));
  4336. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4337. if (enable)
  4338. mcp->mb[7] = 0xE;
  4339. else
  4340. mcp->mb[7] = 0xD;
  4341. mcp->out_mb = MBX_7|MBX_0;
  4342. mcp->in_mb = MBX_0;
  4343. mcp->tov = MBX_TOV_SECONDS;
  4344. mcp->flags = 0;
  4345. rval = qla2x00_mailbox_command(vha, mcp);
  4346. if (rval != QLA_SUCCESS) {
  4347. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4348. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4349. } else {
  4350. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4351. "Done %s.\n", __func__);
  4352. }
  4353. return rval;
  4354. }
  4355. int
  4356. qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4357. {
  4358. int rval;
  4359. struct qla_hw_data *ha = vha->hw;
  4360. mbx_cmd_t mc;
  4361. mbx_cmd_t *mcp = &mc;
  4362. if (!IS_QLA83XX(ha))
  4363. return QLA_FUNCTION_FAILED;
  4364. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4365. "Entered %s.\n", __func__);
  4366. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4367. mcp->mb[1] = LSW(reg);
  4368. mcp->mb[2] = MSW(reg);
  4369. mcp->mb[3] = LSW(data);
  4370. mcp->mb[4] = MSW(data);
  4371. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4372. mcp->in_mb = MBX_1|MBX_0;
  4373. mcp->tov = MBX_TOV_SECONDS;
  4374. mcp->flags = 0;
  4375. rval = qla2x00_mailbox_command(vha, mcp);
  4376. if (rval != QLA_SUCCESS) {
  4377. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4378. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4379. } else {
  4380. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4381. "Done %s.\n", __func__);
  4382. }
  4383. return rval;
  4384. }
  4385. int
  4386. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4387. {
  4388. int rval;
  4389. struct qla_hw_data *ha = vha->hw;
  4390. mbx_cmd_t mc;
  4391. mbx_cmd_t *mcp = &mc;
  4392. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4393. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4394. "Implicit LOGO Unsupported.\n");
  4395. return QLA_FUNCTION_FAILED;
  4396. }
  4397. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4398. "Entering %s.\n", __func__);
  4399. /* Perform Implicit LOGO. */
  4400. mcp->mb[0] = MBC_PORT_LOGOUT;
  4401. mcp->mb[1] = fcport->loop_id;
  4402. mcp->mb[10] = BIT_15;
  4403. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4404. mcp->in_mb = MBX_0;
  4405. mcp->tov = MBX_TOV_SECONDS;
  4406. mcp->flags = 0;
  4407. rval = qla2x00_mailbox_command(vha, mcp);
  4408. if (rval != QLA_SUCCESS)
  4409. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4411. else
  4412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4413. "Done %s.\n", __func__);
  4414. return rval;
  4415. }
  4416. int
  4417. qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
  4418. {
  4419. int rval;
  4420. mbx_cmd_t mc;
  4421. mbx_cmd_t *mcp = &mc;
  4422. struct qla_hw_data *ha = vha->hw;
  4423. unsigned long retry_max_time = jiffies + (2 * HZ);
  4424. if (!IS_QLA83XX(ha))
  4425. return QLA_FUNCTION_FAILED;
  4426. ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
  4427. retry_rd_reg:
  4428. mcp->mb[0] = MBC_READ_REMOTE_REG;
  4429. mcp->mb[1] = LSW(reg);
  4430. mcp->mb[2] = MSW(reg);
  4431. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4432. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4433. mcp->tov = MBX_TOV_SECONDS;
  4434. mcp->flags = 0;
  4435. rval = qla2x00_mailbox_command(vha, mcp);
  4436. if (rval != QLA_SUCCESS) {
  4437. ql_dbg(ql_dbg_mbx, vha, 0x114c,
  4438. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4439. rval, mcp->mb[0], mcp->mb[1]);
  4440. } else {
  4441. *data = (mcp->mb[3] | (mcp->mb[4] << 16));
  4442. if (*data == QLA8XXX_BAD_VALUE) {
  4443. /*
  4444. * During soft-reset CAMRAM register reads might
  4445. * return 0xbad0bad0. So retry for MAX of 2 sec
  4446. * while reading camram registers.
  4447. */
  4448. if (time_after(jiffies, retry_max_time)) {
  4449. ql_dbg(ql_dbg_mbx, vha, 0x1141,
  4450. "Failure to read CAMRAM register. "
  4451. "data=0x%x.\n", *data);
  4452. return QLA_FUNCTION_FAILED;
  4453. }
  4454. msleep(100);
  4455. goto retry_rd_reg;
  4456. }
  4457. ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
  4458. }
  4459. return rval;
  4460. }
  4461. int
  4462. qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
  4463. {
  4464. int rval;
  4465. mbx_cmd_t mc;
  4466. mbx_cmd_t *mcp = &mc;
  4467. struct qla_hw_data *ha = vha->hw;
  4468. if (!IS_QLA83XX(ha))
  4469. return QLA_FUNCTION_FAILED;
  4470. ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
  4471. mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
  4472. mcp->out_mb = MBX_0;
  4473. mcp->in_mb = MBX_1|MBX_0;
  4474. mcp->tov = MBX_TOV_SECONDS;
  4475. mcp->flags = 0;
  4476. rval = qla2x00_mailbox_command(vha, mcp);
  4477. if (rval != QLA_SUCCESS) {
  4478. ql_dbg(ql_dbg_mbx, vha, 0x1144,
  4479. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4480. rval, mcp->mb[0], mcp->mb[1]);
  4481. ha->isp_ops->fw_dump(vha, 0);
  4482. } else {
  4483. ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
  4484. }
  4485. return rval;
  4486. }
  4487. int
  4488. qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
  4489. uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
  4490. {
  4491. int rval;
  4492. mbx_cmd_t mc;
  4493. mbx_cmd_t *mcp = &mc;
  4494. uint8_t subcode = (uint8_t)options;
  4495. struct qla_hw_data *ha = vha->hw;
  4496. if (!IS_QLA8031(ha))
  4497. return QLA_FUNCTION_FAILED;
  4498. ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
  4499. mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
  4500. mcp->mb[1] = options;
  4501. mcp->out_mb = MBX_1|MBX_0;
  4502. if (subcode & BIT_2) {
  4503. mcp->mb[2] = LSW(start_addr);
  4504. mcp->mb[3] = MSW(start_addr);
  4505. mcp->mb[4] = LSW(end_addr);
  4506. mcp->mb[5] = MSW(end_addr);
  4507. mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
  4508. }
  4509. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4510. if (!(subcode & (BIT_2 | BIT_5)))
  4511. mcp->in_mb |= MBX_4|MBX_3;
  4512. mcp->tov = MBX_TOV_SECONDS;
  4513. mcp->flags = 0;
  4514. rval = qla2x00_mailbox_command(vha, mcp);
  4515. if (rval != QLA_SUCCESS) {
  4516. ql_dbg(ql_dbg_mbx, vha, 0x1147,
  4517. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
  4518. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
  4519. mcp->mb[4]);
  4520. ha->isp_ops->fw_dump(vha, 0);
  4521. } else {
  4522. if (subcode & BIT_5)
  4523. *sector_size = mcp->mb[1];
  4524. else if (subcode & (BIT_6 | BIT_7)) {
  4525. ql_dbg(ql_dbg_mbx, vha, 0x1148,
  4526. "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4527. } else if (subcode & (BIT_3 | BIT_4)) {
  4528. ql_dbg(ql_dbg_mbx, vha, 0x1149,
  4529. "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4530. }
  4531. ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
  4532. }
  4533. return rval;
  4534. }
  4535. int
  4536. qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  4537. uint32_t size)
  4538. {
  4539. int rval;
  4540. mbx_cmd_t mc;
  4541. mbx_cmd_t *mcp = &mc;
  4542. if (!IS_MCTP_CAPABLE(vha->hw))
  4543. return QLA_FUNCTION_FAILED;
  4544. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
  4545. "Entered %s.\n", __func__);
  4546. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  4547. mcp->mb[1] = LSW(addr);
  4548. mcp->mb[2] = MSW(req_dma);
  4549. mcp->mb[3] = LSW(req_dma);
  4550. mcp->mb[4] = MSW(size);
  4551. mcp->mb[5] = LSW(size);
  4552. mcp->mb[6] = MSW(MSD(req_dma));
  4553. mcp->mb[7] = LSW(MSD(req_dma));
  4554. mcp->mb[8] = MSW(addr);
  4555. /* Setting RAM ID to valid */
  4556. mcp->mb[10] |= BIT_7;
  4557. /* For MCTP RAM ID is 0x40 */
  4558. mcp->mb[10] |= 0x40;
  4559. mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
  4560. MBX_0;
  4561. mcp->in_mb = MBX_0;
  4562. mcp->tov = MBX_TOV_SECONDS;
  4563. mcp->flags = 0;
  4564. rval = qla2x00_mailbox_command(vha, mcp);
  4565. if (rval != QLA_SUCCESS) {
  4566. ql_dbg(ql_dbg_mbx, vha, 0x114e,
  4567. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4568. } else {
  4569. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
  4570. "Done %s.\n", __func__);
  4571. }
  4572. return rval;
  4573. }