resource_tracker.c 103 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct vlan_res {
  54. struct list_head list;
  55. u16 vlan;
  56. int ref_count;
  57. int vlan_index;
  58. u8 port;
  59. };
  60. struct res_common {
  61. struct list_head list;
  62. struct rb_node node;
  63. u64 res_id;
  64. int owner;
  65. int state;
  66. int from_state;
  67. int to_state;
  68. int removing;
  69. };
  70. enum {
  71. RES_ANY_BUSY = 1
  72. };
  73. struct res_gid {
  74. struct list_head list;
  75. u8 gid[16];
  76. enum mlx4_protocol prot;
  77. enum mlx4_steer_type steer;
  78. u64 reg_id;
  79. };
  80. enum res_qp_states {
  81. RES_QP_BUSY = RES_ANY_BUSY,
  82. /* QP number was allocated */
  83. RES_QP_RESERVED,
  84. /* ICM memory for QP context was mapped */
  85. RES_QP_MAPPED,
  86. /* QP is in hw ownership */
  87. RES_QP_HW
  88. };
  89. struct res_qp {
  90. struct res_common com;
  91. struct res_mtt *mtt;
  92. struct res_cq *rcq;
  93. struct res_cq *scq;
  94. struct res_srq *srq;
  95. struct list_head mcg_list;
  96. spinlock_t mcg_spl;
  97. int local_qpn;
  98. atomic_t ref_count;
  99. u32 qpc_flags;
  100. u8 sched_queue;
  101. };
  102. enum res_mtt_states {
  103. RES_MTT_BUSY = RES_ANY_BUSY,
  104. RES_MTT_ALLOCATED,
  105. };
  106. static inline const char *mtt_states_str(enum res_mtt_states state)
  107. {
  108. switch (state) {
  109. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  110. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  111. default: return "Unknown";
  112. }
  113. }
  114. struct res_mtt {
  115. struct res_common com;
  116. int order;
  117. atomic_t ref_count;
  118. };
  119. enum res_mpt_states {
  120. RES_MPT_BUSY = RES_ANY_BUSY,
  121. RES_MPT_RESERVED,
  122. RES_MPT_MAPPED,
  123. RES_MPT_HW,
  124. };
  125. struct res_mpt {
  126. struct res_common com;
  127. struct res_mtt *mtt;
  128. int key;
  129. };
  130. enum res_eq_states {
  131. RES_EQ_BUSY = RES_ANY_BUSY,
  132. RES_EQ_RESERVED,
  133. RES_EQ_HW,
  134. };
  135. struct res_eq {
  136. struct res_common com;
  137. struct res_mtt *mtt;
  138. };
  139. enum res_cq_states {
  140. RES_CQ_BUSY = RES_ANY_BUSY,
  141. RES_CQ_ALLOCATED,
  142. RES_CQ_HW,
  143. };
  144. struct res_cq {
  145. struct res_common com;
  146. struct res_mtt *mtt;
  147. atomic_t ref_count;
  148. };
  149. enum res_srq_states {
  150. RES_SRQ_BUSY = RES_ANY_BUSY,
  151. RES_SRQ_ALLOCATED,
  152. RES_SRQ_HW,
  153. };
  154. struct res_srq {
  155. struct res_common com;
  156. struct res_mtt *mtt;
  157. struct res_cq *cq;
  158. atomic_t ref_count;
  159. };
  160. enum res_counter_states {
  161. RES_COUNTER_BUSY = RES_ANY_BUSY,
  162. RES_COUNTER_ALLOCATED,
  163. };
  164. struct res_counter {
  165. struct res_common com;
  166. int port;
  167. };
  168. enum res_xrcdn_states {
  169. RES_XRCD_BUSY = RES_ANY_BUSY,
  170. RES_XRCD_ALLOCATED,
  171. };
  172. struct res_xrcdn {
  173. struct res_common com;
  174. int port;
  175. };
  176. enum res_fs_rule_states {
  177. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  178. RES_FS_RULE_ALLOCATED,
  179. };
  180. struct res_fs_rule {
  181. struct res_common com;
  182. int qpn;
  183. };
  184. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  185. {
  186. struct rb_node *node = root->rb_node;
  187. while (node) {
  188. struct res_common *res = container_of(node, struct res_common,
  189. node);
  190. if (res_id < res->res_id)
  191. node = node->rb_left;
  192. else if (res_id > res->res_id)
  193. node = node->rb_right;
  194. else
  195. return res;
  196. }
  197. return NULL;
  198. }
  199. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  200. {
  201. struct rb_node **new = &(root->rb_node), *parent = NULL;
  202. /* Figure out where to put new node */
  203. while (*new) {
  204. struct res_common *this = container_of(*new, struct res_common,
  205. node);
  206. parent = *new;
  207. if (res->res_id < this->res_id)
  208. new = &((*new)->rb_left);
  209. else if (res->res_id > this->res_id)
  210. new = &((*new)->rb_right);
  211. else
  212. return -EEXIST;
  213. }
  214. /* Add new node and rebalance tree. */
  215. rb_link_node(&res->node, parent, new);
  216. rb_insert_color(&res->node, root);
  217. return 0;
  218. }
  219. enum qp_transition {
  220. QP_TRANS_INIT2RTR,
  221. QP_TRANS_RTR2RTS,
  222. QP_TRANS_RTS2RTS,
  223. QP_TRANS_SQERR2RTS,
  224. QP_TRANS_SQD2SQD,
  225. QP_TRANS_SQD2RTS
  226. };
  227. /* For Debug uses */
  228. static const char *ResourceType(enum mlx4_resource rt)
  229. {
  230. switch (rt) {
  231. case RES_QP: return "RES_QP";
  232. case RES_CQ: return "RES_CQ";
  233. case RES_SRQ: return "RES_SRQ";
  234. case RES_MPT: return "RES_MPT";
  235. case RES_MTT: return "RES_MTT";
  236. case RES_MAC: return "RES_MAC";
  237. case RES_VLAN: return "RES_VLAN";
  238. case RES_EQ: return "RES_EQ";
  239. case RES_COUNTER: return "RES_COUNTER";
  240. case RES_FS_RULE: return "RES_FS_RULE";
  241. case RES_XRCD: return "RES_XRCD";
  242. default: return "Unknown resource type !!!";
  243. };
  244. }
  245. static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
  246. static inline void initialize_res_quotas(struct mlx4_dev *dev,
  247. struct resource_allocator *res_alloc,
  248. enum mlx4_resource res_type,
  249. int vf, int num_instances)
  250. {
  251. res_alloc->guaranteed[vf] = num_instances / (2 * (dev->num_vfs + 1));
  252. res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
  253. if (vf == mlx4_master_func_num(dev)) {
  254. res_alloc->res_free = num_instances;
  255. if (res_type == RES_MTT) {
  256. /* reserved mtts will be taken out of the PF allocation */
  257. res_alloc->res_free += dev->caps.reserved_mtts;
  258. res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
  259. res_alloc->quota[vf] += dev->caps.reserved_mtts;
  260. }
  261. }
  262. }
  263. void mlx4_init_quotas(struct mlx4_dev *dev)
  264. {
  265. struct mlx4_priv *priv = mlx4_priv(dev);
  266. int pf;
  267. /* quotas for VFs are initialized in mlx4_slave_cap */
  268. if (mlx4_is_slave(dev))
  269. return;
  270. if (!mlx4_is_mfunc(dev)) {
  271. dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
  272. mlx4_num_reserved_sqps(dev);
  273. dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
  274. dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
  275. dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
  276. dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
  277. return;
  278. }
  279. pf = mlx4_master_func_num(dev);
  280. dev->quotas.qp =
  281. priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
  282. dev->quotas.cq =
  283. priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
  284. dev->quotas.srq =
  285. priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
  286. dev->quotas.mtt =
  287. priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
  288. dev->quotas.mpt =
  289. priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
  290. }
  291. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  292. {
  293. struct mlx4_priv *priv = mlx4_priv(dev);
  294. int i, j;
  295. int t;
  296. priv->mfunc.master.res_tracker.slave_list =
  297. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  298. GFP_KERNEL);
  299. if (!priv->mfunc.master.res_tracker.slave_list)
  300. return -ENOMEM;
  301. for (i = 0 ; i < dev->num_slaves; i++) {
  302. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  303. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  304. slave_list[i].res_list[t]);
  305. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  306. }
  307. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  308. dev->num_slaves);
  309. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  310. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  311. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  312. struct resource_allocator *res_alloc =
  313. &priv->mfunc.master.res_tracker.res_alloc[i];
  314. res_alloc->quota = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  315. res_alloc->guaranteed = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  316. if (i == RES_MAC || i == RES_VLAN)
  317. res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
  318. (dev->num_vfs + 1) * sizeof(int),
  319. GFP_KERNEL);
  320. else
  321. res_alloc->allocated = kzalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  322. if (!res_alloc->quota || !res_alloc->guaranteed ||
  323. !res_alloc->allocated)
  324. goto no_mem_err;
  325. for (t = 0; t < dev->num_vfs + 1; t++) {
  326. switch (i) {
  327. case RES_QP:
  328. initialize_res_quotas(dev, res_alloc, RES_QP,
  329. t, dev->caps.num_qps -
  330. dev->caps.reserved_qps -
  331. mlx4_num_reserved_sqps(dev));
  332. break;
  333. case RES_CQ:
  334. initialize_res_quotas(dev, res_alloc, RES_CQ,
  335. t, dev->caps.num_cqs -
  336. dev->caps.reserved_cqs);
  337. break;
  338. case RES_SRQ:
  339. initialize_res_quotas(dev, res_alloc, RES_SRQ,
  340. t, dev->caps.num_srqs -
  341. dev->caps.reserved_srqs);
  342. break;
  343. case RES_MPT:
  344. initialize_res_quotas(dev, res_alloc, RES_MPT,
  345. t, dev->caps.num_mpts -
  346. dev->caps.reserved_mrws);
  347. break;
  348. case RES_MTT:
  349. initialize_res_quotas(dev, res_alloc, RES_MTT,
  350. t, dev->caps.num_mtts -
  351. dev->caps.reserved_mtts);
  352. break;
  353. case RES_MAC:
  354. if (t == mlx4_master_func_num(dev)) {
  355. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  356. res_alloc->guaranteed[t] = 2;
  357. for (j = 0; j < MLX4_MAX_PORTS; j++)
  358. res_alloc->res_port_free[j] = MLX4_MAX_MAC_NUM;
  359. } else {
  360. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  361. res_alloc->guaranteed[t] = 2;
  362. }
  363. break;
  364. case RES_VLAN:
  365. if (t == mlx4_master_func_num(dev)) {
  366. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
  367. res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
  368. for (j = 0; j < MLX4_MAX_PORTS; j++)
  369. res_alloc->res_port_free[j] =
  370. res_alloc->quota[t];
  371. } else {
  372. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
  373. res_alloc->guaranteed[t] = 0;
  374. }
  375. break;
  376. case RES_COUNTER:
  377. res_alloc->quota[t] = dev->caps.max_counters;
  378. res_alloc->guaranteed[t] = 0;
  379. if (t == mlx4_master_func_num(dev))
  380. res_alloc->res_free = res_alloc->quota[t];
  381. break;
  382. default:
  383. break;
  384. }
  385. if (i == RES_MAC || i == RES_VLAN) {
  386. for (j = 0; j < MLX4_MAX_PORTS; j++)
  387. res_alloc->res_port_rsvd[j] +=
  388. res_alloc->guaranteed[t];
  389. } else {
  390. res_alloc->res_reserved += res_alloc->guaranteed[t];
  391. }
  392. }
  393. }
  394. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  395. return 0;
  396. no_mem_err:
  397. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  398. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  399. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  400. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  401. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  402. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  403. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  404. }
  405. return -ENOMEM;
  406. }
  407. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  408. enum mlx4_res_tracker_free_type type)
  409. {
  410. struct mlx4_priv *priv = mlx4_priv(dev);
  411. int i;
  412. if (priv->mfunc.master.res_tracker.slave_list) {
  413. if (type != RES_TR_FREE_STRUCTS_ONLY) {
  414. for (i = 0; i < dev->num_slaves; i++) {
  415. if (type == RES_TR_FREE_ALL ||
  416. dev->caps.function != i)
  417. mlx4_delete_all_resources_for_slave(dev, i);
  418. }
  419. /* free master's vlans */
  420. i = dev->caps.function;
  421. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  422. rem_slave_vlans(dev, i);
  423. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  424. }
  425. if (type != RES_TR_FREE_SLAVES_ONLY) {
  426. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  427. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  428. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  429. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  430. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  431. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  432. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  433. }
  434. kfree(priv->mfunc.master.res_tracker.slave_list);
  435. priv->mfunc.master.res_tracker.slave_list = NULL;
  436. }
  437. }
  438. }
  439. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  440. struct mlx4_cmd_mailbox *inbox)
  441. {
  442. u8 sched = *(u8 *)(inbox->buf + 64);
  443. u8 orig_index = *(u8 *)(inbox->buf + 35);
  444. u8 new_index;
  445. struct mlx4_priv *priv = mlx4_priv(dev);
  446. int port;
  447. port = (sched >> 6 & 1) + 1;
  448. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  449. *(u8 *)(inbox->buf + 35) = new_index;
  450. }
  451. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  452. u8 slave)
  453. {
  454. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  455. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  456. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  457. if (MLX4_QP_ST_UD == ts)
  458. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  459. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  460. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  461. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  462. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  463. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  464. }
  465. }
  466. static int update_vport_qp_param(struct mlx4_dev *dev,
  467. struct mlx4_cmd_mailbox *inbox,
  468. u8 slave, u32 qpn)
  469. {
  470. struct mlx4_qp_context *qpc = inbox->buf + 8;
  471. struct mlx4_vport_oper_state *vp_oper;
  472. struct mlx4_priv *priv;
  473. u32 qp_type;
  474. int port;
  475. port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
  476. priv = mlx4_priv(dev);
  477. vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
  478. if (MLX4_VGT != vp_oper->state.default_vlan) {
  479. qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  480. if (MLX4_QP_ST_RC == qp_type ||
  481. (MLX4_QP_ST_UD == qp_type &&
  482. !mlx4_is_qp_reserved(dev, qpn)))
  483. return -EINVAL;
  484. /* the reserved QPs (special, proxy, tunnel)
  485. * do not operate over vlans
  486. */
  487. if (mlx4_is_qp_reserved(dev, qpn))
  488. return 0;
  489. /* force strip vlan by clear vsd */
  490. qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
  491. if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
  492. dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
  493. qpc->pri_path.vlan_control =
  494. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  495. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  496. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  497. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  498. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  499. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  500. } else if (0 != vp_oper->state.default_vlan) {
  501. qpc->pri_path.vlan_control =
  502. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  503. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  504. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  505. } else { /* priority tagged */
  506. qpc->pri_path.vlan_control =
  507. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  508. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  509. }
  510. qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
  511. qpc->pri_path.vlan_index = vp_oper->vlan_idx;
  512. qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
  513. qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  514. qpc->pri_path.sched_queue &= 0xC7;
  515. qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
  516. }
  517. if (vp_oper->state.spoofchk) {
  518. qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
  519. qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
  520. }
  521. return 0;
  522. }
  523. static int mpt_mask(struct mlx4_dev *dev)
  524. {
  525. return dev->caps.num_mpts - 1;
  526. }
  527. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  528. enum mlx4_resource type)
  529. {
  530. struct mlx4_priv *priv = mlx4_priv(dev);
  531. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  532. res_id);
  533. }
  534. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  535. enum mlx4_resource type,
  536. void *res)
  537. {
  538. struct res_common *r;
  539. int err = 0;
  540. spin_lock_irq(mlx4_tlock(dev));
  541. r = find_res(dev, res_id, type);
  542. if (!r) {
  543. err = -ENONET;
  544. goto exit;
  545. }
  546. if (r->state == RES_ANY_BUSY) {
  547. err = -EBUSY;
  548. goto exit;
  549. }
  550. if (r->owner != slave) {
  551. err = -EPERM;
  552. goto exit;
  553. }
  554. r->from_state = r->state;
  555. r->state = RES_ANY_BUSY;
  556. if (res)
  557. *((struct res_common **)res) = r;
  558. exit:
  559. spin_unlock_irq(mlx4_tlock(dev));
  560. return err;
  561. }
  562. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  563. enum mlx4_resource type,
  564. u64 res_id, int *slave)
  565. {
  566. struct res_common *r;
  567. int err = -ENOENT;
  568. int id = res_id;
  569. if (type == RES_QP)
  570. id &= 0x7fffff;
  571. spin_lock(mlx4_tlock(dev));
  572. r = find_res(dev, id, type);
  573. if (r) {
  574. *slave = r->owner;
  575. err = 0;
  576. }
  577. spin_unlock(mlx4_tlock(dev));
  578. return err;
  579. }
  580. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  581. enum mlx4_resource type)
  582. {
  583. struct res_common *r;
  584. spin_lock_irq(mlx4_tlock(dev));
  585. r = find_res(dev, res_id, type);
  586. if (r)
  587. r->state = r->from_state;
  588. spin_unlock_irq(mlx4_tlock(dev));
  589. }
  590. static struct res_common *alloc_qp_tr(int id)
  591. {
  592. struct res_qp *ret;
  593. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  594. if (!ret)
  595. return NULL;
  596. ret->com.res_id = id;
  597. ret->com.state = RES_QP_RESERVED;
  598. ret->local_qpn = id;
  599. INIT_LIST_HEAD(&ret->mcg_list);
  600. spin_lock_init(&ret->mcg_spl);
  601. atomic_set(&ret->ref_count, 0);
  602. return &ret->com;
  603. }
  604. static struct res_common *alloc_mtt_tr(int id, int order)
  605. {
  606. struct res_mtt *ret;
  607. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  608. if (!ret)
  609. return NULL;
  610. ret->com.res_id = id;
  611. ret->order = order;
  612. ret->com.state = RES_MTT_ALLOCATED;
  613. atomic_set(&ret->ref_count, 0);
  614. return &ret->com;
  615. }
  616. static struct res_common *alloc_mpt_tr(int id, int key)
  617. {
  618. struct res_mpt *ret;
  619. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  620. if (!ret)
  621. return NULL;
  622. ret->com.res_id = id;
  623. ret->com.state = RES_MPT_RESERVED;
  624. ret->key = key;
  625. return &ret->com;
  626. }
  627. static struct res_common *alloc_eq_tr(int id)
  628. {
  629. struct res_eq *ret;
  630. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  631. if (!ret)
  632. return NULL;
  633. ret->com.res_id = id;
  634. ret->com.state = RES_EQ_RESERVED;
  635. return &ret->com;
  636. }
  637. static struct res_common *alloc_cq_tr(int id)
  638. {
  639. struct res_cq *ret;
  640. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  641. if (!ret)
  642. return NULL;
  643. ret->com.res_id = id;
  644. ret->com.state = RES_CQ_ALLOCATED;
  645. atomic_set(&ret->ref_count, 0);
  646. return &ret->com;
  647. }
  648. static struct res_common *alloc_srq_tr(int id)
  649. {
  650. struct res_srq *ret;
  651. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  652. if (!ret)
  653. return NULL;
  654. ret->com.res_id = id;
  655. ret->com.state = RES_SRQ_ALLOCATED;
  656. atomic_set(&ret->ref_count, 0);
  657. return &ret->com;
  658. }
  659. static struct res_common *alloc_counter_tr(int id)
  660. {
  661. struct res_counter *ret;
  662. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  663. if (!ret)
  664. return NULL;
  665. ret->com.res_id = id;
  666. ret->com.state = RES_COUNTER_ALLOCATED;
  667. return &ret->com;
  668. }
  669. static struct res_common *alloc_xrcdn_tr(int id)
  670. {
  671. struct res_xrcdn *ret;
  672. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  673. if (!ret)
  674. return NULL;
  675. ret->com.res_id = id;
  676. ret->com.state = RES_XRCD_ALLOCATED;
  677. return &ret->com;
  678. }
  679. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  680. {
  681. struct res_fs_rule *ret;
  682. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  683. if (!ret)
  684. return NULL;
  685. ret->com.res_id = id;
  686. ret->com.state = RES_FS_RULE_ALLOCATED;
  687. ret->qpn = qpn;
  688. return &ret->com;
  689. }
  690. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  691. int extra)
  692. {
  693. struct res_common *ret;
  694. switch (type) {
  695. case RES_QP:
  696. ret = alloc_qp_tr(id);
  697. break;
  698. case RES_MPT:
  699. ret = alloc_mpt_tr(id, extra);
  700. break;
  701. case RES_MTT:
  702. ret = alloc_mtt_tr(id, extra);
  703. break;
  704. case RES_EQ:
  705. ret = alloc_eq_tr(id);
  706. break;
  707. case RES_CQ:
  708. ret = alloc_cq_tr(id);
  709. break;
  710. case RES_SRQ:
  711. ret = alloc_srq_tr(id);
  712. break;
  713. case RES_MAC:
  714. printk(KERN_ERR "implementation missing\n");
  715. return NULL;
  716. case RES_COUNTER:
  717. ret = alloc_counter_tr(id);
  718. break;
  719. case RES_XRCD:
  720. ret = alloc_xrcdn_tr(id);
  721. break;
  722. case RES_FS_RULE:
  723. ret = alloc_fs_rule_tr(id, extra);
  724. break;
  725. default:
  726. return NULL;
  727. }
  728. if (ret)
  729. ret->owner = slave;
  730. return ret;
  731. }
  732. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  733. enum mlx4_resource type, int extra)
  734. {
  735. int i;
  736. int err;
  737. struct mlx4_priv *priv = mlx4_priv(dev);
  738. struct res_common **res_arr;
  739. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  740. struct rb_root *root = &tracker->res_tree[type];
  741. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  742. if (!res_arr)
  743. return -ENOMEM;
  744. for (i = 0; i < count; ++i) {
  745. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  746. if (!res_arr[i]) {
  747. for (--i; i >= 0; --i)
  748. kfree(res_arr[i]);
  749. kfree(res_arr);
  750. return -ENOMEM;
  751. }
  752. }
  753. spin_lock_irq(mlx4_tlock(dev));
  754. for (i = 0; i < count; ++i) {
  755. if (find_res(dev, base + i, type)) {
  756. err = -EEXIST;
  757. goto undo;
  758. }
  759. err = res_tracker_insert(root, res_arr[i]);
  760. if (err)
  761. goto undo;
  762. list_add_tail(&res_arr[i]->list,
  763. &tracker->slave_list[slave].res_list[type]);
  764. }
  765. spin_unlock_irq(mlx4_tlock(dev));
  766. kfree(res_arr);
  767. return 0;
  768. undo:
  769. for (--i; i >= base; --i)
  770. rb_erase(&res_arr[i]->node, root);
  771. spin_unlock_irq(mlx4_tlock(dev));
  772. for (i = 0; i < count; ++i)
  773. kfree(res_arr[i]);
  774. kfree(res_arr);
  775. return err;
  776. }
  777. static int remove_qp_ok(struct res_qp *res)
  778. {
  779. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  780. !list_empty(&res->mcg_list)) {
  781. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  782. res->com.state, atomic_read(&res->ref_count));
  783. return -EBUSY;
  784. } else if (res->com.state != RES_QP_RESERVED) {
  785. return -EPERM;
  786. }
  787. return 0;
  788. }
  789. static int remove_mtt_ok(struct res_mtt *res, int order)
  790. {
  791. if (res->com.state == RES_MTT_BUSY ||
  792. atomic_read(&res->ref_count)) {
  793. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  794. __func__, __LINE__,
  795. mtt_states_str(res->com.state),
  796. atomic_read(&res->ref_count));
  797. return -EBUSY;
  798. } else if (res->com.state != RES_MTT_ALLOCATED)
  799. return -EPERM;
  800. else if (res->order != order)
  801. return -EINVAL;
  802. return 0;
  803. }
  804. static int remove_mpt_ok(struct res_mpt *res)
  805. {
  806. if (res->com.state == RES_MPT_BUSY)
  807. return -EBUSY;
  808. else if (res->com.state != RES_MPT_RESERVED)
  809. return -EPERM;
  810. return 0;
  811. }
  812. static int remove_eq_ok(struct res_eq *res)
  813. {
  814. if (res->com.state == RES_MPT_BUSY)
  815. return -EBUSY;
  816. else if (res->com.state != RES_MPT_RESERVED)
  817. return -EPERM;
  818. return 0;
  819. }
  820. static int remove_counter_ok(struct res_counter *res)
  821. {
  822. if (res->com.state == RES_COUNTER_BUSY)
  823. return -EBUSY;
  824. else if (res->com.state != RES_COUNTER_ALLOCATED)
  825. return -EPERM;
  826. return 0;
  827. }
  828. static int remove_xrcdn_ok(struct res_xrcdn *res)
  829. {
  830. if (res->com.state == RES_XRCD_BUSY)
  831. return -EBUSY;
  832. else if (res->com.state != RES_XRCD_ALLOCATED)
  833. return -EPERM;
  834. return 0;
  835. }
  836. static int remove_fs_rule_ok(struct res_fs_rule *res)
  837. {
  838. if (res->com.state == RES_FS_RULE_BUSY)
  839. return -EBUSY;
  840. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  841. return -EPERM;
  842. return 0;
  843. }
  844. static int remove_cq_ok(struct res_cq *res)
  845. {
  846. if (res->com.state == RES_CQ_BUSY)
  847. return -EBUSY;
  848. else if (res->com.state != RES_CQ_ALLOCATED)
  849. return -EPERM;
  850. return 0;
  851. }
  852. static int remove_srq_ok(struct res_srq *res)
  853. {
  854. if (res->com.state == RES_SRQ_BUSY)
  855. return -EBUSY;
  856. else if (res->com.state != RES_SRQ_ALLOCATED)
  857. return -EPERM;
  858. return 0;
  859. }
  860. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  861. {
  862. switch (type) {
  863. case RES_QP:
  864. return remove_qp_ok((struct res_qp *)res);
  865. case RES_CQ:
  866. return remove_cq_ok((struct res_cq *)res);
  867. case RES_SRQ:
  868. return remove_srq_ok((struct res_srq *)res);
  869. case RES_MPT:
  870. return remove_mpt_ok((struct res_mpt *)res);
  871. case RES_MTT:
  872. return remove_mtt_ok((struct res_mtt *)res, extra);
  873. case RES_MAC:
  874. return -ENOSYS;
  875. case RES_EQ:
  876. return remove_eq_ok((struct res_eq *)res);
  877. case RES_COUNTER:
  878. return remove_counter_ok((struct res_counter *)res);
  879. case RES_XRCD:
  880. return remove_xrcdn_ok((struct res_xrcdn *)res);
  881. case RES_FS_RULE:
  882. return remove_fs_rule_ok((struct res_fs_rule *)res);
  883. default:
  884. return -EINVAL;
  885. }
  886. }
  887. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  888. enum mlx4_resource type, int extra)
  889. {
  890. u64 i;
  891. int err;
  892. struct mlx4_priv *priv = mlx4_priv(dev);
  893. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  894. struct res_common *r;
  895. spin_lock_irq(mlx4_tlock(dev));
  896. for (i = base; i < base + count; ++i) {
  897. r = res_tracker_lookup(&tracker->res_tree[type], i);
  898. if (!r) {
  899. err = -ENOENT;
  900. goto out;
  901. }
  902. if (r->owner != slave) {
  903. err = -EPERM;
  904. goto out;
  905. }
  906. err = remove_ok(r, type, extra);
  907. if (err)
  908. goto out;
  909. }
  910. for (i = base; i < base + count; ++i) {
  911. r = res_tracker_lookup(&tracker->res_tree[type], i);
  912. rb_erase(&r->node, &tracker->res_tree[type]);
  913. list_del(&r->list);
  914. kfree(r);
  915. }
  916. err = 0;
  917. out:
  918. spin_unlock_irq(mlx4_tlock(dev));
  919. return err;
  920. }
  921. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  922. enum res_qp_states state, struct res_qp **qp,
  923. int alloc)
  924. {
  925. struct mlx4_priv *priv = mlx4_priv(dev);
  926. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  927. struct res_qp *r;
  928. int err = 0;
  929. spin_lock_irq(mlx4_tlock(dev));
  930. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  931. if (!r)
  932. err = -ENOENT;
  933. else if (r->com.owner != slave)
  934. err = -EPERM;
  935. else {
  936. switch (state) {
  937. case RES_QP_BUSY:
  938. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  939. __func__, r->com.res_id);
  940. err = -EBUSY;
  941. break;
  942. case RES_QP_RESERVED:
  943. if (r->com.state == RES_QP_MAPPED && !alloc)
  944. break;
  945. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  946. err = -EINVAL;
  947. break;
  948. case RES_QP_MAPPED:
  949. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  950. r->com.state == RES_QP_HW)
  951. break;
  952. else {
  953. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  954. r->com.res_id);
  955. err = -EINVAL;
  956. }
  957. break;
  958. case RES_QP_HW:
  959. if (r->com.state != RES_QP_MAPPED)
  960. err = -EINVAL;
  961. break;
  962. default:
  963. err = -EINVAL;
  964. }
  965. if (!err) {
  966. r->com.from_state = r->com.state;
  967. r->com.to_state = state;
  968. r->com.state = RES_QP_BUSY;
  969. if (qp)
  970. *qp = r;
  971. }
  972. }
  973. spin_unlock_irq(mlx4_tlock(dev));
  974. return err;
  975. }
  976. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  977. enum res_mpt_states state, struct res_mpt **mpt)
  978. {
  979. struct mlx4_priv *priv = mlx4_priv(dev);
  980. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  981. struct res_mpt *r;
  982. int err = 0;
  983. spin_lock_irq(mlx4_tlock(dev));
  984. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  985. if (!r)
  986. err = -ENOENT;
  987. else if (r->com.owner != slave)
  988. err = -EPERM;
  989. else {
  990. switch (state) {
  991. case RES_MPT_BUSY:
  992. err = -EINVAL;
  993. break;
  994. case RES_MPT_RESERVED:
  995. if (r->com.state != RES_MPT_MAPPED)
  996. err = -EINVAL;
  997. break;
  998. case RES_MPT_MAPPED:
  999. if (r->com.state != RES_MPT_RESERVED &&
  1000. r->com.state != RES_MPT_HW)
  1001. err = -EINVAL;
  1002. break;
  1003. case RES_MPT_HW:
  1004. if (r->com.state != RES_MPT_MAPPED)
  1005. err = -EINVAL;
  1006. break;
  1007. default:
  1008. err = -EINVAL;
  1009. }
  1010. if (!err) {
  1011. r->com.from_state = r->com.state;
  1012. r->com.to_state = state;
  1013. r->com.state = RES_MPT_BUSY;
  1014. if (mpt)
  1015. *mpt = r;
  1016. }
  1017. }
  1018. spin_unlock_irq(mlx4_tlock(dev));
  1019. return err;
  1020. }
  1021. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1022. enum res_eq_states state, struct res_eq **eq)
  1023. {
  1024. struct mlx4_priv *priv = mlx4_priv(dev);
  1025. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1026. struct res_eq *r;
  1027. int err = 0;
  1028. spin_lock_irq(mlx4_tlock(dev));
  1029. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  1030. if (!r)
  1031. err = -ENOENT;
  1032. else if (r->com.owner != slave)
  1033. err = -EPERM;
  1034. else {
  1035. switch (state) {
  1036. case RES_EQ_BUSY:
  1037. err = -EINVAL;
  1038. break;
  1039. case RES_EQ_RESERVED:
  1040. if (r->com.state != RES_EQ_HW)
  1041. err = -EINVAL;
  1042. break;
  1043. case RES_EQ_HW:
  1044. if (r->com.state != RES_EQ_RESERVED)
  1045. err = -EINVAL;
  1046. break;
  1047. default:
  1048. err = -EINVAL;
  1049. }
  1050. if (!err) {
  1051. r->com.from_state = r->com.state;
  1052. r->com.to_state = state;
  1053. r->com.state = RES_EQ_BUSY;
  1054. if (eq)
  1055. *eq = r;
  1056. }
  1057. }
  1058. spin_unlock_irq(mlx4_tlock(dev));
  1059. return err;
  1060. }
  1061. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  1062. enum res_cq_states state, struct res_cq **cq)
  1063. {
  1064. struct mlx4_priv *priv = mlx4_priv(dev);
  1065. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1066. struct res_cq *r;
  1067. int err;
  1068. spin_lock_irq(mlx4_tlock(dev));
  1069. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  1070. if (!r)
  1071. err = -ENOENT;
  1072. else if (r->com.owner != slave)
  1073. err = -EPERM;
  1074. else {
  1075. switch (state) {
  1076. case RES_CQ_BUSY:
  1077. err = -EBUSY;
  1078. break;
  1079. case RES_CQ_ALLOCATED:
  1080. if (r->com.state != RES_CQ_HW)
  1081. err = -EINVAL;
  1082. else if (atomic_read(&r->ref_count))
  1083. err = -EBUSY;
  1084. else
  1085. err = 0;
  1086. break;
  1087. case RES_CQ_HW:
  1088. if (r->com.state != RES_CQ_ALLOCATED)
  1089. err = -EINVAL;
  1090. else
  1091. err = 0;
  1092. break;
  1093. default:
  1094. err = -EINVAL;
  1095. }
  1096. if (!err) {
  1097. r->com.from_state = r->com.state;
  1098. r->com.to_state = state;
  1099. r->com.state = RES_CQ_BUSY;
  1100. if (cq)
  1101. *cq = r;
  1102. }
  1103. }
  1104. spin_unlock_irq(mlx4_tlock(dev));
  1105. return err;
  1106. }
  1107. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1108. enum res_cq_states state, struct res_srq **srq)
  1109. {
  1110. struct mlx4_priv *priv = mlx4_priv(dev);
  1111. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1112. struct res_srq *r;
  1113. int err = 0;
  1114. spin_lock_irq(mlx4_tlock(dev));
  1115. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  1116. if (!r)
  1117. err = -ENOENT;
  1118. else if (r->com.owner != slave)
  1119. err = -EPERM;
  1120. else {
  1121. switch (state) {
  1122. case RES_SRQ_BUSY:
  1123. err = -EINVAL;
  1124. break;
  1125. case RES_SRQ_ALLOCATED:
  1126. if (r->com.state != RES_SRQ_HW)
  1127. err = -EINVAL;
  1128. else if (atomic_read(&r->ref_count))
  1129. err = -EBUSY;
  1130. break;
  1131. case RES_SRQ_HW:
  1132. if (r->com.state != RES_SRQ_ALLOCATED)
  1133. err = -EINVAL;
  1134. break;
  1135. default:
  1136. err = -EINVAL;
  1137. }
  1138. if (!err) {
  1139. r->com.from_state = r->com.state;
  1140. r->com.to_state = state;
  1141. r->com.state = RES_SRQ_BUSY;
  1142. if (srq)
  1143. *srq = r;
  1144. }
  1145. }
  1146. spin_unlock_irq(mlx4_tlock(dev));
  1147. return err;
  1148. }
  1149. static void res_abort_move(struct mlx4_dev *dev, int slave,
  1150. enum mlx4_resource type, int id)
  1151. {
  1152. struct mlx4_priv *priv = mlx4_priv(dev);
  1153. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1154. struct res_common *r;
  1155. spin_lock_irq(mlx4_tlock(dev));
  1156. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1157. if (r && (r->owner == slave))
  1158. r->state = r->from_state;
  1159. spin_unlock_irq(mlx4_tlock(dev));
  1160. }
  1161. static void res_end_move(struct mlx4_dev *dev, int slave,
  1162. enum mlx4_resource type, int id)
  1163. {
  1164. struct mlx4_priv *priv = mlx4_priv(dev);
  1165. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1166. struct res_common *r;
  1167. spin_lock_irq(mlx4_tlock(dev));
  1168. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1169. if (r && (r->owner == slave))
  1170. r->state = r->to_state;
  1171. spin_unlock_irq(mlx4_tlock(dev));
  1172. }
  1173. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  1174. {
  1175. return mlx4_is_qp_reserved(dev, qpn) &&
  1176. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  1177. }
  1178. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  1179. {
  1180. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  1181. }
  1182. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1183. u64 in_param, u64 *out_param)
  1184. {
  1185. int err;
  1186. int count;
  1187. int align;
  1188. int base;
  1189. int qpn;
  1190. switch (op) {
  1191. case RES_OP_RESERVE:
  1192. count = get_param_l(&in_param);
  1193. align = get_param_h(&in_param);
  1194. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  1195. if (err)
  1196. return err;
  1197. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  1198. if (err) {
  1199. __mlx4_qp_release_range(dev, base, count);
  1200. return err;
  1201. }
  1202. set_param_l(out_param, base);
  1203. break;
  1204. case RES_OP_MAP_ICM:
  1205. qpn = get_param_l(&in_param) & 0x7fffff;
  1206. if (valid_reserved(dev, slave, qpn)) {
  1207. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1208. if (err)
  1209. return err;
  1210. }
  1211. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  1212. NULL, 1);
  1213. if (err)
  1214. return err;
  1215. if (!fw_reserved(dev, qpn)) {
  1216. err = __mlx4_qp_alloc_icm(dev, qpn);
  1217. if (err) {
  1218. res_abort_move(dev, slave, RES_QP, qpn);
  1219. return err;
  1220. }
  1221. }
  1222. res_end_move(dev, slave, RES_QP, qpn);
  1223. break;
  1224. default:
  1225. err = -EINVAL;
  1226. break;
  1227. }
  1228. return err;
  1229. }
  1230. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1231. u64 in_param, u64 *out_param)
  1232. {
  1233. int err = -EINVAL;
  1234. int base;
  1235. int order;
  1236. if (op != RES_OP_RESERVE_AND_MAP)
  1237. return err;
  1238. order = get_param_l(&in_param);
  1239. base = __mlx4_alloc_mtt_range(dev, order);
  1240. if (base == -1)
  1241. return -ENOMEM;
  1242. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1243. if (err)
  1244. __mlx4_free_mtt_range(dev, base, order);
  1245. else
  1246. set_param_l(out_param, base);
  1247. return err;
  1248. }
  1249. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1250. u64 in_param, u64 *out_param)
  1251. {
  1252. int err = -EINVAL;
  1253. int index;
  1254. int id;
  1255. struct res_mpt *mpt;
  1256. switch (op) {
  1257. case RES_OP_RESERVE:
  1258. index = __mlx4_mpt_reserve(dev);
  1259. if (index == -1)
  1260. break;
  1261. id = index & mpt_mask(dev);
  1262. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1263. if (err) {
  1264. __mlx4_mpt_release(dev, index);
  1265. break;
  1266. }
  1267. set_param_l(out_param, index);
  1268. break;
  1269. case RES_OP_MAP_ICM:
  1270. index = get_param_l(&in_param);
  1271. id = index & mpt_mask(dev);
  1272. err = mr_res_start_move_to(dev, slave, id,
  1273. RES_MPT_MAPPED, &mpt);
  1274. if (err)
  1275. return err;
  1276. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1277. if (err) {
  1278. res_abort_move(dev, slave, RES_MPT, id);
  1279. return err;
  1280. }
  1281. res_end_move(dev, slave, RES_MPT, id);
  1282. break;
  1283. }
  1284. return err;
  1285. }
  1286. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1287. u64 in_param, u64 *out_param)
  1288. {
  1289. int cqn;
  1290. int err;
  1291. switch (op) {
  1292. case RES_OP_RESERVE_AND_MAP:
  1293. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1294. if (err)
  1295. break;
  1296. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1297. if (err) {
  1298. __mlx4_cq_free_icm(dev, cqn);
  1299. break;
  1300. }
  1301. set_param_l(out_param, cqn);
  1302. break;
  1303. default:
  1304. err = -EINVAL;
  1305. }
  1306. return err;
  1307. }
  1308. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1309. u64 in_param, u64 *out_param)
  1310. {
  1311. int srqn;
  1312. int err;
  1313. switch (op) {
  1314. case RES_OP_RESERVE_AND_MAP:
  1315. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1316. if (err)
  1317. break;
  1318. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1319. if (err) {
  1320. __mlx4_srq_free_icm(dev, srqn);
  1321. break;
  1322. }
  1323. set_param_l(out_param, srqn);
  1324. break;
  1325. default:
  1326. err = -EINVAL;
  1327. }
  1328. return err;
  1329. }
  1330. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1331. {
  1332. struct mlx4_priv *priv = mlx4_priv(dev);
  1333. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1334. struct mac_res *res;
  1335. res = kzalloc(sizeof *res, GFP_KERNEL);
  1336. if (!res)
  1337. return -ENOMEM;
  1338. res->mac = mac;
  1339. res->port = (u8) port;
  1340. list_add_tail(&res->list,
  1341. &tracker->slave_list[slave].res_list[RES_MAC]);
  1342. return 0;
  1343. }
  1344. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1345. int port)
  1346. {
  1347. struct mlx4_priv *priv = mlx4_priv(dev);
  1348. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1349. struct list_head *mac_list =
  1350. &tracker->slave_list[slave].res_list[RES_MAC];
  1351. struct mac_res *res, *tmp;
  1352. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1353. if (res->mac == mac && res->port == (u8) port) {
  1354. list_del(&res->list);
  1355. kfree(res);
  1356. break;
  1357. }
  1358. }
  1359. }
  1360. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1361. {
  1362. struct mlx4_priv *priv = mlx4_priv(dev);
  1363. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1364. struct list_head *mac_list =
  1365. &tracker->slave_list[slave].res_list[RES_MAC];
  1366. struct mac_res *res, *tmp;
  1367. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1368. list_del(&res->list);
  1369. __mlx4_unregister_mac(dev, res->port, res->mac);
  1370. kfree(res);
  1371. }
  1372. }
  1373. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1374. u64 in_param, u64 *out_param, int in_port)
  1375. {
  1376. int err = -EINVAL;
  1377. int port;
  1378. u64 mac;
  1379. if (op != RES_OP_RESERVE_AND_MAP)
  1380. return err;
  1381. port = !in_port ? get_param_l(out_param) : in_port;
  1382. mac = in_param;
  1383. err = __mlx4_register_mac(dev, port, mac);
  1384. if (err >= 0) {
  1385. set_param_l(out_param, err);
  1386. err = 0;
  1387. }
  1388. if (!err) {
  1389. err = mac_add_to_slave(dev, slave, mac, port);
  1390. if (err)
  1391. __mlx4_unregister_mac(dev, port, mac);
  1392. }
  1393. return err;
  1394. }
  1395. static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1396. int port, int vlan_index)
  1397. {
  1398. struct mlx4_priv *priv = mlx4_priv(dev);
  1399. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1400. struct list_head *vlan_list =
  1401. &tracker->slave_list[slave].res_list[RES_VLAN];
  1402. struct vlan_res *res, *tmp;
  1403. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1404. if (res->vlan == vlan && res->port == (u8) port) {
  1405. /* vlan found. update ref count */
  1406. ++res->ref_count;
  1407. return 0;
  1408. }
  1409. }
  1410. res = kzalloc(sizeof(*res), GFP_KERNEL);
  1411. if (!res)
  1412. return -ENOMEM;
  1413. res->vlan = vlan;
  1414. res->port = (u8) port;
  1415. res->vlan_index = vlan_index;
  1416. res->ref_count = 1;
  1417. list_add_tail(&res->list,
  1418. &tracker->slave_list[slave].res_list[RES_VLAN]);
  1419. return 0;
  1420. }
  1421. static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1422. int port)
  1423. {
  1424. struct mlx4_priv *priv = mlx4_priv(dev);
  1425. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1426. struct list_head *vlan_list =
  1427. &tracker->slave_list[slave].res_list[RES_VLAN];
  1428. struct vlan_res *res, *tmp;
  1429. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1430. if (res->vlan == vlan && res->port == (u8) port) {
  1431. if (!--res->ref_count) {
  1432. list_del(&res->list);
  1433. kfree(res);
  1434. }
  1435. break;
  1436. }
  1437. }
  1438. }
  1439. static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
  1440. {
  1441. struct mlx4_priv *priv = mlx4_priv(dev);
  1442. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1443. struct list_head *vlan_list =
  1444. &tracker->slave_list[slave].res_list[RES_VLAN];
  1445. struct vlan_res *res, *tmp;
  1446. int i;
  1447. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1448. list_del(&res->list);
  1449. /* dereference the vlan the num times the slave referenced it */
  1450. for (i = 0; i < res->ref_count; i++)
  1451. __mlx4_unregister_vlan(dev, res->port, res->vlan);
  1452. kfree(res);
  1453. }
  1454. }
  1455. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1456. u64 in_param, u64 *out_param, int in_port)
  1457. {
  1458. struct mlx4_priv *priv = mlx4_priv(dev);
  1459. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1460. int err;
  1461. u16 vlan;
  1462. int vlan_index;
  1463. int port;
  1464. port = !in_port ? get_param_l(out_param) : in_port;
  1465. if (!port || op != RES_OP_RESERVE_AND_MAP)
  1466. return -EINVAL;
  1467. /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
  1468. if (!in_port && port > 0 && port <= dev->caps.num_ports) {
  1469. slave_state[slave].old_vlan_api = true;
  1470. return 0;
  1471. }
  1472. vlan = (u16) in_param;
  1473. err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
  1474. if (!err) {
  1475. set_param_l(out_param, (u32) vlan_index);
  1476. err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
  1477. if (err)
  1478. __mlx4_unregister_vlan(dev, port, vlan);
  1479. }
  1480. return err;
  1481. }
  1482. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1483. u64 in_param, u64 *out_param)
  1484. {
  1485. u32 index;
  1486. int err;
  1487. if (op != RES_OP_RESERVE)
  1488. return -EINVAL;
  1489. err = __mlx4_counter_alloc(dev, &index);
  1490. if (err)
  1491. return err;
  1492. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1493. if (err)
  1494. __mlx4_counter_free(dev, index);
  1495. else
  1496. set_param_l(out_param, index);
  1497. return err;
  1498. }
  1499. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1500. u64 in_param, u64 *out_param)
  1501. {
  1502. u32 xrcdn;
  1503. int err;
  1504. if (op != RES_OP_RESERVE)
  1505. return -EINVAL;
  1506. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1507. if (err)
  1508. return err;
  1509. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1510. if (err)
  1511. __mlx4_xrcd_free(dev, xrcdn);
  1512. else
  1513. set_param_l(out_param, xrcdn);
  1514. return err;
  1515. }
  1516. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1517. struct mlx4_vhcr *vhcr,
  1518. struct mlx4_cmd_mailbox *inbox,
  1519. struct mlx4_cmd_mailbox *outbox,
  1520. struct mlx4_cmd_info *cmd)
  1521. {
  1522. int err;
  1523. int alop = vhcr->op_modifier;
  1524. switch (vhcr->in_modifier & 0xFF) {
  1525. case RES_QP:
  1526. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1527. vhcr->in_param, &vhcr->out_param);
  1528. break;
  1529. case RES_MTT:
  1530. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1531. vhcr->in_param, &vhcr->out_param);
  1532. break;
  1533. case RES_MPT:
  1534. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1535. vhcr->in_param, &vhcr->out_param);
  1536. break;
  1537. case RES_CQ:
  1538. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1539. vhcr->in_param, &vhcr->out_param);
  1540. break;
  1541. case RES_SRQ:
  1542. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1543. vhcr->in_param, &vhcr->out_param);
  1544. break;
  1545. case RES_MAC:
  1546. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1547. vhcr->in_param, &vhcr->out_param,
  1548. (vhcr->in_modifier >> 8) & 0xFF);
  1549. break;
  1550. case RES_VLAN:
  1551. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1552. vhcr->in_param, &vhcr->out_param,
  1553. (vhcr->in_modifier >> 8) & 0xFF);
  1554. break;
  1555. case RES_COUNTER:
  1556. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1557. vhcr->in_param, &vhcr->out_param);
  1558. break;
  1559. case RES_XRCD:
  1560. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1561. vhcr->in_param, &vhcr->out_param);
  1562. break;
  1563. default:
  1564. err = -EINVAL;
  1565. break;
  1566. }
  1567. return err;
  1568. }
  1569. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1570. u64 in_param)
  1571. {
  1572. int err;
  1573. int count;
  1574. int base;
  1575. int qpn;
  1576. switch (op) {
  1577. case RES_OP_RESERVE:
  1578. base = get_param_l(&in_param) & 0x7fffff;
  1579. count = get_param_h(&in_param);
  1580. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1581. if (err)
  1582. break;
  1583. __mlx4_qp_release_range(dev, base, count);
  1584. break;
  1585. case RES_OP_MAP_ICM:
  1586. qpn = get_param_l(&in_param) & 0x7fffff;
  1587. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1588. NULL, 0);
  1589. if (err)
  1590. return err;
  1591. if (!fw_reserved(dev, qpn))
  1592. __mlx4_qp_free_icm(dev, qpn);
  1593. res_end_move(dev, slave, RES_QP, qpn);
  1594. if (valid_reserved(dev, slave, qpn))
  1595. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1596. break;
  1597. default:
  1598. err = -EINVAL;
  1599. break;
  1600. }
  1601. return err;
  1602. }
  1603. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1604. u64 in_param, u64 *out_param)
  1605. {
  1606. int err = -EINVAL;
  1607. int base;
  1608. int order;
  1609. if (op != RES_OP_RESERVE_AND_MAP)
  1610. return err;
  1611. base = get_param_l(&in_param);
  1612. order = get_param_h(&in_param);
  1613. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1614. if (!err)
  1615. __mlx4_free_mtt_range(dev, base, order);
  1616. return err;
  1617. }
  1618. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1619. u64 in_param)
  1620. {
  1621. int err = -EINVAL;
  1622. int index;
  1623. int id;
  1624. struct res_mpt *mpt;
  1625. switch (op) {
  1626. case RES_OP_RESERVE:
  1627. index = get_param_l(&in_param);
  1628. id = index & mpt_mask(dev);
  1629. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1630. if (err)
  1631. break;
  1632. index = mpt->key;
  1633. put_res(dev, slave, id, RES_MPT);
  1634. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1635. if (err)
  1636. break;
  1637. __mlx4_mpt_release(dev, index);
  1638. break;
  1639. case RES_OP_MAP_ICM:
  1640. index = get_param_l(&in_param);
  1641. id = index & mpt_mask(dev);
  1642. err = mr_res_start_move_to(dev, slave, id,
  1643. RES_MPT_RESERVED, &mpt);
  1644. if (err)
  1645. return err;
  1646. __mlx4_mpt_free_icm(dev, mpt->key);
  1647. res_end_move(dev, slave, RES_MPT, id);
  1648. return err;
  1649. break;
  1650. default:
  1651. err = -EINVAL;
  1652. break;
  1653. }
  1654. return err;
  1655. }
  1656. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1657. u64 in_param, u64 *out_param)
  1658. {
  1659. int cqn;
  1660. int err;
  1661. switch (op) {
  1662. case RES_OP_RESERVE_AND_MAP:
  1663. cqn = get_param_l(&in_param);
  1664. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1665. if (err)
  1666. break;
  1667. __mlx4_cq_free_icm(dev, cqn);
  1668. break;
  1669. default:
  1670. err = -EINVAL;
  1671. break;
  1672. }
  1673. return err;
  1674. }
  1675. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1676. u64 in_param, u64 *out_param)
  1677. {
  1678. int srqn;
  1679. int err;
  1680. switch (op) {
  1681. case RES_OP_RESERVE_AND_MAP:
  1682. srqn = get_param_l(&in_param);
  1683. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1684. if (err)
  1685. break;
  1686. __mlx4_srq_free_icm(dev, srqn);
  1687. break;
  1688. default:
  1689. err = -EINVAL;
  1690. break;
  1691. }
  1692. return err;
  1693. }
  1694. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1695. u64 in_param, u64 *out_param, int in_port)
  1696. {
  1697. int port;
  1698. int err = 0;
  1699. switch (op) {
  1700. case RES_OP_RESERVE_AND_MAP:
  1701. port = !in_port ? get_param_l(out_param) : in_port;
  1702. mac_del_from_slave(dev, slave, in_param, port);
  1703. __mlx4_unregister_mac(dev, port, in_param);
  1704. break;
  1705. default:
  1706. err = -EINVAL;
  1707. break;
  1708. }
  1709. return err;
  1710. }
  1711. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1712. u64 in_param, u64 *out_param, int port)
  1713. {
  1714. struct mlx4_priv *priv = mlx4_priv(dev);
  1715. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1716. int err = 0;
  1717. switch (op) {
  1718. case RES_OP_RESERVE_AND_MAP:
  1719. if (slave_state[slave].old_vlan_api)
  1720. return 0;
  1721. if (!port)
  1722. return -EINVAL;
  1723. vlan_del_from_slave(dev, slave, in_param, port);
  1724. __mlx4_unregister_vlan(dev, port, in_param);
  1725. break;
  1726. default:
  1727. err = -EINVAL;
  1728. break;
  1729. }
  1730. return err;
  1731. }
  1732. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1733. u64 in_param, u64 *out_param)
  1734. {
  1735. int index;
  1736. int err;
  1737. if (op != RES_OP_RESERVE)
  1738. return -EINVAL;
  1739. index = get_param_l(&in_param);
  1740. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1741. if (err)
  1742. return err;
  1743. __mlx4_counter_free(dev, index);
  1744. return err;
  1745. }
  1746. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1747. u64 in_param, u64 *out_param)
  1748. {
  1749. int xrcdn;
  1750. int err;
  1751. if (op != RES_OP_RESERVE)
  1752. return -EINVAL;
  1753. xrcdn = get_param_l(&in_param);
  1754. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1755. if (err)
  1756. return err;
  1757. __mlx4_xrcd_free(dev, xrcdn);
  1758. return err;
  1759. }
  1760. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1761. struct mlx4_vhcr *vhcr,
  1762. struct mlx4_cmd_mailbox *inbox,
  1763. struct mlx4_cmd_mailbox *outbox,
  1764. struct mlx4_cmd_info *cmd)
  1765. {
  1766. int err = -EINVAL;
  1767. int alop = vhcr->op_modifier;
  1768. switch (vhcr->in_modifier & 0xFF) {
  1769. case RES_QP:
  1770. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1771. vhcr->in_param);
  1772. break;
  1773. case RES_MTT:
  1774. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1775. vhcr->in_param, &vhcr->out_param);
  1776. break;
  1777. case RES_MPT:
  1778. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1779. vhcr->in_param);
  1780. break;
  1781. case RES_CQ:
  1782. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1783. vhcr->in_param, &vhcr->out_param);
  1784. break;
  1785. case RES_SRQ:
  1786. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1787. vhcr->in_param, &vhcr->out_param);
  1788. break;
  1789. case RES_MAC:
  1790. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1791. vhcr->in_param, &vhcr->out_param,
  1792. (vhcr->in_modifier >> 8) & 0xFF);
  1793. break;
  1794. case RES_VLAN:
  1795. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1796. vhcr->in_param, &vhcr->out_param,
  1797. (vhcr->in_modifier >> 8) & 0xFF);
  1798. break;
  1799. case RES_COUNTER:
  1800. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1801. vhcr->in_param, &vhcr->out_param);
  1802. break;
  1803. case RES_XRCD:
  1804. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1805. vhcr->in_param, &vhcr->out_param);
  1806. default:
  1807. break;
  1808. }
  1809. return err;
  1810. }
  1811. /* ugly but other choices are uglier */
  1812. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1813. {
  1814. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1815. }
  1816. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1817. {
  1818. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1819. }
  1820. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1821. {
  1822. return be32_to_cpu(mpt->mtt_sz);
  1823. }
  1824. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  1825. {
  1826. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  1827. }
  1828. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  1829. {
  1830. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  1831. }
  1832. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  1833. {
  1834. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  1835. }
  1836. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  1837. {
  1838. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  1839. }
  1840. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1841. {
  1842. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1843. }
  1844. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1845. {
  1846. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1847. }
  1848. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1849. {
  1850. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1851. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1852. int log_sq_sride = qpc->sq_size_stride & 7;
  1853. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1854. int log_rq_stride = qpc->rq_size_stride & 7;
  1855. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1856. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1857. u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  1858. int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
  1859. int sq_size;
  1860. int rq_size;
  1861. int total_pages;
  1862. int total_mem;
  1863. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1864. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1865. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1866. total_mem = sq_size + rq_size;
  1867. total_pages =
  1868. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1869. page_shift);
  1870. return total_pages;
  1871. }
  1872. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1873. int size, struct res_mtt *mtt)
  1874. {
  1875. int res_start = mtt->com.res_id;
  1876. int res_size = (1 << mtt->order);
  1877. if (start < res_start || start + size > res_start + res_size)
  1878. return -EPERM;
  1879. return 0;
  1880. }
  1881. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1882. struct mlx4_vhcr *vhcr,
  1883. struct mlx4_cmd_mailbox *inbox,
  1884. struct mlx4_cmd_mailbox *outbox,
  1885. struct mlx4_cmd_info *cmd)
  1886. {
  1887. int err;
  1888. int index = vhcr->in_modifier;
  1889. struct res_mtt *mtt;
  1890. struct res_mpt *mpt;
  1891. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1892. int phys;
  1893. int id;
  1894. u32 pd;
  1895. int pd_slave;
  1896. id = index & mpt_mask(dev);
  1897. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1898. if (err)
  1899. return err;
  1900. /* Disable memory windows for VFs. */
  1901. if (!mr_is_region(inbox->buf)) {
  1902. err = -EPERM;
  1903. goto ex_abort;
  1904. }
  1905. /* Make sure that the PD bits related to the slave id are zeros. */
  1906. pd = mr_get_pd(inbox->buf);
  1907. pd_slave = (pd >> 17) & 0x7f;
  1908. if (pd_slave != 0 && pd_slave != slave) {
  1909. err = -EPERM;
  1910. goto ex_abort;
  1911. }
  1912. if (mr_is_fmr(inbox->buf)) {
  1913. /* FMR and Bind Enable are forbidden in slave devices. */
  1914. if (mr_is_bind_enabled(inbox->buf)) {
  1915. err = -EPERM;
  1916. goto ex_abort;
  1917. }
  1918. /* FMR and Memory Windows are also forbidden. */
  1919. if (!mr_is_region(inbox->buf)) {
  1920. err = -EPERM;
  1921. goto ex_abort;
  1922. }
  1923. }
  1924. phys = mr_phys_mpt(inbox->buf);
  1925. if (!phys) {
  1926. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1927. if (err)
  1928. goto ex_abort;
  1929. err = check_mtt_range(dev, slave, mtt_base,
  1930. mr_get_mtt_size(inbox->buf), mtt);
  1931. if (err)
  1932. goto ex_put;
  1933. mpt->mtt = mtt;
  1934. }
  1935. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1936. if (err)
  1937. goto ex_put;
  1938. if (!phys) {
  1939. atomic_inc(&mtt->ref_count);
  1940. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1941. }
  1942. res_end_move(dev, slave, RES_MPT, id);
  1943. return 0;
  1944. ex_put:
  1945. if (!phys)
  1946. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1947. ex_abort:
  1948. res_abort_move(dev, slave, RES_MPT, id);
  1949. return err;
  1950. }
  1951. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1952. struct mlx4_vhcr *vhcr,
  1953. struct mlx4_cmd_mailbox *inbox,
  1954. struct mlx4_cmd_mailbox *outbox,
  1955. struct mlx4_cmd_info *cmd)
  1956. {
  1957. int err;
  1958. int index = vhcr->in_modifier;
  1959. struct res_mpt *mpt;
  1960. int id;
  1961. id = index & mpt_mask(dev);
  1962. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1963. if (err)
  1964. return err;
  1965. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1966. if (err)
  1967. goto ex_abort;
  1968. if (mpt->mtt)
  1969. atomic_dec(&mpt->mtt->ref_count);
  1970. res_end_move(dev, slave, RES_MPT, id);
  1971. return 0;
  1972. ex_abort:
  1973. res_abort_move(dev, slave, RES_MPT, id);
  1974. return err;
  1975. }
  1976. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1977. struct mlx4_vhcr *vhcr,
  1978. struct mlx4_cmd_mailbox *inbox,
  1979. struct mlx4_cmd_mailbox *outbox,
  1980. struct mlx4_cmd_info *cmd)
  1981. {
  1982. int err;
  1983. int index = vhcr->in_modifier;
  1984. struct res_mpt *mpt;
  1985. int id;
  1986. id = index & mpt_mask(dev);
  1987. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1988. if (err)
  1989. return err;
  1990. if (mpt->com.from_state != RES_MPT_HW) {
  1991. err = -EBUSY;
  1992. goto out;
  1993. }
  1994. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1995. out:
  1996. put_res(dev, slave, id, RES_MPT);
  1997. return err;
  1998. }
  1999. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  2000. {
  2001. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  2002. }
  2003. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  2004. {
  2005. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  2006. }
  2007. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  2008. {
  2009. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  2010. }
  2011. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  2012. struct mlx4_qp_context *context)
  2013. {
  2014. u32 qpn = vhcr->in_modifier & 0xffffff;
  2015. u32 qkey = 0;
  2016. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  2017. return;
  2018. /* adjust qkey in qp context */
  2019. context->qkey = cpu_to_be32(qkey);
  2020. }
  2021. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2022. struct mlx4_vhcr *vhcr,
  2023. struct mlx4_cmd_mailbox *inbox,
  2024. struct mlx4_cmd_mailbox *outbox,
  2025. struct mlx4_cmd_info *cmd)
  2026. {
  2027. int err;
  2028. int qpn = vhcr->in_modifier & 0x7fffff;
  2029. struct res_mtt *mtt;
  2030. struct res_qp *qp;
  2031. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2032. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  2033. int mtt_size = qp_get_mtt_size(qpc);
  2034. struct res_cq *rcq;
  2035. struct res_cq *scq;
  2036. int rcqn = qp_get_rcqn(qpc);
  2037. int scqn = qp_get_scqn(qpc);
  2038. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  2039. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  2040. struct res_srq *srq;
  2041. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  2042. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  2043. if (err)
  2044. return err;
  2045. qp->local_qpn = local_qpn;
  2046. qp->sched_queue = 0;
  2047. qp->qpc_flags = be32_to_cpu(qpc->flags);
  2048. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2049. if (err)
  2050. goto ex_abort;
  2051. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2052. if (err)
  2053. goto ex_put_mtt;
  2054. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  2055. if (err)
  2056. goto ex_put_mtt;
  2057. if (scqn != rcqn) {
  2058. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  2059. if (err)
  2060. goto ex_put_rcq;
  2061. } else
  2062. scq = rcq;
  2063. if (use_srq) {
  2064. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2065. if (err)
  2066. goto ex_put_scq;
  2067. }
  2068. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2069. update_pkey_index(dev, slave, inbox);
  2070. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2071. if (err)
  2072. goto ex_put_srq;
  2073. atomic_inc(&mtt->ref_count);
  2074. qp->mtt = mtt;
  2075. atomic_inc(&rcq->ref_count);
  2076. qp->rcq = rcq;
  2077. atomic_inc(&scq->ref_count);
  2078. qp->scq = scq;
  2079. if (scqn != rcqn)
  2080. put_res(dev, slave, scqn, RES_CQ);
  2081. if (use_srq) {
  2082. atomic_inc(&srq->ref_count);
  2083. put_res(dev, slave, srqn, RES_SRQ);
  2084. qp->srq = srq;
  2085. }
  2086. put_res(dev, slave, rcqn, RES_CQ);
  2087. put_res(dev, slave, mtt_base, RES_MTT);
  2088. res_end_move(dev, slave, RES_QP, qpn);
  2089. return 0;
  2090. ex_put_srq:
  2091. if (use_srq)
  2092. put_res(dev, slave, srqn, RES_SRQ);
  2093. ex_put_scq:
  2094. if (scqn != rcqn)
  2095. put_res(dev, slave, scqn, RES_CQ);
  2096. ex_put_rcq:
  2097. put_res(dev, slave, rcqn, RES_CQ);
  2098. ex_put_mtt:
  2099. put_res(dev, slave, mtt_base, RES_MTT);
  2100. ex_abort:
  2101. res_abort_move(dev, slave, RES_QP, qpn);
  2102. return err;
  2103. }
  2104. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  2105. {
  2106. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  2107. }
  2108. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  2109. {
  2110. int log_eq_size = eqc->log_eq_size & 0x1f;
  2111. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  2112. if (log_eq_size + 5 < page_shift)
  2113. return 1;
  2114. return 1 << (log_eq_size + 5 - page_shift);
  2115. }
  2116. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  2117. {
  2118. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  2119. }
  2120. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  2121. {
  2122. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  2123. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  2124. if (log_cq_size + 5 < page_shift)
  2125. return 1;
  2126. return 1 << (log_cq_size + 5 - page_shift);
  2127. }
  2128. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2129. struct mlx4_vhcr *vhcr,
  2130. struct mlx4_cmd_mailbox *inbox,
  2131. struct mlx4_cmd_mailbox *outbox,
  2132. struct mlx4_cmd_info *cmd)
  2133. {
  2134. int err;
  2135. int eqn = vhcr->in_modifier;
  2136. int res_id = (slave << 8) | eqn;
  2137. struct mlx4_eq_context *eqc = inbox->buf;
  2138. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  2139. int mtt_size = eq_get_mtt_size(eqc);
  2140. struct res_eq *eq;
  2141. struct res_mtt *mtt;
  2142. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2143. if (err)
  2144. return err;
  2145. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  2146. if (err)
  2147. goto out_add;
  2148. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2149. if (err)
  2150. goto out_move;
  2151. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2152. if (err)
  2153. goto out_put;
  2154. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2155. if (err)
  2156. goto out_put;
  2157. atomic_inc(&mtt->ref_count);
  2158. eq->mtt = mtt;
  2159. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2160. res_end_move(dev, slave, RES_EQ, res_id);
  2161. return 0;
  2162. out_put:
  2163. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2164. out_move:
  2165. res_abort_move(dev, slave, RES_EQ, res_id);
  2166. out_add:
  2167. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2168. return err;
  2169. }
  2170. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  2171. int len, struct res_mtt **res)
  2172. {
  2173. struct mlx4_priv *priv = mlx4_priv(dev);
  2174. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2175. struct res_mtt *mtt;
  2176. int err = -EINVAL;
  2177. spin_lock_irq(mlx4_tlock(dev));
  2178. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  2179. com.list) {
  2180. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  2181. *res = mtt;
  2182. mtt->com.from_state = mtt->com.state;
  2183. mtt->com.state = RES_MTT_BUSY;
  2184. err = 0;
  2185. break;
  2186. }
  2187. }
  2188. spin_unlock_irq(mlx4_tlock(dev));
  2189. return err;
  2190. }
  2191. static int verify_qp_parameters(struct mlx4_dev *dev,
  2192. struct mlx4_cmd_mailbox *inbox,
  2193. enum qp_transition transition, u8 slave)
  2194. {
  2195. u32 qp_type;
  2196. struct mlx4_qp_context *qp_ctx;
  2197. enum mlx4_qp_optpar optpar;
  2198. qp_ctx = inbox->buf + 8;
  2199. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  2200. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  2201. switch (qp_type) {
  2202. case MLX4_QP_ST_RC:
  2203. case MLX4_QP_ST_UC:
  2204. switch (transition) {
  2205. case QP_TRANS_INIT2RTR:
  2206. case QP_TRANS_RTR2RTS:
  2207. case QP_TRANS_RTS2RTS:
  2208. case QP_TRANS_SQD2SQD:
  2209. case QP_TRANS_SQD2RTS:
  2210. if (slave != mlx4_master_func_num(dev))
  2211. /* slaves have only gid index 0 */
  2212. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  2213. if (qp_ctx->pri_path.mgid_index)
  2214. return -EINVAL;
  2215. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  2216. if (qp_ctx->alt_path.mgid_index)
  2217. return -EINVAL;
  2218. break;
  2219. default:
  2220. break;
  2221. }
  2222. break;
  2223. default:
  2224. break;
  2225. }
  2226. return 0;
  2227. }
  2228. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  2229. struct mlx4_vhcr *vhcr,
  2230. struct mlx4_cmd_mailbox *inbox,
  2231. struct mlx4_cmd_mailbox *outbox,
  2232. struct mlx4_cmd_info *cmd)
  2233. {
  2234. struct mlx4_mtt mtt;
  2235. __be64 *page_list = inbox->buf;
  2236. u64 *pg_list = (u64 *)page_list;
  2237. int i;
  2238. struct res_mtt *rmtt = NULL;
  2239. int start = be64_to_cpu(page_list[0]);
  2240. int npages = vhcr->in_modifier;
  2241. int err;
  2242. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  2243. if (err)
  2244. return err;
  2245. /* Call the SW implementation of write_mtt:
  2246. * - Prepare a dummy mtt struct
  2247. * - Translate inbox contents to simple addresses in host endianess */
  2248. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  2249. we don't really use it */
  2250. mtt.order = 0;
  2251. mtt.page_shift = 0;
  2252. for (i = 0; i < npages; ++i)
  2253. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  2254. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  2255. ((u64 *)page_list + 2));
  2256. if (rmtt)
  2257. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  2258. return err;
  2259. }
  2260. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2261. struct mlx4_vhcr *vhcr,
  2262. struct mlx4_cmd_mailbox *inbox,
  2263. struct mlx4_cmd_mailbox *outbox,
  2264. struct mlx4_cmd_info *cmd)
  2265. {
  2266. int eqn = vhcr->in_modifier;
  2267. int res_id = eqn | (slave << 8);
  2268. struct res_eq *eq;
  2269. int err;
  2270. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  2271. if (err)
  2272. return err;
  2273. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  2274. if (err)
  2275. goto ex_abort;
  2276. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2277. if (err)
  2278. goto ex_put;
  2279. atomic_dec(&eq->mtt->ref_count);
  2280. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2281. res_end_move(dev, slave, RES_EQ, res_id);
  2282. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2283. return 0;
  2284. ex_put:
  2285. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2286. ex_abort:
  2287. res_abort_move(dev, slave, RES_EQ, res_id);
  2288. return err;
  2289. }
  2290. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  2291. {
  2292. struct mlx4_priv *priv = mlx4_priv(dev);
  2293. struct mlx4_slave_event_eq_info *event_eq;
  2294. struct mlx4_cmd_mailbox *mailbox;
  2295. u32 in_modifier = 0;
  2296. int err;
  2297. int res_id;
  2298. struct res_eq *req;
  2299. if (!priv->mfunc.master.slave_state)
  2300. return -EINVAL;
  2301. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  2302. /* Create the event only if the slave is registered */
  2303. if (event_eq->eqn < 0)
  2304. return 0;
  2305. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2306. res_id = (slave << 8) | event_eq->eqn;
  2307. err = get_res(dev, slave, res_id, RES_EQ, &req);
  2308. if (err)
  2309. goto unlock;
  2310. if (req->com.from_state != RES_EQ_HW) {
  2311. err = -EINVAL;
  2312. goto put;
  2313. }
  2314. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2315. if (IS_ERR(mailbox)) {
  2316. err = PTR_ERR(mailbox);
  2317. goto put;
  2318. }
  2319. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  2320. ++event_eq->token;
  2321. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  2322. }
  2323. memcpy(mailbox->buf, (u8 *) eqe, 28);
  2324. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  2325. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  2326. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2327. MLX4_CMD_NATIVE);
  2328. put_res(dev, slave, res_id, RES_EQ);
  2329. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2330. mlx4_free_cmd_mailbox(dev, mailbox);
  2331. return err;
  2332. put:
  2333. put_res(dev, slave, res_id, RES_EQ);
  2334. unlock:
  2335. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2336. return err;
  2337. }
  2338. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2339. struct mlx4_vhcr *vhcr,
  2340. struct mlx4_cmd_mailbox *inbox,
  2341. struct mlx4_cmd_mailbox *outbox,
  2342. struct mlx4_cmd_info *cmd)
  2343. {
  2344. int eqn = vhcr->in_modifier;
  2345. int res_id = eqn | (slave << 8);
  2346. struct res_eq *eq;
  2347. int err;
  2348. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2349. if (err)
  2350. return err;
  2351. if (eq->com.from_state != RES_EQ_HW) {
  2352. err = -EINVAL;
  2353. goto ex_put;
  2354. }
  2355. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2356. ex_put:
  2357. put_res(dev, slave, res_id, RES_EQ);
  2358. return err;
  2359. }
  2360. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2361. struct mlx4_vhcr *vhcr,
  2362. struct mlx4_cmd_mailbox *inbox,
  2363. struct mlx4_cmd_mailbox *outbox,
  2364. struct mlx4_cmd_info *cmd)
  2365. {
  2366. int err;
  2367. int cqn = vhcr->in_modifier;
  2368. struct mlx4_cq_context *cqc = inbox->buf;
  2369. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2370. struct res_cq *cq;
  2371. struct res_mtt *mtt;
  2372. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2373. if (err)
  2374. return err;
  2375. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2376. if (err)
  2377. goto out_move;
  2378. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2379. if (err)
  2380. goto out_put;
  2381. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2382. if (err)
  2383. goto out_put;
  2384. atomic_inc(&mtt->ref_count);
  2385. cq->mtt = mtt;
  2386. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2387. res_end_move(dev, slave, RES_CQ, cqn);
  2388. return 0;
  2389. out_put:
  2390. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2391. out_move:
  2392. res_abort_move(dev, slave, RES_CQ, cqn);
  2393. return err;
  2394. }
  2395. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2396. struct mlx4_vhcr *vhcr,
  2397. struct mlx4_cmd_mailbox *inbox,
  2398. struct mlx4_cmd_mailbox *outbox,
  2399. struct mlx4_cmd_info *cmd)
  2400. {
  2401. int err;
  2402. int cqn = vhcr->in_modifier;
  2403. struct res_cq *cq;
  2404. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2405. if (err)
  2406. return err;
  2407. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2408. if (err)
  2409. goto out_move;
  2410. atomic_dec(&cq->mtt->ref_count);
  2411. res_end_move(dev, slave, RES_CQ, cqn);
  2412. return 0;
  2413. out_move:
  2414. res_abort_move(dev, slave, RES_CQ, cqn);
  2415. return err;
  2416. }
  2417. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2418. struct mlx4_vhcr *vhcr,
  2419. struct mlx4_cmd_mailbox *inbox,
  2420. struct mlx4_cmd_mailbox *outbox,
  2421. struct mlx4_cmd_info *cmd)
  2422. {
  2423. int cqn = vhcr->in_modifier;
  2424. struct res_cq *cq;
  2425. int err;
  2426. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2427. if (err)
  2428. return err;
  2429. if (cq->com.from_state != RES_CQ_HW)
  2430. goto ex_put;
  2431. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2432. ex_put:
  2433. put_res(dev, slave, cqn, RES_CQ);
  2434. return err;
  2435. }
  2436. static int handle_resize(struct mlx4_dev *dev, int slave,
  2437. struct mlx4_vhcr *vhcr,
  2438. struct mlx4_cmd_mailbox *inbox,
  2439. struct mlx4_cmd_mailbox *outbox,
  2440. struct mlx4_cmd_info *cmd,
  2441. struct res_cq *cq)
  2442. {
  2443. int err;
  2444. struct res_mtt *orig_mtt;
  2445. struct res_mtt *mtt;
  2446. struct mlx4_cq_context *cqc = inbox->buf;
  2447. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2448. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2449. if (err)
  2450. return err;
  2451. if (orig_mtt != cq->mtt) {
  2452. err = -EINVAL;
  2453. goto ex_put;
  2454. }
  2455. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2456. if (err)
  2457. goto ex_put;
  2458. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2459. if (err)
  2460. goto ex_put1;
  2461. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2462. if (err)
  2463. goto ex_put1;
  2464. atomic_dec(&orig_mtt->ref_count);
  2465. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2466. atomic_inc(&mtt->ref_count);
  2467. cq->mtt = mtt;
  2468. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2469. return 0;
  2470. ex_put1:
  2471. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2472. ex_put:
  2473. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2474. return err;
  2475. }
  2476. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2477. struct mlx4_vhcr *vhcr,
  2478. struct mlx4_cmd_mailbox *inbox,
  2479. struct mlx4_cmd_mailbox *outbox,
  2480. struct mlx4_cmd_info *cmd)
  2481. {
  2482. int cqn = vhcr->in_modifier;
  2483. struct res_cq *cq;
  2484. int err;
  2485. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2486. if (err)
  2487. return err;
  2488. if (cq->com.from_state != RES_CQ_HW)
  2489. goto ex_put;
  2490. if (vhcr->op_modifier == 0) {
  2491. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2492. goto ex_put;
  2493. }
  2494. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2495. ex_put:
  2496. put_res(dev, slave, cqn, RES_CQ);
  2497. return err;
  2498. }
  2499. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2500. {
  2501. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2502. int log_rq_stride = srqc->logstride & 7;
  2503. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2504. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2505. return 1;
  2506. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2507. }
  2508. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2509. struct mlx4_vhcr *vhcr,
  2510. struct mlx4_cmd_mailbox *inbox,
  2511. struct mlx4_cmd_mailbox *outbox,
  2512. struct mlx4_cmd_info *cmd)
  2513. {
  2514. int err;
  2515. int srqn = vhcr->in_modifier;
  2516. struct res_mtt *mtt;
  2517. struct res_srq *srq;
  2518. struct mlx4_srq_context *srqc = inbox->buf;
  2519. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2520. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2521. return -EINVAL;
  2522. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2523. if (err)
  2524. return err;
  2525. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2526. if (err)
  2527. goto ex_abort;
  2528. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2529. mtt);
  2530. if (err)
  2531. goto ex_put_mtt;
  2532. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2533. if (err)
  2534. goto ex_put_mtt;
  2535. atomic_inc(&mtt->ref_count);
  2536. srq->mtt = mtt;
  2537. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2538. res_end_move(dev, slave, RES_SRQ, srqn);
  2539. return 0;
  2540. ex_put_mtt:
  2541. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2542. ex_abort:
  2543. res_abort_move(dev, slave, RES_SRQ, srqn);
  2544. return err;
  2545. }
  2546. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2547. struct mlx4_vhcr *vhcr,
  2548. struct mlx4_cmd_mailbox *inbox,
  2549. struct mlx4_cmd_mailbox *outbox,
  2550. struct mlx4_cmd_info *cmd)
  2551. {
  2552. int err;
  2553. int srqn = vhcr->in_modifier;
  2554. struct res_srq *srq;
  2555. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2556. if (err)
  2557. return err;
  2558. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2559. if (err)
  2560. goto ex_abort;
  2561. atomic_dec(&srq->mtt->ref_count);
  2562. if (srq->cq)
  2563. atomic_dec(&srq->cq->ref_count);
  2564. res_end_move(dev, slave, RES_SRQ, srqn);
  2565. return 0;
  2566. ex_abort:
  2567. res_abort_move(dev, slave, RES_SRQ, srqn);
  2568. return err;
  2569. }
  2570. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2571. struct mlx4_vhcr *vhcr,
  2572. struct mlx4_cmd_mailbox *inbox,
  2573. struct mlx4_cmd_mailbox *outbox,
  2574. struct mlx4_cmd_info *cmd)
  2575. {
  2576. int err;
  2577. int srqn = vhcr->in_modifier;
  2578. struct res_srq *srq;
  2579. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2580. if (err)
  2581. return err;
  2582. if (srq->com.from_state != RES_SRQ_HW) {
  2583. err = -EBUSY;
  2584. goto out;
  2585. }
  2586. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2587. out:
  2588. put_res(dev, slave, srqn, RES_SRQ);
  2589. return err;
  2590. }
  2591. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2592. struct mlx4_vhcr *vhcr,
  2593. struct mlx4_cmd_mailbox *inbox,
  2594. struct mlx4_cmd_mailbox *outbox,
  2595. struct mlx4_cmd_info *cmd)
  2596. {
  2597. int err;
  2598. int srqn = vhcr->in_modifier;
  2599. struct res_srq *srq;
  2600. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2601. if (err)
  2602. return err;
  2603. if (srq->com.from_state != RES_SRQ_HW) {
  2604. err = -EBUSY;
  2605. goto out;
  2606. }
  2607. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2608. out:
  2609. put_res(dev, slave, srqn, RES_SRQ);
  2610. return err;
  2611. }
  2612. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2613. struct mlx4_vhcr *vhcr,
  2614. struct mlx4_cmd_mailbox *inbox,
  2615. struct mlx4_cmd_mailbox *outbox,
  2616. struct mlx4_cmd_info *cmd)
  2617. {
  2618. int err;
  2619. int qpn = vhcr->in_modifier & 0x7fffff;
  2620. struct res_qp *qp;
  2621. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2622. if (err)
  2623. return err;
  2624. if (qp->com.from_state != RES_QP_HW) {
  2625. err = -EBUSY;
  2626. goto out;
  2627. }
  2628. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2629. out:
  2630. put_res(dev, slave, qpn, RES_QP);
  2631. return err;
  2632. }
  2633. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2634. struct mlx4_vhcr *vhcr,
  2635. struct mlx4_cmd_mailbox *inbox,
  2636. struct mlx4_cmd_mailbox *outbox,
  2637. struct mlx4_cmd_info *cmd)
  2638. {
  2639. struct mlx4_qp_context *context = inbox->buf + 8;
  2640. adjust_proxy_tun_qkey(dev, vhcr, context);
  2641. update_pkey_index(dev, slave, inbox);
  2642. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2643. }
  2644. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2645. struct mlx4_vhcr *vhcr,
  2646. struct mlx4_cmd_mailbox *inbox,
  2647. struct mlx4_cmd_mailbox *outbox,
  2648. struct mlx4_cmd_info *cmd)
  2649. {
  2650. int err;
  2651. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2652. int qpn = vhcr->in_modifier & 0x7fffff;
  2653. struct res_qp *qp;
  2654. u8 orig_sched_queue;
  2655. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2656. if (err)
  2657. return err;
  2658. update_pkey_index(dev, slave, inbox);
  2659. update_gid(dev, inbox, (u8)slave);
  2660. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2661. orig_sched_queue = qpc->pri_path.sched_queue;
  2662. err = update_vport_qp_param(dev, inbox, slave, qpn);
  2663. if (err)
  2664. return err;
  2665. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2666. if (err)
  2667. return err;
  2668. if (qp->com.from_state != RES_QP_HW) {
  2669. err = -EBUSY;
  2670. goto out;
  2671. }
  2672. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2673. out:
  2674. /* if no error, save sched queue value passed in by VF. This is
  2675. * essentially the QOS value provided by the VF. This will be useful
  2676. * if we allow dynamic changes from VST back to VGT
  2677. */
  2678. if (!err)
  2679. qp->sched_queue = orig_sched_queue;
  2680. put_res(dev, slave, qpn, RES_QP);
  2681. return err;
  2682. }
  2683. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2684. struct mlx4_vhcr *vhcr,
  2685. struct mlx4_cmd_mailbox *inbox,
  2686. struct mlx4_cmd_mailbox *outbox,
  2687. struct mlx4_cmd_info *cmd)
  2688. {
  2689. int err;
  2690. struct mlx4_qp_context *context = inbox->buf + 8;
  2691. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2692. if (err)
  2693. return err;
  2694. update_pkey_index(dev, slave, inbox);
  2695. update_gid(dev, inbox, (u8)slave);
  2696. adjust_proxy_tun_qkey(dev, vhcr, context);
  2697. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2698. }
  2699. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2700. struct mlx4_vhcr *vhcr,
  2701. struct mlx4_cmd_mailbox *inbox,
  2702. struct mlx4_cmd_mailbox *outbox,
  2703. struct mlx4_cmd_info *cmd)
  2704. {
  2705. int err;
  2706. struct mlx4_qp_context *context = inbox->buf + 8;
  2707. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2708. if (err)
  2709. return err;
  2710. update_pkey_index(dev, slave, inbox);
  2711. update_gid(dev, inbox, (u8)slave);
  2712. adjust_proxy_tun_qkey(dev, vhcr, context);
  2713. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2714. }
  2715. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2716. struct mlx4_vhcr *vhcr,
  2717. struct mlx4_cmd_mailbox *inbox,
  2718. struct mlx4_cmd_mailbox *outbox,
  2719. struct mlx4_cmd_info *cmd)
  2720. {
  2721. struct mlx4_qp_context *context = inbox->buf + 8;
  2722. adjust_proxy_tun_qkey(dev, vhcr, context);
  2723. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2724. }
  2725. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2726. struct mlx4_vhcr *vhcr,
  2727. struct mlx4_cmd_mailbox *inbox,
  2728. struct mlx4_cmd_mailbox *outbox,
  2729. struct mlx4_cmd_info *cmd)
  2730. {
  2731. int err;
  2732. struct mlx4_qp_context *context = inbox->buf + 8;
  2733. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2734. if (err)
  2735. return err;
  2736. adjust_proxy_tun_qkey(dev, vhcr, context);
  2737. update_gid(dev, inbox, (u8)slave);
  2738. update_pkey_index(dev, slave, inbox);
  2739. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2740. }
  2741. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2742. struct mlx4_vhcr *vhcr,
  2743. struct mlx4_cmd_mailbox *inbox,
  2744. struct mlx4_cmd_mailbox *outbox,
  2745. struct mlx4_cmd_info *cmd)
  2746. {
  2747. int err;
  2748. struct mlx4_qp_context *context = inbox->buf + 8;
  2749. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2750. if (err)
  2751. return err;
  2752. adjust_proxy_tun_qkey(dev, vhcr, context);
  2753. update_gid(dev, inbox, (u8)slave);
  2754. update_pkey_index(dev, slave, inbox);
  2755. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2756. }
  2757. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2758. struct mlx4_vhcr *vhcr,
  2759. struct mlx4_cmd_mailbox *inbox,
  2760. struct mlx4_cmd_mailbox *outbox,
  2761. struct mlx4_cmd_info *cmd)
  2762. {
  2763. int err;
  2764. int qpn = vhcr->in_modifier & 0x7fffff;
  2765. struct res_qp *qp;
  2766. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2767. if (err)
  2768. return err;
  2769. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2770. if (err)
  2771. goto ex_abort;
  2772. atomic_dec(&qp->mtt->ref_count);
  2773. atomic_dec(&qp->rcq->ref_count);
  2774. atomic_dec(&qp->scq->ref_count);
  2775. if (qp->srq)
  2776. atomic_dec(&qp->srq->ref_count);
  2777. res_end_move(dev, slave, RES_QP, qpn);
  2778. return 0;
  2779. ex_abort:
  2780. res_abort_move(dev, slave, RES_QP, qpn);
  2781. return err;
  2782. }
  2783. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2784. struct res_qp *rqp, u8 *gid)
  2785. {
  2786. struct res_gid *res;
  2787. list_for_each_entry(res, &rqp->mcg_list, list) {
  2788. if (!memcmp(res->gid, gid, 16))
  2789. return res;
  2790. }
  2791. return NULL;
  2792. }
  2793. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2794. u8 *gid, enum mlx4_protocol prot,
  2795. enum mlx4_steer_type steer, u64 reg_id)
  2796. {
  2797. struct res_gid *res;
  2798. int err;
  2799. res = kzalloc(sizeof *res, GFP_KERNEL);
  2800. if (!res)
  2801. return -ENOMEM;
  2802. spin_lock_irq(&rqp->mcg_spl);
  2803. if (find_gid(dev, slave, rqp, gid)) {
  2804. kfree(res);
  2805. err = -EEXIST;
  2806. } else {
  2807. memcpy(res->gid, gid, 16);
  2808. res->prot = prot;
  2809. res->steer = steer;
  2810. res->reg_id = reg_id;
  2811. list_add_tail(&res->list, &rqp->mcg_list);
  2812. err = 0;
  2813. }
  2814. spin_unlock_irq(&rqp->mcg_spl);
  2815. return err;
  2816. }
  2817. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2818. u8 *gid, enum mlx4_protocol prot,
  2819. enum mlx4_steer_type steer, u64 *reg_id)
  2820. {
  2821. struct res_gid *res;
  2822. int err;
  2823. spin_lock_irq(&rqp->mcg_spl);
  2824. res = find_gid(dev, slave, rqp, gid);
  2825. if (!res || res->prot != prot || res->steer != steer)
  2826. err = -EINVAL;
  2827. else {
  2828. *reg_id = res->reg_id;
  2829. list_del(&res->list);
  2830. kfree(res);
  2831. err = 0;
  2832. }
  2833. spin_unlock_irq(&rqp->mcg_spl);
  2834. return err;
  2835. }
  2836. static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2837. int block_loopback, enum mlx4_protocol prot,
  2838. enum mlx4_steer_type type, u64 *reg_id)
  2839. {
  2840. switch (dev->caps.steering_mode) {
  2841. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2842. return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
  2843. block_loopback, prot,
  2844. reg_id);
  2845. case MLX4_STEERING_MODE_B0:
  2846. return mlx4_qp_attach_common(dev, qp, gid,
  2847. block_loopback, prot, type);
  2848. default:
  2849. return -EINVAL;
  2850. }
  2851. }
  2852. static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2853. enum mlx4_protocol prot, enum mlx4_steer_type type,
  2854. u64 reg_id)
  2855. {
  2856. switch (dev->caps.steering_mode) {
  2857. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2858. return mlx4_flow_detach(dev, reg_id);
  2859. case MLX4_STEERING_MODE_B0:
  2860. return mlx4_qp_detach_common(dev, qp, gid, prot, type);
  2861. default:
  2862. return -EINVAL;
  2863. }
  2864. }
  2865. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2866. struct mlx4_vhcr *vhcr,
  2867. struct mlx4_cmd_mailbox *inbox,
  2868. struct mlx4_cmd_mailbox *outbox,
  2869. struct mlx4_cmd_info *cmd)
  2870. {
  2871. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2872. u8 *gid = inbox->buf;
  2873. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2874. int err;
  2875. int qpn;
  2876. struct res_qp *rqp;
  2877. u64 reg_id = 0;
  2878. int attach = vhcr->op_modifier;
  2879. int block_loopback = vhcr->in_modifier >> 31;
  2880. u8 steer_type_mask = 2;
  2881. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2882. qpn = vhcr->in_modifier & 0xffffff;
  2883. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2884. if (err)
  2885. return err;
  2886. qp.qpn = qpn;
  2887. if (attach) {
  2888. err = qp_attach(dev, &qp, gid, block_loopback, prot,
  2889. type, &reg_id);
  2890. if (err) {
  2891. pr_err("Fail to attach rule to qp 0x%x\n", qpn);
  2892. goto ex_put;
  2893. }
  2894. err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
  2895. if (err)
  2896. goto ex_detach;
  2897. } else {
  2898. err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
  2899. if (err)
  2900. goto ex_put;
  2901. err = qp_detach(dev, &qp, gid, prot, type, reg_id);
  2902. if (err)
  2903. pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
  2904. qpn, reg_id);
  2905. }
  2906. put_res(dev, slave, qpn, RES_QP);
  2907. return err;
  2908. ex_detach:
  2909. qp_detach(dev, &qp, gid, prot, type, reg_id);
  2910. ex_put:
  2911. put_res(dev, slave, qpn, RES_QP);
  2912. return err;
  2913. }
  2914. /*
  2915. * MAC validation for Flow Steering rules.
  2916. * VF can attach rules only with a mac address which is assigned to it.
  2917. */
  2918. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  2919. struct list_head *rlist)
  2920. {
  2921. struct mac_res *res, *tmp;
  2922. __be64 be_mac;
  2923. /* make sure it isn't multicast or broadcast mac*/
  2924. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  2925. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  2926. list_for_each_entry_safe(res, tmp, rlist, list) {
  2927. be_mac = cpu_to_be64(res->mac << 16);
  2928. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  2929. return 0;
  2930. }
  2931. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  2932. eth_header->eth.dst_mac, slave);
  2933. return -EINVAL;
  2934. }
  2935. return 0;
  2936. }
  2937. /*
  2938. * In case of missing eth header, append eth header with a MAC address
  2939. * assigned to the VF.
  2940. */
  2941. static int add_eth_header(struct mlx4_dev *dev, int slave,
  2942. struct mlx4_cmd_mailbox *inbox,
  2943. struct list_head *rlist, int header_id)
  2944. {
  2945. struct mac_res *res, *tmp;
  2946. u8 port;
  2947. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2948. struct mlx4_net_trans_rule_hw_eth *eth_header;
  2949. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  2950. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  2951. __be64 be_mac = 0;
  2952. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  2953. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2954. port = ctrl->port;
  2955. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  2956. /* Clear a space in the inbox for eth header */
  2957. switch (header_id) {
  2958. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2959. ip_header =
  2960. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  2961. memmove(ip_header, eth_header,
  2962. sizeof(*ip_header) + sizeof(*l4_header));
  2963. break;
  2964. case MLX4_NET_TRANS_RULE_ID_TCP:
  2965. case MLX4_NET_TRANS_RULE_ID_UDP:
  2966. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  2967. (eth_header + 1);
  2968. memmove(l4_header, eth_header, sizeof(*l4_header));
  2969. break;
  2970. default:
  2971. return -EINVAL;
  2972. }
  2973. list_for_each_entry_safe(res, tmp, rlist, list) {
  2974. if (port == res->port) {
  2975. be_mac = cpu_to_be64(res->mac << 16);
  2976. break;
  2977. }
  2978. }
  2979. if (!be_mac) {
  2980. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  2981. port);
  2982. return -EINVAL;
  2983. }
  2984. memset(eth_header, 0, sizeof(*eth_header));
  2985. eth_header->size = sizeof(*eth_header) >> 2;
  2986. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  2987. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  2988. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  2989. return 0;
  2990. }
  2991. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2992. struct mlx4_vhcr *vhcr,
  2993. struct mlx4_cmd_mailbox *inbox,
  2994. struct mlx4_cmd_mailbox *outbox,
  2995. struct mlx4_cmd_info *cmd)
  2996. {
  2997. struct mlx4_priv *priv = mlx4_priv(dev);
  2998. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2999. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  3000. int err;
  3001. int qpn;
  3002. struct res_qp *rqp;
  3003. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3004. struct _rule_hw *rule_header;
  3005. int header_id;
  3006. if (dev->caps.steering_mode !=
  3007. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3008. return -EOPNOTSUPP;
  3009. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3010. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  3011. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3012. if (err) {
  3013. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  3014. return err;
  3015. }
  3016. rule_header = (struct _rule_hw *)(ctrl + 1);
  3017. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  3018. switch (header_id) {
  3019. case MLX4_NET_TRANS_RULE_ID_ETH:
  3020. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  3021. err = -EINVAL;
  3022. goto err_put;
  3023. }
  3024. break;
  3025. case MLX4_NET_TRANS_RULE_ID_IB:
  3026. break;
  3027. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3028. case MLX4_NET_TRANS_RULE_ID_TCP:
  3029. case MLX4_NET_TRANS_RULE_ID_UDP:
  3030. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  3031. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  3032. err = -EINVAL;
  3033. goto err_put;
  3034. }
  3035. vhcr->in_modifier +=
  3036. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  3037. break;
  3038. default:
  3039. pr_err("Corrupted mailbox.\n");
  3040. err = -EINVAL;
  3041. goto err_put;
  3042. }
  3043. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  3044. vhcr->in_modifier, 0,
  3045. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  3046. MLX4_CMD_NATIVE);
  3047. if (err)
  3048. goto err_put;
  3049. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  3050. if (err) {
  3051. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  3052. /* detach rule*/
  3053. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  3054. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3055. MLX4_CMD_NATIVE);
  3056. goto err_put;
  3057. }
  3058. atomic_inc(&rqp->ref_count);
  3059. err_put:
  3060. put_res(dev, slave, qpn, RES_QP);
  3061. return err;
  3062. }
  3063. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  3064. struct mlx4_vhcr *vhcr,
  3065. struct mlx4_cmd_mailbox *inbox,
  3066. struct mlx4_cmd_mailbox *outbox,
  3067. struct mlx4_cmd_info *cmd)
  3068. {
  3069. int err;
  3070. struct res_qp *rqp;
  3071. struct res_fs_rule *rrule;
  3072. if (dev->caps.steering_mode !=
  3073. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3074. return -EOPNOTSUPP;
  3075. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  3076. if (err)
  3077. return err;
  3078. /* Release the rule form busy state before removal */
  3079. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  3080. err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
  3081. if (err)
  3082. return err;
  3083. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  3084. if (err) {
  3085. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  3086. goto out;
  3087. }
  3088. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  3089. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3090. MLX4_CMD_NATIVE);
  3091. if (!err)
  3092. atomic_dec(&rqp->ref_count);
  3093. out:
  3094. put_res(dev, slave, rrule->qpn, RES_QP);
  3095. return err;
  3096. }
  3097. enum {
  3098. BUSY_MAX_RETRIES = 10
  3099. };
  3100. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  3101. struct mlx4_vhcr *vhcr,
  3102. struct mlx4_cmd_mailbox *inbox,
  3103. struct mlx4_cmd_mailbox *outbox,
  3104. struct mlx4_cmd_info *cmd)
  3105. {
  3106. int err;
  3107. int index = vhcr->in_modifier & 0xffff;
  3108. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  3109. if (err)
  3110. return err;
  3111. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3112. put_res(dev, slave, index, RES_COUNTER);
  3113. return err;
  3114. }
  3115. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  3116. {
  3117. struct res_gid *rgid;
  3118. struct res_gid *tmp;
  3119. struct mlx4_qp qp; /* dummy for calling attach/detach */
  3120. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  3121. switch (dev->caps.steering_mode) {
  3122. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  3123. mlx4_flow_detach(dev, rgid->reg_id);
  3124. break;
  3125. case MLX4_STEERING_MODE_B0:
  3126. qp.qpn = rqp->local_qpn;
  3127. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
  3128. rgid->prot, rgid->steer);
  3129. break;
  3130. }
  3131. list_del(&rgid->list);
  3132. kfree(rgid);
  3133. }
  3134. }
  3135. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  3136. enum mlx4_resource type, int print)
  3137. {
  3138. struct mlx4_priv *priv = mlx4_priv(dev);
  3139. struct mlx4_resource_tracker *tracker =
  3140. &priv->mfunc.master.res_tracker;
  3141. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  3142. struct res_common *r;
  3143. struct res_common *tmp;
  3144. int busy;
  3145. busy = 0;
  3146. spin_lock_irq(mlx4_tlock(dev));
  3147. list_for_each_entry_safe(r, tmp, rlist, list) {
  3148. if (r->owner == slave) {
  3149. if (!r->removing) {
  3150. if (r->state == RES_ANY_BUSY) {
  3151. if (print)
  3152. mlx4_dbg(dev,
  3153. "%s id 0x%llx is busy\n",
  3154. ResourceType(type),
  3155. r->res_id);
  3156. ++busy;
  3157. } else {
  3158. r->from_state = r->state;
  3159. r->state = RES_ANY_BUSY;
  3160. r->removing = 1;
  3161. }
  3162. }
  3163. }
  3164. }
  3165. spin_unlock_irq(mlx4_tlock(dev));
  3166. return busy;
  3167. }
  3168. static int move_all_busy(struct mlx4_dev *dev, int slave,
  3169. enum mlx4_resource type)
  3170. {
  3171. unsigned long begin;
  3172. int busy;
  3173. begin = jiffies;
  3174. do {
  3175. busy = _move_all_busy(dev, slave, type, 0);
  3176. if (time_after(jiffies, begin + 5 * HZ))
  3177. break;
  3178. if (busy)
  3179. cond_resched();
  3180. } while (busy);
  3181. if (busy)
  3182. busy = _move_all_busy(dev, slave, type, 1);
  3183. return busy;
  3184. }
  3185. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  3186. {
  3187. struct mlx4_priv *priv = mlx4_priv(dev);
  3188. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3189. struct list_head *qp_list =
  3190. &tracker->slave_list[slave].res_list[RES_QP];
  3191. struct res_qp *qp;
  3192. struct res_qp *tmp;
  3193. int state;
  3194. u64 in_param;
  3195. int qpn;
  3196. int err;
  3197. err = move_all_busy(dev, slave, RES_QP);
  3198. if (err)
  3199. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  3200. "for slave %d\n", slave);
  3201. spin_lock_irq(mlx4_tlock(dev));
  3202. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3203. spin_unlock_irq(mlx4_tlock(dev));
  3204. if (qp->com.owner == slave) {
  3205. qpn = qp->com.res_id;
  3206. detach_qp(dev, slave, qp);
  3207. state = qp->com.from_state;
  3208. while (state != 0) {
  3209. switch (state) {
  3210. case RES_QP_RESERVED:
  3211. spin_lock_irq(mlx4_tlock(dev));
  3212. rb_erase(&qp->com.node,
  3213. &tracker->res_tree[RES_QP]);
  3214. list_del(&qp->com.list);
  3215. spin_unlock_irq(mlx4_tlock(dev));
  3216. kfree(qp);
  3217. state = 0;
  3218. break;
  3219. case RES_QP_MAPPED:
  3220. if (!valid_reserved(dev, slave, qpn))
  3221. __mlx4_qp_free_icm(dev, qpn);
  3222. state = RES_QP_RESERVED;
  3223. break;
  3224. case RES_QP_HW:
  3225. in_param = slave;
  3226. err = mlx4_cmd(dev, in_param,
  3227. qp->local_qpn, 2,
  3228. MLX4_CMD_2RST_QP,
  3229. MLX4_CMD_TIME_CLASS_A,
  3230. MLX4_CMD_NATIVE);
  3231. if (err)
  3232. mlx4_dbg(dev, "rem_slave_qps: failed"
  3233. " to move slave %d qpn %d to"
  3234. " reset\n", slave,
  3235. qp->local_qpn);
  3236. atomic_dec(&qp->rcq->ref_count);
  3237. atomic_dec(&qp->scq->ref_count);
  3238. atomic_dec(&qp->mtt->ref_count);
  3239. if (qp->srq)
  3240. atomic_dec(&qp->srq->ref_count);
  3241. state = RES_QP_MAPPED;
  3242. break;
  3243. default:
  3244. state = 0;
  3245. }
  3246. }
  3247. }
  3248. spin_lock_irq(mlx4_tlock(dev));
  3249. }
  3250. spin_unlock_irq(mlx4_tlock(dev));
  3251. }
  3252. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  3253. {
  3254. struct mlx4_priv *priv = mlx4_priv(dev);
  3255. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3256. struct list_head *srq_list =
  3257. &tracker->slave_list[slave].res_list[RES_SRQ];
  3258. struct res_srq *srq;
  3259. struct res_srq *tmp;
  3260. int state;
  3261. u64 in_param;
  3262. LIST_HEAD(tlist);
  3263. int srqn;
  3264. int err;
  3265. err = move_all_busy(dev, slave, RES_SRQ);
  3266. if (err)
  3267. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  3268. "busy for slave %d\n", slave);
  3269. spin_lock_irq(mlx4_tlock(dev));
  3270. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  3271. spin_unlock_irq(mlx4_tlock(dev));
  3272. if (srq->com.owner == slave) {
  3273. srqn = srq->com.res_id;
  3274. state = srq->com.from_state;
  3275. while (state != 0) {
  3276. switch (state) {
  3277. case RES_SRQ_ALLOCATED:
  3278. __mlx4_srq_free_icm(dev, srqn);
  3279. spin_lock_irq(mlx4_tlock(dev));
  3280. rb_erase(&srq->com.node,
  3281. &tracker->res_tree[RES_SRQ]);
  3282. list_del(&srq->com.list);
  3283. spin_unlock_irq(mlx4_tlock(dev));
  3284. kfree(srq);
  3285. state = 0;
  3286. break;
  3287. case RES_SRQ_HW:
  3288. in_param = slave;
  3289. err = mlx4_cmd(dev, in_param, srqn, 1,
  3290. MLX4_CMD_HW2SW_SRQ,
  3291. MLX4_CMD_TIME_CLASS_A,
  3292. MLX4_CMD_NATIVE);
  3293. if (err)
  3294. mlx4_dbg(dev, "rem_slave_srqs: failed"
  3295. " to move slave %d srq %d to"
  3296. " SW ownership\n",
  3297. slave, srqn);
  3298. atomic_dec(&srq->mtt->ref_count);
  3299. if (srq->cq)
  3300. atomic_dec(&srq->cq->ref_count);
  3301. state = RES_SRQ_ALLOCATED;
  3302. break;
  3303. default:
  3304. state = 0;
  3305. }
  3306. }
  3307. }
  3308. spin_lock_irq(mlx4_tlock(dev));
  3309. }
  3310. spin_unlock_irq(mlx4_tlock(dev));
  3311. }
  3312. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  3313. {
  3314. struct mlx4_priv *priv = mlx4_priv(dev);
  3315. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3316. struct list_head *cq_list =
  3317. &tracker->slave_list[slave].res_list[RES_CQ];
  3318. struct res_cq *cq;
  3319. struct res_cq *tmp;
  3320. int state;
  3321. u64 in_param;
  3322. LIST_HEAD(tlist);
  3323. int cqn;
  3324. int err;
  3325. err = move_all_busy(dev, slave, RES_CQ);
  3326. if (err)
  3327. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  3328. "busy for slave %d\n", slave);
  3329. spin_lock_irq(mlx4_tlock(dev));
  3330. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  3331. spin_unlock_irq(mlx4_tlock(dev));
  3332. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  3333. cqn = cq->com.res_id;
  3334. state = cq->com.from_state;
  3335. while (state != 0) {
  3336. switch (state) {
  3337. case RES_CQ_ALLOCATED:
  3338. __mlx4_cq_free_icm(dev, cqn);
  3339. spin_lock_irq(mlx4_tlock(dev));
  3340. rb_erase(&cq->com.node,
  3341. &tracker->res_tree[RES_CQ]);
  3342. list_del(&cq->com.list);
  3343. spin_unlock_irq(mlx4_tlock(dev));
  3344. kfree(cq);
  3345. state = 0;
  3346. break;
  3347. case RES_CQ_HW:
  3348. in_param = slave;
  3349. err = mlx4_cmd(dev, in_param, cqn, 1,
  3350. MLX4_CMD_HW2SW_CQ,
  3351. MLX4_CMD_TIME_CLASS_A,
  3352. MLX4_CMD_NATIVE);
  3353. if (err)
  3354. mlx4_dbg(dev, "rem_slave_cqs: failed"
  3355. " to move slave %d cq %d to"
  3356. " SW ownership\n",
  3357. slave, cqn);
  3358. atomic_dec(&cq->mtt->ref_count);
  3359. state = RES_CQ_ALLOCATED;
  3360. break;
  3361. default:
  3362. state = 0;
  3363. }
  3364. }
  3365. }
  3366. spin_lock_irq(mlx4_tlock(dev));
  3367. }
  3368. spin_unlock_irq(mlx4_tlock(dev));
  3369. }
  3370. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  3371. {
  3372. struct mlx4_priv *priv = mlx4_priv(dev);
  3373. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3374. struct list_head *mpt_list =
  3375. &tracker->slave_list[slave].res_list[RES_MPT];
  3376. struct res_mpt *mpt;
  3377. struct res_mpt *tmp;
  3378. int state;
  3379. u64 in_param;
  3380. LIST_HEAD(tlist);
  3381. int mptn;
  3382. int err;
  3383. err = move_all_busy(dev, slave, RES_MPT);
  3384. if (err)
  3385. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  3386. "busy for slave %d\n", slave);
  3387. spin_lock_irq(mlx4_tlock(dev));
  3388. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  3389. spin_unlock_irq(mlx4_tlock(dev));
  3390. if (mpt->com.owner == slave) {
  3391. mptn = mpt->com.res_id;
  3392. state = mpt->com.from_state;
  3393. while (state != 0) {
  3394. switch (state) {
  3395. case RES_MPT_RESERVED:
  3396. __mlx4_mpt_release(dev, mpt->key);
  3397. spin_lock_irq(mlx4_tlock(dev));
  3398. rb_erase(&mpt->com.node,
  3399. &tracker->res_tree[RES_MPT]);
  3400. list_del(&mpt->com.list);
  3401. spin_unlock_irq(mlx4_tlock(dev));
  3402. kfree(mpt);
  3403. state = 0;
  3404. break;
  3405. case RES_MPT_MAPPED:
  3406. __mlx4_mpt_free_icm(dev, mpt->key);
  3407. state = RES_MPT_RESERVED;
  3408. break;
  3409. case RES_MPT_HW:
  3410. in_param = slave;
  3411. err = mlx4_cmd(dev, in_param, mptn, 0,
  3412. MLX4_CMD_HW2SW_MPT,
  3413. MLX4_CMD_TIME_CLASS_A,
  3414. MLX4_CMD_NATIVE);
  3415. if (err)
  3416. mlx4_dbg(dev, "rem_slave_mrs: failed"
  3417. " to move slave %d mpt %d to"
  3418. " SW ownership\n",
  3419. slave, mptn);
  3420. if (mpt->mtt)
  3421. atomic_dec(&mpt->mtt->ref_count);
  3422. state = RES_MPT_MAPPED;
  3423. break;
  3424. default:
  3425. state = 0;
  3426. }
  3427. }
  3428. }
  3429. spin_lock_irq(mlx4_tlock(dev));
  3430. }
  3431. spin_unlock_irq(mlx4_tlock(dev));
  3432. }
  3433. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  3434. {
  3435. struct mlx4_priv *priv = mlx4_priv(dev);
  3436. struct mlx4_resource_tracker *tracker =
  3437. &priv->mfunc.master.res_tracker;
  3438. struct list_head *mtt_list =
  3439. &tracker->slave_list[slave].res_list[RES_MTT];
  3440. struct res_mtt *mtt;
  3441. struct res_mtt *tmp;
  3442. int state;
  3443. LIST_HEAD(tlist);
  3444. int base;
  3445. int err;
  3446. err = move_all_busy(dev, slave, RES_MTT);
  3447. if (err)
  3448. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  3449. "busy for slave %d\n", slave);
  3450. spin_lock_irq(mlx4_tlock(dev));
  3451. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  3452. spin_unlock_irq(mlx4_tlock(dev));
  3453. if (mtt->com.owner == slave) {
  3454. base = mtt->com.res_id;
  3455. state = mtt->com.from_state;
  3456. while (state != 0) {
  3457. switch (state) {
  3458. case RES_MTT_ALLOCATED:
  3459. __mlx4_free_mtt_range(dev, base,
  3460. mtt->order);
  3461. spin_lock_irq(mlx4_tlock(dev));
  3462. rb_erase(&mtt->com.node,
  3463. &tracker->res_tree[RES_MTT]);
  3464. list_del(&mtt->com.list);
  3465. spin_unlock_irq(mlx4_tlock(dev));
  3466. kfree(mtt);
  3467. state = 0;
  3468. break;
  3469. default:
  3470. state = 0;
  3471. }
  3472. }
  3473. }
  3474. spin_lock_irq(mlx4_tlock(dev));
  3475. }
  3476. spin_unlock_irq(mlx4_tlock(dev));
  3477. }
  3478. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3479. {
  3480. struct mlx4_priv *priv = mlx4_priv(dev);
  3481. struct mlx4_resource_tracker *tracker =
  3482. &priv->mfunc.master.res_tracker;
  3483. struct list_head *fs_rule_list =
  3484. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3485. struct res_fs_rule *fs_rule;
  3486. struct res_fs_rule *tmp;
  3487. int state;
  3488. u64 base;
  3489. int err;
  3490. err = move_all_busy(dev, slave, RES_FS_RULE);
  3491. if (err)
  3492. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3493. slave);
  3494. spin_lock_irq(mlx4_tlock(dev));
  3495. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3496. spin_unlock_irq(mlx4_tlock(dev));
  3497. if (fs_rule->com.owner == slave) {
  3498. base = fs_rule->com.res_id;
  3499. state = fs_rule->com.from_state;
  3500. while (state != 0) {
  3501. switch (state) {
  3502. case RES_FS_RULE_ALLOCATED:
  3503. /* detach rule */
  3504. err = mlx4_cmd(dev, base, 0, 0,
  3505. MLX4_QP_FLOW_STEERING_DETACH,
  3506. MLX4_CMD_TIME_CLASS_A,
  3507. MLX4_CMD_NATIVE);
  3508. spin_lock_irq(mlx4_tlock(dev));
  3509. rb_erase(&fs_rule->com.node,
  3510. &tracker->res_tree[RES_FS_RULE]);
  3511. list_del(&fs_rule->com.list);
  3512. spin_unlock_irq(mlx4_tlock(dev));
  3513. kfree(fs_rule);
  3514. state = 0;
  3515. break;
  3516. default:
  3517. state = 0;
  3518. }
  3519. }
  3520. }
  3521. spin_lock_irq(mlx4_tlock(dev));
  3522. }
  3523. spin_unlock_irq(mlx4_tlock(dev));
  3524. }
  3525. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3526. {
  3527. struct mlx4_priv *priv = mlx4_priv(dev);
  3528. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3529. struct list_head *eq_list =
  3530. &tracker->slave_list[slave].res_list[RES_EQ];
  3531. struct res_eq *eq;
  3532. struct res_eq *tmp;
  3533. int err;
  3534. int state;
  3535. LIST_HEAD(tlist);
  3536. int eqn;
  3537. struct mlx4_cmd_mailbox *mailbox;
  3538. err = move_all_busy(dev, slave, RES_EQ);
  3539. if (err)
  3540. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3541. "busy for slave %d\n", slave);
  3542. spin_lock_irq(mlx4_tlock(dev));
  3543. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3544. spin_unlock_irq(mlx4_tlock(dev));
  3545. if (eq->com.owner == slave) {
  3546. eqn = eq->com.res_id;
  3547. state = eq->com.from_state;
  3548. while (state != 0) {
  3549. switch (state) {
  3550. case RES_EQ_RESERVED:
  3551. spin_lock_irq(mlx4_tlock(dev));
  3552. rb_erase(&eq->com.node,
  3553. &tracker->res_tree[RES_EQ]);
  3554. list_del(&eq->com.list);
  3555. spin_unlock_irq(mlx4_tlock(dev));
  3556. kfree(eq);
  3557. state = 0;
  3558. break;
  3559. case RES_EQ_HW:
  3560. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3561. if (IS_ERR(mailbox)) {
  3562. cond_resched();
  3563. continue;
  3564. }
  3565. err = mlx4_cmd_box(dev, slave, 0,
  3566. eqn & 0xff, 0,
  3567. MLX4_CMD_HW2SW_EQ,
  3568. MLX4_CMD_TIME_CLASS_A,
  3569. MLX4_CMD_NATIVE);
  3570. if (err)
  3571. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3572. " to move slave %d eqs %d to"
  3573. " SW ownership\n", slave, eqn);
  3574. mlx4_free_cmd_mailbox(dev, mailbox);
  3575. atomic_dec(&eq->mtt->ref_count);
  3576. state = RES_EQ_RESERVED;
  3577. break;
  3578. default:
  3579. state = 0;
  3580. }
  3581. }
  3582. }
  3583. spin_lock_irq(mlx4_tlock(dev));
  3584. }
  3585. spin_unlock_irq(mlx4_tlock(dev));
  3586. }
  3587. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3588. {
  3589. struct mlx4_priv *priv = mlx4_priv(dev);
  3590. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3591. struct list_head *counter_list =
  3592. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3593. struct res_counter *counter;
  3594. struct res_counter *tmp;
  3595. int err;
  3596. int index;
  3597. err = move_all_busy(dev, slave, RES_COUNTER);
  3598. if (err)
  3599. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3600. "busy for slave %d\n", slave);
  3601. spin_lock_irq(mlx4_tlock(dev));
  3602. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3603. if (counter->com.owner == slave) {
  3604. index = counter->com.res_id;
  3605. rb_erase(&counter->com.node,
  3606. &tracker->res_tree[RES_COUNTER]);
  3607. list_del(&counter->com.list);
  3608. kfree(counter);
  3609. __mlx4_counter_free(dev, index);
  3610. }
  3611. }
  3612. spin_unlock_irq(mlx4_tlock(dev));
  3613. }
  3614. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3615. {
  3616. struct mlx4_priv *priv = mlx4_priv(dev);
  3617. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3618. struct list_head *xrcdn_list =
  3619. &tracker->slave_list[slave].res_list[RES_XRCD];
  3620. struct res_xrcdn *xrcd;
  3621. struct res_xrcdn *tmp;
  3622. int err;
  3623. int xrcdn;
  3624. err = move_all_busy(dev, slave, RES_XRCD);
  3625. if (err)
  3626. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3627. "busy for slave %d\n", slave);
  3628. spin_lock_irq(mlx4_tlock(dev));
  3629. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3630. if (xrcd->com.owner == slave) {
  3631. xrcdn = xrcd->com.res_id;
  3632. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3633. list_del(&xrcd->com.list);
  3634. kfree(xrcd);
  3635. __mlx4_xrcd_free(dev, xrcdn);
  3636. }
  3637. }
  3638. spin_unlock_irq(mlx4_tlock(dev));
  3639. }
  3640. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3641. {
  3642. struct mlx4_priv *priv = mlx4_priv(dev);
  3643. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3644. rem_slave_vlans(dev, slave);
  3645. rem_slave_macs(dev, slave);
  3646. rem_slave_fs_rule(dev, slave);
  3647. rem_slave_qps(dev, slave);
  3648. rem_slave_srqs(dev, slave);
  3649. rem_slave_cqs(dev, slave);
  3650. rem_slave_mrs(dev, slave);
  3651. rem_slave_eqs(dev, slave);
  3652. rem_slave_mtts(dev, slave);
  3653. rem_slave_counters(dev, slave);
  3654. rem_slave_xrcdns(dev, slave);
  3655. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3656. }
  3657. void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
  3658. {
  3659. struct mlx4_vf_immed_vlan_work *work =
  3660. container_of(_work, struct mlx4_vf_immed_vlan_work, work);
  3661. struct mlx4_cmd_mailbox *mailbox;
  3662. struct mlx4_update_qp_context *upd_context;
  3663. struct mlx4_dev *dev = &work->priv->dev;
  3664. struct mlx4_resource_tracker *tracker =
  3665. &work->priv->mfunc.master.res_tracker;
  3666. struct list_head *qp_list =
  3667. &tracker->slave_list[work->slave].res_list[RES_QP];
  3668. struct res_qp *qp;
  3669. struct res_qp *tmp;
  3670. u64 qp_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
  3671. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
  3672. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
  3673. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
  3674. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
  3675. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED) |
  3676. (1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
  3677. (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
  3678. int err;
  3679. int port, errors = 0;
  3680. u8 vlan_control;
  3681. if (mlx4_is_slave(dev)) {
  3682. mlx4_warn(dev, "Trying to update-qp in slave %d\n",
  3683. work->slave);
  3684. goto out;
  3685. }
  3686. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3687. if (IS_ERR(mailbox))
  3688. goto out;
  3689. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
  3690. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3691. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  3692. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  3693. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  3694. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  3695. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  3696. else if (!work->vlan_id)
  3697. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3698. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  3699. else
  3700. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3701. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  3702. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  3703. upd_context = mailbox->buf;
  3704. upd_context->primary_addr_path_mask = cpu_to_be64(qp_mask);
  3705. upd_context->qp_context.pri_path.vlan_control = vlan_control;
  3706. upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
  3707. spin_lock_irq(mlx4_tlock(dev));
  3708. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3709. spin_unlock_irq(mlx4_tlock(dev));
  3710. if (qp->com.owner == work->slave) {
  3711. if (qp->com.from_state != RES_QP_HW ||
  3712. !qp->sched_queue || /* no INIT2RTR trans yet */
  3713. mlx4_is_qp_reserved(dev, qp->local_qpn) ||
  3714. qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
  3715. spin_lock_irq(mlx4_tlock(dev));
  3716. continue;
  3717. }
  3718. port = (qp->sched_queue >> 6 & 1) + 1;
  3719. if (port != work->port) {
  3720. spin_lock_irq(mlx4_tlock(dev));
  3721. continue;
  3722. }
  3723. upd_context->qp_context.pri_path.sched_queue =
  3724. qp->sched_queue & 0xC7;
  3725. upd_context->qp_context.pri_path.sched_queue |=
  3726. ((work->qos & 0x7) << 3);
  3727. err = mlx4_cmd(dev, mailbox->dma,
  3728. qp->local_qpn & 0xffffff,
  3729. 0, MLX4_CMD_UPDATE_QP,
  3730. MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
  3731. if (err) {
  3732. mlx4_info(dev, "UPDATE_QP failed for slave %d, "
  3733. "port %d, qpn %d (%d)\n",
  3734. work->slave, port, qp->local_qpn,
  3735. err);
  3736. errors++;
  3737. }
  3738. }
  3739. spin_lock_irq(mlx4_tlock(dev));
  3740. }
  3741. spin_unlock_irq(mlx4_tlock(dev));
  3742. mlx4_free_cmd_mailbox(dev, mailbox);
  3743. if (errors)
  3744. mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
  3745. errors, work->slave, work->port);
  3746. /* unregister previous vlan_id if needed and we had no errors
  3747. * while updating the QPs
  3748. */
  3749. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
  3750. NO_INDX != work->orig_vlan_ix)
  3751. __mlx4_unregister_vlan(&work->priv->dev, work->port,
  3752. work->orig_vlan_id);
  3753. out:
  3754. kfree(work);
  3755. return;
  3756. }