ufshcd.c 55 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver Core
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2013 Samsung India Software Operations
  6. *
  7. * Authors:
  8. * Santosh Yaraganavi <santosh.sy@samsung.com>
  9. * Vinayak Holikatti <h.vinayak@samsung.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version 2
  14. * of the License, or (at your option) any later version.
  15. * See the COPYING file in the top-level directory or visit
  16. * <http://www.gnu.org/licenses/gpl-2.0.html>
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * This program is provided "AS IS" and "WITH ALL FAULTS" and
  24. * without warranty of any kind. You are solely responsible for
  25. * determining the appropriateness of using and distributing
  26. * the program and assume all risks associated with your exercise
  27. * of rights with respect to the program, including but not limited
  28. * to infringement of third party rights, the risks and costs of
  29. * program errors, damage to or loss of data, programs or equipment,
  30. * and unavailability or interruption of operations. Under no
  31. * circumstances will the contributor of this Program be liable for
  32. * any damages of any kind arising from your use or distribution of
  33. * this program.
  34. */
  35. #include <linux/async.h>
  36. #include "ufshcd.h"
  37. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  38. UTP_TASK_REQ_COMPL |\
  39. UFSHCD_ERROR_MASK)
  40. /* UIC command timeout, unit: ms */
  41. #define UIC_CMD_TIMEOUT 500
  42. /* NOP OUT retries waiting for NOP IN response */
  43. #define NOP_OUT_RETRIES 10
  44. /* Timeout after 30 msecs if NOP OUT hangs without response */
  45. #define NOP_OUT_TIMEOUT 30 /* msecs */
  46. enum {
  47. UFSHCD_MAX_CHANNEL = 0,
  48. UFSHCD_MAX_ID = 1,
  49. UFSHCD_MAX_LUNS = 8,
  50. UFSHCD_CMD_PER_LUN = 32,
  51. UFSHCD_CAN_QUEUE = 32,
  52. };
  53. /* UFSHCD states */
  54. enum {
  55. UFSHCD_STATE_OPERATIONAL,
  56. UFSHCD_STATE_RESET,
  57. UFSHCD_STATE_ERROR,
  58. };
  59. /* Interrupt configuration options */
  60. enum {
  61. UFSHCD_INT_DISABLE,
  62. UFSHCD_INT_ENABLE,
  63. UFSHCD_INT_CLEAR,
  64. };
  65. /* Interrupt aggregation options */
  66. enum {
  67. INT_AGGR_RESET,
  68. INT_AGGR_CONFIG,
  69. };
  70. /*
  71. * ufshcd_wait_for_register - wait for register value to change
  72. * @hba - per-adapter interface
  73. * @reg - mmio register offset
  74. * @mask - mask to apply to read register value
  75. * @val - wait condition
  76. * @interval_us - polling interval in microsecs
  77. * @timeout_ms - timeout in millisecs
  78. *
  79. * Returns -ETIMEDOUT on error, zero on success
  80. */
  81. static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  82. u32 val, unsigned long interval_us, unsigned long timeout_ms)
  83. {
  84. int err = 0;
  85. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  86. /* ignore bits that we don't intend to wait on */
  87. val = val & mask;
  88. while ((ufshcd_readl(hba, reg) & mask) != val) {
  89. /* wakeup within 50us of expiry */
  90. usleep_range(interval_us, interval_us + 50);
  91. if (time_after(jiffies, timeout)) {
  92. if ((ufshcd_readl(hba, reg) & mask) != val)
  93. err = -ETIMEDOUT;
  94. break;
  95. }
  96. }
  97. return err;
  98. }
  99. /**
  100. * ufshcd_get_intr_mask - Get the interrupt bit mask
  101. * @hba - Pointer to adapter instance
  102. *
  103. * Returns interrupt bit mask per version
  104. */
  105. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  106. {
  107. if (hba->ufs_version == UFSHCI_VERSION_10)
  108. return INTERRUPT_MASK_ALL_VER_10;
  109. else
  110. return INTERRUPT_MASK_ALL_VER_11;
  111. }
  112. /**
  113. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  114. * @hba - Pointer to adapter instance
  115. *
  116. * Returns UFSHCI version supported by the controller
  117. */
  118. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  119. {
  120. return ufshcd_readl(hba, REG_UFS_VERSION);
  121. }
  122. /**
  123. * ufshcd_is_device_present - Check if any device connected to
  124. * the host controller
  125. * @reg_hcs - host controller status register value
  126. *
  127. * Returns 1 if device present, 0 if no device detected
  128. */
  129. static inline int ufshcd_is_device_present(u32 reg_hcs)
  130. {
  131. return (DEVICE_PRESENT & reg_hcs) ? 1 : 0;
  132. }
  133. /**
  134. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  135. * @lrb: pointer to local command reference block
  136. *
  137. * This function is used to get the OCS field from UTRD
  138. * Returns the OCS field in the UTRD
  139. */
  140. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  141. {
  142. return lrbp->utr_descriptor_ptr->header.dword_2 & MASK_OCS;
  143. }
  144. /**
  145. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  146. * @task_req_descp: pointer to utp_task_req_desc structure
  147. *
  148. * This function is used to get the OCS field from UTMRD
  149. * Returns the OCS field in the UTMRD
  150. */
  151. static inline int
  152. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  153. {
  154. return task_req_descp->header.dword_2 & MASK_OCS;
  155. }
  156. /**
  157. * ufshcd_get_tm_free_slot - get a free slot for task management request
  158. * @hba: per adapter instance
  159. *
  160. * Returns maximum number of task management request slots in case of
  161. * task management queue full or returns the free slot number
  162. */
  163. static inline int ufshcd_get_tm_free_slot(struct ufs_hba *hba)
  164. {
  165. return find_first_zero_bit(&hba->outstanding_tasks, hba->nutmrs);
  166. }
  167. /**
  168. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  169. * @hba: per adapter instance
  170. * @pos: position of the bit to be cleared
  171. */
  172. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  173. {
  174. ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  175. }
  176. /**
  177. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  178. * @reg: Register value of host controller status
  179. *
  180. * Returns integer, 0 on Success and positive value if failed
  181. */
  182. static inline int ufshcd_get_lists_status(u32 reg)
  183. {
  184. /*
  185. * The mask 0xFF is for the following HCS register bits
  186. * Bit Description
  187. * 0 Device Present
  188. * 1 UTRLRDY
  189. * 2 UTMRLRDY
  190. * 3 UCRDY
  191. * 4 HEI
  192. * 5 DEI
  193. * 6-7 reserved
  194. */
  195. return (((reg) & (0xFF)) >> 1) ^ (0x07);
  196. }
  197. /**
  198. * ufshcd_get_uic_cmd_result - Get the UIC command result
  199. * @hba: Pointer to adapter instance
  200. *
  201. * This function gets the result of UIC command completion
  202. * Returns 0 on success, non zero value on error
  203. */
  204. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  205. {
  206. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  207. MASK_UIC_COMMAND_RESULT;
  208. }
  209. /**
  210. * ufshcd_get_req_rsp - returns the TR response transaction type
  211. * @ucd_rsp_ptr: pointer to response UPIU
  212. */
  213. static inline int
  214. ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  215. {
  216. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  217. }
  218. /**
  219. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  220. * @ucd_rsp_ptr: pointer to response UPIU
  221. *
  222. * This function gets the response status and scsi_status from response UPIU
  223. * Returns the response result code.
  224. */
  225. static inline int
  226. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  227. {
  228. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  229. }
  230. /**
  231. * ufshcd_config_int_aggr - Configure interrupt aggregation values.
  232. * Currently there is no use case where we want to configure
  233. * interrupt aggregation dynamically. So to configure interrupt
  234. * aggregation, #define INT_AGGR_COUNTER_THRESHOLD_VALUE and
  235. * INT_AGGR_TIMEOUT_VALUE are used.
  236. * @hba: per adapter instance
  237. * @option: Interrupt aggregation option
  238. */
  239. static inline void
  240. ufshcd_config_int_aggr(struct ufs_hba *hba, int option)
  241. {
  242. switch (option) {
  243. case INT_AGGR_RESET:
  244. ufshcd_writel(hba, INT_AGGR_ENABLE |
  245. INT_AGGR_COUNTER_AND_TIMER_RESET,
  246. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  247. break;
  248. case INT_AGGR_CONFIG:
  249. ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
  250. INT_AGGR_COUNTER_THRESHOLD_VALUE |
  251. INT_AGGR_TIMEOUT_VALUE,
  252. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  253. break;
  254. }
  255. }
  256. /**
  257. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  258. * When run-stop registers are set to 1, it indicates the
  259. * host controller that it can process the requests
  260. * @hba: per adapter instance
  261. */
  262. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  263. {
  264. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  265. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  266. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  267. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  268. }
  269. /**
  270. * ufshcd_hba_start - Start controller initialization sequence
  271. * @hba: per adapter instance
  272. */
  273. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  274. {
  275. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  276. }
  277. /**
  278. * ufshcd_is_hba_active - Get controller state
  279. * @hba: per adapter instance
  280. *
  281. * Returns zero if controller is active, 1 otherwise
  282. */
  283. static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
  284. {
  285. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
  286. }
  287. /**
  288. * ufshcd_send_command - Send SCSI or device management commands
  289. * @hba: per adapter instance
  290. * @task_tag: Task tag of the command
  291. */
  292. static inline
  293. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  294. {
  295. __set_bit(task_tag, &hba->outstanding_reqs);
  296. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  297. }
  298. /**
  299. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  300. * @lrb - pointer to local reference block
  301. */
  302. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  303. {
  304. int len;
  305. if (lrbp->sense_buffer) {
  306. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
  307. memcpy(lrbp->sense_buffer,
  308. lrbp->ucd_rsp_ptr->sr.sense_data,
  309. min_t(int, len, SCSI_SENSE_BUFFERSIZE));
  310. }
  311. }
  312. /**
  313. * ufshcd_hba_capabilities - Read controller capabilities
  314. * @hba: per adapter instance
  315. */
  316. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  317. {
  318. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  319. /* nutrs and nutmrs are 0 based values */
  320. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  321. hba->nutmrs =
  322. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  323. }
  324. /**
  325. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  326. * to accept UIC commands
  327. * @hba: per adapter instance
  328. * Return true on success, else false
  329. */
  330. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  331. {
  332. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  333. return true;
  334. else
  335. return false;
  336. }
  337. /**
  338. * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
  339. * @hba: per adapter instance
  340. * @uic_cmd: UIC command
  341. *
  342. * Mutex must be held.
  343. */
  344. static inline void
  345. ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  346. {
  347. WARN_ON(hba->active_uic_cmd);
  348. hba->active_uic_cmd = uic_cmd;
  349. /* Write Args */
  350. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  351. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  352. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  353. /* Write UIC Cmd */
  354. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  355. REG_UIC_COMMAND);
  356. }
  357. /**
  358. * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
  359. * @hba: per adapter instance
  360. * @uic_command: UIC command
  361. *
  362. * Must be called with mutex held.
  363. * Returns 0 only if success.
  364. */
  365. static int
  366. ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  367. {
  368. int ret;
  369. unsigned long flags;
  370. if (wait_for_completion_timeout(&uic_cmd->done,
  371. msecs_to_jiffies(UIC_CMD_TIMEOUT)))
  372. ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
  373. else
  374. ret = -ETIMEDOUT;
  375. spin_lock_irqsave(hba->host->host_lock, flags);
  376. hba->active_uic_cmd = NULL;
  377. spin_unlock_irqrestore(hba->host->host_lock, flags);
  378. return ret;
  379. }
  380. /**
  381. * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  382. * @hba: per adapter instance
  383. * @uic_cmd: UIC command
  384. *
  385. * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
  386. * with mutex held.
  387. * Returns 0 only if success.
  388. */
  389. static int
  390. __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  391. {
  392. int ret;
  393. unsigned long flags;
  394. if (!ufshcd_ready_for_uic_cmd(hba)) {
  395. dev_err(hba->dev,
  396. "Controller not ready to accept UIC commands\n");
  397. return -EIO;
  398. }
  399. init_completion(&uic_cmd->done);
  400. spin_lock_irqsave(hba->host->host_lock, flags);
  401. ufshcd_dispatch_uic_cmd(hba, uic_cmd);
  402. spin_unlock_irqrestore(hba->host->host_lock, flags);
  403. ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
  404. return ret;
  405. }
  406. /**
  407. * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  408. * @hba: per adapter instance
  409. * @uic_cmd: UIC command
  410. *
  411. * Returns 0 only if success.
  412. */
  413. static int
  414. ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  415. {
  416. int ret;
  417. mutex_lock(&hba->uic_cmd_mutex);
  418. ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
  419. mutex_unlock(&hba->uic_cmd_mutex);
  420. return ret;
  421. }
  422. /**
  423. * ufshcd_map_sg - Map scatter-gather list to prdt
  424. * @lrbp - pointer to local reference block
  425. *
  426. * Returns 0 in case of success, non-zero value in case of failure
  427. */
  428. static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
  429. {
  430. struct ufshcd_sg_entry *prd_table;
  431. struct scatterlist *sg;
  432. struct scsi_cmnd *cmd;
  433. int sg_segments;
  434. int i;
  435. cmd = lrbp->cmd;
  436. sg_segments = scsi_dma_map(cmd);
  437. if (sg_segments < 0)
  438. return sg_segments;
  439. if (sg_segments) {
  440. lrbp->utr_descriptor_ptr->prd_table_length =
  441. cpu_to_le16((u16) (sg_segments));
  442. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  443. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  444. prd_table[i].size =
  445. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  446. prd_table[i].base_addr =
  447. cpu_to_le32(lower_32_bits(sg->dma_address));
  448. prd_table[i].upper_addr =
  449. cpu_to_le32(upper_32_bits(sg->dma_address));
  450. }
  451. } else {
  452. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  453. }
  454. return 0;
  455. }
  456. /**
  457. * ufshcd_enable_intr - enable interrupts
  458. * @hba: per adapter instance
  459. * @intrs: interrupt bits
  460. */
  461. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  462. {
  463. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  464. if (hba->ufs_version == UFSHCI_VERSION_10) {
  465. u32 rw;
  466. rw = set & INTERRUPT_MASK_RW_VER_10;
  467. set = rw | ((set ^ intrs) & intrs);
  468. } else {
  469. set |= intrs;
  470. }
  471. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  472. }
  473. /**
  474. * ufshcd_disable_intr - disable interrupts
  475. * @hba: per adapter instance
  476. * @intrs: interrupt bits
  477. */
  478. static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
  479. {
  480. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  481. if (hba->ufs_version == UFSHCI_VERSION_10) {
  482. u32 rw;
  483. rw = (set & INTERRUPT_MASK_RW_VER_10) &
  484. ~(intrs & INTERRUPT_MASK_RW_VER_10);
  485. set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
  486. } else {
  487. set &= ~intrs;
  488. }
  489. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  490. }
  491. /**
  492. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  493. * descriptor according to request
  494. * @lrbp: pointer to local reference block
  495. * @upiu_flags: flags required in the header
  496. * @cmd_dir: requests data direction
  497. */
  498. static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
  499. u32 *upiu_flags, enum dma_data_direction cmd_dir)
  500. {
  501. struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
  502. u32 data_direction;
  503. u32 dword_0;
  504. if (cmd_dir == DMA_FROM_DEVICE) {
  505. data_direction = UTP_DEVICE_TO_HOST;
  506. *upiu_flags = UPIU_CMD_FLAGS_READ;
  507. } else if (cmd_dir == DMA_TO_DEVICE) {
  508. data_direction = UTP_HOST_TO_DEVICE;
  509. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  510. } else {
  511. data_direction = UTP_NO_DATA_TRANSFER;
  512. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  513. }
  514. dword_0 = data_direction | (lrbp->command_type
  515. << UPIU_COMMAND_TYPE_OFFSET);
  516. if (lrbp->intr_cmd)
  517. dword_0 |= UTP_REQ_DESC_INT_CMD;
  518. /* Transfer request descriptor header fields */
  519. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  520. /*
  521. * assigning invalid value for command status. Controller
  522. * updates OCS on command completion, with the command
  523. * status
  524. */
  525. req_desc->header.dword_2 =
  526. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  527. }
  528. /**
  529. * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
  530. * for scsi commands
  531. * @lrbp - local reference block pointer
  532. * @upiu_flags - flags
  533. */
  534. static
  535. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
  536. {
  537. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  538. /* command descriptor fields */
  539. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  540. UPIU_TRANSACTION_COMMAND, upiu_flags,
  541. lrbp->lun, lrbp->task_tag);
  542. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  543. UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  544. /* Total EHS length and Data segment length will be zero */
  545. ucd_req_ptr->header.dword_2 = 0;
  546. ucd_req_ptr->sc.exp_data_transfer_len =
  547. cpu_to_be32(lrbp->cmd->sdb.length);
  548. memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
  549. (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
  550. }
  551. static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
  552. {
  553. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  554. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  555. /* command descriptor fields */
  556. ucd_req_ptr->header.dword_0 =
  557. UPIU_HEADER_DWORD(
  558. UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
  559. }
  560. /**
  561. * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
  562. * @hba - per adapter instance
  563. * @lrb - pointer to local reference block
  564. */
  565. static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  566. {
  567. u32 upiu_flags;
  568. int ret = 0;
  569. switch (lrbp->command_type) {
  570. case UTP_CMD_TYPE_SCSI:
  571. if (likely(lrbp->cmd)) {
  572. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
  573. lrbp->cmd->sc_data_direction);
  574. ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
  575. } else {
  576. ret = -EINVAL;
  577. }
  578. break;
  579. case UTP_CMD_TYPE_DEV_MANAGE:
  580. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
  581. if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
  582. ufshcd_prepare_utp_nop_upiu(lrbp);
  583. else
  584. ret = -EINVAL;
  585. break;
  586. case UTP_CMD_TYPE_UFS:
  587. /* For UFS native command implementation */
  588. ret = -ENOTSUPP;
  589. dev_err(hba->dev, "%s: UFS native command are not supported\n",
  590. __func__);
  591. break;
  592. default:
  593. ret = -ENOTSUPP;
  594. dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
  595. __func__, lrbp->command_type);
  596. break;
  597. } /* end of switch */
  598. return ret;
  599. }
  600. /**
  601. * ufshcd_queuecommand - main entry point for SCSI requests
  602. * @cmd: command from SCSI Midlayer
  603. * @done: call back function
  604. *
  605. * Returns 0 for success, non-zero in case of failure
  606. */
  607. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  608. {
  609. struct ufshcd_lrb *lrbp;
  610. struct ufs_hba *hba;
  611. unsigned long flags;
  612. int tag;
  613. int err = 0;
  614. hba = shost_priv(host);
  615. tag = cmd->request->tag;
  616. if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
  617. err = SCSI_MLQUEUE_HOST_BUSY;
  618. goto out;
  619. }
  620. /* acquire the tag to make sure device cmds don't use it */
  621. if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
  622. /*
  623. * Dev manage command in progress, requeue the command.
  624. * Requeuing the command helps in cases where the request *may*
  625. * find different tag instead of waiting for dev manage command
  626. * completion.
  627. */
  628. err = SCSI_MLQUEUE_HOST_BUSY;
  629. goto out;
  630. }
  631. lrbp = &hba->lrb[tag];
  632. WARN_ON(lrbp->cmd);
  633. lrbp->cmd = cmd;
  634. lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  635. lrbp->sense_buffer = cmd->sense_buffer;
  636. lrbp->task_tag = tag;
  637. lrbp->lun = cmd->device->lun;
  638. lrbp->intr_cmd = false;
  639. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  640. /* form UPIU before issuing the command */
  641. ufshcd_compose_upiu(hba, lrbp);
  642. err = ufshcd_map_sg(lrbp);
  643. if (err) {
  644. lrbp->cmd = NULL;
  645. clear_bit_unlock(tag, &hba->lrb_in_use);
  646. goto out;
  647. }
  648. /* issue command to the controller */
  649. spin_lock_irqsave(hba->host->host_lock, flags);
  650. ufshcd_send_command(hba, tag);
  651. spin_unlock_irqrestore(hba->host->host_lock, flags);
  652. out:
  653. return err;
  654. }
  655. static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
  656. struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
  657. {
  658. lrbp->cmd = NULL;
  659. lrbp->sense_bufflen = 0;
  660. lrbp->sense_buffer = NULL;
  661. lrbp->task_tag = tag;
  662. lrbp->lun = 0; /* device management cmd is not specific to any LUN */
  663. lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
  664. lrbp->intr_cmd = true; /* No interrupt aggregation */
  665. hba->dev_cmd.type = cmd_type;
  666. return ufshcd_compose_upiu(hba, lrbp);
  667. }
  668. static int
  669. ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
  670. {
  671. int err = 0;
  672. unsigned long flags;
  673. u32 mask = 1 << tag;
  674. /* clear outstanding transaction before retry */
  675. spin_lock_irqsave(hba->host->host_lock, flags);
  676. ufshcd_utrl_clear(hba, tag);
  677. spin_unlock_irqrestore(hba->host->host_lock, flags);
  678. /*
  679. * wait for for h/w to clear corresponding bit in door-bell.
  680. * max. wait is 1 sec.
  681. */
  682. err = ufshcd_wait_for_register(hba,
  683. REG_UTP_TRANSFER_REQ_DOOR_BELL,
  684. mask, ~mask, 1000, 1000);
  685. return err;
  686. }
  687. /**
  688. * ufshcd_dev_cmd_completion() - handles device management command responses
  689. * @hba: per adapter instance
  690. * @lrbp: pointer to local reference block
  691. */
  692. static int
  693. ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  694. {
  695. int resp;
  696. int err = 0;
  697. resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  698. switch (resp) {
  699. case UPIU_TRANSACTION_NOP_IN:
  700. if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
  701. err = -EINVAL;
  702. dev_err(hba->dev, "%s: unexpected response %x\n",
  703. __func__, resp);
  704. }
  705. break;
  706. case UPIU_TRANSACTION_REJECT_UPIU:
  707. /* TODO: handle Reject UPIU Response */
  708. err = -EPERM;
  709. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  710. __func__);
  711. break;
  712. default:
  713. err = -EINVAL;
  714. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  715. __func__, resp);
  716. break;
  717. }
  718. return err;
  719. }
  720. static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
  721. struct ufshcd_lrb *lrbp, int max_timeout)
  722. {
  723. int err = 0;
  724. unsigned long time_left;
  725. unsigned long flags;
  726. time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
  727. msecs_to_jiffies(max_timeout));
  728. spin_lock_irqsave(hba->host->host_lock, flags);
  729. hba->dev_cmd.complete = NULL;
  730. if (likely(time_left)) {
  731. err = ufshcd_get_tr_ocs(lrbp);
  732. if (!err)
  733. err = ufshcd_dev_cmd_completion(hba, lrbp);
  734. }
  735. spin_unlock_irqrestore(hba->host->host_lock, flags);
  736. if (!time_left) {
  737. err = -ETIMEDOUT;
  738. if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
  739. /* sucessfully cleared the command, retry if needed */
  740. err = -EAGAIN;
  741. }
  742. return err;
  743. }
  744. /**
  745. * ufshcd_get_dev_cmd_tag - Get device management command tag
  746. * @hba: per-adapter instance
  747. * @tag: pointer to variable with available slot value
  748. *
  749. * Get a free slot and lock it until device management command
  750. * completes.
  751. *
  752. * Returns false if free slot is unavailable for locking, else
  753. * return true with tag value in @tag.
  754. */
  755. static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
  756. {
  757. int tag;
  758. bool ret = false;
  759. unsigned long tmp;
  760. if (!tag_out)
  761. goto out;
  762. do {
  763. tmp = ~hba->lrb_in_use;
  764. tag = find_last_bit(&tmp, hba->nutrs);
  765. if (tag >= hba->nutrs)
  766. goto out;
  767. } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
  768. *tag_out = tag;
  769. ret = true;
  770. out:
  771. return ret;
  772. }
  773. static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
  774. {
  775. clear_bit_unlock(tag, &hba->lrb_in_use);
  776. }
  777. /**
  778. * ufshcd_exec_dev_cmd - API for sending device management requests
  779. * @hba - UFS hba
  780. * @cmd_type - specifies the type (NOP, Query...)
  781. * @timeout - time in seconds
  782. *
  783. * NOTE: There is only one available tag for device management commands. Thus
  784. * synchronisation is the responsibilty of the user.
  785. */
  786. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
  787. enum dev_cmd_type cmd_type, int timeout)
  788. {
  789. struct ufshcd_lrb *lrbp;
  790. int err;
  791. int tag;
  792. struct completion wait;
  793. unsigned long flags;
  794. /*
  795. * Get free slot, sleep if slots are unavailable.
  796. * Even though we use wait_event() which sleeps indefinitely,
  797. * the maximum wait time is bounded by SCSI request timeout.
  798. */
  799. wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
  800. init_completion(&wait);
  801. lrbp = &hba->lrb[tag];
  802. WARN_ON(lrbp->cmd);
  803. err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
  804. if (unlikely(err))
  805. goto out_put_tag;
  806. hba->dev_cmd.complete = &wait;
  807. spin_lock_irqsave(hba->host->host_lock, flags);
  808. ufshcd_send_command(hba, tag);
  809. spin_unlock_irqrestore(hba->host->host_lock, flags);
  810. err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
  811. out_put_tag:
  812. ufshcd_put_dev_cmd_tag(hba, tag);
  813. wake_up(&hba->dev_cmd.tag_wq);
  814. return err;
  815. }
  816. /**
  817. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  818. * @hba: per adapter instance
  819. *
  820. * 1. Allocate DMA memory for Command Descriptor array
  821. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  822. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  823. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  824. * (UTMRDL)
  825. * 4. Allocate memory for local reference block(lrb).
  826. *
  827. * Returns 0 for success, non-zero in case of failure
  828. */
  829. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  830. {
  831. size_t utmrdl_size, utrdl_size, ucdl_size;
  832. /* Allocate memory for UTP command descriptors */
  833. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  834. hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
  835. ucdl_size,
  836. &hba->ucdl_dma_addr,
  837. GFP_KERNEL);
  838. /*
  839. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  840. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  841. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  842. * be aligned to 128 bytes as well
  843. */
  844. if (!hba->ucdl_base_addr ||
  845. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  846. dev_err(hba->dev,
  847. "Command Descriptor Memory allocation failed\n");
  848. goto out;
  849. }
  850. /*
  851. * Allocate memory for UTP Transfer descriptors
  852. * UFSHCI requires 1024 byte alignment of UTRD
  853. */
  854. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  855. hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
  856. utrdl_size,
  857. &hba->utrdl_dma_addr,
  858. GFP_KERNEL);
  859. if (!hba->utrdl_base_addr ||
  860. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  861. dev_err(hba->dev,
  862. "Transfer Descriptor Memory allocation failed\n");
  863. goto out;
  864. }
  865. /*
  866. * Allocate memory for UTP Task Management descriptors
  867. * UFSHCI requires 1024 byte alignment of UTMRD
  868. */
  869. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  870. hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
  871. utmrdl_size,
  872. &hba->utmrdl_dma_addr,
  873. GFP_KERNEL);
  874. if (!hba->utmrdl_base_addr ||
  875. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  876. dev_err(hba->dev,
  877. "Task Management Descriptor Memory allocation failed\n");
  878. goto out;
  879. }
  880. /* Allocate memory for local reference block */
  881. hba->lrb = devm_kzalloc(hba->dev,
  882. hba->nutrs * sizeof(struct ufshcd_lrb),
  883. GFP_KERNEL);
  884. if (!hba->lrb) {
  885. dev_err(hba->dev, "LRB Memory allocation failed\n");
  886. goto out;
  887. }
  888. return 0;
  889. out:
  890. return -ENOMEM;
  891. }
  892. /**
  893. * ufshcd_host_memory_configure - configure local reference block with
  894. * memory offsets
  895. * @hba: per adapter instance
  896. *
  897. * Configure Host memory space
  898. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  899. * address.
  900. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  901. * and PRDT offset.
  902. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  903. * into local reference block.
  904. */
  905. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  906. {
  907. struct utp_transfer_cmd_desc *cmd_descp;
  908. struct utp_transfer_req_desc *utrdlp;
  909. dma_addr_t cmd_desc_dma_addr;
  910. dma_addr_t cmd_desc_element_addr;
  911. u16 response_offset;
  912. u16 prdt_offset;
  913. int cmd_desc_size;
  914. int i;
  915. utrdlp = hba->utrdl_base_addr;
  916. cmd_descp = hba->ucdl_base_addr;
  917. response_offset =
  918. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  919. prdt_offset =
  920. offsetof(struct utp_transfer_cmd_desc, prd_table);
  921. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  922. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  923. for (i = 0; i < hba->nutrs; i++) {
  924. /* Configure UTRD with command descriptor base address */
  925. cmd_desc_element_addr =
  926. (cmd_desc_dma_addr + (cmd_desc_size * i));
  927. utrdlp[i].command_desc_base_addr_lo =
  928. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  929. utrdlp[i].command_desc_base_addr_hi =
  930. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  931. /* Response upiu and prdt offset should be in double words */
  932. utrdlp[i].response_upiu_offset =
  933. cpu_to_le16((response_offset >> 2));
  934. utrdlp[i].prd_table_offset =
  935. cpu_to_le16((prdt_offset >> 2));
  936. utrdlp[i].response_upiu_length =
  937. cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  938. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  939. hba->lrb[i].ucd_req_ptr =
  940. (struct utp_upiu_req *)(cmd_descp + i);
  941. hba->lrb[i].ucd_rsp_ptr =
  942. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  943. hba->lrb[i].ucd_prdt_ptr =
  944. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  945. }
  946. }
  947. /**
  948. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  949. * @hba: per adapter instance
  950. *
  951. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  952. * in order to initialize the Unipro link startup procedure.
  953. * Once the Unipro links are up, the device connected to the controller
  954. * is detected.
  955. *
  956. * Returns 0 on success, non-zero value on failure
  957. */
  958. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  959. {
  960. struct uic_command uic_cmd = {0};
  961. int ret;
  962. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  963. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  964. if (ret)
  965. dev_err(hba->dev,
  966. "dme-link-startup: error code %d\n", ret);
  967. return ret;
  968. }
  969. /**
  970. * ufshcd_make_hba_operational - Make UFS controller operational
  971. * @hba: per adapter instance
  972. *
  973. * To bring UFS host controller to operational state,
  974. * 1. Check if device is present
  975. * 2. Enable required interrupts
  976. * 3. Configure interrupt aggregation
  977. * 4. Program UTRL and UTMRL base addres
  978. * 5. Configure run-stop-registers
  979. *
  980. * Returns 0 on success, non-zero value on failure
  981. */
  982. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  983. {
  984. int err = 0;
  985. u32 reg;
  986. /* check if device present */
  987. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  988. if (!ufshcd_is_device_present(reg)) {
  989. dev_err(hba->dev, "cc: Device not present\n");
  990. err = -ENXIO;
  991. goto out;
  992. }
  993. /* Enable required interrupts */
  994. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  995. /* Configure interrupt aggregation */
  996. ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG);
  997. /* Configure UTRL and UTMRL base address registers */
  998. ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
  999. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  1000. ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
  1001. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  1002. ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
  1003. REG_UTP_TASK_REQ_LIST_BASE_L);
  1004. ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
  1005. REG_UTP_TASK_REQ_LIST_BASE_H);
  1006. /*
  1007. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  1008. * DEI, HEI bits must be 0
  1009. */
  1010. if (!(ufshcd_get_lists_status(reg))) {
  1011. ufshcd_enable_run_stop_reg(hba);
  1012. } else {
  1013. dev_err(hba->dev,
  1014. "Host controller not ready to process requests");
  1015. err = -EIO;
  1016. goto out;
  1017. }
  1018. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  1019. scsi_unblock_requests(hba->host);
  1020. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  1021. out:
  1022. return err;
  1023. }
  1024. /**
  1025. * ufshcd_hba_enable - initialize the controller
  1026. * @hba: per adapter instance
  1027. *
  1028. * The controller resets itself and controller firmware initialization
  1029. * sequence kicks off. When controller is ready it will set
  1030. * the Host Controller Enable bit to 1.
  1031. *
  1032. * Returns 0 on success, non-zero value on failure
  1033. */
  1034. static int ufshcd_hba_enable(struct ufs_hba *hba)
  1035. {
  1036. int retry;
  1037. /*
  1038. * msleep of 1 and 5 used in this function might result in msleep(20),
  1039. * but it was necessary to send the UFS FPGA to reset mode during
  1040. * development and testing of this driver. msleep can be changed to
  1041. * mdelay and retry count can be reduced based on the controller.
  1042. */
  1043. if (!ufshcd_is_hba_active(hba)) {
  1044. /* change controller state to "reset state" */
  1045. ufshcd_hba_stop(hba);
  1046. /*
  1047. * This delay is based on the testing done with UFS host
  1048. * controller FPGA. The delay can be changed based on the
  1049. * host controller used.
  1050. */
  1051. msleep(5);
  1052. }
  1053. /* start controller initialization sequence */
  1054. ufshcd_hba_start(hba);
  1055. /*
  1056. * To initialize a UFS host controller HCE bit must be set to 1.
  1057. * During initialization the HCE bit value changes from 1->0->1.
  1058. * When the host controller completes initialization sequence
  1059. * it sets the value of HCE bit to 1. The same HCE bit is read back
  1060. * to check if the controller has completed initialization sequence.
  1061. * So without this delay the value HCE = 1, set in the previous
  1062. * instruction might be read back.
  1063. * This delay can be changed based on the controller.
  1064. */
  1065. msleep(1);
  1066. /* wait for the host controller to complete initialization */
  1067. retry = 10;
  1068. while (ufshcd_is_hba_active(hba)) {
  1069. if (retry) {
  1070. retry--;
  1071. } else {
  1072. dev_err(hba->dev,
  1073. "Controller enable failed\n");
  1074. return -EIO;
  1075. }
  1076. msleep(5);
  1077. }
  1078. return 0;
  1079. }
  1080. /**
  1081. * ufshcd_link_startup - Initialize unipro link startup
  1082. * @hba: per adapter instance
  1083. *
  1084. * Returns 0 for success, non-zero in case of failure
  1085. */
  1086. static int ufshcd_link_startup(struct ufs_hba *hba)
  1087. {
  1088. int ret;
  1089. /* enable UIC related interrupts */
  1090. ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
  1091. ret = ufshcd_dme_link_startup(hba);
  1092. if (ret)
  1093. goto out;
  1094. ret = ufshcd_make_hba_operational(hba);
  1095. out:
  1096. if (ret)
  1097. dev_err(hba->dev, "link startup failed %d\n", ret);
  1098. return ret;
  1099. }
  1100. /**
  1101. * ufshcd_verify_dev_init() - Verify device initialization
  1102. * @hba: per-adapter instance
  1103. *
  1104. * Send NOP OUT UPIU and wait for NOP IN response to check whether the
  1105. * device Transport Protocol (UTP) layer is ready after a reset.
  1106. * If the UTP layer at the device side is not initialized, it may
  1107. * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
  1108. * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
  1109. */
  1110. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  1111. {
  1112. int err = 0;
  1113. int retries;
  1114. mutex_lock(&hba->dev_cmd.lock);
  1115. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  1116. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  1117. NOP_OUT_TIMEOUT);
  1118. if (!err || err == -ETIMEDOUT)
  1119. break;
  1120. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  1121. }
  1122. mutex_unlock(&hba->dev_cmd.lock);
  1123. if (err)
  1124. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  1125. return err;
  1126. }
  1127. /**
  1128. * ufshcd_do_reset - reset the host controller
  1129. * @hba: per adapter instance
  1130. *
  1131. * Returns SUCCESS/FAILED
  1132. */
  1133. static int ufshcd_do_reset(struct ufs_hba *hba)
  1134. {
  1135. struct ufshcd_lrb *lrbp;
  1136. unsigned long flags;
  1137. int tag;
  1138. /* block commands from midlayer */
  1139. scsi_block_requests(hba->host);
  1140. spin_lock_irqsave(hba->host->host_lock, flags);
  1141. hba->ufshcd_state = UFSHCD_STATE_RESET;
  1142. /* send controller to reset state */
  1143. ufshcd_hba_stop(hba);
  1144. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1145. /* abort outstanding commands */
  1146. for (tag = 0; tag < hba->nutrs; tag++) {
  1147. if (test_bit(tag, &hba->outstanding_reqs)) {
  1148. lrbp = &hba->lrb[tag];
  1149. if (lrbp->cmd) {
  1150. scsi_dma_unmap(lrbp->cmd);
  1151. lrbp->cmd->result = DID_RESET << 16;
  1152. lrbp->cmd->scsi_done(lrbp->cmd);
  1153. lrbp->cmd = NULL;
  1154. clear_bit_unlock(tag, &hba->lrb_in_use);
  1155. }
  1156. }
  1157. }
  1158. /* complete device management command */
  1159. if (hba->dev_cmd.complete)
  1160. complete(hba->dev_cmd.complete);
  1161. /* clear outstanding request/task bit maps */
  1162. hba->outstanding_reqs = 0;
  1163. hba->outstanding_tasks = 0;
  1164. /* Host controller enable */
  1165. if (ufshcd_hba_enable(hba)) {
  1166. dev_err(hba->dev,
  1167. "Reset: Controller initialization failed\n");
  1168. return FAILED;
  1169. }
  1170. if (ufshcd_link_startup(hba)) {
  1171. dev_err(hba->dev,
  1172. "Reset: Link start-up failed\n");
  1173. return FAILED;
  1174. }
  1175. return SUCCESS;
  1176. }
  1177. /**
  1178. * ufshcd_slave_alloc - handle initial SCSI device configurations
  1179. * @sdev: pointer to SCSI device
  1180. *
  1181. * Returns success
  1182. */
  1183. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  1184. {
  1185. struct ufs_hba *hba;
  1186. hba = shost_priv(sdev->host);
  1187. sdev->tagged_supported = 1;
  1188. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  1189. sdev->use_10_for_ms = 1;
  1190. scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
  1191. /*
  1192. * Inform SCSI Midlayer that the LUN queue depth is same as the
  1193. * controller queue depth. If a LUN queue depth is less than the
  1194. * controller queue depth and if the LUN reports
  1195. * SAM_STAT_TASK_SET_FULL, the LUN queue depth will be adjusted
  1196. * with scsi_adjust_queue_depth.
  1197. */
  1198. scsi_activate_tcq(sdev, hba->nutrs);
  1199. return 0;
  1200. }
  1201. /**
  1202. * ufshcd_slave_destroy - remove SCSI device configurations
  1203. * @sdev: pointer to SCSI device
  1204. */
  1205. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  1206. {
  1207. struct ufs_hba *hba;
  1208. hba = shost_priv(sdev->host);
  1209. scsi_deactivate_tcq(sdev, hba->nutrs);
  1210. }
  1211. /**
  1212. * ufshcd_task_req_compl - handle task management request completion
  1213. * @hba: per adapter instance
  1214. * @index: index of the completed request
  1215. *
  1216. * Returns SUCCESS/FAILED
  1217. */
  1218. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index)
  1219. {
  1220. struct utp_task_req_desc *task_req_descp;
  1221. struct utp_upiu_task_rsp *task_rsp_upiup;
  1222. unsigned long flags;
  1223. int ocs_value;
  1224. int task_result;
  1225. spin_lock_irqsave(hba->host->host_lock, flags);
  1226. /* Clear completed tasks from outstanding_tasks */
  1227. __clear_bit(index, &hba->outstanding_tasks);
  1228. task_req_descp = hba->utmrdl_base_addr;
  1229. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  1230. if (ocs_value == OCS_SUCCESS) {
  1231. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  1232. task_req_descp[index].task_rsp_upiu;
  1233. task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
  1234. task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
  1235. if (task_result != UPIU_TASK_MANAGEMENT_FUNC_COMPL &&
  1236. task_result != UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED)
  1237. task_result = FAILED;
  1238. else
  1239. task_result = SUCCESS;
  1240. } else {
  1241. task_result = FAILED;
  1242. dev_err(hba->dev,
  1243. "trc: Invalid ocs = %x\n", ocs_value);
  1244. }
  1245. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1246. return task_result;
  1247. }
  1248. /**
  1249. * ufshcd_adjust_lun_qdepth - Update LUN queue depth if device responds with
  1250. * SAM_STAT_TASK_SET_FULL SCSI command status.
  1251. * @cmd: pointer to SCSI command
  1252. */
  1253. static void ufshcd_adjust_lun_qdepth(struct scsi_cmnd *cmd)
  1254. {
  1255. struct ufs_hba *hba;
  1256. int i;
  1257. int lun_qdepth = 0;
  1258. hba = shost_priv(cmd->device->host);
  1259. /*
  1260. * LUN queue depth can be obtained by counting outstanding commands
  1261. * on the LUN.
  1262. */
  1263. for (i = 0; i < hba->nutrs; i++) {
  1264. if (test_bit(i, &hba->outstanding_reqs)) {
  1265. /*
  1266. * Check if the outstanding command belongs
  1267. * to the LUN which reported SAM_STAT_TASK_SET_FULL.
  1268. */
  1269. if (cmd->device->lun == hba->lrb[i].lun)
  1270. lun_qdepth++;
  1271. }
  1272. }
  1273. /*
  1274. * LUN queue depth will be total outstanding commands, except the
  1275. * command for which the LUN reported SAM_STAT_TASK_SET_FULL.
  1276. */
  1277. scsi_adjust_queue_depth(cmd->device, MSG_SIMPLE_TAG, lun_qdepth - 1);
  1278. }
  1279. /**
  1280. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  1281. * @lrb: pointer to local reference block of completed command
  1282. * @scsi_status: SCSI command status
  1283. *
  1284. * Returns value base on SCSI command status
  1285. */
  1286. static inline int
  1287. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  1288. {
  1289. int result = 0;
  1290. switch (scsi_status) {
  1291. case SAM_STAT_GOOD:
  1292. result |= DID_OK << 16 |
  1293. COMMAND_COMPLETE << 8 |
  1294. SAM_STAT_GOOD;
  1295. break;
  1296. case SAM_STAT_CHECK_CONDITION:
  1297. result |= DID_OK << 16 |
  1298. COMMAND_COMPLETE << 8 |
  1299. SAM_STAT_CHECK_CONDITION;
  1300. ufshcd_copy_sense_data(lrbp);
  1301. break;
  1302. case SAM_STAT_BUSY:
  1303. result |= SAM_STAT_BUSY;
  1304. break;
  1305. case SAM_STAT_TASK_SET_FULL:
  1306. /*
  1307. * If a LUN reports SAM_STAT_TASK_SET_FULL, then the LUN queue
  1308. * depth needs to be adjusted to the exact number of
  1309. * outstanding commands the LUN can handle at any given time.
  1310. */
  1311. ufshcd_adjust_lun_qdepth(lrbp->cmd);
  1312. result |= SAM_STAT_TASK_SET_FULL;
  1313. break;
  1314. case SAM_STAT_TASK_ABORTED:
  1315. result |= SAM_STAT_TASK_ABORTED;
  1316. break;
  1317. default:
  1318. result |= DID_ERROR << 16;
  1319. break;
  1320. } /* end of switch */
  1321. return result;
  1322. }
  1323. /**
  1324. * ufshcd_transfer_rsp_status - Get overall status of the response
  1325. * @hba: per adapter instance
  1326. * @lrb: pointer to local reference block of completed command
  1327. *
  1328. * Returns result of the command to notify SCSI midlayer
  1329. */
  1330. static inline int
  1331. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1332. {
  1333. int result = 0;
  1334. int scsi_status;
  1335. int ocs;
  1336. /* overall command status of utrd */
  1337. ocs = ufshcd_get_tr_ocs(lrbp);
  1338. switch (ocs) {
  1339. case OCS_SUCCESS:
  1340. result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  1341. switch (result) {
  1342. case UPIU_TRANSACTION_RESPONSE:
  1343. /*
  1344. * get the response UPIU result to extract
  1345. * the SCSI command status
  1346. */
  1347. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  1348. /*
  1349. * get the result based on SCSI status response
  1350. * to notify the SCSI midlayer of the command status
  1351. */
  1352. scsi_status = result & MASK_SCSI_STATUS;
  1353. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  1354. break;
  1355. case UPIU_TRANSACTION_REJECT_UPIU:
  1356. /* TODO: handle Reject UPIU Response */
  1357. result = DID_ERROR << 16;
  1358. dev_err(hba->dev,
  1359. "Reject UPIU not fully implemented\n");
  1360. break;
  1361. default:
  1362. result = DID_ERROR << 16;
  1363. dev_err(hba->dev,
  1364. "Unexpected request response code = %x\n",
  1365. result);
  1366. break;
  1367. }
  1368. break;
  1369. case OCS_ABORTED:
  1370. result |= DID_ABORT << 16;
  1371. break;
  1372. case OCS_INVALID_CMD_TABLE_ATTR:
  1373. case OCS_INVALID_PRDT_ATTR:
  1374. case OCS_MISMATCH_DATA_BUF_SIZE:
  1375. case OCS_MISMATCH_RESP_UPIU_SIZE:
  1376. case OCS_PEER_COMM_FAILURE:
  1377. case OCS_FATAL_ERROR:
  1378. default:
  1379. result |= DID_ERROR << 16;
  1380. dev_err(hba->dev,
  1381. "OCS error from controller = %x\n", ocs);
  1382. break;
  1383. } /* end of switch */
  1384. return result;
  1385. }
  1386. /**
  1387. * ufshcd_uic_cmd_compl - handle completion of uic command
  1388. * @hba: per adapter instance
  1389. */
  1390. static void ufshcd_uic_cmd_compl(struct ufs_hba *hba)
  1391. {
  1392. if (hba->active_uic_cmd) {
  1393. hba->active_uic_cmd->argument2 |=
  1394. ufshcd_get_uic_cmd_result(hba);
  1395. complete(&hba->active_uic_cmd->done);
  1396. }
  1397. }
  1398. /**
  1399. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  1400. * @hba: per adapter instance
  1401. */
  1402. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  1403. {
  1404. struct ufshcd_lrb *lrbp;
  1405. struct scsi_cmnd *cmd;
  1406. unsigned long completed_reqs;
  1407. u32 tr_doorbell;
  1408. int result;
  1409. int index;
  1410. bool int_aggr_reset = false;
  1411. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  1412. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  1413. for (index = 0; index < hba->nutrs; index++) {
  1414. if (test_bit(index, &completed_reqs)) {
  1415. lrbp = &hba->lrb[index];
  1416. cmd = lrbp->cmd;
  1417. /*
  1418. * Don't skip resetting interrupt aggregation counters
  1419. * if a regular command is present.
  1420. */
  1421. int_aggr_reset |= !lrbp->intr_cmd;
  1422. if (cmd) {
  1423. result = ufshcd_transfer_rsp_status(hba, lrbp);
  1424. scsi_dma_unmap(cmd);
  1425. cmd->result = result;
  1426. /* Mark completed command as NULL in LRB */
  1427. lrbp->cmd = NULL;
  1428. clear_bit_unlock(index, &hba->lrb_in_use);
  1429. /* Do not touch lrbp after scsi done */
  1430. cmd->scsi_done(cmd);
  1431. } else if (lrbp->command_type ==
  1432. UTP_CMD_TYPE_DEV_MANAGE) {
  1433. if (hba->dev_cmd.complete)
  1434. complete(hba->dev_cmd.complete);
  1435. }
  1436. } /* end of if */
  1437. } /* end of for */
  1438. /* clear corresponding bits of completed commands */
  1439. hba->outstanding_reqs ^= completed_reqs;
  1440. /* we might have free'd some tags above */
  1441. wake_up(&hba->dev_cmd.tag_wq);
  1442. /* Reset interrupt aggregation counters */
  1443. if (int_aggr_reset)
  1444. ufshcd_config_int_aggr(hba, INT_AGGR_RESET);
  1445. }
  1446. /**
  1447. * ufshcd_fatal_err_handler - handle fatal errors
  1448. * @hba: per adapter instance
  1449. */
  1450. static void ufshcd_fatal_err_handler(struct work_struct *work)
  1451. {
  1452. struct ufs_hba *hba;
  1453. hba = container_of(work, struct ufs_hba, feh_workq);
  1454. /* check if reset is already in progress */
  1455. if (hba->ufshcd_state != UFSHCD_STATE_RESET)
  1456. ufshcd_do_reset(hba);
  1457. }
  1458. /**
  1459. * ufshcd_err_handler - Check for fatal errors
  1460. * @work: pointer to a work queue structure
  1461. */
  1462. static void ufshcd_err_handler(struct ufs_hba *hba)
  1463. {
  1464. u32 reg;
  1465. if (hba->errors & INT_FATAL_ERRORS)
  1466. goto fatal_eh;
  1467. if (hba->errors & UIC_ERROR) {
  1468. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
  1469. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  1470. goto fatal_eh;
  1471. }
  1472. return;
  1473. fatal_eh:
  1474. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  1475. schedule_work(&hba->feh_workq);
  1476. }
  1477. /**
  1478. * ufshcd_tmc_handler - handle task management function completion
  1479. * @hba: per adapter instance
  1480. */
  1481. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  1482. {
  1483. u32 tm_doorbell;
  1484. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  1485. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  1486. wake_up_interruptible(&hba->ufshcd_tm_wait_queue);
  1487. }
  1488. /**
  1489. * ufshcd_sl_intr - Interrupt service routine
  1490. * @hba: per adapter instance
  1491. * @intr_status: contains interrupts generated by the controller
  1492. */
  1493. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  1494. {
  1495. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  1496. if (hba->errors)
  1497. ufshcd_err_handler(hba);
  1498. if (intr_status & UIC_COMMAND_COMPL)
  1499. ufshcd_uic_cmd_compl(hba);
  1500. if (intr_status & UTP_TASK_REQ_COMPL)
  1501. ufshcd_tmc_handler(hba);
  1502. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  1503. ufshcd_transfer_req_compl(hba);
  1504. }
  1505. /**
  1506. * ufshcd_intr - Main interrupt service routine
  1507. * @irq: irq number
  1508. * @__hba: pointer to adapter instance
  1509. *
  1510. * Returns IRQ_HANDLED - If interrupt is valid
  1511. * IRQ_NONE - If invalid interrupt
  1512. */
  1513. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  1514. {
  1515. u32 intr_status;
  1516. irqreturn_t retval = IRQ_NONE;
  1517. struct ufs_hba *hba = __hba;
  1518. spin_lock(hba->host->host_lock);
  1519. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  1520. if (intr_status) {
  1521. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  1522. ufshcd_sl_intr(hba, intr_status);
  1523. retval = IRQ_HANDLED;
  1524. }
  1525. spin_unlock(hba->host->host_lock);
  1526. return retval;
  1527. }
  1528. /**
  1529. * ufshcd_issue_tm_cmd - issues task management commands to controller
  1530. * @hba: per adapter instance
  1531. * @lrbp: pointer to local reference block
  1532. *
  1533. * Returns SUCCESS/FAILED
  1534. */
  1535. static int
  1536. ufshcd_issue_tm_cmd(struct ufs_hba *hba,
  1537. struct ufshcd_lrb *lrbp,
  1538. u8 tm_function)
  1539. {
  1540. struct utp_task_req_desc *task_req_descp;
  1541. struct utp_upiu_task_req *task_req_upiup;
  1542. struct Scsi_Host *host;
  1543. unsigned long flags;
  1544. int free_slot = 0;
  1545. int err;
  1546. host = hba->host;
  1547. spin_lock_irqsave(host->host_lock, flags);
  1548. /* If task management queue is full */
  1549. free_slot = ufshcd_get_tm_free_slot(hba);
  1550. if (free_slot >= hba->nutmrs) {
  1551. spin_unlock_irqrestore(host->host_lock, flags);
  1552. dev_err(hba->dev, "Task management queue full\n");
  1553. err = FAILED;
  1554. goto out;
  1555. }
  1556. task_req_descp = hba->utmrdl_base_addr;
  1557. task_req_descp += free_slot;
  1558. /* Configure task request descriptor */
  1559. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  1560. task_req_descp->header.dword_2 =
  1561. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  1562. /* Configure task request UPIU */
  1563. task_req_upiup =
  1564. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  1565. task_req_upiup->header.dword_0 =
  1566. UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  1567. lrbp->lun, lrbp->task_tag);
  1568. task_req_upiup->header.dword_1 =
  1569. UPIU_HEADER_DWORD(0, tm_function, 0, 0);
  1570. task_req_upiup->input_param1 = lrbp->lun;
  1571. task_req_upiup->input_param1 =
  1572. cpu_to_be32(task_req_upiup->input_param1);
  1573. task_req_upiup->input_param2 = lrbp->task_tag;
  1574. task_req_upiup->input_param2 =
  1575. cpu_to_be32(task_req_upiup->input_param2);
  1576. /* send command to the controller */
  1577. __set_bit(free_slot, &hba->outstanding_tasks);
  1578. ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
  1579. spin_unlock_irqrestore(host->host_lock, flags);
  1580. /* wait until the task management command is completed */
  1581. err =
  1582. wait_event_interruptible_timeout(hba->ufshcd_tm_wait_queue,
  1583. (test_bit(free_slot,
  1584. &hba->tm_condition) != 0),
  1585. 60 * HZ);
  1586. if (!err) {
  1587. dev_err(hba->dev,
  1588. "Task management command timed-out\n");
  1589. err = FAILED;
  1590. goto out;
  1591. }
  1592. clear_bit(free_slot, &hba->tm_condition);
  1593. err = ufshcd_task_req_compl(hba, free_slot);
  1594. out:
  1595. return err;
  1596. }
  1597. /**
  1598. * ufshcd_device_reset - reset device and abort all the pending commands
  1599. * @cmd: SCSI command pointer
  1600. *
  1601. * Returns SUCCESS/FAILED
  1602. */
  1603. static int ufshcd_device_reset(struct scsi_cmnd *cmd)
  1604. {
  1605. struct Scsi_Host *host;
  1606. struct ufs_hba *hba;
  1607. unsigned int tag;
  1608. u32 pos;
  1609. int err;
  1610. host = cmd->device->host;
  1611. hba = shost_priv(host);
  1612. tag = cmd->request->tag;
  1613. err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_LOGICAL_RESET);
  1614. if (err == FAILED)
  1615. goto out;
  1616. for (pos = 0; pos < hba->nutrs; pos++) {
  1617. if (test_bit(pos, &hba->outstanding_reqs) &&
  1618. (hba->lrb[tag].lun == hba->lrb[pos].lun)) {
  1619. /* clear the respective UTRLCLR register bit */
  1620. ufshcd_utrl_clear(hba, pos);
  1621. clear_bit(pos, &hba->outstanding_reqs);
  1622. if (hba->lrb[pos].cmd) {
  1623. scsi_dma_unmap(hba->lrb[pos].cmd);
  1624. hba->lrb[pos].cmd->result =
  1625. DID_ABORT << 16;
  1626. hba->lrb[pos].cmd->scsi_done(cmd);
  1627. hba->lrb[pos].cmd = NULL;
  1628. clear_bit_unlock(pos, &hba->lrb_in_use);
  1629. wake_up(&hba->dev_cmd.tag_wq);
  1630. }
  1631. }
  1632. } /* end of for */
  1633. out:
  1634. return err;
  1635. }
  1636. /**
  1637. * ufshcd_host_reset - Main reset function registered with scsi layer
  1638. * @cmd: SCSI command pointer
  1639. *
  1640. * Returns SUCCESS/FAILED
  1641. */
  1642. static int ufshcd_host_reset(struct scsi_cmnd *cmd)
  1643. {
  1644. struct ufs_hba *hba;
  1645. hba = shost_priv(cmd->device->host);
  1646. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  1647. return SUCCESS;
  1648. return ufshcd_do_reset(hba);
  1649. }
  1650. /**
  1651. * ufshcd_abort - abort a specific command
  1652. * @cmd: SCSI command pointer
  1653. *
  1654. * Returns SUCCESS/FAILED
  1655. */
  1656. static int ufshcd_abort(struct scsi_cmnd *cmd)
  1657. {
  1658. struct Scsi_Host *host;
  1659. struct ufs_hba *hba;
  1660. unsigned long flags;
  1661. unsigned int tag;
  1662. int err;
  1663. host = cmd->device->host;
  1664. hba = shost_priv(host);
  1665. tag = cmd->request->tag;
  1666. spin_lock_irqsave(host->host_lock, flags);
  1667. /* check if command is still pending */
  1668. if (!(test_bit(tag, &hba->outstanding_reqs))) {
  1669. err = FAILED;
  1670. spin_unlock_irqrestore(host->host_lock, flags);
  1671. goto out;
  1672. }
  1673. spin_unlock_irqrestore(host->host_lock, flags);
  1674. err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_ABORT_TASK);
  1675. if (err == FAILED)
  1676. goto out;
  1677. scsi_dma_unmap(cmd);
  1678. spin_lock_irqsave(host->host_lock, flags);
  1679. /* clear the respective UTRLCLR register bit */
  1680. ufshcd_utrl_clear(hba, tag);
  1681. __clear_bit(tag, &hba->outstanding_reqs);
  1682. hba->lrb[tag].cmd = NULL;
  1683. spin_unlock_irqrestore(host->host_lock, flags);
  1684. clear_bit_unlock(tag, &hba->lrb_in_use);
  1685. wake_up(&hba->dev_cmd.tag_wq);
  1686. out:
  1687. return err;
  1688. }
  1689. /**
  1690. * ufshcd_async_scan - asynchronous execution for link startup
  1691. * @data: data pointer to pass to this function
  1692. * @cookie: cookie data
  1693. */
  1694. static void ufshcd_async_scan(void *data, async_cookie_t cookie)
  1695. {
  1696. struct ufs_hba *hba = (struct ufs_hba *)data;
  1697. int ret;
  1698. ret = ufshcd_link_startup(hba);
  1699. if (ret)
  1700. goto out;
  1701. ret = ufshcd_verify_dev_init(hba);
  1702. if (ret)
  1703. goto out;
  1704. scsi_scan_host(hba->host);
  1705. out:
  1706. return;
  1707. }
  1708. static struct scsi_host_template ufshcd_driver_template = {
  1709. .module = THIS_MODULE,
  1710. .name = UFSHCD,
  1711. .proc_name = UFSHCD,
  1712. .queuecommand = ufshcd_queuecommand,
  1713. .slave_alloc = ufshcd_slave_alloc,
  1714. .slave_destroy = ufshcd_slave_destroy,
  1715. .eh_abort_handler = ufshcd_abort,
  1716. .eh_device_reset_handler = ufshcd_device_reset,
  1717. .eh_host_reset_handler = ufshcd_host_reset,
  1718. .this_id = -1,
  1719. .sg_tablesize = SG_ALL,
  1720. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  1721. .can_queue = UFSHCD_CAN_QUEUE,
  1722. };
  1723. /**
  1724. * ufshcd_suspend - suspend power management function
  1725. * @hba: per adapter instance
  1726. * @state: power state
  1727. *
  1728. * Returns -ENOSYS
  1729. */
  1730. int ufshcd_suspend(struct ufs_hba *hba, pm_message_t state)
  1731. {
  1732. /*
  1733. * TODO:
  1734. * 1. Block SCSI requests from SCSI midlayer
  1735. * 2. Change the internal driver state to non operational
  1736. * 3. Set UTRLRSR and UTMRLRSR bits to zero
  1737. * 4. Wait until outstanding commands are completed
  1738. * 5. Set HCE to zero to send the UFS host controller to reset state
  1739. */
  1740. return -ENOSYS;
  1741. }
  1742. EXPORT_SYMBOL_GPL(ufshcd_suspend);
  1743. /**
  1744. * ufshcd_resume - resume power management function
  1745. * @hba: per adapter instance
  1746. *
  1747. * Returns -ENOSYS
  1748. */
  1749. int ufshcd_resume(struct ufs_hba *hba)
  1750. {
  1751. /*
  1752. * TODO:
  1753. * 1. Set HCE to 1, to start the UFS host controller
  1754. * initialization process
  1755. * 2. Set UTRLRSR and UTMRLRSR bits to 1
  1756. * 3. Change the internal driver state to operational
  1757. * 4. Unblock SCSI requests from SCSI midlayer
  1758. */
  1759. return -ENOSYS;
  1760. }
  1761. EXPORT_SYMBOL_GPL(ufshcd_resume);
  1762. /**
  1763. * ufshcd_remove - de-allocate SCSI host and host memory space
  1764. * data structure memory
  1765. * @hba - per adapter instance
  1766. */
  1767. void ufshcd_remove(struct ufs_hba *hba)
  1768. {
  1769. /* disable interrupts */
  1770. ufshcd_disable_intr(hba, hba->intr_mask);
  1771. ufshcd_hba_stop(hba);
  1772. scsi_remove_host(hba->host);
  1773. scsi_host_put(hba->host);
  1774. }
  1775. EXPORT_SYMBOL_GPL(ufshcd_remove);
  1776. /**
  1777. * ufshcd_init - Driver initialization routine
  1778. * @dev: pointer to device handle
  1779. * @hba_handle: driver private handle
  1780. * @mmio_base: base register address
  1781. * @irq: Interrupt line of device
  1782. * Returns 0 on success, non-zero value on failure
  1783. */
  1784. int ufshcd_init(struct device *dev, struct ufs_hba **hba_handle,
  1785. void __iomem *mmio_base, unsigned int irq)
  1786. {
  1787. struct Scsi_Host *host;
  1788. struct ufs_hba *hba;
  1789. int err;
  1790. if (!dev) {
  1791. dev_err(dev,
  1792. "Invalid memory reference for dev is NULL\n");
  1793. err = -ENODEV;
  1794. goto out_error;
  1795. }
  1796. if (!mmio_base) {
  1797. dev_err(dev,
  1798. "Invalid memory reference for mmio_base is NULL\n");
  1799. err = -ENODEV;
  1800. goto out_error;
  1801. }
  1802. host = scsi_host_alloc(&ufshcd_driver_template,
  1803. sizeof(struct ufs_hba));
  1804. if (!host) {
  1805. dev_err(dev, "scsi_host_alloc failed\n");
  1806. err = -ENOMEM;
  1807. goto out_error;
  1808. }
  1809. hba = shost_priv(host);
  1810. hba->host = host;
  1811. hba->dev = dev;
  1812. hba->mmio_base = mmio_base;
  1813. hba->irq = irq;
  1814. /* Read capabilities registers */
  1815. ufshcd_hba_capabilities(hba);
  1816. /* Get UFS version supported by the controller */
  1817. hba->ufs_version = ufshcd_get_ufs_version(hba);
  1818. /* Get Interrupt bit mask per version */
  1819. hba->intr_mask = ufshcd_get_intr_mask(hba);
  1820. /* Allocate memory for host memory space */
  1821. err = ufshcd_memory_alloc(hba);
  1822. if (err) {
  1823. dev_err(hba->dev, "Memory allocation failed\n");
  1824. goto out_disable;
  1825. }
  1826. /* Configure LRB */
  1827. ufshcd_host_memory_configure(hba);
  1828. host->can_queue = hba->nutrs;
  1829. host->cmd_per_lun = hba->nutrs;
  1830. host->max_id = UFSHCD_MAX_ID;
  1831. host->max_lun = UFSHCD_MAX_LUNS;
  1832. host->max_channel = UFSHCD_MAX_CHANNEL;
  1833. host->unique_id = host->host_no;
  1834. host->max_cmd_len = MAX_CDB_SIZE;
  1835. /* Initailize wait queue for task management */
  1836. init_waitqueue_head(&hba->ufshcd_tm_wait_queue);
  1837. /* Initialize work queues */
  1838. INIT_WORK(&hba->feh_workq, ufshcd_fatal_err_handler);
  1839. /* Initialize UIC command mutex */
  1840. mutex_init(&hba->uic_cmd_mutex);
  1841. /* Initialize mutex for device management commands */
  1842. mutex_init(&hba->dev_cmd.lock);
  1843. /* Initialize device management tag acquire wait queue */
  1844. init_waitqueue_head(&hba->dev_cmd.tag_wq);
  1845. /* IRQ registration */
  1846. err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  1847. if (err) {
  1848. dev_err(hba->dev, "request irq failed\n");
  1849. goto out_disable;
  1850. }
  1851. /* Enable SCSI tag mapping */
  1852. err = scsi_init_shared_tag_map(host, host->can_queue);
  1853. if (err) {
  1854. dev_err(hba->dev, "init shared queue failed\n");
  1855. goto out_disable;
  1856. }
  1857. err = scsi_add_host(host, hba->dev);
  1858. if (err) {
  1859. dev_err(hba->dev, "scsi_add_host failed\n");
  1860. goto out_disable;
  1861. }
  1862. /* Host controller enable */
  1863. err = ufshcd_hba_enable(hba);
  1864. if (err) {
  1865. dev_err(hba->dev, "Host controller enable failed\n");
  1866. goto out_remove_scsi_host;
  1867. }
  1868. *hba_handle = hba;
  1869. async_schedule(ufshcd_async_scan, hba);
  1870. return 0;
  1871. out_remove_scsi_host:
  1872. scsi_remove_host(hba->host);
  1873. out_disable:
  1874. scsi_host_put(host);
  1875. out_error:
  1876. return err;
  1877. }
  1878. EXPORT_SYMBOL_GPL(ufshcd_init);
  1879. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
  1880. MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
  1881. MODULE_DESCRIPTION("Generic UFS host controller driver Core");
  1882. MODULE_LICENSE("GPL");
  1883. MODULE_VERSION(UFSHCD_DRIVER_VERSION);