cnic.c 140 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  29. #define BCM_VLAN 1
  30. #endif
  31. #include <net/ip.h>
  32. #include <net/tcp.h>
  33. #include <net/route.h>
  34. #include <net/ipv6.h>
  35. #include <net/ip6_route.h>
  36. #include <net/ip6_checksum.h>
  37. #include <scsi/iscsi_if.h>
  38. #include "cnic_if.h"
  39. #include "bnx2.h"
  40. #include "bnx2x/bnx2x_reg.h"
  41. #include "bnx2x/bnx2x_fw_defs.h"
  42. #include "bnx2x/bnx2x_hsi.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  44. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  45. #include "cnic.h"
  46. #include "cnic_defs.h"
  47. #define DRV_MODULE_NAME "cnic"
  48. static char version[] __devinitdata =
  49. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  50. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  51. "Chen (zongxi@broadcom.com");
  52. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  53. MODULE_LICENSE("GPL");
  54. MODULE_VERSION(CNIC_MODULE_VERSION);
  55. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  56. static LIST_HEAD(cnic_dev_list);
  57. static LIST_HEAD(cnic_udev_list);
  58. static DEFINE_RWLOCK(cnic_dev_lock);
  59. static DEFINE_MUTEX(cnic_lock);
  60. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  61. /* helper function, assuming cnic_lock is held */
  62. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  63. {
  64. return rcu_dereference_protected(cnic_ulp_tbl[type],
  65. lockdep_is_held(&cnic_lock));
  66. }
  67. static int cnic_service_bnx2(void *, void *);
  68. static int cnic_service_bnx2x(void *, void *);
  69. static int cnic_ctl(void *, struct cnic_ctl_info *);
  70. static struct cnic_ops cnic_bnx2_ops = {
  71. .cnic_owner = THIS_MODULE,
  72. .cnic_handler = cnic_service_bnx2,
  73. .cnic_ctl = cnic_ctl,
  74. };
  75. static struct cnic_ops cnic_bnx2x_ops = {
  76. .cnic_owner = THIS_MODULE,
  77. .cnic_handler = cnic_service_bnx2x,
  78. .cnic_ctl = cnic_ctl,
  79. };
  80. static struct workqueue_struct *cnic_wq;
  81. static void cnic_shutdown_rings(struct cnic_dev *);
  82. static void cnic_init_rings(struct cnic_dev *);
  83. static int cnic_cm_set_pg(struct cnic_sock *);
  84. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  85. {
  86. struct cnic_uio_dev *udev = uinfo->priv;
  87. struct cnic_dev *dev;
  88. if (!capable(CAP_NET_ADMIN))
  89. return -EPERM;
  90. if (udev->uio_dev != -1)
  91. return -EBUSY;
  92. rtnl_lock();
  93. dev = udev->dev;
  94. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  95. rtnl_unlock();
  96. return -ENODEV;
  97. }
  98. udev->uio_dev = iminor(inode);
  99. cnic_shutdown_rings(dev);
  100. cnic_init_rings(dev);
  101. rtnl_unlock();
  102. return 0;
  103. }
  104. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  105. {
  106. struct cnic_uio_dev *udev = uinfo->priv;
  107. udev->uio_dev = -1;
  108. return 0;
  109. }
  110. static inline void cnic_hold(struct cnic_dev *dev)
  111. {
  112. atomic_inc(&dev->ref_count);
  113. }
  114. static inline void cnic_put(struct cnic_dev *dev)
  115. {
  116. atomic_dec(&dev->ref_count);
  117. }
  118. static inline void csk_hold(struct cnic_sock *csk)
  119. {
  120. atomic_inc(&csk->ref_count);
  121. }
  122. static inline void csk_put(struct cnic_sock *csk)
  123. {
  124. atomic_dec(&csk->ref_count);
  125. }
  126. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  127. {
  128. struct cnic_dev *cdev;
  129. read_lock(&cnic_dev_lock);
  130. list_for_each_entry(cdev, &cnic_dev_list, list) {
  131. if (netdev == cdev->netdev) {
  132. cnic_hold(cdev);
  133. read_unlock(&cnic_dev_lock);
  134. return cdev;
  135. }
  136. }
  137. read_unlock(&cnic_dev_lock);
  138. return NULL;
  139. }
  140. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  141. {
  142. atomic_inc(&ulp_ops->ref_count);
  143. }
  144. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  145. {
  146. atomic_dec(&ulp_ops->ref_count);
  147. }
  148. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  149. {
  150. struct cnic_local *cp = dev->cnic_priv;
  151. struct cnic_eth_dev *ethdev = cp->ethdev;
  152. struct drv_ctl_info info;
  153. struct drv_ctl_io *io = &info.data.io;
  154. info.cmd = DRV_CTL_CTX_WR_CMD;
  155. io->cid_addr = cid_addr;
  156. io->offset = off;
  157. io->data = val;
  158. ethdev->drv_ctl(dev->netdev, &info);
  159. }
  160. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  161. {
  162. struct cnic_local *cp = dev->cnic_priv;
  163. struct cnic_eth_dev *ethdev = cp->ethdev;
  164. struct drv_ctl_info info;
  165. struct drv_ctl_io *io = &info.data.io;
  166. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  167. io->offset = off;
  168. io->dma_addr = addr;
  169. ethdev->drv_ctl(dev->netdev, &info);
  170. }
  171. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  172. {
  173. struct cnic_local *cp = dev->cnic_priv;
  174. struct cnic_eth_dev *ethdev = cp->ethdev;
  175. struct drv_ctl_info info;
  176. struct drv_ctl_l2_ring *ring = &info.data.ring;
  177. if (start)
  178. info.cmd = DRV_CTL_START_L2_CMD;
  179. else
  180. info.cmd = DRV_CTL_STOP_L2_CMD;
  181. ring->cid = cid;
  182. ring->client_id = cl_id;
  183. ethdev->drv_ctl(dev->netdev, &info);
  184. }
  185. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  186. {
  187. struct cnic_local *cp = dev->cnic_priv;
  188. struct cnic_eth_dev *ethdev = cp->ethdev;
  189. struct drv_ctl_info info;
  190. struct drv_ctl_io *io = &info.data.io;
  191. info.cmd = DRV_CTL_IO_WR_CMD;
  192. io->offset = off;
  193. io->data = val;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. }
  196. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  197. {
  198. struct cnic_local *cp = dev->cnic_priv;
  199. struct cnic_eth_dev *ethdev = cp->ethdev;
  200. struct drv_ctl_info info;
  201. struct drv_ctl_io *io = &info.data.io;
  202. info.cmd = DRV_CTL_IO_RD_CMD;
  203. io->offset = off;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. return io->data;
  206. }
  207. static int cnic_in_use(struct cnic_sock *csk)
  208. {
  209. return test_bit(SK_F_INUSE, &csk->flags);
  210. }
  211. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  212. {
  213. struct cnic_local *cp = dev->cnic_priv;
  214. struct cnic_eth_dev *ethdev = cp->ethdev;
  215. struct drv_ctl_info info;
  216. info.cmd = cmd;
  217. info.data.credit.credit_count = count;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  221. {
  222. u32 i;
  223. for (i = 0; i < cp->max_cid_space; i++) {
  224. if (cp->ctx_tbl[i].cid == cid) {
  225. *l5_cid = i;
  226. return 0;
  227. }
  228. }
  229. return -EINVAL;
  230. }
  231. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  232. struct cnic_sock *csk)
  233. {
  234. struct iscsi_path path_req;
  235. char *buf = NULL;
  236. u16 len = 0;
  237. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  238. struct cnic_ulp_ops *ulp_ops;
  239. struct cnic_uio_dev *udev = cp->udev;
  240. int rc = 0, retry = 0;
  241. if (!udev || udev->uio_dev == -1)
  242. return -ENODEV;
  243. if (csk) {
  244. len = sizeof(path_req);
  245. buf = (char *) &path_req;
  246. memset(&path_req, 0, len);
  247. msg_type = ISCSI_KEVENT_PATH_REQ;
  248. path_req.handle = (u64) csk->l5_cid;
  249. if (test_bit(SK_F_IPV6, &csk->flags)) {
  250. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  251. sizeof(struct in6_addr));
  252. path_req.ip_addr_len = 16;
  253. } else {
  254. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  255. sizeof(struct in_addr));
  256. path_req.ip_addr_len = 4;
  257. }
  258. path_req.vlan_id = csk->vlan_id;
  259. path_req.pmtu = csk->mtu;
  260. }
  261. while (retry < 3) {
  262. rc = 0;
  263. rcu_read_lock();
  264. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  265. if (ulp_ops)
  266. rc = ulp_ops->iscsi_nl_send_msg(
  267. cp->ulp_handle[CNIC_ULP_ISCSI],
  268. msg_type, buf, len);
  269. rcu_read_unlock();
  270. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  271. break;
  272. msleep(100);
  273. retry++;
  274. }
  275. return 0;
  276. }
  277. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  278. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  279. char *buf, u16 len)
  280. {
  281. int rc = -EINVAL;
  282. switch (msg_type) {
  283. case ISCSI_UEVENT_PATH_UPDATE: {
  284. struct cnic_local *cp;
  285. u32 l5_cid;
  286. struct cnic_sock *csk;
  287. struct iscsi_path *path_resp;
  288. if (len < sizeof(*path_resp))
  289. break;
  290. path_resp = (struct iscsi_path *) buf;
  291. cp = dev->cnic_priv;
  292. l5_cid = (u32) path_resp->handle;
  293. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  294. break;
  295. rcu_read_lock();
  296. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  297. rc = -ENODEV;
  298. rcu_read_unlock();
  299. break;
  300. }
  301. csk = &cp->csk_tbl[l5_cid];
  302. csk_hold(csk);
  303. if (cnic_in_use(csk) &&
  304. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  305. memcpy(csk->ha, path_resp->mac_addr, 6);
  306. if (test_bit(SK_F_IPV6, &csk->flags))
  307. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  308. sizeof(struct in6_addr));
  309. else
  310. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  311. sizeof(struct in_addr));
  312. if (is_valid_ether_addr(csk->ha)) {
  313. cnic_cm_set_pg(csk);
  314. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  315. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  316. cnic_cm_upcall(cp, csk,
  317. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  318. clear_bit(SK_F_CONNECT_START, &csk->flags);
  319. }
  320. }
  321. csk_put(csk);
  322. rcu_read_unlock();
  323. rc = 0;
  324. }
  325. }
  326. return rc;
  327. }
  328. static int cnic_offld_prep(struct cnic_sock *csk)
  329. {
  330. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  331. return 0;
  332. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  333. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  334. return 0;
  335. }
  336. return 1;
  337. }
  338. static int cnic_close_prep(struct cnic_sock *csk)
  339. {
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. smp_mb__after_clear_bit();
  342. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  343. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  344. msleep(1);
  345. return 1;
  346. }
  347. return 0;
  348. }
  349. static int cnic_abort_prep(struct cnic_sock *csk)
  350. {
  351. clear_bit(SK_F_CONNECT_START, &csk->flags);
  352. smp_mb__after_clear_bit();
  353. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  354. msleep(1);
  355. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  356. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  357. return 1;
  358. }
  359. return 0;
  360. }
  361. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  362. {
  363. struct cnic_dev *dev;
  364. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  365. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  366. return -EINVAL;
  367. }
  368. mutex_lock(&cnic_lock);
  369. if (cnic_ulp_tbl_prot(ulp_type)) {
  370. pr_err("%s: Type %d has already been registered\n",
  371. __func__, ulp_type);
  372. mutex_unlock(&cnic_lock);
  373. return -EBUSY;
  374. }
  375. read_lock(&cnic_dev_lock);
  376. list_for_each_entry(dev, &cnic_dev_list, list) {
  377. struct cnic_local *cp = dev->cnic_priv;
  378. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  379. }
  380. read_unlock(&cnic_dev_lock);
  381. atomic_set(&ulp_ops->ref_count, 0);
  382. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  383. mutex_unlock(&cnic_lock);
  384. /* Prevent race conditions with netdev_event */
  385. rtnl_lock();
  386. list_for_each_entry(dev, &cnic_dev_list, list) {
  387. struct cnic_local *cp = dev->cnic_priv;
  388. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  389. ulp_ops->cnic_init(dev);
  390. }
  391. rtnl_unlock();
  392. return 0;
  393. }
  394. int cnic_unregister_driver(int ulp_type)
  395. {
  396. struct cnic_dev *dev;
  397. struct cnic_ulp_ops *ulp_ops;
  398. int i = 0;
  399. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  400. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  401. return -EINVAL;
  402. }
  403. mutex_lock(&cnic_lock);
  404. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  405. if (!ulp_ops) {
  406. pr_err("%s: Type %d has not been registered\n",
  407. __func__, ulp_type);
  408. goto out_unlock;
  409. }
  410. read_lock(&cnic_dev_lock);
  411. list_for_each_entry(dev, &cnic_dev_list, list) {
  412. struct cnic_local *cp = dev->cnic_priv;
  413. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  414. pr_err("%s: Type %d still has devices registered\n",
  415. __func__, ulp_type);
  416. read_unlock(&cnic_dev_lock);
  417. goto out_unlock;
  418. }
  419. }
  420. read_unlock(&cnic_dev_lock);
  421. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  422. mutex_unlock(&cnic_lock);
  423. synchronize_rcu();
  424. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  425. msleep(100);
  426. i++;
  427. }
  428. if (atomic_read(&ulp_ops->ref_count) != 0)
  429. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  430. return 0;
  431. out_unlock:
  432. mutex_unlock(&cnic_lock);
  433. return -EINVAL;
  434. }
  435. static int cnic_start_hw(struct cnic_dev *);
  436. static void cnic_stop_hw(struct cnic_dev *);
  437. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  438. void *ulp_ctx)
  439. {
  440. struct cnic_local *cp = dev->cnic_priv;
  441. struct cnic_ulp_ops *ulp_ops;
  442. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  443. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  444. return -EINVAL;
  445. }
  446. mutex_lock(&cnic_lock);
  447. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  448. pr_err("%s: Driver with type %d has not been registered\n",
  449. __func__, ulp_type);
  450. mutex_unlock(&cnic_lock);
  451. return -EAGAIN;
  452. }
  453. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  454. pr_err("%s: Type %d has already been registered to this device\n",
  455. __func__, ulp_type);
  456. mutex_unlock(&cnic_lock);
  457. return -EBUSY;
  458. }
  459. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  460. cp->ulp_handle[ulp_type] = ulp_ctx;
  461. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  462. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  463. cnic_hold(dev);
  464. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  465. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  466. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  467. mutex_unlock(&cnic_lock);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL(cnic_register_driver);
  471. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  472. {
  473. struct cnic_local *cp = dev->cnic_priv;
  474. int i = 0;
  475. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  476. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  477. return -EINVAL;
  478. }
  479. mutex_lock(&cnic_lock);
  480. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  481. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  482. cnic_put(dev);
  483. } else {
  484. pr_err("%s: device not registered to this ulp type %d\n",
  485. __func__, ulp_type);
  486. mutex_unlock(&cnic_lock);
  487. return -EINVAL;
  488. }
  489. mutex_unlock(&cnic_lock);
  490. if (ulp_type == CNIC_ULP_ISCSI)
  491. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  492. synchronize_rcu();
  493. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  494. i < 20) {
  495. msleep(100);
  496. i++;
  497. }
  498. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  499. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(cnic_unregister_driver);
  503. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  504. u32 next)
  505. {
  506. id_tbl->start = start_id;
  507. id_tbl->max = size;
  508. id_tbl->next = next;
  509. spin_lock_init(&id_tbl->lock);
  510. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  511. if (!id_tbl->table)
  512. return -ENOMEM;
  513. return 0;
  514. }
  515. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  516. {
  517. kfree(id_tbl->table);
  518. id_tbl->table = NULL;
  519. }
  520. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  521. {
  522. int ret = -1;
  523. id -= id_tbl->start;
  524. if (id >= id_tbl->max)
  525. return ret;
  526. spin_lock(&id_tbl->lock);
  527. if (!test_bit(id, id_tbl->table)) {
  528. set_bit(id, id_tbl->table);
  529. ret = 0;
  530. }
  531. spin_unlock(&id_tbl->lock);
  532. return ret;
  533. }
  534. /* Returns -1 if not successful */
  535. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  536. {
  537. u32 id;
  538. spin_lock(&id_tbl->lock);
  539. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  540. if (id >= id_tbl->max) {
  541. id = -1;
  542. if (id_tbl->next != 0) {
  543. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  544. if (id >= id_tbl->next)
  545. id = -1;
  546. }
  547. }
  548. if (id < id_tbl->max) {
  549. set_bit(id, id_tbl->table);
  550. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  551. id += id_tbl->start;
  552. }
  553. spin_unlock(&id_tbl->lock);
  554. return id;
  555. }
  556. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  557. {
  558. if (id == -1)
  559. return;
  560. id -= id_tbl->start;
  561. if (id >= id_tbl->max)
  562. return;
  563. clear_bit(id, id_tbl->table);
  564. }
  565. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  566. {
  567. int i;
  568. if (!dma->pg_arr)
  569. return;
  570. for (i = 0; i < dma->num_pages; i++) {
  571. if (dma->pg_arr[i]) {
  572. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  573. dma->pg_arr[i], dma->pg_map_arr[i]);
  574. dma->pg_arr[i] = NULL;
  575. }
  576. }
  577. if (dma->pgtbl) {
  578. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  579. dma->pgtbl, dma->pgtbl_map);
  580. dma->pgtbl = NULL;
  581. }
  582. kfree(dma->pg_arr);
  583. dma->pg_arr = NULL;
  584. dma->num_pages = 0;
  585. }
  586. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  587. {
  588. int i;
  589. __le32 *page_table = (__le32 *) dma->pgtbl;
  590. for (i = 0; i < dma->num_pages; i++) {
  591. /* Each entry needs to be in big endian format. */
  592. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  593. page_table++;
  594. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  595. page_table++;
  596. }
  597. }
  598. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  599. {
  600. int i;
  601. __le32 *page_table = (__le32 *) dma->pgtbl;
  602. for (i = 0; i < dma->num_pages; i++) {
  603. /* Each entry needs to be in little endian format. */
  604. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  605. page_table++;
  606. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  607. page_table++;
  608. }
  609. }
  610. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  611. int pages, int use_pg_tbl)
  612. {
  613. int i, size;
  614. struct cnic_local *cp = dev->cnic_priv;
  615. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  616. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  617. if (dma->pg_arr == NULL)
  618. return -ENOMEM;
  619. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  620. dma->num_pages = pages;
  621. for (i = 0; i < pages; i++) {
  622. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  623. BCM_PAGE_SIZE,
  624. &dma->pg_map_arr[i],
  625. GFP_ATOMIC);
  626. if (dma->pg_arr[i] == NULL)
  627. goto error;
  628. }
  629. if (!use_pg_tbl)
  630. return 0;
  631. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  632. ~(BCM_PAGE_SIZE - 1);
  633. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  634. &dma->pgtbl_map, GFP_ATOMIC);
  635. if (dma->pgtbl == NULL)
  636. goto error;
  637. cp->setup_pgtbl(dev, dma);
  638. return 0;
  639. error:
  640. cnic_free_dma(dev, dma);
  641. return -ENOMEM;
  642. }
  643. static void cnic_free_context(struct cnic_dev *dev)
  644. {
  645. struct cnic_local *cp = dev->cnic_priv;
  646. int i;
  647. for (i = 0; i < cp->ctx_blks; i++) {
  648. if (cp->ctx_arr[i].ctx) {
  649. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  650. cp->ctx_arr[i].ctx,
  651. cp->ctx_arr[i].mapping);
  652. cp->ctx_arr[i].ctx = NULL;
  653. }
  654. }
  655. }
  656. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  657. {
  658. uio_unregister_device(&udev->cnic_uinfo);
  659. if (udev->l2_buf) {
  660. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  661. udev->l2_buf, udev->l2_buf_map);
  662. udev->l2_buf = NULL;
  663. }
  664. if (udev->l2_ring) {
  665. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  666. udev->l2_ring, udev->l2_ring_map);
  667. udev->l2_ring = NULL;
  668. }
  669. pci_dev_put(udev->pdev);
  670. kfree(udev);
  671. }
  672. static void cnic_free_uio(struct cnic_uio_dev *udev)
  673. {
  674. if (!udev)
  675. return;
  676. write_lock(&cnic_dev_lock);
  677. list_del_init(&udev->list);
  678. write_unlock(&cnic_dev_lock);
  679. __cnic_free_uio(udev);
  680. }
  681. static void cnic_free_resc(struct cnic_dev *dev)
  682. {
  683. struct cnic_local *cp = dev->cnic_priv;
  684. struct cnic_uio_dev *udev = cp->udev;
  685. if (udev) {
  686. udev->dev = NULL;
  687. cp->udev = NULL;
  688. }
  689. cnic_free_context(dev);
  690. kfree(cp->ctx_arr);
  691. cp->ctx_arr = NULL;
  692. cp->ctx_blks = 0;
  693. cnic_free_dma(dev, &cp->gbl_buf_info);
  694. cnic_free_dma(dev, &cp->conn_buf_info);
  695. cnic_free_dma(dev, &cp->kwq_info);
  696. cnic_free_dma(dev, &cp->kwq_16_data_info);
  697. cnic_free_dma(dev, &cp->kcq2.dma);
  698. cnic_free_dma(dev, &cp->kcq1.dma);
  699. kfree(cp->iscsi_tbl);
  700. cp->iscsi_tbl = NULL;
  701. kfree(cp->ctx_tbl);
  702. cp->ctx_tbl = NULL;
  703. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  704. cnic_free_id_tbl(&cp->cid_tbl);
  705. }
  706. static int cnic_alloc_context(struct cnic_dev *dev)
  707. {
  708. struct cnic_local *cp = dev->cnic_priv;
  709. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  710. int i, k, arr_size;
  711. cp->ctx_blk_size = BCM_PAGE_SIZE;
  712. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  713. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  714. sizeof(struct cnic_ctx);
  715. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  716. if (cp->ctx_arr == NULL)
  717. return -ENOMEM;
  718. k = 0;
  719. for (i = 0; i < 2; i++) {
  720. u32 j, reg, off, lo, hi;
  721. if (i == 0)
  722. off = BNX2_PG_CTX_MAP;
  723. else
  724. off = BNX2_ISCSI_CTX_MAP;
  725. reg = cnic_reg_rd_ind(dev, off);
  726. lo = reg >> 16;
  727. hi = reg & 0xffff;
  728. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  729. cp->ctx_arr[k].cid = j;
  730. }
  731. cp->ctx_blks = k;
  732. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  733. cp->ctx_blks = 0;
  734. return -ENOMEM;
  735. }
  736. for (i = 0; i < cp->ctx_blks; i++) {
  737. cp->ctx_arr[i].ctx =
  738. dma_alloc_coherent(&dev->pcidev->dev,
  739. BCM_PAGE_SIZE,
  740. &cp->ctx_arr[i].mapping,
  741. GFP_KERNEL);
  742. if (cp->ctx_arr[i].ctx == NULL)
  743. return -ENOMEM;
  744. }
  745. }
  746. return 0;
  747. }
  748. static u16 cnic_bnx2_next_idx(u16 idx)
  749. {
  750. return idx + 1;
  751. }
  752. static u16 cnic_bnx2_hw_idx(u16 idx)
  753. {
  754. return idx;
  755. }
  756. static u16 cnic_bnx2x_next_idx(u16 idx)
  757. {
  758. idx++;
  759. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  760. idx++;
  761. return idx;
  762. }
  763. static u16 cnic_bnx2x_hw_idx(u16 idx)
  764. {
  765. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  766. idx++;
  767. return idx;
  768. }
  769. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  770. bool use_pg_tbl)
  771. {
  772. int err, i, use_page_tbl = 0;
  773. struct kcqe **kcq;
  774. if (use_pg_tbl)
  775. use_page_tbl = 1;
  776. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  777. if (err)
  778. return err;
  779. kcq = (struct kcqe **) info->dma.pg_arr;
  780. info->kcq = kcq;
  781. info->next_idx = cnic_bnx2_next_idx;
  782. info->hw_idx = cnic_bnx2_hw_idx;
  783. if (use_pg_tbl)
  784. return 0;
  785. info->next_idx = cnic_bnx2x_next_idx;
  786. info->hw_idx = cnic_bnx2x_hw_idx;
  787. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  788. struct bnx2x_bd_chain_next *next =
  789. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  790. int j = i + 1;
  791. if (j >= KCQ_PAGE_CNT)
  792. j = 0;
  793. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  794. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  795. }
  796. return 0;
  797. }
  798. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  799. {
  800. struct cnic_local *cp = dev->cnic_priv;
  801. struct cnic_uio_dev *udev;
  802. read_lock(&cnic_dev_lock);
  803. list_for_each_entry(udev, &cnic_udev_list, list) {
  804. if (udev->pdev == dev->pcidev) {
  805. udev->dev = dev;
  806. cp->udev = udev;
  807. read_unlock(&cnic_dev_lock);
  808. return 0;
  809. }
  810. }
  811. read_unlock(&cnic_dev_lock);
  812. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  813. if (!udev)
  814. return -ENOMEM;
  815. udev->uio_dev = -1;
  816. udev->dev = dev;
  817. udev->pdev = dev->pcidev;
  818. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  819. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  820. &udev->l2_ring_map,
  821. GFP_KERNEL | __GFP_COMP);
  822. if (!udev->l2_ring)
  823. goto err_udev;
  824. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  825. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  826. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  827. &udev->l2_buf_map,
  828. GFP_KERNEL | __GFP_COMP);
  829. if (!udev->l2_buf)
  830. goto err_dma;
  831. write_lock(&cnic_dev_lock);
  832. list_add(&udev->list, &cnic_udev_list);
  833. write_unlock(&cnic_dev_lock);
  834. pci_dev_get(udev->pdev);
  835. cp->udev = udev;
  836. return 0;
  837. err_dma:
  838. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  839. udev->l2_ring, udev->l2_ring_map);
  840. err_udev:
  841. kfree(udev);
  842. return -ENOMEM;
  843. }
  844. static int cnic_init_uio(struct cnic_dev *dev)
  845. {
  846. struct cnic_local *cp = dev->cnic_priv;
  847. struct cnic_uio_dev *udev = cp->udev;
  848. struct uio_info *uinfo;
  849. int ret = 0;
  850. if (!udev)
  851. return -ENOMEM;
  852. uinfo = &udev->cnic_uinfo;
  853. uinfo->mem[0].addr = dev->netdev->base_addr;
  854. uinfo->mem[0].internal_addr = dev->regview;
  855. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  856. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  857. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  858. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  859. PAGE_MASK;
  860. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  861. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  862. else
  863. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  864. uinfo->name = "bnx2_cnic";
  865. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  866. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  867. PAGE_MASK;
  868. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  869. uinfo->name = "bnx2x_cnic";
  870. }
  871. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  872. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  873. uinfo->mem[2].size = udev->l2_ring_size;
  874. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  875. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  876. uinfo->mem[3].size = udev->l2_buf_size;
  877. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  878. uinfo->version = CNIC_MODULE_VERSION;
  879. uinfo->irq = UIO_IRQ_CUSTOM;
  880. uinfo->open = cnic_uio_open;
  881. uinfo->release = cnic_uio_close;
  882. if (udev->uio_dev == -1) {
  883. if (!uinfo->priv) {
  884. uinfo->priv = udev;
  885. ret = uio_register_device(&udev->pdev->dev, uinfo);
  886. }
  887. } else {
  888. cnic_init_rings(dev);
  889. }
  890. return ret;
  891. }
  892. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  893. {
  894. struct cnic_local *cp = dev->cnic_priv;
  895. int ret;
  896. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  897. if (ret)
  898. goto error;
  899. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  900. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  901. if (ret)
  902. goto error;
  903. ret = cnic_alloc_context(dev);
  904. if (ret)
  905. goto error;
  906. ret = cnic_alloc_uio_rings(dev, 2);
  907. if (ret)
  908. goto error;
  909. ret = cnic_init_uio(dev);
  910. if (ret)
  911. goto error;
  912. return 0;
  913. error:
  914. cnic_free_resc(dev);
  915. return ret;
  916. }
  917. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  918. {
  919. struct cnic_local *cp = dev->cnic_priv;
  920. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  921. int total_mem, blks, i;
  922. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  923. blks = total_mem / ctx_blk_size;
  924. if (total_mem % ctx_blk_size)
  925. blks++;
  926. if (blks > cp->ethdev->ctx_tbl_len)
  927. return -ENOMEM;
  928. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  929. if (cp->ctx_arr == NULL)
  930. return -ENOMEM;
  931. cp->ctx_blks = blks;
  932. cp->ctx_blk_size = ctx_blk_size;
  933. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  934. cp->ctx_align = 0;
  935. else
  936. cp->ctx_align = ctx_blk_size;
  937. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  938. for (i = 0; i < blks; i++) {
  939. cp->ctx_arr[i].ctx =
  940. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  941. &cp->ctx_arr[i].mapping,
  942. GFP_KERNEL);
  943. if (cp->ctx_arr[i].ctx == NULL)
  944. return -ENOMEM;
  945. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  946. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  947. cnic_free_context(dev);
  948. cp->ctx_blk_size += cp->ctx_align;
  949. i = -1;
  950. continue;
  951. }
  952. }
  953. }
  954. return 0;
  955. }
  956. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  957. {
  958. struct cnic_local *cp = dev->cnic_priv;
  959. struct cnic_eth_dev *ethdev = cp->ethdev;
  960. u32 start_cid = ethdev->starting_cid;
  961. int i, j, n, ret, pages;
  962. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  963. cp->iro_arr = ethdev->iro_arr;
  964. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  965. cp->iscsi_start_cid = start_cid;
  966. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  967. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  968. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  969. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  970. if (!cp->fcoe_init_cid)
  971. cp->fcoe_init_cid = 0x10;
  972. }
  973. if (start_cid < BNX2X_ISCSI_START_CID) {
  974. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  975. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  976. cp->fcoe_start_cid += delta;
  977. cp->max_cid_space += delta;
  978. }
  979. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  980. GFP_KERNEL);
  981. if (!cp->iscsi_tbl)
  982. goto error;
  983. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  984. cp->max_cid_space, GFP_KERNEL);
  985. if (!cp->ctx_tbl)
  986. goto error;
  987. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  988. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  989. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  990. }
  991. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  992. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  993. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  994. PAGE_SIZE;
  995. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  996. if (ret)
  997. return -ENOMEM;
  998. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  999. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1000. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1001. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1002. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1003. off;
  1004. if ((i % n) == (n - 1))
  1005. j++;
  1006. }
  1007. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1008. if (ret)
  1009. goto error;
  1010. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  1011. ret = cnic_alloc_kcq(dev, &cp->kcq2, false);
  1012. if (ret)
  1013. goto error;
  1014. }
  1015. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  1016. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  1017. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  1018. if (ret)
  1019. goto error;
  1020. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1021. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1022. if (ret)
  1023. goto error;
  1024. ret = cnic_alloc_bnx2x_context(dev);
  1025. if (ret)
  1026. goto error;
  1027. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1028. cp->l2_rx_ring_size = 15;
  1029. ret = cnic_alloc_uio_rings(dev, 4);
  1030. if (ret)
  1031. goto error;
  1032. ret = cnic_init_uio(dev);
  1033. if (ret)
  1034. goto error;
  1035. return 0;
  1036. error:
  1037. cnic_free_resc(dev);
  1038. return -ENOMEM;
  1039. }
  1040. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1041. {
  1042. return cp->max_kwq_idx -
  1043. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1044. }
  1045. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1046. u32 num_wqes)
  1047. {
  1048. struct cnic_local *cp = dev->cnic_priv;
  1049. struct kwqe *prod_qe;
  1050. u16 prod, sw_prod, i;
  1051. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1052. return -EAGAIN; /* bnx2 is down */
  1053. spin_lock_bh(&cp->cnic_ulp_lock);
  1054. if (num_wqes > cnic_kwq_avail(cp) &&
  1055. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1056. spin_unlock_bh(&cp->cnic_ulp_lock);
  1057. return -EAGAIN;
  1058. }
  1059. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1060. prod = cp->kwq_prod_idx;
  1061. sw_prod = prod & MAX_KWQ_IDX;
  1062. for (i = 0; i < num_wqes; i++) {
  1063. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1064. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1065. prod++;
  1066. sw_prod = prod & MAX_KWQ_IDX;
  1067. }
  1068. cp->kwq_prod_idx = prod;
  1069. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1070. spin_unlock_bh(&cp->cnic_ulp_lock);
  1071. return 0;
  1072. }
  1073. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1074. union l5cm_specific_data *l5_data)
  1075. {
  1076. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1077. dma_addr_t map;
  1078. map = ctx->kwqe_data_mapping;
  1079. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1080. l5_data->phy_address.hi = (u64) map >> 32;
  1081. return ctx->kwqe_data;
  1082. }
  1083. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1084. u32 type, union l5cm_specific_data *l5_data)
  1085. {
  1086. struct cnic_local *cp = dev->cnic_priv;
  1087. struct l5cm_spe kwqe;
  1088. struct kwqe_16 *kwq[1];
  1089. u16 type_16;
  1090. int ret;
  1091. kwqe.hdr.conn_and_cmd_data =
  1092. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1093. BNX2X_HW_CID(cp, cid)));
  1094. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1095. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1096. SPE_HDR_FUNCTION_ID;
  1097. kwqe.hdr.type = cpu_to_le16(type_16);
  1098. kwqe.hdr.reserved1 = 0;
  1099. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1100. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1101. kwq[0] = (struct kwqe_16 *) &kwqe;
  1102. spin_lock_bh(&cp->cnic_ulp_lock);
  1103. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1104. spin_unlock_bh(&cp->cnic_ulp_lock);
  1105. if (ret == 1)
  1106. return 0;
  1107. return -EBUSY;
  1108. }
  1109. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1110. struct kcqe *cqes[], u32 num_cqes)
  1111. {
  1112. struct cnic_local *cp = dev->cnic_priv;
  1113. struct cnic_ulp_ops *ulp_ops;
  1114. rcu_read_lock();
  1115. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1116. if (likely(ulp_ops)) {
  1117. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1118. cqes, num_cqes);
  1119. }
  1120. rcu_read_unlock();
  1121. }
  1122. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1123. {
  1124. struct cnic_local *cp = dev->cnic_priv;
  1125. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1126. int hq_bds, pages;
  1127. u32 pfid = cp->pfid;
  1128. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1129. cp->num_ccells = req1->num_ccells_per_conn;
  1130. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1131. cp->num_iscsi_tasks;
  1132. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1133. BNX2X_ISCSI_R2TQE_SIZE;
  1134. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1135. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1136. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1137. cp->num_cqs = req1->num_cqs;
  1138. if (!dev->max_iscsi_conn)
  1139. return 0;
  1140. /* init Tstorm RAM */
  1141. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1142. req1->rq_num_wqes);
  1143. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1144. PAGE_SIZE);
  1145. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1146. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1147. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1148. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1149. req1->num_tasks_per_conn);
  1150. /* init Ustorm RAM */
  1151. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1152. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1153. req1->rq_buffer_size);
  1154. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1155. PAGE_SIZE);
  1156. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1157. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1158. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1159. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1160. req1->num_tasks_per_conn);
  1161. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1162. req1->rq_num_wqes);
  1163. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1164. req1->cq_num_wqes);
  1165. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1166. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1167. /* init Xstorm RAM */
  1168. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1169. PAGE_SIZE);
  1170. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1171. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1172. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1173. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1174. req1->num_tasks_per_conn);
  1175. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1176. hq_bds);
  1177. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1178. req1->num_tasks_per_conn);
  1179. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1180. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1181. /* init Cstorm RAM */
  1182. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1183. PAGE_SIZE);
  1184. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1185. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1186. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1187. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1188. req1->num_tasks_per_conn);
  1189. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1190. req1->cq_num_wqes);
  1191. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1192. hq_bds);
  1193. return 0;
  1194. }
  1195. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1196. {
  1197. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1198. struct cnic_local *cp = dev->cnic_priv;
  1199. u32 pfid = cp->pfid;
  1200. struct iscsi_kcqe kcqe;
  1201. struct kcqe *cqes[1];
  1202. memset(&kcqe, 0, sizeof(kcqe));
  1203. if (!dev->max_iscsi_conn) {
  1204. kcqe.completion_status =
  1205. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1206. goto done;
  1207. }
  1208. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1209. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1210. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1211. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1212. req2->error_bit_map[1]);
  1213. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1214. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1215. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1216. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1217. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1218. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1219. req2->error_bit_map[1]);
  1220. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1221. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1222. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1223. done:
  1224. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1225. cqes[0] = (struct kcqe *) &kcqe;
  1226. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1227. return 0;
  1228. }
  1229. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1230. {
  1231. struct cnic_local *cp = dev->cnic_priv;
  1232. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1233. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1234. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1235. cnic_free_dma(dev, &iscsi->hq_info);
  1236. cnic_free_dma(dev, &iscsi->r2tq_info);
  1237. cnic_free_dma(dev, &iscsi->task_array_info);
  1238. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1239. } else {
  1240. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1241. }
  1242. ctx->cid = 0;
  1243. }
  1244. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1245. {
  1246. u32 cid;
  1247. int ret, pages;
  1248. struct cnic_local *cp = dev->cnic_priv;
  1249. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1250. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1251. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1252. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1253. if (cid == -1) {
  1254. ret = -ENOMEM;
  1255. goto error;
  1256. }
  1257. ctx->cid = cid;
  1258. return 0;
  1259. }
  1260. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1261. if (cid == -1) {
  1262. ret = -ENOMEM;
  1263. goto error;
  1264. }
  1265. ctx->cid = cid;
  1266. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1267. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1268. if (ret)
  1269. goto error;
  1270. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1271. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1272. if (ret)
  1273. goto error;
  1274. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1275. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1276. if (ret)
  1277. goto error;
  1278. return 0;
  1279. error:
  1280. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1281. return ret;
  1282. }
  1283. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1284. struct regpair *ctx_addr)
  1285. {
  1286. struct cnic_local *cp = dev->cnic_priv;
  1287. struct cnic_eth_dev *ethdev = cp->ethdev;
  1288. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1289. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1290. unsigned long align_off = 0;
  1291. dma_addr_t ctx_map;
  1292. void *ctx;
  1293. if (cp->ctx_align) {
  1294. unsigned long mask = cp->ctx_align - 1;
  1295. if (cp->ctx_arr[blk].mapping & mask)
  1296. align_off = cp->ctx_align -
  1297. (cp->ctx_arr[blk].mapping & mask);
  1298. }
  1299. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1300. (off * BNX2X_CONTEXT_MEM_SIZE);
  1301. ctx = cp->ctx_arr[blk].ctx + align_off +
  1302. (off * BNX2X_CONTEXT_MEM_SIZE);
  1303. if (init)
  1304. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1305. ctx_addr->lo = ctx_map & 0xffffffff;
  1306. ctx_addr->hi = (u64) ctx_map >> 32;
  1307. return ctx;
  1308. }
  1309. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1310. u32 num)
  1311. {
  1312. struct cnic_local *cp = dev->cnic_priv;
  1313. struct iscsi_kwqe_conn_offload1 *req1 =
  1314. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1315. struct iscsi_kwqe_conn_offload2 *req2 =
  1316. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1317. struct iscsi_kwqe_conn_offload3 *req3;
  1318. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1319. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1320. u32 cid = ctx->cid;
  1321. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1322. struct iscsi_context *ictx;
  1323. struct regpair context_addr;
  1324. int i, j, n = 2, n_max;
  1325. ctx->ctx_flags = 0;
  1326. if (!req2->num_additional_wqes)
  1327. return -EINVAL;
  1328. n_max = req2->num_additional_wqes + 2;
  1329. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1330. if (ictx == NULL)
  1331. return -ENOMEM;
  1332. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1333. ictx->xstorm_ag_context.hq_prod = 1;
  1334. ictx->xstorm_st_context.iscsi.first_burst_length =
  1335. ISCSI_DEF_FIRST_BURST_LEN;
  1336. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1337. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1338. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1339. req1->sq_page_table_addr_lo;
  1340. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1341. req1->sq_page_table_addr_hi;
  1342. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1343. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1344. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1345. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1346. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1347. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1348. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1349. iscsi->hq_info.pgtbl[0];
  1350. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1351. iscsi->hq_info.pgtbl[1];
  1352. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1353. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1354. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1355. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1356. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1357. iscsi->r2tq_info.pgtbl[0];
  1358. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1359. iscsi->r2tq_info.pgtbl[1];
  1360. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1361. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1362. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1363. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1364. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1365. BNX2X_ISCSI_PBL_NOT_CACHED;
  1366. ictx->xstorm_st_context.iscsi.flags.flags |=
  1367. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1368. ictx->xstorm_st_context.iscsi.flags.flags |=
  1369. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1370. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1371. /* TSTORM requires the base address of RQ DB & not PTE */
  1372. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1373. req2->rq_page_table_addr_lo & PAGE_MASK;
  1374. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1375. req2->rq_page_table_addr_hi;
  1376. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1377. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1378. ictx->tstorm_st_context.tcp.flags2 |=
  1379. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1380. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1381. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1382. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1383. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1384. req2->rq_page_table_addr_lo;
  1385. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1386. req2->rq_page_table_addr_hi;
  1387. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1388. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1389. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1390. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1391. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1392. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1393. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1394. iscsi->r2tq_info.pgtbl[0];
  1395. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1396. iscsi->r2tq_info.pgtbl[1];
  1397. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1398. req1->cq_page_table_addr_lo;
  1399. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1400. req1->cq_page_table_addr_hi;
  1401. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1402. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1403. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1404. ictx->ustorm_st_context.task_pbe_cache_index =
  1405. BNX2X_ISCSI_PBL_NOT_CACHED;
  1406. ictx->ustorm_st_context.task_pdu_cache_index =
  1407. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1408. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1409. if (j == 3) {
  1410. if (n >= n_max)
  1411. break;
  1412. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1413. j = 0;
  1414. }
  1415. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1416. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1417. req3->qp_first_pte[j].hi;
  1418. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1419. req3->qp_first_pte[j].lo;
  1420. }
  1421. ictx->ustorm_st_context.task_pbl_base.lo =
  1422. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1423. ictx->ustorm_st_context.task_pbl_base.hi =
  1424. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1425. ictx->ustorm_st_context.tce_phy_addr.lo =
  1426. iscsi->task_array_info.pgtbl[0];
  1427. ictx->ustorm_st_context.tce_phy_addr.hi =
  1428. iscsi->task_array_info.pgtbl[1];
  1429. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1430. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1431. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1432. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1433. ISCSI_DEF_MAX_BURST_LEN;
  1434. ictx->ustorm_st_context.negotiated_rx |=
  1435. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1436. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1437. ictx->cstorm_st_context.hq_pbl_base.lo =
  1438. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1439. ictx->cstorm_st_context.hq_pbl_base.hi =
  1440. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1441. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1442. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1443. ictx->cstorm_st_context.task_pbl_base.lo =
  1444. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1445. ictx->cstorm_st_context.task_pbl_base.hi =
  1446. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1447. /* CSTORM and USTORM initialization is different, CSTORM requires
  1448. * CQ DB base & not PTE addr */
  1449. ictx->cstorm_st_context.cq_db_base.lo =
  1450. req1->cq_page_table_addr_lo & PAGE_MASK;
  1451. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1452. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1453. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1454. for (i = 0; i < cp->num_cqs; i++) {
  1455. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1456. ISCSI_INITIAL_SN;
  1457. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1458. ISCSI_INITIAL_SN;
  1459. }
  1460. ictx->xstorm_ag_context.cdu_reserved =
  1461. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1462. ISCSI_CONNECTION_TYPE);
  1463. ictx->ustorm_ag_context.cdu_usage =
  1464. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1465. ISCSI_CONNECTION_TYPE);
  1466. return 0;
  1467. }
  1468. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1469. u32 num, int *work)
  1470. {
  1471. struct iscsi_kwqe_conn_offload1 *req1;
  1472. struct iscsi_kwqe_conn_offload2 *req2;
  1473. struct cnic_local *cp = dev->cnic_priv;
  1474. struct cnic_context *ctx;
  1475. struct iscsi_kcqe kcqe;
  1476. struct kcqe *cqes[1];
  1477. u32 l5_cid;
  1478. int ret = 0;
  1479. if (num < 2) {
  1480. *work = num;
  1481. return -EINVAL;
  1482. }
  1483. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1484. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1485. if ((num - 2) < req2->num_additional_wqes) {
  1486. *work = num;
  1487. return -EINVAL;
  1488. }
  1489. *work = 2 + req2->num_additional_wqes;
  1490. l5_cid = req1->iscsi_conn_id;
  1491. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1492. return -EINVAL;
  1493. memset(&kcqe, 0, sizeof(kcqe));
  1494. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1495. kcqe.iscsi_conn_id = l5_cid;
  1496. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1497. ctx = &cp->ctx_tbl[l5_cid];
  1498. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1499. kcqe.completion_status =
  1500. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1501. goto done;
  1502. }
  1503. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1504. atomic_dec(&cp->iscsi_conn);
  1505. goto done;
  1506. }
  1507. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1508. if (ret) {
  1509. atomic_dec(&cp->iscsi_conn);
  1510. ret = 0;
  1511. goto done;
  1512. }
  1513. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1514. if (ret < 0) {
  1515. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1516. atomic_dec(&cp->iscsi_conn);
  1517. goto done;
  1518. }
  1519. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1520. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1521. done:
  1522. cqes[0] = (struct kcqe *) &kcqe;
  1523. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1524. return ret;
  1525. }
  1526. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1527. {
  1528. struct cnic_local *cp = dev->cnic_priv;
  1529. struct iscsi_kwqe_conn_update *req =
  1530. (struct iscsi_kwqe_conn_update *) kwqe;
  1531. void *data;
  1532. union l5cm_specific_data l5_data;
  1533. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1534. int ret;
  1535. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1536. return -EINVAL;
  1537. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1538. if (!data)
  1539. return -ENOMEM;
  1540. memcpy(data, kwqe, sizeof(struct kwqe));
  1541. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1542. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1543. return ret;
  1544. }
  1545. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1546. {
  1547. struct cnic_local *cp = dev->cnic_priv;
  1548. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1549. union l5cm_specific_data l5_data;
  1550. int ret;
  1551. u32 hw_cid;
  1552. init_waitqueue_head(&ctx->waitq);
  1553. ctx->wait_cond = 0;
  1554. memset(&l5_data, 0, sizeof(l5_data));
  1555. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1556. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1557. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1558. if (ret == 0)
  1559. wait_event(ctx->waitq, ctx->wait_cond);
  1560. return ret;
  1561. }
  1562. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1563. {
  1564. struct cnic_local *cp = dev->cnic_priv;
  1565. struct iscsi_kwqe_conn_destroy *req =
  1566. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1567. u32 l5_cid = req->reserved0;
  1568. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1569. int ret = 0;
  1570. struct iscsi_kcqe kcqe;
  1571. struct kcqe *cqes[1];
  1572. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1573. goto skip_cfc_delete;
  1574. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1575. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1576. if (delta > (2 * HZ))
  1577. delta = 0;
  1578. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1579. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1580. goto destroy_reply;
  1581. }
  1582. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1583. skip_cfc_delete:
  1584. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1585. atomic_dec(&cp->iscsi_conn);
  1586. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1587. destroy_reply:
  1588. memset(&kcqe, 0, sizeof(kcqe));
  1589. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1590. kcqe.iscsi_conn_id = l5_cid;
  1591. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1592. kcqe.iscsi_conn_context_id = req->context_id;
  1593. cqes[0] = (struct kcqe *) &kcqe;
  1594. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1595. return ret;
  1596. }
  1597. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1598. struct l4_kwq_connect_req1 *kwqe1,
  1599. struct l4_kwq_connect_req3 *kwqe3,
  1600. struct l5cm_active_conn_buffer *conn_buf)
  1601. {
  1602. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1603. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1604. &conn_buf->xstorm_conn_buffer;
  1605. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1606. &conn_buf->tstorm_conn_buffer;
  1607. struct regpair context_addr;
  1608. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1609. struct in6_addr src_ip, dst_ip;
  1610. int i;
  1611. u32 *addrp;
  1612. addrp = (u32 *) &conn_addr->local_ip_addr;
  1613. for (i = 0; i < 4; i++, addrp++)
  1614. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1615. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1616. for (i = 0; i < 4; i++, addrp++)
  1617. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1618. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1619. xstorm_buf->context_addr.hi = context_addr.hi;
  1620. xstorm_buf->context_addr.lo = context_addr.lo;
  1621. xstorm_buf->mss = 0xffff;
  1622. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1623. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1624. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1625. xstorm_buf->pseudo_header_checksum =
  1626. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1627. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1628. tstorm_buf->params |=
  1629. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1630. if (kwqe3->ka_timeout) {
  1631. tstorm_buf->ka_enable = 1;
  1632. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1633. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1634. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1635. }
  1636. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1637. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1638. tstorm_buf->max_rt_time = 0xffffffff;
  1639. }
  1640. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1641. {
  1642. struct cnic_local *cp = dev->cnic_priv;
  1643. u32 pfid = cp->pfid;
  1644. u8 *mac = dev->mac_addr;
  1645. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1646. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1647. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1648. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1649. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1650. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1651. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1652. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1653. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1654. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1655. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1656. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1657. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1658. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1659. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1660. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1661. mac[4]);
  1662. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1663. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1664. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1665. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1666. mac[2]);
  1667. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1668. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1669. mac[1]);
  1670. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1671. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1672. mac[0]);
  1673. }
  1674. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1675. {
  1676. struct cnic_local *cp = dev->cnic_priv;
  1677. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1678. u16 tstorm_flags = 0;
  1679. if (tcp_ts) {
  1680. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1681. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1682. }
  1683. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1684. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1685. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1686. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1687. }
  1688. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1689. u32 num, int *work)
  1690. {
  1691. struct cnic_local *cp = dev->cnic_priv;
  1692. struct l4_kwq_connect_req1 *kwqe1 =
  1693. (struct l4_kwq_connect_req1 *) wqes[0];
  1694. struct l4_kwq_connect_req3 *kwqe3;
  1695. struct l5cm_active_conn_buffer *conn_buf;
  1696. struct l5cm_conn_addr_params *conn_addr;
  1697. union l5cm_specific_data l5_data;
  1698. u32 l5_cid = kwqe1->pg_cid;
  1699. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1700. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1701. int ret;
  1702. if (num < 2) {
  1703. *work = num;
  1704. return -EINVAL;
  1705. }
  1706. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1707. *work = 3;
  1708. else
  1709. *work = 2;
  1710. if (num < *work) {
  1711. *work = num;
  1712. return -EINVAL;
  1713. }
  1714. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1715. netdev_err(dev->netdev, "conn_buf size too big\n");
  1716. return -ENOMEM;
  1717. }
  1718. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1719. if (!conn_buf)
  1720. return -ENOMEM;
  1721. memset(conn_buf, 0, sizeof(*conn_buf));
  1722. conn_addr = &conn_buf->conn_addr_buf;
  1723. conn_addr->remote_addr_0 = csk->ha[0];
  1724. conn_addr->remote_addr_1 = csk->ha[1];
  1725. conn_addr->remote_addr_2 = csk->ha[2];
  1726. conn_addr->remote_addr_3 = csk->ha[3];
  1727. conn_addr->remote_addr_4 = csk->ha[4];
  1728. conn_addr->remote_addr_5 = csk->ha[5];
  1729. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1730. struct l4_kwq_connect_req2 *kwqe2 =
  1731. (struct l4_kwq_connect_req2 *) wqes[1];
  1732. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1733. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1734. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1735. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1736. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1737. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1738. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1739. }
  1740. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1741. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1742. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1743. conn_addr->local_tcp_port = kwqe1->src_port;
  1744. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1745. conn_addr->pmtu = kwqe3->pmtu;
  1746. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1747. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1748. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1749. cnic_bnx2x_set_tcp_timestamp(dev,
  1750. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1751. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1752. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1753. if (!ret)
  1754. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1755. return ret;
  1756. }
  1757. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1758. {
  1759. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1760. union l5cm_specific_data l5_data;
  1761. int ret;
  1762. memset(&l5_data, 0, sizeof(l5_data));
  1763. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1764. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1765. return ret;
  1766. }
  1767. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1768. {
  1769. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1770. union l5cm_specific_data l5_data;
  1771. int ret;
  1772. memset(&l5_data, 0, sizeof(l5_data));
  1773. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1774. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1775. return ret;
  1776. }
  1777. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1778. {
  1779. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1780. struct l4_kcq kcqe;
  1781. struct kcqe *cqes[1];
  1782. memset(&kcqe, 0, sizeof(kcqe));
  1783. kcqe.pg_host_opaque = req->host_opaque;
  1784. kcqe.pg_cid = req->host_opaque;
  1785. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1786. cqes[0] = (struct kcqe *) &kcqe;
  1787. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1788. return 0;
  1789. }
  1790. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1791. {
  1792. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1793. struct l4_kcq kcqe;
  1794. struct kcqe *cqes[1];
  1795. memset(&kcqe, 0, sizeof(kcqe));
  1796. kcqe.pg_host_opaque = req->pg_host_opaque;
  1797. kcqe.pg_cid = req->pg_cid;
  1798. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1799. cqes[0] = (struct kcqe *) &kcqe;
  1800. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1801. return 0;
  1802. }
  1803. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1804. {
  1805. struct fcoe_kwqe_stat *req;
  1806. struct fcoe_stat_ramrod_params *fcoe_stat;
  1807. union l5cm_specific_data l5_data;
  1808. struct cnic_local *cp = dev->cnic_priv;
  1809. int ret;
  1810. u32 cid;
  1811. req = (struct fcoe_kwqe_stat *) kwqe;
  1812. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1813. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1814. if (!fcoe_stat)
  1815. return -ENOMEM;
  1816. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1817. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1818. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
  1819. FCOE_CONNECTION_TYPE, &l5_data);
  1820. return ret;
  1821. }
  1822. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1823. u32 num, int *work)
  1824. {
  1825. int ret;
  1826. struct cnic_local *cp = dev->cnic_priv;
  1827. u32 cid;
  1828. struct fcoe_init_ramrod_params *fcoe_init;
  1829. struct fcoe_kwqe_init1 *req1;
  1830. struct fcoe_kwqe_init2 *req2;
  1831. struct fcoe_kwqe_init3 *req3;
  1832. union l5cm_specific_data l5_data;
  1833. if (num < 3) {
  1834. *work = num;
  1835. return -EINVAL;
  1836. }
  1837. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1838. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1839. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1840. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1841. *work = 1;
  1842. return -EINVAL;
  1843. }
  1844. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1845. *work = 2;
  1846. return -EINVAL;
  1847. }
  1848. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1849. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1850. return -ENOMEM;
  1851. }
  1852. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1853. if (!fcoe_init)
  1854. return -ENOMEM;
  1855. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1856. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1857. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1858. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1859. fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
  1860. fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
  1861. fcoe_init->eq_next_page_addr.lo =
  1862. cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
  1863. fcoe_init->eq_next_page_addr.hi =
  1864. (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
  1865. fcoe_init->sb_num = cp->status_blk_num;
  1866. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1867. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1868. cp->kcq2.sw_prod_idx = 0;
  1869. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1870. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
  1871. FCOE_CONNECTION_TYPE, &l5_data);
  1872. *work = 3;
  1873. return ret;
  1874. }
  1875. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1876. u32 num, int *work)
  1877. {
  1878. int ret = 0;
  1879. u32 cid = -1, l5_cid;
  1880. struct cnic_local *cp = dev->cnic_priv;
  1881. struct fcoe_kwqe_conn_offload1 *req1;
  1882. struct fcoe_kwqe_conn_offload2 *req2;
  1883. struct fcoe_kwqe_conn_offload3 *req3;
  1884. struct fcoe_kwqe_conn_offload4 *req4;
  1885. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1886. struct cnic_context *ctx;
  1887. struct fcoe_context *fctx;
  1888. struct regpair ctx_addr;
  1889. union l5cm_specific_data l5_data;
  1890. struct fcoe_kcqe kcqe;
  1891. struct kcqe *cqes[1];
  1892. if (num < 4) {
  1893. *work = num;
  1894. return -EINVAL;
  1895. }
  1896. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1897. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1898. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1899. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1900. *work = 4;
  1901. l5_cid = req1->fcoe_conn_id;
  1902. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1903. goto err_reply;
  1904. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1905. ctx = &cp->ctx_tbl[l5_cid];
  1906. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1907. goto err_reply;
  1908. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1909. if (ret) {
  1910. ret = 0;
  1911. goto err_reply;
  1912. }
  1913. cid = ctx->cid;
  1914. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1915. if (fctx) {
  1916. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1917. u32 val;
  1918. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1919. FCOE_CONNECTION_TYPE);
  1920. fctx->xstorm_ag_context.cdu_reserved = val;
  1921. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1922. FCOE_CONNECTION_TYPE);
  1923. fctx->ustorm_ag_context.cdu_usage = val;
  1924. }
  1925. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1926. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1927. goto err_reply;
  1928. }
  1929. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1930. if (!fcoe_offload)
  1931. goto err_reply;
  1932. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1933. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1934. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1935. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1936. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1937. cid = BNX2X_HW_CID(cp, cid);
  1938. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1939. FCOE_CONNECTION_TYPE, &l5_data);
  1940. if (!ret)
  1941. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1942. return ret;
  1943. err_reply:
  1944. if (cid != -1)
  1945. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1946. memset(&kcqe, 0, sizeof(kcqe));
  1947. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1948. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1949. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1950. cqes[0] = (struct kcqe *) &kcqe;
  1951. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1952. return ret;
  1953. }
  1954. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1955. {
  1956. struct fcoe_kwqe_conn_enable_disable *req;
  1957. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1958. union l5cm_specific_data l5_data;
  1959. int ret;
  1960. u32 cid, l5_cid;
  1961. struct cnic_local *cp = dev->cnic_priv;
  1962. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1963. cid = req->context_id;
  1964. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1965. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1966. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1967. return -ENOMEM;
  1968. }
  1969. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1970. if (!fcoe_enable)
  1971. return -ENOMEM;
  1972. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1973. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1974. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1975. FCOE_CONNECTION_TYPE, &l5_data);
  1976. return ret;
  1977. }
  1978. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1979. {
  1980. struct fcoe_kwqe_conn_enable_disable *req;
  1981. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1982. union l5cm_specific_data l5_data;
  1983. int ret;
  1984. u32 cid, l5_cid;
  1985. struct cnic_local *cp = dev->cnic_priv;
  1986. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1987. cid = req->context_id;
  1988. l5_cid = req->conn_id;
  1989. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1990. return -EINVAL;
  1991. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1992. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1993. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1994. return -ENOMEM;
  1995. }
  1996. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1997. if (!fcoe_disable)
  1998. return -ENOMEM;
  1999. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2000. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2001. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2002. FCOE_CONNECTION_TYPE, &l5_data);
  2003. return ret;
  2004. }
  2005. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2006. {
  2007. struct fcoe_kwqe_conn_destroy *req;
  2008. union l5cm_specific_data l5_data;
  2009. int ret;
  2010. u32 cid, l5_cid;
  2011. struct cnic_local *cp = dev->cnic_priv;
  2012. struct cnic_context *ctx;
  2013. struct fcoe_kcqe kcqe;
  2014. struct kcqe *cqes[1];
  2015. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2016. cid = req->context_id;
  2017. l5_cid = req->conn_id;
  2018. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  2019. return -EINVAL;
  2020. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2021. ctx = &cp->ctx_tbl[l5_cid];
  2022. init_waitqueue_head(&ctx->waitq);
  2023. ctx->wait_cond = 0;
  2024. memset(&l5_data, 0, sizeof(l5_data));
  2025. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2026. FCOE_CONNECTION_TYPE, &l5_data);
  2027. if (ret == 0) {
  2028. wait_event(ctx->waitq, ctx->wait_cond);
  2029. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2030. queue_delayed_work(cnic_wq, &cp->delete_task,
  2031. msecs_to_jiffies(2000));
  2032. }
  2033. memset(&kcqe, 0, sizeof(kcqe));
  2034. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2035. kcqe.fcoe_conn_id = req->conn_id;
  2036. kcqe.fcoe_conn_context_id = cid;
  2037. cqes[0] = (struct kcqe *) &kcqe;
  2038. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2039. return ret;
  2040. }
  2041. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2042. {
  2043. struct fcoe_kwqe_destroy *req;
  2044. union l5cm_specific_data l5_data;
  2045. struct cnic_local *cp = dev->cnic_priv;
  2046. int ret;
  2047. u32 cid;
  2048. req = (struct fcoe_kwqe_destroy *) kwqe;
  2049. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2050. memset(&l5_data, 0, sizeof(l5_data));
  2051. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
  2052. FCOE_CONNECTION_TYPE, &l5_data);
  2053. return ret;
  2054. }
  2055. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2056. struct kwqe *wqes[], u32 num_wqes)
  2057. {
  2058. int i, work, ret;
  2059. u32 opcode;
  2060. struct kwqe *kwqe;
  2061. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2062. return -EAGAIN; /* bnx2 is down */
  2063. for (i = 0; i < num_wqes; ) {
  2064. kwqe = wqes[i];
  2065. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2066. work = 1;
  2067. switch (opcode) {
  2068. case ISCSI_KWQE_OPCODE_INIT1:
  2069. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2070. break;
  2071. case ISCSI_KWQE_OPCODE_INIT2:
  2072. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2073. break;
  2074. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2075. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2076. num_wqes - i, &work);
  2077. break;
  2078. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2079. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2080. break;
  2081. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2082. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2083. break;
  2084. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2085. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2086. &work);
  2087. break;
  2088. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2089. ret = cnic_bnx2x_close(dev, kwqe);
  2090. break;
  2091. case L4_KWQE_OPCODE_VALUE_RESET:
  2092. ret = cnic_bnx2x_reset(dev, kwqe);
  2093. break;
  2094. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2095. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2096. break;
  2097. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2098. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2099. break;
  2100. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2101. ret = 0;
  2102. break;
  2103. default:
  2104. ret = 0;
  2105. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2106. opcode);
  2107. break;
  2108. }
  2109. if (ret < 0)
  2110. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2111. opcode);
  2112. i += work;
  2113. }
  2114. return 0;
  2115. }
  2116. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2117. struct kwqe *wqes[], u32 num_wqes)
  2118. {
  2119. struct cnic_local *cp = dev->cnic_priv;
  2120. int i, work, ret;
  2121. u32 opcode;
  2122. struct kwqe *kwqe;
  2123. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2124. return -EAGAIN; /* bnx2 is down */
  2125. if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
  2126. return -EINVAL;
  2127. for (i = 0; i < num_wqes; ) {
  2128. kwqe = wqes[i];
  2129. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2130. work = 1;
  2131. switch (opcode) {
  2132. case FCOE_KWQE_OPCODE_INIT1:
  2133. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2134. num_wqes - i, &work);
  2135. break;
  2136. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2137. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2138. num_wqes - i, &work);
  2139. break;
  2140. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2141. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2142. break;
  2143. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2144. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2145. break;
  2146. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2147. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2148. break;
  2149. case FCOE_KWQE_OPCODE_DESTROY:
  2150. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2151. break;
  2152. case FCOE_KWQE_OPCODE_STAT:
  2153. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2154. break;
  2155. default:
  2156. ret = 0;
  2157. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2158. opcode);
  2159. break;
  2160. }
  2161. if (ret < 0)
  2162. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2163. opcode);
  2164. i += work;
  2165. }
  2166. return 0;
  2167. }
  2168. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2169. u32 num_wqes)
  2170. {
  2171. int ret = -EINVAL;
  2172. u32 layer_code;
  2173. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2174. return -EAGAIN; /* bnx2x is down */
  2175. if (!num_wqes)
  2176. return 0;
  2177. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2178. switch (layer_code) {
  2179. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2180. case KWQE_FLAGS_LAYER_MASK_L4:
  2181. case KWQE_FLAGS_LAYER_MASK_L2:
  2182. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2183. break;
  2184. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2185. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2186. break;
  2187. }
  2188. return ret;
  2189. }
  2190. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2191. {
  2192. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2193. return KCQE_FLAGS_LAYER_MASK_L4;
  2194. return opflag & KCQE_FLAGS_LAYER_MASK;
  2195. }
  2196. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2197. {
  2198. struct cnic_local *cp = dev->cnic_priv;
  2199. int i, j, comp = 0;
  2200. i = 0;
  2201. j = 1;
  2202. while (num_cqes) {
  2203. struct cnic_ulp_ops *ulp_ops;
  2204. int ulp_type;
  2205. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2206. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2207. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2208. comp++;
  2209. while (j < num_cqes) {
  2210. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2211. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2212. break;
  2213. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2214. comp++;
  2215. j++;
  2216. }
  2217. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2218. ulp_type = CNIC_ULP_RDMA;
  2219. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2220. ulp_type = CNIC_ULP_ISCSI;
  2221. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2222. ulp_type = CNIC_ULP_FCOE;
  2223. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2224. ulp_type = CNIC_ULP_L4;
  2225. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2226. goto end;
  2227. else {
  2228. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2229. kcqe_op_flag);
  2230. goto end;
  2231. }
  2232. rcu_read_lock();
  2233. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2234. if (likely(ulp_ops)) {
  2235. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2236. cp->completed_kcq + i, j);
  2237. }
  2238. rcu_read_unlock();
  2239. end:
  2240. num_cqes -= j;
  2241. i += j;
  2242. j = 1;
  2243. }
  2244. if (unlikely(comp))
  2245. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2246. }
  2247. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2248. {
  2249. struct cnic_local *cp = dev->cnic_priv;
  2250. u16 i, ri, hw_prod, last;
  2251. struct kcqe *kcqe;
  2252. int kcqe_cnt = 0, last_cnt = 0;
  2253. i = ri = last = info->sw_prod_idx;
  2254. ri &= MAX_KCQ_IDX;
  2255. hw_prod = *info->hw_prod_idx_ptr;
  2256. hw_prod = info->hw_idx(hw_prod);
  2257. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2258. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2259. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2260. i = info->next_idx(i);
  2261. ri = i & MAX_KCQ_IDX;
  2262. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2263. last_cnt = kcqe_cnt;
  2264. last = i;
  2265. }
  2266. }
  2267. info->sw_prod_idx = last;
  2268. return last_cnt;
  2269. }
  2270. static int cnic_l2_completion(struct cnic_local *cp)
  2271. {
  2272. u16 hw_cons, sw_cons;
  2273. struct cnic_uio_dev *udev = cp->udev;
  2274. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2275. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2276. u32 cmd;
  2277. int comp = 0;
  2278. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2279. return 0;
  2280. hw_cons = *cp->rx_cons_ptr;
  2281. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2282. hw_cons++;
  2283. sw_cons = cp->rx_cons;
  2284. while (sw_cons != hw_cons) {
  2285. u8 cqe_fp_flags;
  2286. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2287. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2288. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2289. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2290. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2291. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2292. cmd == RAMROD_CMD_ID_ETH_HALT)
  2293. comp++;
  2294. }
  2295. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2296. }
  2297. return comp;
  2298. }
  2299. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2300. {
  2301. u16 rx_cons, tx_cons;
  2302. int comp = 0;
  2303. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2304. return;
  2305. rx_cons = *cp->rx_cons_ptr;
  2306. tx_cons = *cp->tx_cons_ptr;
  2307. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2308. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2309. comp = cnic_l2_completion(cp);
  2310. cp->tx_cons = tx_cons;
  2311. cp->rx_cons = rx_cons;
  2312. if (cp->udev)
  2313. uio_event_notify(&cp->udev->cnic_uinfo);
  2314. }
  2315. if (comp)
  2316. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2317. }
  2318. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2319. {
  2320. struct cnic_local *cp = dev->cnic_priv;
  2321. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2322. int kcqe_cnt;
  2323. /* status block index must be read before reading other fields */
  2324. rmb();
  2325. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2326. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2327. service_kcqes(dev, kcqe_cnt);
  2328. /* Tell compiler that status_blk fields can change. */
  2329. barrier();
  2330. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2331. /* status block index must be read first */
  2332. rmb();
  2333. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2334. }
  2335. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2336. cnic_chk_pkt_rings(cp);
  2337. return status_idx;
  2338. }
  2339. static int cnic_service_bnx2(void *data, void *status_blk)
  2340. {
  2341. struct cnic_dev *dev = data;
  2342. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2343. struct status_block *sblk = status_blk;
  2344. return sblk->status_idx;
  2345. }
  2346. return cnic_service_bnx2_queues(dev);
  2347. }
  2348. static void cnic_service_bnx2_msix(unsigned long data)
  2349. {
  2350. struct cnic_dev *dev = (struct cnic_dev *) data;
  2351. struct cnic_local *cp = dev->cnic_priv;
  2352. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2353. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2354. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2355. }
  2356. static void cnic_doirq(struct cnic_dev *dev)
  2357. {
  2358. struct cnic_local *cp = dev->cnic_priv;
  2359. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2360. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2361. prefetch(cp->status_blk.gen);
  2362. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2363. tasklet_schedule(&cp->cnic_irq_task);
  2364. }
  2365. }
  2366. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2367. {
  2368. struct cnic_dev *dev = dev_instance;
  2369. struct cnic_local *cp = dev->cnic_priv;
  2370. if (cp->ack_int)
  2371. cp->ack_int(dev);
  2372. cnic_doirq(dev);
  2373. return IRQ_HANDLED;
  2374. }
  2375. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2376. u16 index, u8 op, u8 update)
  2377. {
  2378. struct cnic_local *cp = dev->cnic_priv;
  2379. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2380. COMMAND_REG_INT_ACK);
  2381. struct igu_ack_register igu_ack;
  2382. igu_ack.status_block_index = index;
  2383. igu_ack.sb_id_and_flags =
  2384. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2385. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2386. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2387. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2388. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2389. }
  2390. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2391. u16 index, u8 op, u8 update)
  2392. {
  2393. struct igu_regular cmd_data;
  2394. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2395. cmd_data.sb_id_and_flags =
  2396. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2397. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2398. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2399. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2400. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2401. }
  2402. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2403. {
  2404. struct cnic_local *cp = dev->cnic_priv;
  2405. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2406. IGU_INT_DISABLE, 0);
  2407. }
  2408. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2409. {
  2410. struct cnic_local *cp = dev->cnic_priv;
  2411. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2412. IGU_INT_DISABLE, 0);
  2413. }
  2414. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2415. {
  2416. u32 last_status = *info->status_idx_ptr;
  2417. int kcqe_cnt;
  2418. /* status block index must be read before reading the KCQ */
  2419. rmb();
  2420. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2421. service_kcqes(dev, kcqe_cnt);
  2422. /* Tell compiler that sblk fields can change. */
  2423. barrier();
  2424. last_status = *info->status_idx_ptr;
  2425. /* status block index must be read before reading the KCQ */
  2426. rmb();
  2427. }
  2428. return last_status;
  2429. }
  2430. static void cnic_service_bnx2x_bh(unsigned long data)
  2431. {
  2432. struct cnic_dev *dev = (struct cnic_dev *) data;
  2433. struct cnic_local *cp = dev->cnic_priv;
  2434. u32 status_idx, new_status_idx;
  2435. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2436. return;
  2437. while (1) {
  2438. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2439. CNIC_WR16(dev, cp->kcq1.io_addr,
  2440. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2441. if (!BNX2X_CHIP_IS_E2(cp->chip_id)) {
  2442. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2443. status_idx, IGU_INT_ENABLE, 1);
  2444. break;
  2445. }
  2446. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2447. if (new_status_idx != status_idx)
  2448. continue;
  2449. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2450. MAX_KCQ_IDX);
  2451. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2452. status_idx, IGU_INT_ENABLE, 1);
  2453. break;
  2454. }
  2455. }
  2456. static int cnic_service_bnx2x(void *data, void *status_blk)
  2457. {
  2458. struct cnic_dev *dev = data;
  2459. struct cnic_local *cp = dev->cnic_priv;
  2460. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2461. cnic_doirq(dev);
  2462. cnic_chk_pkt_rings(cp);
  2463. return 0;
  2464. }
  2465. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2466. {
  2467. struct cnic_ulp_ops *ulp_ops;
  2468. if (if_type == CNIC_ULP_ISCSI)
  2469. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2470. mutex_lock(&cnic_lock);
  2471. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2472. lockdep_is_held(&cnic_lock));
  2473. if (!ulp_ops) {
  2474. mutex_unlock(&cnic_lock);
  2475. return;
  2476. }
  2477. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2478. mutex_unlock(&cnic_lock);
  2479. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2480. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2481. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2482. }
  2483. static void cnic_ulp_stop(struct cnic_dev *dev)
  2484. {
  2485. struct cnic_local *cp = dev->cnic_priv;
  2486. int if_type;
  2487. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2488. cnic_ulp_stop_one(cp, if_type);
  2489. }
  2490. static void cnic_ulp_start(struct cnic_dev *dev)
  2491. {
  2492. struct cnic_local *cp = dev->cnic_priv;
  2493. int if_type;
  2494. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2495. struct cnic_ulp_ops *ulp_ops;
  2496. mutex_lock(&cnic_lock);
  2497. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2498. lockdep_is_held(&cnic_lock));
  2499. if (!ulp_ops || !ulp_ops->cnic_start) {
  2500. mutex_unlock(&cnic_lock);
  2501. continue;
  2502. }
  2503. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2504. mutex_unlock(&cnic_lock);
  2505. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2506. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2507. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2508. }
  2509. }
  2510. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2511. {
  2512. struct cnic_dev *dev = data;
  2513. switch (info->cmd) {
  2514. case CNIC_CTL_STOP_CMD:
  2515. cnic_hold(dev);
  2516. cnic_ulp_stop(dev);
  2517. cnic_stop_hw(dev);
  2518. cnic_put(dev);
  2519. break;
  2520. case CNIC_CTL_START_CMD:
  2521. cnic_hold(dev);
  2522. if (!cnic_start_hw(dev))
  2523. cnic_ulp_start(dev);
  2524. cnic_put(dev);
  2525. break;
  2526. case CNIC_CTL_STOP_ISCSI_CMD: {
  2527. struct cnic_local *cp = dev->cnic_priv;
  2528. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2529. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2530. break;
  2531. }
  2532. case CNIC_CTL_COMPLETION_CMD: {
  2533. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2534. u32 l5_cid;
  2535. struct cnic_local *cp = dev->cnic_priv;
  2536. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2537. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2538. ctx->wait_cond = 1;
  2539. wake_up(&ctx->waitq);
  2540. }
  2541. break;
  2542. }
  2543. default:
  2544. return -EINVAL;
  2545. }
  2546. return 0;
  2547. }
  2548. static void cnic_ulp_init(struct cnic_dev *dev)
  2549. {
  2550. int i;
  2551. struct cnic_local *cp = dev->cnic_priv;
  2552. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2553. struct cnic_ulp_ops *ulp_ops;
  2554. mutex_lock(&cnic_lock);
  2555. ulp_ops = cnic_ulp_tbl_prot(i);
  2556. if (!ulp_ops || !ulp_ops->cnic_init) {
  2557. mutex_unlock(&cnic_lock);
  2558. continue;
  2559. }
  2560. ulp_get(ulp_ops);
  2561. mutex_unlock(&cnic_lock);
  2562. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2563. ulp_ops->cnic_init(dev);
  2564. ulp_put(ulp_ops);
  2565. }
  2566. }
  2567. static void cnic_ulp_exit(struct cnic_dev *dev)
  2568. {
  2569. int i;
  2570. struct cnic_local *cp = dev->cnic_priv;
  2571. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2572. struct cnic_ulp_ops *ulp_ops;
  2573. mutex_lock(&cnic_lock);
  2574. ulp_ops = cnic_ulp_tbl_prot(i);
  2575. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2576. mutex_unlock(&cnic_lock);
  2577. continue;
  2578. }
  2579. ulp_get(ulp_ops);
  2580. mutex_unlock(&cnic_lock);
  2581. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2582. ulp_ops->cnic_exit(dev);
  2583. ulp_put(ulp_ops);
  2584. }
  2585. }
  2586. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2587. {
  2588. struct cnic_dev *dev = csk->dev;
  2589. struct l4_kwq_offload_pg *l4kwqe;
  2590. struct kwqe *wqes[1];
  2591. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2592. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2593. wqes[0] = (struct kwqe *) l4kwqe;
  2594. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2595. l4kwqe->flags =
  2596. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2597. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2598. l4kwqe->da0 = csk->ha[0];
  2599. l4kwqe->da1 = csk->ha[1];
  2600. l4kwqe->da2 = csk->ha[2];
  2601. l4kwqe->da3 = csk->ha[3];
  2602. l4kwqe->da4 = csk->ha[4];
  2603. l4kwqe->da5 = csk->ha[5];
  2604. l4kwqe->sa0 = dev->mac_addr[0];
  2605. l4kwqe->sa1 = dev->mac_addr[1];
  2606. l4kwqe->sa2 = dev->mac_addr[2];
  2607. l4kwqe->sa3 = dev->mac_addr[3];
  2608. l4kwqe->sa4 = dev->mac_addr[4];
  2609. l4kwqe->sa5 = dev->mac_addr[5];
  2610. l4kwqe->etype = ETH_P_IP;
  2611. l4kwqe->ipid_start = DEF_IPID_START;
  2612. l4kwqe->host_opaque = csk->l5_cid;
  2613. if (csk->vlan_id) {
  2614. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2615. l4kwqe->vlan_tag = csk->vlan_id;
  2616. l4kwqe->l2hdr_nbytes += 4;
  2617. }
  2618. return dev->submit_kwqes(dev, wqes, 1);
  2619. }
  2620. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2621. {
  2622. struct cnic_dev *dev = csk->dev;
  2623. struct l4_kwq_update_pg *l4kwqe;
  2624. struct kwqe *wqes[1];
  2625. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2626. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2627. wqes[0] = (struct kwqe *) l4kwqe;
  2628. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2629. l4kwqe->flags =
  2630. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2631. l4kwqe->pg_cid = csk->pg_cid;
  2632. l4kwqe->da0 = csk->ha[0];
  2633. l4kwqe->da1 = csk->ha[1];
  2634. l4kwqe->da2 = csk->ha[2];
  2635. l4kwqe->da3 = csk->ha[3];
  2636. l4kwqe->da4 = csk->ha[4];
  2637. l4kwqe->da5 = csk->ha[5];
  2638. l4kwqe->pg_host_opaque = csk->l5_cid;
  2639. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2640. return dev->submit_kwqes(dev, wqes, 1);
  2641. }
  2642. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2643. {
  2644. struct cnic_dev *dev = csk->dev;
  2645. struct l4_kwq_upload *l4kwqe;
  2646. struct kwqe *wqes[1];
  2647. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2648. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2649. wqes[0] = (struct kwqe *) l4kwqe;
  2650. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2651. l4kwqe->flags =
  2652. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2653. l4kwqe->cid = csk->pg_cid;
  2654. return dev->submit_kwqes(dev, wqes, 1);
  2655. }
  2656. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2657. {
  2658. struct cnic_dev *dev = csk->dev;
  2659. struct l4_kwq_connect_req1 *l4kwqe1;
  2660. struct l4_kwq_connect_req2 *l4kwqe2;
  2661. struct l4_kwq_connect_req3 *l4kwqe3;
  2662. struct kwqe *wqes[3];
  2663. u8 tcp_flags = 0;
  2664. int num_wqes = 2;
  2665. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2666. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2667. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2668. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2669. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2670. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2671. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2672. l4kwqe3->flags =
  2673. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2674. l4kwqe3->ka_timeout = csk->ka_timeout;
  2675. l4kwqe3->ka_interval = csk->ka_interval;
  2676. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2677. l4kwqe3->tos = csk->tos;
  2678. l4kwqe3->ttl = csk->ttl;
  2679. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2680. l4kwqe3->pmtu = csk->mtu;
  2681. l4kwqe3->rcv_buf = csk->rcv_buf;
  2682. l4kwqe3->snd_buf = csk->snd_buf;
  2683. l4kwqe3->seed = csk->seed;
  2684. wqes[0] = (struct kwqe *) l4kwqe1;
  2685. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2686. wqes[1] = (struct kwqe *) l4kwqe2;
  2687. wqes[2] = (struct kwqe *) l4kwqe3;
  2688. num_wqes = 3;
  2689. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2690. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2691. l4kwqe2->flags =
  2692. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2693. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2694. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2695. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2696. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2697. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2698. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2699. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2700. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2701. sizeof(struct tcphdr);
  2702. } else {
  2703. wqes[1] = (struct kwqe *) l4kwqe3;
  2704. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2705. sizeof(struct tcphdr);
  2706. }
  2707. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2708. l4kwqe1->flags =
  2709. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2710. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2711. l4kwqe1->cid = csk->cid;
  2712. l4kwqe1->pg_cid = csk->pg_cid;
  2713. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2714. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2715. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2716. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2717. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2718. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2719. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2720. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2721. if (csk->tcp_flags & SK_TCP_NAGLE)
  2722. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2723. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2724. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2725. if (csk->tcp_flags & SK_TCP_SACK)
  2726. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2727. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2728. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2729. l4kwqe1->tcp_flags = tcp_flags;
  2730. return dev->submit_kwqes(dev, wqes, num_wqes);
  2731. }
  2732. static int cnic_cm_close_req(struct cnic_sock *csk)
  2733. {
  2734. struct cnic_dev *dev = csk->dev;
  2735. struct l4_kwq_close_req *l4kwqe;
  2736. struct kwqe *wqes[1];
  2737. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2738. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2739. wqes[0] = (struct kwqe *) l4kwqe;
  2740. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2741. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2742. l4kwqe->cid = csk->cid;
  2743. return dev->submit_kwqes(dev, wqes, 1);
  2744. }
  2745. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2746. {
  2747. struct cnic_dev *dev = csk->dev;
  2748. struct l4_kwq_reset_req *l4kwqe;
  2749. struct kwqe *wqes[1];
  2750. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2751. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2752. wqes[0] = (struct kwqe *) l4kwqe;
  2753. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2754. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2755. l4kwqe->cid = csk->cid;
  2756. return dev->submit_kwqes(dev, wqes, 1);
  2757. }
  2758. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2759. u32 l5_cid, struct cnic_sock **csk, void *context)
  2760. {
  2761. struct cnic_local *cp = dev->cnic_priv;
  2762. struct cnic_sock *csk1;
  2763. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2764. return -EINVAL;
  2765. if (cp->ctx_tbl) {
  2766. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2767. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2768. return -EAGAIN;
  2769. }
  2770. csk1 = &cp->csk_tbl[l5_cid];
  2771. if (atomic_read(&csk1->ref_count))
  2772. return -EAGAIN;
  2773. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2774. return -EBUSY;
  2775. csk1->dev = dev;
  2776. csk1->cid = cid;
  2777. csk1->l5_cid = l5_cid;
  2778. csk1->ulp_type = ulp_type;
  2779. csk1->context = context;
  2780. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2781. csk1->ka_interval = DEF_KA_INTERVAL;
  2782. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2783. csk1->tos = DEF_TOS;
  2784. csk1->ttl = DEF_TTL;
  2785. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2786. csk1->rcv_buf = DEF_RCV_BUF;
  2787. csk1->snd_buf = DEF_SND_BUF;
  2788. csk1->seed = DEF_SEED;
  2789. *csk = csk1;
  2790. return 0;
  2791. }
  2792. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2793. {
  2794. if (csk->src_port) {
  2795. struct cnic_dev *dev = csk->dev;
  2796. struct cnic_local *cp = dev->cnic_priv;
  2797. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2798. csk->src_port = 0;
  2799. }
  2800. }
  2801. static void cnic_close_conn(struct cnic_sock *csk)
  2802. {
  2803. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2804. cnic_cm_upload_pg(csk);
  2805. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2806. }
  2807. cnic_cm_cleanup(csk);
  2808. }
  2809. static int cnic_cm_destroy(struct cnic_sock *csk)
  2810. {
  2811. if (!cnic_in_use(csk))
  2812. return -EINVAL;
  2813. csk_hold(csk);
  2814. clear_bit(SK_F_INUSE, &csk->flags);
  2815. smp_mb__after_clear_bit();
  2816. while (atomic_read(&csk->ref_count) != 1)
  2817. msleep(1);
  2818. cnic_cm_cleanup(csk);
  2819. csk->flags = 0;
  2820. csk_put(csk);
  2821. return 0;
  2822. }
  2823. static inline u16 cnic_get_vlan(struct net_device *dev,
  2824. struct net_device **vlan_dev)
  2825. {
  2826. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2827. *vlan_dev = vlan_dev_real_dev(dev);
  2828. return vlan_dev_vlan_id(dev);
  2829. }
  2830. *vlan_dev = dev;
  2831. return 0;
  2832. }
  2833. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2834. struct dst_entry **dst)
  2835. {
  2836. #if defined(CONFIG_INET)
  2837. struct rtable *rt;
  2838. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2839. if (!IS_ERR(rt)) {
  2840. *dst = &rt->dst;
  2841. return 0;
  2842. }
  2843. return PTR_ERR(rt);
  2844. #else
  2845. return -ENETUNREACH;
  2846. #endif
  2847. }
  2848. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2849. struct dst_entry **dst)
  2850. {
  2851. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2852. struct flowi6 fl6;
  2853. memset(&fl6, 0, sizeof(fl6));
  2854. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2855. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2856. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2857. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2858. if (*dst)
  2859. return 0;
  2860. #endif
  2861. return -ENETUNREACH;
  2862. }
  2863. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2864. int ulp_type)
  2865. {
  2866. struct cnic_dev *dev = NULL;
  2867. struct dst_entry *dst;
  2868. struct net_device *netdev = NULL;
  2869. int err = -ENETUNREACH;
  2870. if (dst_addr->sin_family == AF_INET)
  2871. err = cnic_get_v4_route(dst_addr, &dst);
  2872. else if (dst_addr->sin_family == AF_INET6) {
  2873. struct sockaddr_in6 *dst_addr6 =
  2874. (struct sockaddr_in6 *) dst_addr;
  2875. err = cnic_get_v6_route(dst_addr6, &dst);
  2876. } else
  2877. return NULL;
  2878. if (err)
  2879. return NULL;
  2880. if (!dst->dev)
  2881. goto done;
  2882. cnic_get_vlan(dst->dev, &netdev);
  2883. dev = cnic_from_netdev(netdev);
  2884. done:
  2885. dst_release(dst);
  2886. if (dev)
  2887. cnic_put(dev);
  2888. return dev;
  2889. }
  2890. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2891. {
  2892. struct cnic_dev *dev = csk->dev;
  2893. struct cnic_local *cp = dev->cnic_priv;
  2894. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2895. }
  2896. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2897. {
  2898. struct cnic_dev *dev = csk->dev;
  2899. struct cnic_local *cp = dev->cnic_priv;
  2900. int is_v6, rc = 0;
  2901. struct dst_entry *dst = NULL;
  2902. struct net_device *realdev;
  2903. __be16 local_port;
  2904. u32 port_id;
  2905. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2906. saddr->remote.v6.sin6_family == AF_INET6)
  2907. is_v6 = 1;
  2908. else if (saddr->local.v4.sin_family == AF_INET &&
  2909. saddr->remote.v4.sin_family == AF_INET)
  2910. is_v6 = 0;
  2911. else
  2912. return -EINVAL;
  2913. clear_bit(SK_F_IPV6, &csk->flags);
  2914. if (is_v6) {
  2915. set_bit(SK_F_IPV6, &csk->flags);
  2916. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2917. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2918. sizeof(struct in6_addr));
  2919. csk->dst_port = saddr->remote.v6.sin6_port;
  2920. local_port = saddr->local.v6.sin6_port;
  2921. } else {
  2922. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2923. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2924. csk->dst_port = saddr->remote.v4.sin_port;
  2925. local_port = saddr->local.v4.sin_port;
  2926. }
  2927. csk->vlan_id = 0;
  2928. csk->mtu = dev->netdev->mtu;
  2929. if (dst && dst->dev) {
  2930. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2931. if (realdev == dev->netdev) {
  2932. csk->vlan_id = vlan;
  2933. csk->mtu = dst_mtu(dst);
  2934. }
  2935. }
  2936. port_id = be16_to_cpu(local_port);
  2937. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2938. port_id < CNIC_LOCAL_PORT_MAX) {
  2939. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2940. port_id = 0;
  2941. } else
  2942. port_id = 0;
  2943. if (!port_id) {
  2944. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2945. if (port_id == -1) {
  2946. rc = -ENOMEM;
  2947. goto err_out;
  2948. }
  2949. local_port = cpu_to_be16(port_id);
  2950. }
  2951. csk->src_port = local_port;
  2952. err_out:
  2953. dst_release(dst);
  2954. return rc;
  2955. }
  2956. static void cnic_init_csk_state(struct cnic_sock *csk)
  2957. {
  2958. csk->state = 0;
  2959. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2960. clear_bit(SK_F_CLOSING, &csk->flags);
  2961. }
  2962. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2963. {
  2964. struct cnic_local *cp = csk->dev->cnic_priv;
  2965. int err = 0;
  2966. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  2967. return -EOPNOTSUPP;
  2968. if (!cnic_in_use(csk))
  2969. return -EINVAL;
  2970. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2971. return -EINVAL;
  2972. cnic_init_csk_state(csk);
  2973. err = cnic_get_route(csk, saddr);
  2974. if (err)
  2975. goto err_out;
  2976. err = cnic_resolve_addr(csk, saddr);
  2977. if (!err)
  2978. return 0;
  2979. err_out:
  2980. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2981. return err;
  2982. }
  2983. static int cnic_cm_abort(struct cnic_sock *csk)
  2984. {
  2985. struct cnic_local *cp = csk->dev->cnic_priv;
  2986. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2987. if (!cnic_in_use(csk))
  2988. return -EINVAL;
  2989. if (cnic_abort_prep(csk))
  2990. return cnic_cm_abort_req(csk);
  2991. /* Getting here means that we haven't started connect, or
  2992. * connect was not successful.
  2993. */
  2994. cp->close_conn(csk, opcode);
  2995. if (csk->state != opcode)
  2996. return -EALREADY;
  2997. return 0;
  2998. }
  2999. static int cnic_cm_close(struct cnic_sock *csk)
  3000. {
  3001. if (!cnic_in_use(csk))
  3002. return -EINVAL;
  3003. if (cnic_close_prep(csk)) {
  3004. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3005. return cnic_cm_close_req(csk);
  3006. } else {
  3007. return -EALREADY;
  3008. }
  3009. return 0;
  3010. }
  3011. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3012. u8 opcode)
  3013. {
  3014. struct cnic_ulp_ops *ulp_ops;
  3015. int ulp_type = csk->ulp_type;
  3016. rcu_read_lock();
  3017. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3018. if (ulp_ops) {
  3019. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3020. ulp_ops->cm_connect_complete(csk);
  3021. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3022. ulp_ops->cm_close_complete(csk);
  3023. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3024. ulp_ops->cm_remote_abort(csk);
  3025. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3026. ulp_ops->cm_abort_complete(csk);
  3027. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3028. ulp_ops->cm_remote_close(csk);
  3029. }
  3030. rcu_read_unlock();
  3031. }
  3032. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3033. {
  3034. if (cnic_offld_prep(csk)) {
  3035. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3036. cnic_cm_update_pg(csk);
  3037. else
  3038. cnic_cm_offload_pg(csk);
  3039. }
  3040. return 0;
  3041. }
  3042. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3043. {
  3044. struct cnic_local *cp = dev->cnic_priv;
  3045. u32 l5_cid = kcqe->pg_host_opaque;
  3046. u8 opcode = kcqe->op_code;
  3047. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3048. csk_hold(csk);
  3049. if (!cnic_in_use(csk))
  3050. goto done;
  3051. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3052. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3053. goto done;
  3054. }
  3055. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3056. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3057. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3058. cnic_cm_upcall(cp, csk,
  3059. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3060. goto done;
  3061. }
  3062. csk->pg_cid = kcqe->pg_cid;
  3063. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3064. cnic_cm_conn_req(csk);
  3065. done:
  3066. csk_put(csk);
  3067. }
  3068. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3069. {
  3070. struct cnic_local *cp = dev->cnic_priv;
  3071. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3072. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3073. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3074. ctx->timestamp = jiffies;
  3075. ctx->wait_cond = 1;
  3076. wake_up(&ctx->waitq);
  3077. }
  3078. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3079. {
  3080. struct cnic_local *cp = dev->cnic_priv;
  3081. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3082. u8 opcode = l4kcqe->op_code;
  3083. u32 l5_cid;
  3084. struct cnic_sock *csk;
  3085. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3086. cnic_process_fcoe_term_conn(dev, kcqe);
  3087. return;
  3088. }
  3089. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3090. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3091. cnic_cm_process_offld_pg(dev, l4kcqe);
  3092. return;
  3093. }
  3094. l5_cid = l4kcqe->conn_id;
  3095. if (opcode & 0x80)
  3096. l5_cid = l4kcqe->cid;
  3097. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3098. return;
  3099. csk = &cp->csk_tbl[l5_cid];
  3100. csk_hold(csk);
  3101. if (!cnic_in_use(csk)) {
  3102. csk_put(csk);
  3103. return;
  3104. }
  3105. switch (opcode) {
  3106. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3107. if (l4kcqe->status != 0) {
  3108. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3109. cnic_cm_upcall(cp, csk,
  3110. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3111. }
  3112. break;
  3113. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3114. if (l4kcqe->status == 0)
  3115. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3116. smp_mb__before_clear_bit();
  3117. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3118. cnic_cm_upcall(cp, csk, opcode);
  3119. break;
  3120. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3121. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3122. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3123. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3124. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3125. cp->close_conn(csk, opcode);
  3126. break;
  3127. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3128. /* after we already sent CLOSE_REQ */
  3129. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3130. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3131. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3132. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3133. else
  3134. cnic_cm_upcall(cp, csk, opcode);
  3135. break;
  3136. }
  3137. csk_put(csk);
  3138. }
  3139. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3140. {
  3141. struct cnic_dev *dev = data;
  3142. int i;
  3143. for (i = 0; i < num; i++)
  3144. cnic_cm_process_kcqe(dev, kcqe[i]);
  3145. }
  3146. static struct cnic_ulp_ops cm_ulp_ops = {
  3147. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3148. };
  3149. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3150. {
  3151. struct cnic_local *cp = dev->cnic_priv;
  3152. kfree(cp->csk_tbl);
  3153. cp->csk_tbl = NULL;
  3154. cnic_free_id_tbl(&cp->csk_port_tbl);
  3155. }
  3156. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3157. {
  3158. struct cnic_local *cp = dev->cnic_priv;
  3159. u32 port_id;
  3160. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3161. GFP_KERNEL);
  3162. if (!cp->csk_tbl)
  3163. return -ENOMEM;
  3164. get_random_bytes(&port_id, sizeof(port_id));
  3165. port_id %= CNIC_LOCAL_PORT_RANGE;
  3166. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3167. CNIC_LOCAL_PORT_MIN, port_id)) {
  3168. cnic_cm_free_mem(dev);
  3169. return -ENOMEM;
  3170. }
  3171. return 0;
  3172. }
  3173. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3174. {
  3175. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3176. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3177. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3178. csk->state = opcode;
  3179. }
  3180. /* 1. If event opcode matches the expected event in csk->state
  3181. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3182. * event
  3183. * 3. If the expected event is 0, meaning the connection was never
  3184. * never established, we accept the opcode from cm_abort.
  3185. */
  3186. if (opcode == csk->state || csk->state == 0 ||
  3187. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3188. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3189. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3190. if (csk->state == 0)
  3191. csk->state = opcode;
  3192. return 1;
  3193. }
  3194. }
  3195. return 0;
  3196. }
  3197. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3198. {
  3199. struct cnic_dev *dev = csk->dev;
  3200. struct cnic_local *cp = dev->cnic_priv;
  3201. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3202. cnic_cm_upcall(cp, csk, opcode);
  3203. return;
  3204. }
  3205. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3206. cnic_close_conn(csk);
  3207. csk->state = opcode;
  3208. cnic_cm_upcall(cp, csk, opcode);
  3209. }
  3210. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3211. {
  3212. }
  3213. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3214. {
  3215. u32 seed;
  3216. get_random_bytes(&seed, 4);
  3217. cnic_ctx_wr(dev, 45, 0, seed);
  3218. return 0;
  3219. }
  3220. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3221. {
  3222. struct cnic_dev *dev = csk->dev;
  3223. struct cnic_local *cp = dev->cnic_priv;
  3224. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3225. union l5cm_specific_data l5_data;
  3226. u32 cmd = 0;
  3227. int close_complete = 0;
  3228. switch (opcode) {
  3229. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3230. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3231. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3232. if (cnic_ready_to_close(csk, opcode)) {
  3233. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3234. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3235. else
  3236. close_complete = 1;
  3237. }
  3238. break;
  3239. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3240. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3241. break;
  3242. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3243. close_complete = 1;
  3244. break;
  3245. }
  3246. if (cmd) {
  3247. memset(&l5_data, 0, sizeof(l5_data));
  3248. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3249. &l5_data);
  3250. } else if (close_complete) {
  3251. ctx->timestamp = jiffies;
  3252. cnic_close_conn(csk);
  3253. cnic_cm_upcall(cp, csk, csk->state);
  3254. }
  3255. }
  3256. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3257. {
  3258. struct cnic_local *cp = dev->cnic_priv;
  3259. int i;
  3260. if (!cp->ctx_tbl)
  3261. return;
  3262. if (!netif_running(dev->netdev))
  3263. return;
  3264. for (i = 0; i < cp->max_cid_space; i++) {
  3265. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3266. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3267. msleep(10);
  3268. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3269. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3270. ctx->cid);
  3271. }
  3272. cancel_delayed_work(&cp->delete_task);
  3273. flush_workqueue(cnic_wq);
  3274. if (atomic_read(&cp->iscsi_conn) != 0)
  3275. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3276. atomic_read(&cp->iscsi_conn));
  3277. }
  3278. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3279. {
  3280. struct cnic_local *cp = dev->cnic_priv;
  3281. u32 pfid = cp->pfid;
  3282. u32 port = CNIC_PORT(cp);
  3283. cnic_init_bnx2x_mac(dev);
  3284. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3285. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3286. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3287. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3288. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3289. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3290. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3291. DEF_MAX_DA_COUNT);
  3292. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3293. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3294. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3295. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3296. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3297. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3298. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3299. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3300. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3301. DEF_MAX_CWND);
  3302. return 0;
  3303. }
  3304. static void cnic_delete_task(struct work_struct *work)
  3305. {
  3306. struct cnic_local *cp;
  3307. struct cnic_dev *dev;
  3308. u32 i;
  3309. int need_resched = 0;
  3310. cp = container_of(work, struct cnic_local, delete_task.work);
  3311. dev = cp->dev;
  3312. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3313. struct drv_ctl_info info;
  3314. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3315. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3316. cp->ethdev->drv_ctl(dev->netdev, &info);
  3317. }
  3318. for (i = 0; i < cp->max_cid_space; i++) {
  3319. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3320. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3321. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3322. continue;
  3323. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3324. need_resched = 1;
  3325. continue;
  3326. }
  3327. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3328. continue;
  3329. cnic_bnx2x_destroy_ramrod(dev, i);
  3330. cnic_free_bnx2x_conn_resc(dev, i);
  3331. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3332. atomic_dec(&cp->iscsi_conn);
  3333. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3334. }
  3335. if (need_resched)
  3336. queue_delayed_work(cnic_wq, &cp->delete_task,
  3337. msecs_to_jiffies(10));
  3338. }
  3339. static int cnic_cm_open(struct cnic_dev *dev)
  3340. {
  3341. struct cnic_local *cp = dev->cnic_priv;
  3342. int err;
  3343. err = cnic_cm_alloc_mem(dev);
  3344. if (err)
  3345. return err;
  3346. err = cp->start_cm(dev);
  3347. if (err)
  3348. goto err_out;
  3349. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3350. dev->cm_create = cnic_cm_create;
  3351. dev->cm_destroy = cnic_cm_destroy;
  3352. dev->cm_connect = cnic_cm_connect;
  3353. dev->cm_abort = cnic_cm_abort;
  3354. dev->cm_close = cnic_cm_close;
  3355. dev->cm_select_dev = cnic_cm_select_dev;
  3356. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3357. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3358. return 0;
  3359. err_out:
  3360. cnic_cm_free_mem(dev);
  3361. return err;
  3362. }
  3363. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3364. {
  3365. struct cnic_local *cp = dev->cnic_priv;
  3366. int i;
  3367. cp->stop_cm(dev);
  3368. if (!cp->csk_tbl)
  3369. return 0;
  3370. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3371. struct cnic_sock *csk = &cp->csk_tbl[i];
  3372. clear_bit(SK_F_INUSE, &csk->flags);
  3373. cnic_cm_cleanup(csk);
  3374. }
  3375. cnic_cm_free_mem(dev);
  3376. return 0;
  3377. }
  3378. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3379. {
  3380. u32 cid_addr;
  3381. int i;
  3382. cid_addr = GET_CID_ADDR(cid);
  3383. for (i = 0; i < CTX_SIZE; i += 4)
  3384. cnic_ctx_wr(dev, cid_addr, i, 0);
  3385. }
  3386. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3387. {
  3388. struct cnic_local *cp = dev->cnic_priv;
  3389. int ret = 0, i;
  3390. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3391. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3392. return 0;
  3393. for (i = 0; i < cp->ctx_blks; i++) {
  3394. int j;
  3395. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3396. u32 val;
  3397. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3398. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3399. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3400. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3401. (u64) cp->ctx_arr[i].mapping >> 32);
  3402. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3403. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3404. for (j = 0; j < 10; j++) {
  3405. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3406. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3407. break;
  3408. udelay(5);
  3409. }
  3410. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3411. ret = -EBUSY;
  3412. break;
  3413. }
  3414. }
  3415. return ret;
  3416. }
  3417. static void cnic_free_irq(struct cnic_dev *dev)
  3418. {
  3419. struct cnic_local *cp = dev->cnic_priv;
  3420. struct cnic_eth_dev *ethdev = cp->ethdev;
  3421. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3422. cp->disable_int_sync(dev);
  3423. tasklet_kill(&cp->cnic_irq_task);
  3424. free_irq(ethdev->irq_arr[0].vector, dev);
  3425. }
  3426. }
  3427. static int cnic_request_irq(struct cnic_dev *dev)
  3428. {
  3429. struct cnic_local *cp = dev->cnic_priv;
  3430. struct cnic_eth_dev *ethdev = cp->ethdev;
  3431. int err;
  3432. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3433. if (err)
  3434. tasklet_disable(&cp->cnic_irq_task);
  3435. return err;
  3436. }
  3437. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3438. {
  3439. struct cnic_local *cp = dev->cnic_priv;
  3440. struct cnic_eth_dev *ethdev = cp->ethdev;
  3441. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3442. int err, i = 0;
  3443. int sblk_num = cp->status_blk_num;
  3444. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3445. BNX2_HC_SB_CONFIG_1;
  3446. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3447. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3448. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3449. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3450. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3451. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3452. (unsigned long) dev);
  3453. err = cnic_request_irq(dev);
  3454. if (err)
  3455. return err;
  3456. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3457. i < 10) {
  3458. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3459. 1 << (11 + sblk_num));
  3460. udelay(10);
  3461. i++;
  3462. barrier();
  3463. }
  3464. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3465. cnic_free_irq(dev);
  3466. goto failed;
  3467. }
  3468. } else {
  3469. struct status_block *sblk = cp->status_blk.gen;
  3470. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3471. int i = 0;
  3472. while (sblk->status_completion_producer_index && i < 10) {
  3473. CNIC_WR(dev, BNX2_HC_COMMAND,
  3474. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3475. udelay(10);
  3476. i++;
  3477. barrier();
  3478. }
  3479. if (sblk->status_completion_producer_index)
  3480. goto failed;
  3481. }
  3482. return 0;
  3483. failed:
  3484. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3485. return -EBUSY;
  3486. }
  3487. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3488. {
  3489. struct cnic_local *cp = dev->cnic_priv;
  3490. struct cnic_eth_dev *ethdev = cp->ethdev;
  3491. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3492. return;
  3493. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3494. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3495. }
  3496. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3497. {
  3498. struct cnic_local *cp = dev->cnic_priv;
  3499. struct cnic_eth_dev *ethdev = cp->ethdev;
  3500. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3501. return;
  3502. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3503. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3504. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3505. synchronize_irq(ethdev->irq_arr[0].vector);
  3506. }
  3507. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3508. {
  3509. struct cnic_local *cp = dev->cnic_priv;
  3510. struct cnic_eth_dev *ethdev = cp->ethdev;
  3511. struct cnic_uio_dev *udev = cp->udev;
  3512. u32 cid_addr, tx_cid, sb_id;
  3513. u32 val, offset0, offset1, offset2, offset3;
  3514. int i;
  3515. struct tx_bd *txbd;
  3516. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3517. struct status_block *s_blk = cp->status_blk.gen;
  3518. sb_id = cp->status_blk_num;
  3519. tx_cid = 20;
  3520. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3521. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3522. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3523. tx_cid = TX_TSS_CID + sb_id - 1;
  3524. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3525. (TX_TSS_CID << 7));
  3526. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3527. }
  3528. cp->tx_cons = *cp->tx_cons_ptr;
  3529. cid_addr = GET_CID_ADDR(tx_cid);
  3530. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3531. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3532. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3533. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3534. offset0 = BNX2_L2CTX_TYPE_XI;
  3535. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3536. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3537. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3538. } else {
  3539. cnic_init_context(dev, tx_cid);
  3540. cnic_init_context(dev, tx_cid + 1);
  3541. offset0 = BNX2_L2CTX_TYPE;
  3542. offset1 = BNX2_L2CTX_CMD_TYPE;
  3543. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3544. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3545. }
  3546. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3547. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3548. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3549. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3550. txbd = (struct tx_bd *) udev->l2_ring;
  3551. buf_map = udev->l2_buf_map;
  3552. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3553. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3554. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3555. }
  3556. val = (u64) ring_map >> 32;
  3557. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3558. txbd->tx_bd_haddr_hi = val;
  3559. val = (u64) ring_map & 0xffffffff;
  3560. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3561. txbd->tx_bd_haddr_lo = val;
  3562. }
  3563. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3564. {
  3565. struct cnic_local *cp = dev->cnic_priv;
  3566. struct cnic_eth_dev *ethdev = cp->ethdev;
  3567. struct cnic_uio_dev *udev = cp->udev;
  3568. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3569. int i;
  3570. struct rx_bd *rxbd;
  3571. struct status_block *s_blk = cp->status_blk.gen;
  3572. dma_addr_t ring_map = udev->l2_ring_map;
  3573. sb_id = cp->status_blk_num;
  3574. cnic_init_context(dev, 2);
  3575. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3576. coal_reg = BNX2_HC_COMMAND;
  3577. coal_val = CNIC_RD(dev, coal_reg);
  3578. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3579. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3580. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3581. coal_reg = BNX2_HC_COALESCE_NOW;
  3582. coal_val = 1 << (11 + sb_id);
  3583. }
  3584. i = 0;
  3585. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3586. CNIC_WR(dev, coal_reg, coal_val);
  3587. udelay(10);
  3588. i++;
  3589. barrier();
  3590. }
  3591. cp->rx_cons = *cp->rx_cons_ptr;
  3592. cid_addr = GET_CID_ADDR(2);
  3593. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3594. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3595. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3596. if (sb_id == 0)
  3597. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3598. else
  3599. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3600. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3601. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3602. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3603. dma_addr_t buf_map;
  3604. int n = (i % cp->l2_rx_ring_size) + 1;
  3605. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3606. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3607. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3608. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3609. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3610. }
  3611. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3612. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3613. rxbd->rx_bd_haddr_hi = val;
  3614. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3615. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3616. rxbd->rx_bd_haddr_lo = val;
  3617. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3618. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3619. }
  3620. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3621. {
  3622. struct kwqe *wqes[1], l2kwqe;
  3623. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3624. wqes[0] = &l2kwqe;
  3625. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3626. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3627. KWQE_OPCODE_SHIFT) | 2;
  3628. dev->submit_kwqes(dev, wqes, 1);
  3629. }
  3630. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3631. {
  3632. struct cnic_local *cp = dev->cnic_priv;
  3633. u32 val;
  3634. val = cp->func << 2;
  3635. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3636. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3637. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3638. dev->mac_addr[0] = (u8) (val >> 8);
  3639. dev->mac_addr[1] = (u8) val;
  3640. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3641. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3642. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3643. dev->mac_addr[2] = (u8) (val >> 24);
  3644. dev->mac_addr[3] = (u8) (val >> 16);
  3645. dev->mac_addr[4] = (u8) (val >> 8);
  3646. dev->mac_addr[5] = (u8) val;
  3647. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3648. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3649. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3650. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3651. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3652. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3653. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3654. }
  3655. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3656. {
  3657. struct cnic_local *cp = dev->cnic_priv;
  3658. struct cnic_eth_dev *ethdev = cp->ethdev;
  3659. struct status_block *sblk = cp->status_blk.gen;
  3660. u32 val, kcq_cid_addr, kwq_cid_addr;
  3661. int err;
  3662. cnic_set_bnx2_mac(dev);
  3663. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3664. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3665. if (BCM_PAGE_BITS > 12)
  3666. val |= (12 - 8) << 4;
  3667. else
  3668. val |= (BCM_PAGE_BITS - 8) << 4;
  3669. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3670. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3671. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3672. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3673. err = cnic_setup_5709_context(dev, 1);
  3674. if (err)
  3675. return err;
  3676. cnic_init_context(dev, KWQ_CID);
  3677. cnic_init_context(dev, KCQ_CID);
  3678. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3679. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3680. cp->max_kwq_idx = MAX_KWQ_IDX;
  3681. cp->kwq_prod_idx = 0;
  3682. cp->kwq_con_idx = 0;
  3683. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3684. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3685. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3686. else
  3687. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3688. /* Initialize the kernel work queue context. */
  3689. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3690. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3691. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3692. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3693. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3694. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3695. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3696. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3697. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3698. val = (u32) cp->kwq_info.pgtbl_map;
  3699. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3700. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3701. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3702. cp->kcq1.sw_prod_idx = 0;
  3703. cp->kcq1.hw_prod_idx_ptr =
  3704. (u16 *) &sblk->status_completion_producer_index;
  3705. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3706. /* Initialize the kernel complete queue context. */
  3707. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3708. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3709. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3710. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3711. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3712. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3713. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3714. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3715. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3716. val = (u32) cp->kcq1.dma.pgtbl_map;
  3717. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3718. cp->int_num = 0;
  3719. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3720. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3721. u32 sb_id = cp->status_blk_num;
  3722. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3723. cp->kcq1.hw_prod_idx_ptr =
  3724. (u16 *) &msblk->status_completion_producer_index;
  3725. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3726. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3727. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3728. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3729. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3730. }
  3731. /* Enable Commnad Scheduler notification when we write to the
  3732. * host producer index of the kernel contexts. */
  3733. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3734. /* Enable Command Scheduler notification when we write to either
  3735. * the Send Queue or Receive Queue producer indexes of the kernel
  3736. * bypass contexts. */
  3737. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3738. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3739. /* Notify COM when the driver post an application buffer. */
  3740. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3741. /* Set the CP and COM doorbells. These two processors polls the
  3742. * doorbell for a non zero value before running. This must be done
  3743. * after setting up the kernel queue contexts. */
  3744. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3745. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3746. cnic_init_bnx2_tx_ring(dev);
  3747. cnic_init_bnx2_rx_ring(dev);
  3748. err = cnic_init_bnx2_irq(dev);
  3749. if (err) {
  3750. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3751. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3752. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3753. return err;
  3754. }
  3755. return 0;
  3756. }
  3757. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3758. {
  3759. struct cnic_local *cp = dev->cnic_priv;
  3760. struct cnic_eth_dev *ethdev = cp->ethdev;
  3761. u32 start_offset = ethdev->ctx_tbl_offset;
  3762. int i;
  3763. for (i = 0; i < cp->ctx_blks; i++) {
  3764. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3765. dma_addr_t map = ctx->mapping;
  3766. if (cp->ctx_align) {
  3767. unsigned long mask = cp->ctx_align - 1;
  3768. map = (map + mask) & ~mask;
  3769. }
  3770. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3771. }
  3772. }
  3773. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3774. {
  3775. struct cnic_local *cp = dev->cnic_priv;
  3776. struct cnic_eth_dev *ethdev = cp->ethdev;
  3777. int err = 0;
  3778. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3779. (unsigned long) dev);
  3780. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3781. err = cnic_request_irq(dev);
  3782. return err;
  3783. }
  3784. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3785. u16 sb_id, u8 sb_index,
  3786. u8 disable)
  3787. {
  3788. u32 addr = BAR_CSTRORM_INTMEM +
  3789. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3790. offsetof(struct hc_status_block_data_e1x, index_data) +
  3791. sizeof(struct hc_index_data)*sb_index +
  3792. offsetof(struct hc_index_data, flags);
  3793. u16 flags = CNIC_RD16(dev, addr);
  3794. /* clear and set */
  3795. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3796. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3797. HC_INDEX_DATA_HC_ENABLED);
  3798. CNIC_WR16(dev, addr, flags);
  3799. }
  3800. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3801. {
  3802. struct cnic_local *cp = dev->cnic_priv;
  3803. u8 sb_id = cp->status_blk_num;
  3804. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3805. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3806. offsetof(struct hc_status_block_data_e1x, index_data) +
  3807. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3808. offsetof(struct hc_index_data, timeout), 64 / 12);
  3809. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3810. }
  3811. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3812. {
  3813. }
  3814. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3815. struct client_init_ramrod_data *data)
  3816. {
  3817. struct cnic_local *cp = dev->cnic_priv;
  3818. struct cnic_uio_dev *udev = cp->udev;
  3819. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3820. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3821. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3822. int port = CNIC_PORT(cp);
  3823. int i;
  3824. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3825. u32 val;
  3826. memset(txbd, 0, BCM_PAGE_SIZE);
  3827. buf_map = udev->l2_buf_map;
  3828. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3829. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3830. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3831. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3832. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3833. reg_bd->addr_hi = start_bd->addr_hi;
  3834. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3835. start_bd->nbytes = cpu_to_le16(0x10);
  3836. start_bd->nbd = cpu_to_le16(3);
  3837. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3838. start_bd->general_data = (UNICAST_ADDRESS <<
  3839. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3840. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3841. }
  3842. val = (u64) ring_map >> 32;
  3843. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3844. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3845. val = (u64) ring_map & 0xffffffff;
  3846. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3847. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3848. /* Other ramrod params */
  3849. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3850. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3851. /* reset xstorm per client statistics */
  3852. if (cli < MAX_STAT_COUNTER_ID) {
  3853. val = BAR_XSTRORM_INTMEM +
  3854. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3855. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3856. CNIC_WR(dev, val + i * 4, 0);
  3857. }
  3858. cp->tx_cons_ptr =
  3859. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3860. }
  3861. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3862. struct client_init_ramrod_data *data)
  3863. {
  3864. struct cnic_local *cp = dev->cnic_priv;
  3865. struct cnic_uio_dev *udev = cp->udev;
  3866. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3867. BCM_PAGE_SIZE);
  3868. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3869. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3870. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3871. int i;
  3872. int port = CNIC_PORT(cp);
  3873. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3874. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3875. u32 val;
  3876. dma_addr_t ring_map = udev->l2_ring_map;
  3877. /* General data */
  3878. data->general.client_id = cli;
  3879. data->general.statistics_en_flg = 1;
  3880. data->general.statistics_counter_id = cli;
  3881. data->general.activate_flg = 1;
  3882. data->general.sp_client_id = cli;
  3883. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3884. dma_addr_t buf_map;
  3885. int n = (i % cp->l2_rx_ring_size) + 1;
  3886. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3887. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3888. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3889. }
  3890. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3891. rxbd->addr_hi = cpu_to_le32(val);
  3892. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3893. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3894. rxbd->addr_lo = cpu_to_le32(val);
  3895. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3896. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3897. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3898. rxcqe->addr_hi = cpu_to_le32(val);
  3899. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3900. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3901. rxcqe->addr_lo = cpu_to_le32(val);
  3902. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3903. /* Other ramrod params */
  3904. data->rx.client_qzone_id = cl_qzone_id;
  3905. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3906. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3907. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3908. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3909. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3910. data->rx.outer_vlan_removal_enable_flg = 1;
  3911. /* reset tstorm and ustorm per client statistics */
  3912. if (cli < MAX_STAT_COUNTER_ID) {
  3913. val = BAR_TSTRORM_INTMEM +
  3914. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3915. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3916. CNIC_WR(dev, val + i * 4, 0);
  3917. val = BAR_USTRORM_INTMEM +
  3918. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3919. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3920. CNIC_WR(dev, val + i * 4, 0);
  3921. }
  3922. cp->rx_cons_ptr =
  3923. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3924. cp->rx_cons = *cp->rx_cons_ptr;
  3925. }
  3926. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3927. {
  3928. struct cnic_local *cp = dev->cnic_priv;
  3929. u32 pfid = cp->pfid;
  3930. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3931. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3932. cp->kcq1.sw_prod_idx = 0;
  3933. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3934. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3935. cp->kcq1.hw_prod_idx_ptr =
  3936. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3937. cp->kcq1.status_idx_ptr =
  3938. &sb->sb.running_index[SM_RX_ID];
  3939. } else {
  3940. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3941. cp->kcq1.hw_prod_idx_ptr =
  3942. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3943. cp->kcq1.status_idx_ptr =
  3944. &sb->sb.running_index[SM_RX_ID];
  3945. }
  3946. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3947. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3948. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3949. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3950. cp->kcq2.sw_prod_idx = 0;
  3951. cp->kcq2.hw_prod_idx_ptr =
  3952. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3953. cp->kcq2.status_idx_ptr =
  3954. &sb->sb.running_index[SM_RX_ID];
  3955. }
  3956. }
  3957. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3958. {
  3959. struct cnic_local *cp = dev->cnic_priv;
  3960. struct cnic_eth_dev *ethdev = cp->ethdev;
  3961. int func = CNIC_FUNC(cp), ret, i;
  3962. u32 pfid;
  3963. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3964. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3965. if (!(val & 1))
  3966. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3967. else
  3968. val = (val >> 1) & 1;
  3969. if (val)
  3970. cp->pfid = func >> 1;
  3971. else
  3972. cp->pfid = func & 0x6;
  3973. } else {
  3974. cp->pfid = func;
  3975. }
  3976. pfid = cp->pfid;
  3977. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3978. cp->iscsi_start_cid, 0);
  3979. if (ret)
  3980. return -ENOMEM;
  3981. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3982. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  3983. BNX2X_FCOE_NUM_CONNECTIONS,
  3984. cp->fcoe_start_cid, 0);
  3985. if (ret)
  3986. return -ENOMEM;
  3987. }
  3988. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3989. cnic_init_bnx2x_kcq(dev);
  3990. /* Only 1 EQ */
  3991. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3992. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3993. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3994. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3995. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3996. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3997. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3998. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3999. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4000. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4001. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4002. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4003. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4004. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4005. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4006. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4007. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4008. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4009. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4010. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4011. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4012. HC_INDEX_ISCSI_EQ_CONS);
  4013. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  4014. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4015. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  4016. cp->conn_buf_info.pgtbl[2 * i]);
  4017. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4018. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  4019. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  4020. }
  4021. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4022. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4023. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4024. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4025. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4026. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4027. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4028. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4029. cnic_setup_bnx2x_context(dev);
  4030. ret = cnic_init_bnx2x_irq(dev);
  4031. if (ret)
  4032. return ret;
  4033. return 0;
  4034. }
  4035. static void cnic_init_rings(struct cnic_dev *dev)
  4036. {
  4037. struct cnic_local *cp = dev->cnic_priv;
  4038. struct cnic_uio_dev *udev = cp->udev;
  4039. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4040. return;
  4041. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4042. cnic_init_bnx2_tx_ring(dev);
  4043. cnic_init_bnx2_rx_ring(dev);
  4044. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4045. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4046. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4047. u32 cid = cp->ethdev->iscsi_l2_cid;
  4048. u32 cl_qzone_id;
  4049. struct client_init_ramrod_data *data;
  4050. union l5cm_specific_data l5_data;
  4051. struct ustorm_eth_rx_producers rx_prods = {0};
  4052. u32 off, i;
  4053. rx_prods.bd_prod = 0;
  4054. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4055. barrier();
  4056. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4057. off = BAR_USTRORM_INTMEM +
  4058. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  4059. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4060. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4061. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4062. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4063. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4064. data = udev->l2_buf;
  4065. memset(data, 0, sizeof(*data));
  4066. cnic_init_bnx2x_tx_ring(dev, data);
  4067. cnic_init_bnx2x_rx_ring(dev, data);
  4068. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4069. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4070. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4071. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4072. cid, ETH_CONNECTION_TYPE, &l5_data);
  4073. i = 0;
  4074. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4075. ++i < 10)
  4076. msleep(1);
  4077. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4078. netdev_err(dev->netdev,
  4079. "iSCSI CLIENT_SETUP did not complete\n");
  4080. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4081. cnic_ring_ctl(dev, cid, cli, 1);
  4082. }
  4083. }
  4084. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4085. {
  4086. struct cnic_local *cp = dev->cnic_priv;
  4087. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4088. return;
  4089. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4090. cnic_shutdown_bnx2_rx_ring(dev);
  4091. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4092. struct cnic_local *cp = dev->cnic_priv;
  4093. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4094. u32 cid = cp->ethdev->iscsi_l2_cid;
  4095. union l5cm_specific_data l5_data;
  4096. int i;
  4097. cnic_ring_ctl(dev, cid, cli, 0);
  4098. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4099. l5_data.phy_address.lo = cli;
  4100. l5_data.phy_address.hi = 0;
  4101. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4102. cid, ETH_CONNECTION_TYPE, &l5_data);
  4103. i = 0;
  4104. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4105. ++i < 10)
  4106. msleep(1);
  4107. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4108. netdev_err(dev->netdev,
  4109. "iSCSI CLIENT_HALT did not complete\n");
  4110. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4111. memset(&l5_data, 0, sizeof(l5_data));
  4112. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4113. cid, NONE_CONNECTION_TYPE, &l5_data);
  4114. msleep(10);
  4115. }
  4116. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4117. }
  4118. static int cnic_register_netdev(struct cnic_dev *dev)
  4119. {
  4120. struct cnic_local *cp = dev->cnic_priv;
  4121. struct cnic_eth_dev *ethdev = cp->ethdev;
  4122. int err;
  4123. if (!ethdev)
  4124. return -ENODEV;
  4125. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4126. return 0;
  4127. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4128. if (err)
  4129. netdev_err(dev->netdev, "register_cnic failed\n");
  4130. return err;
  4131. }
  4132. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4133. {
  4134. struct cnic_local *cp = dev->cnic_priv;
  4135. struct cnic_eth_dev *ethdev = cp->ethdev;
  4136. if (!ethdev)
  4137. return;
  4138. ethdev->drv_unregister_cnic(dev->netdev);
  4139. }
  4140. static int cnic_start_hw(struct cnic_dev *dev)
  4141. {
  4142. struct cnic_local *cp = dev->cnic_priv;
  4143. struct cnic_eth_dev *ethdev = cp->ethdev;
  4144. int err;
  4145. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4146. return -EALREADY;
  4147. dev->regview = ethdev->io_base;
  4148. pci_dev_get(dev->pcidev);
  4149. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4150. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4151. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4152. err = cp->alloc_resc(dev);
  4153. if (err) {
  4154. netdev_err(dev->netdev, "allocate resource failure\n");
  4155. goto err1;
  4156. }
  4157. err = cp->start_hw(dev);
  4158. if (err)
  4159. goto err1;
  4160. err = cnic_cm_open(dev);
  4161. if (err)
  4162. goto err1;
  4163. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4164. cp->enable_int(dev);
  4165. return 0;
  4166. err1:
  4167. cp->free_resc(dev);
  4168. pci_dev_put(dev->pcidev);
  4169. return err;
  4170. }
  4171. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4172. {
  4173. cnic_disable_bnx2_int_sync(dev);
  4174. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4175. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4176. cnic_init_context(dev, KWQ_CID);
  4177. cnic_init_context(dev, KCQ_CID);
  4178. cnic_setup_5709_context(dev, 0);
  4179. cnic_free_irq(dev);
  4180. cnic_free_resc(dev);
  4181. }
  4182. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4183. {
  4184. struct cnic_local *cp = dev->cnic_priv;
  4185. cnic_free_irq(dev);
  4186. *cp->kcq1.hw_prod_idx_ptr = 0;
  4187. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4188. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4189. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4190. cnic_free_resc(dev);
  4191. }
  4192. static void cnic_stop_hw(struct cnic_dev *dev)
  4193. {
  4194. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4195. struct cnic_local *cp = dev->cnic_priv;
  4196. int i = 0;
  4197. /* Need to wait for the ring shutdown event to complete
  4198. * before clearing the CNIC_UP flag.
  4199. */
  4200. while (cp->udev->uio_dev != -1 && i < 15) {
  4201. msleep(100);
  4202. i++;
  4203. }
  4204. cnic_shutdown_rings(dev);
  4205. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4206. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4207. synchronize_rcu();
  4208. cnic_cm_shutdown(dev);
  4209. cp->stop_hw(dev);
  4210. pci_dev_put(dev->pcidev);
  4211. }
  4212. }
  4213. static void cnic_free_dev(struct cnic_dev *dev)
  4214. {
  4215. int i = 0;
  4216. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4217. msleep(100);
  4218. i++;
  4219. }
  4220. if (atomic_read(&dev->ref_count) != 0)
  4221. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4222. netdev_info(dev->netdev, "Removed CNIC device\n");
  4223. dev_put(dev->netdev);
  4224. kfree(dev);
  4225. }
  4226. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4227. struct pci_dev *pdev)
  4228. {
  4229. struct cnic_dev *cdev;
  4230. struct cnic_local *cp;
  4231. int alloc_size;
  4232. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4233. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4234. if (cdev == NULL) {
  4235. netdev_err(dev, "allocate dev struct failure\n");
  4236. return NULL;
  4237. }
  4238. cdev->netdev = dev;
  4239. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4240. cdev->register_device = cnic_register_device;
  4241. cdev->unregister_device = cnic_unregister_device;
  4242. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4243. cp = cdev->cnic_priv;
  4244. cp->dev = cdev;
  4245. cp->l2_single_buf_size = 0x400;
  4246. cp->l2_rx_ring_size = 3;
  4247. spin_lock_init(&cp->cnic_ulp_lock);
  4248. netdev_info(dev, "Added CNIC device\n");
  4249. return cdev;
  4250. }
  4251. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4252. {
  4253. struct pci_dev *pdev;
  4254. struct cnic_dev *cdev;
  4255. struct cnic_local *cp;
  4256. struct cnic_eth_dev *ethdev = NULL;
  4257. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4258. probe = symbol_get(bnx2_cnic_probe);
  4259. if (probe) {
  4260. ethdev = (*probe)(dev);
  4261. symbol_put(bnx2_cnic_probe);
  4262. }
  4263. if (!ethdev)
  4264. return NULL;
  4265. pdev = ethdev->pdev;
  4266. if (!pdev)
  4267. return NULL;
  4268. dev_hold(dev);
  4269. pci_dev_get(pdev);
  4270. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4271. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4272. (pdev->revision < 0x10)) {
  4273. pci_dev_put(pdev);
  4274. goto cnic_err;
  4275. }
  4276. pci_dev_put(pdev);
  4277. cdev = cnic_alloc_dev(dev, pdev);
  4278. if (cdev == NULL)
  4279. goto cnic_err;
  4280. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4281. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4282. cp = cdev->cnic_priv;
  4283. cp->ethdev = ethdev;
  4284. cdev->pcidev = pdev;
  4285. cp->chip_id = ethdev->chip_id;
  4286. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4287. cp->cnic_ops = &cnic_bnx2_ops;
  4288. cp->start_hw = cnic_start_bnx2_hw;
  4289. cp->stop_hw = cnic_stop_bnx2_hw;
  4290. cp->setup_pgtbl = cnic_setup_page_tbl;
  4291. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4292. cp->free_resc = cnic_free_resc;
  4293. cp->start_cm = cnic_cm_init_bnx2_hw;
  4294. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4295. cp->enable_int = cnic_enable_bnx2_int;
  4296. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4297. cp->close_conn = cnic_close_bnx2_conn;
  4298. return cdev;
  4299. cnic_err:
  4300. dev_put(dev);
  4301. return NULL;
  4302. }
  4303. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4304. {
  4305. struct pci_dev *pdev;
  4306. struct cnic_dev *cdev;
  4307. struct cnic_local *cp;
  4308. struct cnic_eth_dev *ethdev = NULL;
  4309. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4310. probe = symbol_get(bnx2x_cnic_probe);
  4311. if (probe) {
  4312. ethdev = (*probe)(dev);
  4313. symbol_put(bnx2x_cnic_probe);
  4314. }
  4315. if (!ethdev)
  4316. return NULL;
  4317. pdev = ethdev->pdev;
  4318. if (!pdev)
  4319. return NULL;
  4320. dev_hold(dev);
  4321. cdev = cnic_alloc_dev(dev, pdev);
  4322. if (cdev == NULL) {
  4323. dev_put(dev);
  4324. return NULL;
  4325. }
  4326. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4327. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4328. cp = cdev->cnic_priv;
  4329. cp->ethdev = ethdev;
  4330. cdev->pcidev = pdev;
  4331. cp->chip_id = ethdev->chip_id;
  4332. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4333. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4334. if (BNX2X_CHIP_IS_E2(cp->chip_id) &&
  4335. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4336. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4337. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4338. cp->cnic_ops = &cnic_bnx2x_ops;
  4339. cp->start_hw = cnic_start_bnx2x_hw;
  4340. cp->stop_hw = cnic_stop_bnx2x_hw;
  4341. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4342. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4343. cp->free_resc = cnic_free_resc;
  4344. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4345. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4346. cp->enable_int = cnic_enable_bnx2x_int;
  4347. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4348. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  4349. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4350. else
  4351. cp->ack_int = cnic_ack_bnx2x_msix;
  4352. cp->close_conn = cnic_close_bnx2x_conn;
  4353. return cdev;
  4354. }
  4355. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4356. {
  4357. struct ethtool_drvinfo drvinfo;
  4358. struct cnic_dev *cdev = NULL;
  4359. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4360. memset(&drvinfo, 0, sizeof(drvinfo));
  4361. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4362. if (!strcmp(drvinfo.driver, "bnx2"))
  4363. cdev = init_bnx2_cnic(dev);
  4364. if (!strcmp(drvinfo.driver, "bnx2x"))
  4365. cdev = init_bnx2x_cnic(dev);
  4366. if (cdev) {
  4367. write_lock(&cnic_dev_lock);
  4368. list_add(&cdev->list, &cnic_dev_list);
  4369. write_unlock(&cnic_dev_lock);
  4370. }
  4371. }
  4372. return cdev;
  4373. }
  4374. /**
  4375. * netdev event handler
  4376. */
  4377. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4378. void *ptr)
  4379. {
  4380. struct net_device *netdev = ptr;
  4381. struct cnic_dev *dev;
  4382. int if_type;
  4383. int new_dev = 0;
  4384. dev = cnic_from_netdev(netdev);
  4385. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4386. /* Check for the hot-plug device */
  4387. dev = is_cnic_dev(netdev);
  4388. if (dev) {
  4389. new_dev = 1;
  4390. cnic_hold(dev);
  4391. }
  4392. }
  4393. if (dev) {
  4394. struct cnic_local *cp = dev->cnic_priv;
  4395. if (new_dev)
  4396. cnic_ulp_init(dev);
  4397. else if (event == NETDEV_UNREGISTER)
  4398. cnic_ulp_exit(dev);
  4399. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4400. if (cnic_register_netdev(dev) != 0) {
  4401. cnic_put(dev);
  4402. goto done;
  4403. }
  4404. if (!cnic_start_hw(dev))
  4405. cnic_ulp_start(dev);
  4406. }
  4407. rcu_read_lock();
  4408. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4409. struct cnic_ulp_ops *ulp_ops;
  4410. void *ctx;
  4411. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4412. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4413. continue;
  4414. ctx = cp->ulp_handle[if_type];
  4415. ulp_ops->indicate_netevent(ctx, event);
  4416. }
  4417. rcu_read_unlock();
  4418. if (event == NETDEV_GOING_DOWN) {
  4419. cnic_ulp_stop(dev);
  4420. cnic_stop_hw(dev);
  4421. cnic_unregister_netdev(dev);
  4422. } else if (event == NETDEV_UNREGISTER) {
  4423. write_lock(&cnic_dev_lock);
  4424. list_del_init(&dev->list);
  4425. write_unlock(&cnic_dev_lock);
  4426. cnic_put(dev);
  4427. cnic_free_dev(dev);
  4428. goto done;
  4429. }
  4430. cnic_put(dev);
  4431. }
  4432. done:
  4433. return NOTIFY_DONE;
  4434. }
  4435. static struct notifier_block cnic_netdev_notifier = {
  4436. .notifier_call = cnic_netdev_event
  4437. };
  4438. static void cnic_release(void)
  4439. {
  4440. struct cnic_dev *dev;
  4441. struct cnic_uio_dev *udev;
  4442. while (!list_empty(&cnic_dev_list)) {
  4443. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4444. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4445. cnic_ulp_stop(dev);
  4446. cnic_stop_hw(dev);
  4447. }
  4448. cnic_ulp_exit(dev);
  4449. cnic_unregister_netdev(dev);
  4450. list_del_init(&dev->list);
  4451. cnic_free_dev(dev);
  4452. }
  4453. while (!list_empty(&cnic_udev_list)) {
  4454. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4455. list);
  4456. cnic_free_uio(udev);
  4457. }
  4458. }
  4459. static int __init cnic_init(void)
  4460. {
  4461. int rc = 0;
  4462. pr_info("%s", version);
  4463. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4464. if (rc) {
  4465. cnic_release();
  4466. return rc;
  4467. }
  4468. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4469. if (!cnic_wq) {
  4470. cnic_release();
  4471. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4472. return -ENOMEM;
  4473. }
  4474. return 0;
  4475. }
  4476. static void __exit cnic_exit(void)
  4477. {
  4478. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4479. cnic_release();
  4480. destroy_workqueue(cnic_wq);
  4481. }
  4482. module_init(cnic_init);
  4483. module_exit(cnic_exit);