uhci-q.c 34 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. static void uhci_free_pending_tds(struct uhci_hcd *uhci);
  19. /*
  20. * Technically, updating td->status here is a race, but it's not really a
  21. * problem. The worst that can happen is that we set the IOC bit again
  22. * generating a spurious interrupt. We could fix this by creating another
  23. * QH and leaving the IOC bit always set, but then we would have to play
  24. * games with the FSBR code to make sure we get the correct order in all
  25. * the cases. I don't think it's worth the effort
  26. */
  27. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  28. {
  29. if (uhci->is_stopped)
  30. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  31. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  32. }
  33. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  34. {
  35. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  36. }
  37. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  38. {
  39. dma_addr_t dma_handle;
  40. struct uhci_td *td;
  41. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  42. if (!td)
  43. return NULL;
  44. td->dma_handle = dma_handle;
  45. td->frame = -1;
  46. INIT_LIST_HEAD(&td->list);
  47. INIT_LIST_HEAD(&td->remove_list);
  48. INIT_LIST_HEAD(&td->fl_list);
  49. return td;
  50. }
  51. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  52. {
  53. if (!list_empty(&td->list))
  54. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  55. if (!list_empty(&td->remove_list))
  56. dev_warn(uhci_dev(uhci), "td %p still in remove_list!\n", td);
  57. if (!list_empty(&td->fl_list))
  58. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  59. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  60. }
  61. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  62. u32 token, u32 buffer)
  63. {
  64. td->status = cpu_to_le32(status);
  65. td->token = cpu_to_le32(token);
  66. td->buffer = cpu_to_le32(buffer);
  67. }
  68. /*
  69. * We insert Isochronous URBs directly into the frame list at the beginning
  70. */
  71. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  72. struct uhci_td *td, unsigned framenum)
  73. {
  74. framenum &= (UHCI_NUMFRAMES - 1);
  75. td->frame = framenum;
  76. /* Is there a TD already mapped there? */
  77. if (uhci->frame_cpu[framenum]) {
  78. struct uhci_td *ftd, *ltd;
  79. ftd = uhci->frame_cpu[framenum];
  80. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  81. list_add_tail(&td->fl_list, &ftd->fl_list);
  82. td->link = ltd->link;
  83. wmb();
  84. ltd->link = cpu_to_le32(td->dma_handle);
  85. } else {
  86. td->link = uhci->frame[framenum];
  87. wmb();
  88. uhci->frame[framenum] = cpu_to_le32(td->dma_handle);
  89. uhci->frame_cpu[framenum] = td;
  90. }
  91. }
  92. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  93. struct uhci_td *td)
  94. {
  95. /* If it's not inserted, don't remove it */
  96. if (td->frame == -1) {
  97. WARN_ON(!list_empty(&td->fl_list));
  98. return;
  99. }
  100. if (uhci->frame_cpu[td->frame] == td) {
  101. if (list_empty(&td->fl_list)) {
  102. uhci->frame[td->frame] = td->link;
  103. uhci->frame_cpu[td->frame] = NULL;
  104. } else {
  105. struct uhci_td *ntd;
  106. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  107. uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
  108. uhci->frame_cpu[td->frame] = ntd;
  109. }
  110. } else {
  111. struct uhci_td *ptd;
  112. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  113. ptd->link = td->link;
  114. }
  115. list_del_init(&td->fl_list);
  116. td->frame = -1;
  117. }
  118. /*
  119. * Remove all the TDs for an Isochronous URB from the frame list
  120. */
  121. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  122. {
  123. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  124. struct uhci_td *td;
  125. list_for_each_entry(td, &urbp->td_list, list)
  126. uhci_remove_td_from_frame_list(uhci, td);
  127. wmb();
  128. }
  129. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  130. struct usb_device *udev, struct usb_host_endpoint *hep)
  131. {
  132. dma_addr_t dma_handle;
  133. struct uhci_qh *qh;
  134. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  135. if (!qh)
  136. return NULL;
  137. memset(qh, 0, sizeof(*qh));
  138. qh->dma_handle = dma_handle;
  139. qh->element = UHCI_PTR_TERM;
  140. qh->link = UHCI_PTR_TERM;
  141. INIT_LIST_HEAD(&qh->queue);
  142. INIT_LIST_HEAD(&qh->node);
  143. if (udev) { /* Normal QH */
  144. qh->dummy_td = uhci_alloc_td(uhci);
  145. if (!qh->dummy_td) {
  146. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  147. return NULL;
  148. }
  149. qh->state = QH_STATE_IDLE;
  150. qh->hep = hep;
  151. qh->udev = udev;
  152. hep->hcpriv = qh;
  153. qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  154. } else { /* Skeleton QH */
  155. qh->state = QH_STATE_ACTIVE;
  156. qh->type = -1;
  157. }
  158. return qh;
  159. }
  160. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  161. {
  162. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  163. if (!list_empty(&qh->queue))
  164. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  165. list_del(&qh->node);
  166. if (qh->udev) {
  167. qh->hep->hcpriv = NULL;
  168. uhci_free_td(uhci, qh->dummy_td);
  169. }
  170. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  171. }
  172. /*
  173. * When the currently executing URB is dequeued, save its current toggle value
  174. */
  175. static void uhci_save_toggle(struct uhci_qh *qh, struct urb *urb)
  176. {
  177. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  178. struct uhci_td *td;
  179. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  180. * executing URB has already been unlinked, so this one isn't it. */
  181. if (qh_element(qh) == UHCI_PTR_TERM ||
  182. qh->queue.next != &urbp->node)
  183. return;
  184. qh->element = UHCI_PTR_TERM;
  185. /* Only bulk and interrupt pipes have to worry about toggles */
  186. if (!(qh->type == USB_ENDPOINT_XFER_BULK ||
  187. qh->type == USB_ENDPOINT_XFER_INT))
  188. return;
  189. WARN_ON(list_empty(&urbp->td_list));
  190. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  191. qh->needs_fixup = 1;
  192. qh->initial_toggle = uhci_toggle(td_token(td));
  193. }
  194. /*
  195. * Fix up the data toggles for URBs in a queue, when one of them
  196. * terminates early (short transfer, error, or dequeued).
  197. */
  198. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  199. {
  200. struct urb_priv *urbp = NULL;
  201. struct uhci_td *td;
  202. unsigned int toggle = qh->initial_toggle;
  203. unsigned int pipe;
  204. /* Fixups for a short transfer start with the second URB in the
  205. * queue (the short URB is the first). */
  206. if (skip_first)
  207. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  208. /* When starting with the first URB, if the QH element pointer is
  209. * still valid then we know the URB's toggles are okay. */
  210. else if (qh_element(qh) != UHCI_PTR_TERM)
  211. toggle = 2;
  212. /* Fix up the toggle for the URBs in the queue. Normally this
  213. * loop won't run more than once: When an error or short transfer
  214. * occurs, the queue usually gets emptied. */
  215. urbp = list_prepare_entry(urbp, &qh->queue, node);
  216. list_for_each_entry_continue(urbp, &qh->queue, node) {
  217. /* If the first TD has the right toggle value, we don't
  218. * need to change any toggles in this URB */
  219. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  220. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  221. td = list_entry(urbp->td_list.next, struct uhci_td,
  222. list);
  223. toggle = uhci_toggle(td_token(td)) ^ 1;
  224. /* Otherwise all the toggles in the URB have to be switched */
  225. } else {
  226. list_for_each_entry(td, &urbp->td_list, list) {
  227. td->token ^= __constant_cpu_to_le32(
  228. TD_TOKEN_TOGGLE);
  229. toggle ^= 1;
  230. }
  231. }
  232. }
  233. wmb();
  234. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  235. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  236. usb_pipeout(pipe), toggle);
  237. qh->needs_fixup = 0;
  238. }
  239. /*
  240. * Put a QH on the schedule in both hardware and software
  241. */
  242. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  243. {
  244. struct uhci_qh *pqh;
  245. WARN_ON(list_empty(&qh->queue));
  246. /* Set the element pointer if it isn't set already.
  247. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  248. if (qh_element(qh) == UHCI_PTR_TERM) {
  249. struct urb_priv *urbp = list_entry(qh->queue.next,
  250. struct urb_priv, node);
  251. struct uhci_td *td = list_entry(urbp->td_list.next,
  252. struct uhci_td, list);
  253. qh->element = cpu_to_le32(td->dma_handle);
  254. }
  255. if (qh->state == QH_STATE_ACTIVE)
  256. return;
  257. qh->state = QH_STATE_ACTIVE;
  258. /* Move the QH from its old list to the end of the appropriate
  259. * skeleton's list */
  260. if (qh == uhci->next_qh)
  261. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  262. node);
  263. list_move_tail(&qh->node, &qh->skel->node);
  264. /* Link it into the schedule */
  265. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  266. qh->link = pqh->link;
  267. wmb();
  268. pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle);
  269. }
  270. /*
  271. * Take a QH off the hardware schedule
  272. */
  273. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  274. {
  275. struct uhci_qh *pqh;
  276. if (qh->state == QH_STATE_UNLINKING)
  277. return;
  278. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  279. qh->state = QH_STATE_UNLINKING;
  280. /* Unlink the QH from the schedule and record when we did it */
  281. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  282. pqh->link = qh->link;
  283. mb();
  284. uhci_get_current_frame_number(uhci);
  285. qh->unlink_frame = uhci->frame_number;
  286. /* Force an interrupt so we know when the QH is fully unlinked */
  287. if (list_empty(&uhci->skel_unlink_qh->node))
  288. uhci_set_next_interrupt(uhci);
  289. /* Move the QH from its old list to the end of the unlinking list */
  290. if (qh == uhci->next_qh)
  291. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  292. node);
  293. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  294. }
  295. /*
  296. * When we and the controller are through with a QH, it becomes IDLE.
  297. * This happens when a QH has been off the schedule (on the unlinking
  298. * list) for more than one frame, or when an error occurs while adding
  299. * the first URB onto a new QH.
  300. */
  301. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  302. {
  303. WARN_ON(qh->state == QH_STATE_ACTIVE);
  304. if (qh == uhci->next_qh)
  305. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  306. node);
  307. list_move(&qh->node, &uhci->idle_qh_list);
  308. qh->state = QH_STATE_IDLE;
  309. /* Now that the QH is idle, its post_td isn't being used */
  310. if (qh->post_td) {
  311. uhci_free_td(uhci, qh->post_td);
  312. qh->post_td = NULL;
  313. }
  314. /* If anyone is waiting for a QH to become idle, wake them up */
  315. if (uhci->num_waiting)
  316. wake_up_all(&uhci->waitqh);
  317. }
  318. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  319. struct urb *urb)
  320. {
  321. struct urb_priv *urbp;
  322. urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
  323. if (!urbp)
  324. return NULL;
  325. memset((void *)urbp, 0, sizeof(*urbp));
  326. urbp->urb = urb;
  327. urb->hcpriv = urbp;
  328. INIT_LIST_HEAD(&urbp->node);
  329. INIT_LIST_HEAD(&urbp->td_list);
  330. return urbp;
  331. }
  332. static void uhci_add_td_to_urb(struct urb *urb, struct uhci_td *td)
  333. {
  334. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  335. list_add_tail(&td->list, &urbp->td_list);
  336. }
  337. static void uhci_remove_td_from_urb(struct uhci_td *td)
  338. {
  339. if (list_empty(&td->list))
  340. return;
  341. list_del_init(&td->list);
  342. }
  343. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  344. struct urb_priv *urbp)
  345. {
  346. struct uhci_td *td, *tmp;
  347. if (!list_empty(&urbp->node))
  348. dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
  349. urbp->urb);
  350. uhci_get_current_frame_number(uhci);
  351. if (uhci->frame_number + uhci->is_stopped != uhci->td_remove_age) {
  352. uhci_free_pending_tds(uhci);
  353. uhci->td_remove_age = uhci->frame_number;
  354. }
  355. /* Check to see if the remove list is empty. Set the IOC bit */
  356. /* to force an interrupt so we can remove the TDs. */
  357. if (list_empty(&uhci->td_remove_list))
  358. uhci_set_next_interrupt(uhci);
  359. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  360. uhci_remove_td_from_urb(td);
  361. list_add(&td->remove_list, &uhci->td_remove_list);
  362. }
  363. urbp->urb->hcpriv = NULL;
  364. kmem_cache_free(uhci_up_cachep, urbp);
  365. }
  366. static void uhci_inc_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  367. {
  368. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  369. if ((!(urb->transfer_flags & URB_NO_FSBR)) && !urbp->fsbr) {
  370. urbp->fsbr = 1;
  371. if (!uhci->fsbr++ && !uhci->fsbrtimeout)
  372. uhci->skel_term_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
  373. }
  374. }
  375. static void uhci_dec_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  376. {
  377. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  378. if ((!(urb->transfer_flags & URB_NO_FSBR)) && urbp->fsbr) {
  379. urbp->fsbr = 0;
  380. if (!--uhci->fsbr)
  381. uhci->fsbrtimeout = jiffies + FSBR_DELAY;
  382. }
  383. }
  384. /*
  385. * Map status to standard result codes
  386. *
  387. * <status> is (td_status(td) & 0xF60000), a.k.a.
  388. * uhci_status_bits(td_status(td)).
  389. * Note: <status> does not include the TD_CTRL_NAK bit.
  390. * <dir_out> is True for output TDs and False for input TDs.
  391. */
  392. static int uhci_map_status(int status, int dir_out)
  393. {
  394. if (!status)
  395. return 0;
  396. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  397. return -EPROTO;
  398. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  399. if (dir_out)
  400. return -EPROTO;
  401. else
  402. return -EILSEQ;
  403. }
  404. if (status & TD_CTRL_BABBLE) /* Babble */
  405. return -EOVERFLOW;
  406. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  407. return -ENOSR;
  408. if (status & TD_CTRL_STALLED) /* Stalled */
  409. return -EPIPE;
  410. WARN_ON(status & TD_CTRL_ACTIVE); /* Active */
  411. return 0;
  412. }
  413. /*
  414. * Control transfers
  415. */
  416. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  417. struct uhci_qh *qh)
  418. {
  419. struct uhci_td *td;
  420. unsigned long destination, status;
  421. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  422. int len = urb->transfer_buffer_length;
  423. dma_addr_t data = urb->transfer_dma;
  424. __le32 *plink;
  425. /* The "pipe" thing contains the destination in bits 8--18 */
  426. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  427. /* 3 errors, dummy TD remains inactive */
  428. status = uhci_maxerr(3);
  429. if (urb->dev->speed == USB_SPEED_LOW)
  430. status |= TD_CTRL_LS;
  431. /*
  432. * Build the TD for the control request setup packet
  433. */
  434. td = qh->dummy_td;
  435. uhci_add_td_to_urb(urb, td);
  436. uhci_fill_td(td, status, destination | uhci_explen(8),
  437. urb->setup_dma);
  438. plink = &td->link;
  439. status |= TD_CTRL_ACTIVE;
  440. /*
  441. * If direction is "send", change the packet ID from SETUP (0x2D)
  442. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  443. * set Short Packet Detect (SPD) for all data packets.
  444. */
  445. if (usb_pipeout(urb->pipe))
  446. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  447. else {
  448. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  449. status |= TD_CTRL_SPD;
  450. }
  451. /*
  452. * Build the DATA TDs
  453. */
  454. while (len > 0) {
  455. int pktsze = min(len, maxsze);
  456. td = uhci_alloc_td(uhci);
  457. if (!td)
  458. goto nomem;
  459. *plink = cpu_to_le32(td->dma_handle);
  460. /* Alternate Data0/1 (start with Data1) */
  461. destination ^= TD_TOKEN_TOGGLE;
  462. uhci_add_td_to_urb(urb, td);
  463. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  464. data);
  465. plink = &td->link;
  466. data += pktsze;
  467. len -= pktsze;
  468. }
  469. /*
  470. * Build the final TD for control status
  471. */
  472. td = uhci_alloc_td(uhci);
  473. if (!td)
  474. goto nomem;
  475. *plink = cpu_to_le32(td->dma_handle);
  476. /*
  477. * It's IN if the pipe is an output pipe or we're not expecting
  478. * data back.
  479. */
  480. destination &= ~TD_TOKEN_PID_MASK;
  481. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  482. destination |= USB_PID_IN;
  483. else
  484. destination |= USB_PID_OUT;
  485. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  486. status &= ~TD_CTRL_SPD;
  487. uhci_add_td_to_urb(urb, td);
  488. uhci_fill_td(td, status | TD_CTRL_IOC,
  489. destination | uhci_explen(0), 0);
  490. plink = &td->link;
  491. /*
  492. * Build the new dummy TD and activate the old one
  493. */
  494. td = uhci_alloc_td(uhci);
  495. if (!td)
  496. goto nomem;
  497. *plink = cpu_to_le32(td->dma_handle);
  498. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  499. wmb();
  500. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  501. qh->dummy_td = td;
  502. /* Low-speed transfers get a different queue, and won't hog the bus.
  503. * Also, some devices enumerate better without FSBR; the easiest way
  504. * to do that is to put URBs on the low-speed queue while the device
  505. * isn't in the CONFIGURED state. */
  506. if (urb->dev->speed == USB_SPEED_LOW ||
  507. urb->dev->state != USB_STATE_CONFIGURED)
  508. qh->skel = uhci->skel_ls_control_qh;
  509. else {
  510. qh->skel = uhci->skel_fs_control_qh;
  511. uhci_inc_fsbr(uhci, urb);
  512. }
  513. urb->actual_length = -8; /* Account for the SETUP packet */
  514. return 0;
  515. nomem:
  516. /* Remove the dummy TD from the td_list so it doesn't get freed */
  517. uhci_remove_td_from_urb(qh->dummy_td);
  518. return -ENOMEM;
  519. }
  520. /*
  521. * Common submit for bulk and interrupt
  522. */
  523. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  524. struct uhci_qh *qh)
  525. {
  526. struct uhci_td *td;
  527. unsigned long destination, status;
  528. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  529. int len = urb->transfer_buffer_length;
  530. dma_addr_t data = urb->transfer_dma;
  531. __le32 *plink;
  532. unsigned int toggle;
  533. if (len < 0)
  534. return -EINVAL;
  535. /* The "pipe" thing contains the destination in bits 8--18 */
  536. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  537. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  538. usb_pipeout(urb->pipe));
  539. /* 3 errors, dummy TD remains inactive */
  540. status = uhci_maxerr(3);
  541. if (urb->dev->speed == USB_SPEED_LOW)
  542. status |= TD_CTRL_LS;
  543. if (usb_pipein(urb->pipe))
  544. status |= TD_CTRL_SPD;
  545. /*
  546. * Build the DATA TDs
  547. */
  548. plink = NULL;
  549. td = qh->dummy_td;
  550. do { /* Allow zero length packets */
  551. int pktsze = maxsze;
  552. if (len <= pktsze) { /* The last packet */
  553. pktsze = len;
  554. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  555. status &= ~TD_CTRL_SPD;
  556. }
  557. if (plink) {
  558. td = uhci_alloc_td(uhci);
  559. if (!td)
  560. goto nomem;
  561. *plink = cpu_to_le32(td->dma_handle);
  562. }
  563. uhci_add_td_to_urb(urb, td);
  564. uhci_fill_td(td, status,
  565. destination | uhci_explen(pktsze) |
  566. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  567. data);
  568. plink = &td->link;
  569. status |= TD_CTRL_ACTIVE;
  570. data += pktsze;
  571. len -= maxsze;
  572. toggle ^= 1;
  573. } while (len > 0);
  574. /*
  575. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  576. * is OUT and the transfer_length was an exact multiple of maxsze,
  577. * hence (len = transfer_length - N * maxsze) == 0
  578. * however, if transfer_length == 0, the zero packet was already
  579. * prepared above.
  580. */
  581. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  582. usb_pipeout(urb->pipe) && len == 0 &&
  583. urb->transfer_buffer_length > 0) {
  584. td = uhci_alloc_td(uhci);
  585. if (!td)
  586. goto nomem;
  587. *plink = cpu_to_le32(td->dma_handle);
  588. uhci_add_td_to_urb(urb, td);
  589. uhci_fill_td(td, status,
  590. destination | uhci_explen(0) |
  591. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  592. data);
  593. plink = &td->link;
  594. toggle ^= 1;
  595. }
  596. /* Set the interrupt-on-completion flag on the last packet.
  597. * A more-or-less typical 4 KB URB (= size of one memory page)
  598. * will require about 3 ms to transfer; that's a little on the
  599. * fast side but not enough to justify delaying an interrupt
  600. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  601. * flag setting. */
  602. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  603. /*
  604. * Build the new dummy TD and activate the old one
  605. */
  606. td = uhci_alloc_td(uhci);
  607. if (!td)
  608. goto nomem;
  609. *plink = cpu_to_le32(td->dma_handle);
  610. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  611. wmb();
  612. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  613. qh->dummy_td = td;
  614. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  615. usb_pipeout(urb->pipe), toggle);
  616. return 0;
  617. nomem:
  618. /* Remove the dummy TD from the td_list so it doesn't get freed */
  619. uhci_remove_td_from_urb(qh->dummy_td);
  620. return -ENOMEM;
  621. }
  622. static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  623. struct uhci_qh *qh)
  624. {
  625. int ret;
  626. /* Can't have low-speed bulk transfers */
  627. if (urb->dev->speed == USB_SPEED_LOW)
  628. return -EINVAL;
  629. qh->skel = uhci->skel_bulk_qh;
  630. ret = uhci_submit_common(uhci, urb, qh);
  631. if (ret == 0)
  632. uhci_inc_fsbr(uhci, urb);
  633. return ret;
  634. }
  635. static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  636. struct uhci_qh *qh)
  637. {
  638. /* USB 1.1 interrupt transfers only involve one packet per interval.
  639. * Drivers can submit URBs of any length, but longer ones will need
  640. * multiple intervals to complete.
  641. */
  642. qh->skel = uhci->skelqh[__interval_to_skel(urb->interval)];
  643. return uhci_submit_common(uhci, urb, qh);
  644. }
  645. /*
  646. * Fix up the data structures following a short transfer
  647. */
  648. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  649. struct uhci_qh *qh, struct urb_priv *urbp)
  650. {
  651. struct uhci_td *td;
  652. struct list_head *tmp;
  653. int ret;
  654. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  655. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  656. /* When a control transfer is short, we have to restart
  657. * the queue at the status stage transaction, which is
  658. * the last TD. */
  659. WARN_ON(list_empty(&urbp->td_list));
  660. qh->element = cpu_to_le32(td->dma_handle);
  661. tmp = td->list.prev;
  662. ret = -EINPROGRESS;
  663. } else {
  664. /* When a bulk/interrupt transfer is short, we have to
  665. * fix up the toggles of the following URBs on the queue
  666. * before restarting the queue at the next URB. */
  667. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  668. uhci_fixup_toggles(qh, 1);
  669. if (list_empty(&urbp->td_list))
  670. td = qh->post_td;
  671. qh->element = td->link;
  672. tmp = urbp->td_list.prev;
  673. ret = 0;
  674. }
  675. /* Remove all the TDs we skipped over, from tmp back to the start */
  676. while (tmp != &urbp->td_list) {
  677. td = list_entry(tmp, struct uhci_td, list);
  678. tmp = tmp->prev;
  679. uhci_remove_td_from_urb(td);
  680. list_add(&td->remove_list, &uhci->td_remove_list);
  681. }
  682. return ret;
  683. }
  684. /*
  685. * Common result for control, bulk, and interrupt
  686. */
  687. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  688. {
  689. struct urb_priv *urbp = urb->hcpriv;
  690. struct uhci_qh *qh = urbp->qh;
  691. struct uhci_td *td, *tmp;
  692. unsigned status;
  693. int ret = 0;
  694. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  695. unsigned int ctrlstat;
  696. int len;
  697. ctrlstat = td_status(td);
  698. status = uhci_status_bits(ctrlstat);
  699. if (status & TD_CTRL_ACTIVE)
  700. return -EINPROGRESS;
  701. len = uhci_actual_length(ctrlstat);
  702. urb->actual_length += len;
  703. if (status) {
  704. ret = uhci_map_status(status,
  705. uhci_packetout(td_token(td)));
  706. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  707. /* Some debugging code */
  708. dev_dbg(uhci_dev(uhci),
  709. "%s: failed with status %x\n",
  710. __FUNCTION__, status);
  711. if (debug > 1 && errbuf) {
  712. /* Print the chain for debugging */
  713. uhci_show_qh(urbp->qh, errbuf,
  714. ERRBUF_LEN, 0);
  715. lprintk(errbuf);
  716. }
  717. }
  718. } else if (len < uhci_expected_length(td_token(td))) {
  719. /* We received a short packet */
  720. if (urb->transfer_flags & URB_SHORT_NOT_OK)
  721. ret = -EREMOTEIO;
  722. else if (ctrlstat & TD_CTRL_SPD)
  723. ret = 1;
  724. }
  725. uhci_remove_td_from_urb(td);
  726. if (qh->post_td)
  727. list_add(&qh->post_td->remove_list,
  728. &uhci->td_remove_list);
  729. qh->post_td = td;
  730. if (ret != 0)
  731. goto err;
  732. }
  733. return ret;
  734. err:
  735. if (ret < 0) {
  736. /* In case a control transfer gets an error
  737. * during the setup stage */
  738. urb->actual_length = max(urb->actual_length, 0);
  739. /* Note that the queue has stopped and save
  740. * the next toggle value */
  741. qh->element = UHCI_PTR_TERM;
  742. qh->is_stopped = 1;
  743. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  744. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  745. (ret == -EREMOTEIO);
  746. } else /* Short packet received */
  747. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  748. return ret;
  749. }
  750. /*
  751. * Isochronous transfers
  752. */
  753. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  754. struct uhci_qh *qh)
  755. {
  756. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  757. int i, frame;
  758. unsigned long destination, status;
  759. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  760. if (urb->number_of_packets > 900) /* 900? Why? */
  761. return -EFBIG;
  762. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  763. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  764. /* Figure out the starting frame number */
  765. if (urb->transfer_flags & URB_ISO_ASAP) {
  766. if (list_empty(&qh->queue)) {
  767. uhci_get_current_frame_number(uhci);
  768. urb->start_frame = (uhci->frame_number + 10);
  769. } else { /* Go right after the last one */
  770. struct urb *last_urb;
  771. last_urb = list_entry(qh->queue.prev,
  772. struct urb_priv, node)->urb;
  773. urb->start_frame = (last_urb->start_frame +
  774. last_urb->number_of_packets *
  775. last_urb->interval);
  776. }
  777. } else {
  778. /* FIXME: Sanity check */
  779. }
  780. urb->start_frame &= (UHCI_NUMFRAMES - 1);
  781. for (i = 0; i < urb->number_of_packets; i++) {
  782. td = uhci_alloc_td(uhci);
  783. if (!td)
  784. return -ENOMEM;
  785. uhci_add_td_to_urb(urb, td);
  786. uhci_fill_td(td, status, destination |
  787. uhci_explen(urb->iso_frame_desc[i].length),
  788. urb->transfer_dma +
  789. urb->iso_frame_desc[i].offset);
  790. }
  791. /* Set the interrupt-on-completion flag on the last packet. */
  792. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  793. qh->skel = uhci->skel_iso_qh;
  794. /* Add the TDs to the frame list */
  795. frame = urb->start_frame;
  796. list_for_each_entry(td, &urbp->td_list, list) {
  797. uhci_insert_td_in_frame_list(uhci, td, frame);
  798. frame += urb->interval;
  799. }
  800. return 0;
  801. }
  802. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  803. {
  804. struct uhci_td *td;
  805. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  806. int status;
  807. int i, ret = 0;
  808. urb->actual_length = urb->error_count = 0;
  809. i = 0;
  810. list_for_each_entry(td, &urbp->td_list, list) {
  811. int actlength;
  812. unsigned int ctrlstat = td_status(td);
  813. if (ctrlstat & TD_CTRL_ACTIVE)
  814. return -EINPROGRESS;
  815. actlength = uhci_actual_length(ctrlstat);
  816. urb->iso_frame_desc[i].actual_length = actlength;
  817. urb->actual_length += actlength;
  818. status = uhci_map_status(uhci_status_bits(ctrlstat),
  819. usb_pipeout(urb->pipe));
  820. urb->iso_frame_desc[i].status = status;
  821. if (status) {
  822. urb->error_count++;
  823. ret = status;
  824. }
  825. i++;
  826. }
  827. return ret;
  828. }
  829. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  830. struct usb_host_endpoint *hep,
  831. struct urb *urb, gfp_t mem_flags)
  832. {
  833. int ret;
  834. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  835. unsigned long flags;
  836. struct urb_priv *urbp;
  837. struct uhci_qh *qh;
  838. int bustime;
  839. spin_lock_irqsave(&uhci->lock, flags);
  840. ret = urb->status;
  841. if (ret != -EINPROGRESS) /* URB already unlinked! */
  842. goto done;
  843. ret = -ENOMEM;
  844. urbp = uhci_alloc_urb_priv(uhci, urb);
  845. if (!urbp)
  846. goto done;
  847. if (hep->hcpriv)
  848. qh = (struct uhci_qh *) hep->hcpriv;
  849. else {
  850. qh = uhci_alloc_qh(uhci, urb->dev, hep);
  851. if (!qh)
  852. goto err_no_qh;
  853. }
  854. urbp->qh = qh;
  855. switch (qh->type) {
  856. case USB_ENDPOINT_XFER_CONTROL:
  857. ret = uhci_submit_control(uhci, urb, qh);
  858. break;
  859. case USB_ENDPOINT_XFER_BULK:
  860. ret = uhci_submit_bulk(uhci, urb, qh);
  861. break;
  862. case USB_ENDPOINT_XFER_INT:
  863. if (list_empty(&qh->queue)) {
  864. bustime = usb_check_bandwidth(urb->dev, urb);
  865. if (bustime < 0)
  866. ret = bustime;
  867. else {
  868. ret = uhci_submit_interrupt(uhci, urb, qh);
  869. if (ret == 0)
  870. usb_claim_bandwidth(urb->dev, urb, bustime, 0);
  871. }
  872. } else { /* inherit from parent */
  873. struct urb_priv *eurbp;
  874. eurbp = list_entry(qh->queue.prev, struct urb_priv,
  875. node);
  876. urb->bandwidth = eurbp->urb->bandwidth;
  877. ret = uhci_submit_interrupt(uhci, urb, qh);
  878. }
  879. break;
  880. case USB_ENDPOINT_XFER_ISOC:
  881. bustime = usb_check_bandwidth(urb->dev, urb);
  882. if (bustime < 0) {
  883. ret = bustime;
  884. break;
  885. }
  886. ret = uhci_submit_isochronous(uhci, urb, qh);
  887. if (ret == 0)
  888. usb_claim_bandwidth(urb->dev, urb, bustime, 1);
  889. break;
  890. }
  891. if (ret != 0)
  892. goto err_submit_failed;
  893. /* Add this URB to the QH */
  894. urbp->qh = qh;
  895. list_add_tail(&urbp->node, &qh->queue);
  896. /* If the new URB is the first and only one on this QH then either
  897. * the QH is new and idle or else it's unlinked and waiting to
  898. * become idle, so we can activate it right away. But only if the
  899. * queue isn't stopped. */
  900. if (qh->queue.next == &urbp->node && !qh->is_stopped)
  901. uhci_activate_qh(uhci, qh);
  902. goto done;
  903. err_submit_failed:
  904. if (qh->state == QH_STATE_IDLE)
  905. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  906. err_no_qh:
  907. uhci_free_urb_priv(uhci, urbp);
  908. done:
  909. spin_unlock_irqrestore(&uhci->lock, flags);
  910. return ret;
  911. }
  912. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  913. {
  914. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  915. unsigned long flags;
  916. struct urb_priv *urbp;
  917. spin_lock_irqsave(&uhci->lock, flags);
  918. urbp = urb->hcpriv;
  919. if (!urbp) /* URB was never linked! */
  920. goto done;
  921. /* Remove Isochronous TDs from the frame list ASAP */
  922. if (urbp->qh->type == USB_ENDPOINT_XFER_ISOC)
  923. uhci_unlink_isochronous_tds(uhci, urb);
  924. uhci_unlink_qh(uhci, urbp->qh);
  925. done:
  926. spin_unlock_irqrestore(&uhci->lock, flags);
  927. return 0;
  928. }
  929. /*
  930. * Finish unlinking an URB and give it back
  931. */
  932. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  933. struct urb *urb, struct pt_regs *regs)
  934. __releases(uhci->lock)
  935. __acquires(uhci->lock)
  936. {
  937. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  938. /* Isochronous TDs get unlinked directly from the frame list */
  939. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  940. uhci_unlink_isochronous_tds(uhci, urb);
  941. /* If the URB isn't first on its queue, adjust the link pointer
  942. * of the last TD in the previous URB. */
  943. else if (qh->queue.next != &urbp->node) {
  944. struct urb_priv *purbp;
  945. struct uhci_td *ptd, *ltd;
  946. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  947. WARN_ON(list_empty(&purbp->td_list));
  948. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  949. list);
  950. ltd = list_entry(urbp->td_list.prev, struct uhci_td,
  951. list);
  952. ptd->link = ltd->link;
  953. }
  954. /* Take the URB off the QH's queue. If the queue is now empty,
  955. * this is a perfect time for a toggle fixup. */
  956. list_del_init(&urbp->node);
  957. if (list_empty(&qh->queue) && qh->needs_fixup) {
  958. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  959. usb_pipeout(urb->pipe), qh->initial_toggle);
  960. qh->needs_fixup = 0;
  961. }
  962. uhci_dec_fsbr(uhci, urb); /* Safe since it checks */
  963. uhci_free_urb_priv(uhci, urbp);
  964. switch (qh->type) {
  965. case USB_ENDPOINT_XFER_ISOC:
  966. /* Release bandwidth for Interrupt or Isoc. transfers */
  967. if (urb->bandwidth)
  968. usb_release_bandwidth(urb->dev, urb, 1);
  969. break;
  970. case USB_ENDPOINT_XFER_INT:
  971. /* Release bandwidth for Interrupt or Isoc. transfers */
  972. /* Make sure we don't release if we have a queued URB */
  973. if (list_empty(&qh->queue) && urb->bandwidth)
  974. usb_release_bandwidth(urb->dev, urb, 0);
  975. else
  976. /* bandwidth was passed on to queued URB, */
  977. /* so don't let usb_unlink_urb() release it */
  978. urb->bandwidth = 0;
  979. break;
  980. }
  981. spin_unlock(&uhci->lock);
  982. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, regs);
  983. spin_lock(&uhci->lock);
  984. /* If the queue is now empty, we can unlink the QH and give up its
  985. * reserved bandwidth. */
  986. if (list_empty(&qh->queue)) {
  987. uhci_unlink_qh(uhci, qh);
  988. /* Bandwidth stuff not yet implemented */
  989. }
  990. }
  991. /*
  992. * Scan the URBs in a QH's queue
  993. */
  994. #define QH_FINISHED_UNLINKING(qh) \
  995. (qh->state == QH_STATE_UNLINKING && \
  996. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  997. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh,
  998. struct pt_regs *regs)
  999. {
  1000. struct urb_priv *urbp;
  1001. struct urb *urb;
  1002. int status;
  1003. while (!list_empty(&qh->queue)) {
  1004. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1005. urb = urbp->urb;
  1006. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1007. status = uhci_result_isochronous(uhci, urb);
  1008. else
  1009. status = uhci_result_common(uhci, urb);
  1010. if (status == -EINPROGRESS)
  1011. break;
  1012. spin_lock(&urb->lock);
  1013. if (urb->status == -EINPROGRESS) /* Not dequeued */
  1014. urb->status = status;
  1015. else
  1016. status = ECONNRESET; /* Not -ECONNRESET */
  1017. spin_unlock(&urb->lock);
  1018. /* Dequeued but completed URBs can't be given back unless
  1019. * the QH is stopped or has finished unlinking. */
  1020. if (status == ECONNRESET) {
  1021. if (QH_FINISHED_UNLINKING(qh))
  1022. qh->is_stopped = 1;
  1023. else if (!qh->is_stopped)
  1024. return;
  1025. }
  1026. uhci_giveback_urb(uhci, qh, urb, regs);
  1027. if (status < 0)
  1028. break;
  1029. }
  1030. /* If the QH is neither stopped nor finished unlinking (normal case),
  1031. * our work here is done. */
  1032. if (QH_FINISHED_UNLINKING(qh))
  1033. qh->is_stopped = 1;
  1034. else if (!qh->is_stopped)
  1035. return;
  1036. /* Otherwise give back each of the dequeued URBs */
  1037. restart:
  1038. list_for_each_entry(urbp, &qh->queue, node) {
  1039. urb = urbp->urb;
  1040. if (urb->status != -EINPROGRESS) {
  1041. uhci_save_toggle(qh, urb);
  1042. uhci_giveback_urb(uhci, qh, urb, regs);
  1043. goto restart;
  1044. }
  1045. }
  1046. qh->is_stopped = 0;
  1047. /* There are no more dequeued URBs. If there are still URBs on the
  1048. * queue, the QH can now be re-activated. */
  1049. if (!list_empty(&qh->queue)) {
  1050. if (qh->needs_fixup)
  1051. uhci_fixup_toggles(qh, 0);
  1052. uhci_activate_qh(uhci, qh);
  1053. }
  1054. /* The queue is empty. The QH can become idle if it is fully
  1055. * unlinked. */
  1056. else if (QH_FINISHED_UNLINKING(qh))
  1057. uhci_make_qh_idle(uhci, qh);
  1058. }
  1059. static void uhci_free_pending_tds(struct uhci_hcd *uhci)
  1060. {
  1061. struct uhci_td *td, *tmp;
  1062. list_for_each_entry_safe(td, tmp, &uhci->td_remove_list, remove_list) {
  1063. list_del_init(&td->remove_list);
  1064. uhci_free_td(uhci, td);
  1065. }
  1066. }
  1067. /*
  1068. * Process events in the schedule, but only in one thread at a time
  1069. */
  1070. static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs)
  1071. {
  1072. int i;
  1073. struct uhci_qh *qh;
  1074. /* Don't allow re-entrant calls */
  1075. if (uhci->scan_in_progress) {
  1076. uhci->need_rescan = 1;
  1077. return;
  1078. }
  1079. uhci->scan_in_progress = 1;
  1080. rescan:
  1081. uhci->need_rescan = 0;
  1082. uhci_clear_next_interrupt(uhci);
  1083. uhci_get_current_frame_number(uhci);
  1084. if (uhci->frame_number + uhci->is_stopped != uhci->td_remove_age)
  1085. uhci_free_pending_tds(uhci);
  1086. /* Go through all the QH queues and process the URBs in each one */
  1087. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1088. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1089. struct uhci_qh, node);
  1090. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1091. uhci->next_qh = list_entry(qh->node.next,
  1092. struct uhci_qh, node);
  1093. uhci_scan_qh(uhci, qh, regs);
  1094. }
  1095. }
  1096. if (uhci->need_rescan)
  1097. goto rescan;
  1098. uhci->scan_in_progress = 0;
  1099. /* If the controller is stopped, we can finish these off right now */
  1100. if (uhci->is_stopped)
  1101. uhci_free_pending_tds(uhci);
  1102. if (list_empty(&uhci->td_remove_list) &&
  1103. list_empty(&uhci->skel_unlink_qh->node))
  1104. uhci_clear_next_interrupt(uhci);
  1105. else
  1106. uhci_set_next_interrupt(uhci);
  1107. }
  1108. static void check_fsbr(struct uhci_hcd *uhci)
  1109. {
  1110. /* For now, don't scan URBs for FSBR timeouts.
  1111. * Add it back in later... */
  1112. /* Really disable FSBR */
  1113. if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) {
  1114. uhci->fsbrtimeout = 0;
  1115. uhci->skel_term_qh->link = UHCI_PTR_TERM;
  1116. }
  1117. }