taishan.dts 10 KB

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  1. /*
  2. * Device Tree Source for IBM/AMCC Taishan
  3. *
  4. * Copyright 2007 IBM Corp.
  5. * Hugh Blemings <hugh@au.ibm.com> based off code by
  6. * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without
  10. * any warranty of any kind, whether express or implied.
  11. */
  12. /dts-v1/;
  13. / {
  14. #address-cells = <2>;
  15. #size-cells = <1>;
  16. model = "amcc,taishan";
  17. compatible = "amcc,taishan";
  18. dcr-parent = <&{/cpus/cpu@0}>;
  19. aliases {
  20. ethernet0 = &EMAC2;
  21. ethernet1 = &EMAC3;
  22. serial0 = &UART0;
  23. serial1 = &UART1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. cpu@0 {
  29. device_type = "cpu";
  30. model = "PowerPC,440GX";
  31. reg = <0x00000000>;
  32. clock-frequency = <800000000>; // 800MHz
  33. timebase-frequency = <0>; // Filled in by zImage
  34. i-cache-line-size = <50>;
  35. d-cache-line-size = <50>;
  36. i-cache-size = <32768>; /* 32 kB */
  37. d-cache-size = <32768>; /* 32 kB */
  38. dcr-controller;
  39. dcr-access-method = "native";
  40. };
  41. };
  42. memory {
  43. device_type = "memory";
  44. reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
  45. };
  46. UICB0: interrupt-controller-base {
  47. compatible = "ibm,uic-440gx", "ibm,uic";
  48. interrupt-controller;
  49. cell-index = <3>;
  50. dcr-reg = <0x200 0x009>;
  51. #address-cells = <0>;
  52. #size-cells = <0>;
  53. #interrupt-cells = <2>;
  54. };
  55. UIC0: interrupt-controller0 {
  56. compatible = "ibm,uic-440gx", "ibm,uic";
  57. interrupt-controller;
  58. cell-index = <0>;
  59. dcr-reg = <0x0c0 0x009>;
  60. #address-cells = <0>;
  61. #size-cells = <0>;
  62. #interrupt-cells = <2>;
  63. interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
  64. interrupt-parent = <&UICB0>;
  65. };
  66. UIC1: interrupt-controller1 {
  67. compatible = "ibm,uic-440gx", "ibm,uic";
  68. interrupt-controller;
  69. cell-index = <1>;
  70. dcr-reg = <0x0d0 0x009>;
  71. #address-cells = <0>;
  72. #size-cells = <0>;
  73. #interrupt-cells = <2>;
  74. interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
  75. interrupt-parent = <&UICB0>;
  76. };
  77. UIC2: interrupt-controller2 {
  78. compatible = "ibm,uic-440gx", "ibm,uic";
  79. interrupt-controller;
  80. cell-index = <2>; /* was 1 */
  81. dcr-reg = <0x210 0x009>;
  82. #address-cells = <0>;
  83. #size-cells = <0>;
  84. #interrupt-cells = <2>;
  85. interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
  86. interrupt-parent = <&UICB0>;
  87. };
  88. CPC0: cpc {
  89. compatible = "ibm,cpc-440gp";
  90. dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
  91. // FIXME: anything else?
  92. };
  93. L2C0: l2c {
  94. compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
  95. dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
  96. 0x030 0x008>; /* L2 cache DCR's */
  97. cache-line-size = <32>; /* 32 bytes */
  98. cache-size = <262144>; /* L2, 256K */
  99. interrupt-parent = <&UIC2>;
  100. interrupts = <0x17 0x1>;
  101. };
  102. plb {
  103. compatible = "ibm,plb-440gx", "ibm,plb4";
  104. #address-cells = <2>;
  105. #size-cells = <1>;
  106. ranges;
  107. clock-frequency = <160000000>; // 160MHz
  108. SDRAM0: memory-controller {
  109. compatible = "ibm,sdram-440gp";
  110. dcr-reg = <0x010 0x002>;
  111. // FIXME: anything else?
  112. };
  113. SRAM0: sram {
  114. compatible = "ibm,sram-440gp";
  115. dcr-reg = <0x020 0x008 0x00a 0x001>;
  116. };
  117. DMA0: dma {
  118. // FIXME: ???
  119. compatible = "ibm,dma-440gp";
  120. dcr-reg = <0x100 0x027>;
  121. };
  122. MAL0: mcmal {
  123. compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
  124. dcr-reg = <0x180 0x062>;
  125. num-tx-chans = <4>;
  126. num-rx-chans = <4>;
  127. interrupt-parent = <&MAL0>;
  128. interrupts = <0x0 0x1 0x2 0x3 0x4>;
  129. #interrupt-cells = <1>;
  130. #address-cells = <0>;
  131. #size-cells = <0>;
  132. interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
  133. /*RXEOB*/ 0x1 &UIC0 0xb 0x4
  134. /*SERR*/ 0x2 &UIC1 0x0 0x4
  135. /*TXDE*/ 0x3 &UIC1 0x1 0x4
  136. /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
  137. interrupt-map-mask = <0xffffffff>;
  138. };
  139. POB0: opb {
  140. compatible = "ibm,opb-440gx", "ibm,opb";
  141. #address-cells = <1>;
  142. #size-cells = <1>;
  143. /* Wish there was a nicer way of specifying a full 32-bit
  144. range */
  145. ranges = <0x00000000 0x00000001 0x00000000 0x80000000
  146. 0x80000000 0x00000001 0x80000000 0x80000000>;
  147. dcr-reg = <0x090 0x00b>;
  148. interrupt-parent = <&UIC1>;
  149. interrupts = <0x7 0x4>;
  150. clock-frequency = <80000000>; // 80MHz
  151. EBC0: ebc {
  152. compatible = "ibm,ebc-440gx", "ibm,ebc";
  153. dcr-reg = <0x012 0x002>;
  154. #address-cells = <2>;
  155. #size-cells = <1>;
  156. clock-frequency = <80000000>; // 80MHz
  157. /* ranges property is supplied by zImage
  158. * based on firmware's configuration of the
  159. * EBC bridge */
  160. interrupts = <0x5 0x4>;
  161. interrupt-parent = <&UIC1>;
  162. /* TODO: Add other EBC devices */
  163. };
  164. UART0: serial@40000200 {
  165. device_type = "serial";
  166. compatible = "ns16550";
  167. reg = <0x40000200 0x00000008>;
  168. virtual-reg = <0xe0000200>;
  169. clock-frequency = <11059200>;
  170. current-speed = <115200>; /* 115200 */
  171. interrupt-parent = <&UIC0>;
  172. interrupts = <0x0 0x4>;
  173. };
  174. UART1: serial@40000300 {
  175. device_type = "serial";
  176. compatible = "ns16550";
  177. reg = <0x40000300 0x00000008>;
  178. virtual-reg = <0xe0000300>;
  179. clock-frequency = <11059200>;
  180. current-speed = <115200>; /* 115200 */
  181. interrupt-parent = <&UIC0>;
  182. interrupts = <0x1 0x4>;
  183. };
  184. IIC0: i2c@40000400 {
  185. /* FIXME */
  186. compatible = "ibm,iic-440gp", "ibm,iic";
  187. reg = <0x40000400 0x00000014>;
  188. interrupt-parent = <&UIC0>;
  189. interrupts = <0x2 0x4>;
  190. };
  191. IIC1: i2c@40000500 {
  192. /* FIXME */
  193. compatible = "ibm,iic-440gp", "ibm,iic";
  194. reg = <0x40000500 0x00000014>;
  195. interrupt-parent = <&UIC0>;
  196. interrupts = <0x3 0x4>;
  197. };
  198. GPIO0: gpio@40000700 {
  199. /* FIXME */
  200. compatible = "ibm,gpio-440gp";
  201. reg = <0x40000700 0x00000020>;
  202. };
  203. ZMII0: emac-zmii@40000780 {
  204. compatible = "ibm,zmii-440gx", "ibm,zmii";
  205. reg = <0x40000780 0x0000000c>;
  206. };
  207. RGMII0: emac-rgmii@40000790 {
  208. compatible = "ibm,rgmii";
  209. reg = <0x40000790 0x00000008>;
  210. };
  211. TAH0: emac-tah@40000b50 {
  212. compatible = "ibm,tah-440gx", "ibm,tah";
  213. reg = <0x40000b50 0x00000030>;
  214. };
  215. TAH1: emac-tah@40000d50 {
  216. compatible = "ibm,tah-440gx", "ibm,tah";
  217. reg = <0x40000d50 0x00000030>;
  218. };
  219. EMAC0: ethernet@40000800 {
  220. unused = <0x1>;
  221. device_type = "network";
  222. compatible = "ibm,emac-440gx", "ibm,emac4";
  223. interrupt-parent = <&UIC1>;
  224. interrupts = <0x1c 0x4 0x1d 0x4>;
  225. reg = <0x40000800 0x00000070>;
  226. local-mac-address = [000000000000]; // Filled in by zImage
  227. mal-device = <&MAL0>;
  228. mal-tx-channel = <0>;
  229. mal-rx-channel = <0>;
  230. cell-index = <0>;
  231. max-frame-size = <1500>;
  232. rx-fifo-size = <4096>;
  233. tx-fifo-size = <2048>;
  234. phy-mode = "rmii";
  235. phy-map = <0x00000001>;
  236. zmii-device = <&ZMII0>;
  237. zmii-channel = <0>;
  238. };
  239. EMAC1: ethernet@40000900 {
  240. unused = <0x1>;
  241. device_type = "network";
  242. compatible = "ibm,emac-440gx", "ibm,emac4";
  243. interrupt-parent = <&UIC1>;
  244. interrupts = <0x1e 0x4 0x1f 0x4>;
  245. reg = <0x40000900 0x00000070>;
  246. local-mac-address = [000000000000]; // Filled in by zImage
  247. mal-device = <&MAL0>;
  248. mal-tx-channel = <1>;
  249. mal-rx-channel = <1>;
  250. cell-index = <1>;
  251. max-frame-size = <1500>;
  252. rx-fifo-size = <4096>;
  253. tx-fifo-size = <2048>;
  254. phy-mode = "rmii";
  255. phy-map = <0x00000001>;
  256. zmii-device = <&ZMII0>;
  257. zmii-channel = <1>;
  258. };
  259. EMAC2: ethernet@40000c00 {
  260. device_type = "network";
  261. compatible = "ibm,emac-440gx", "ibm,emac4";
  262. interrupt-parent = <&UIC2>;
  263. interrupts = <0x0 0x4 0x1 0x4>;
  264. reg = <0x40000c00 0x00000070>;
  265. local-mac-address = [000000000000]; // Filled in by zImage
  266. mal-device = <&MAL0>;
  267. mal-tx-channel = <2>;
  268. mal-rx-channel = <2>;
  269. cell-index = <2>;
  270. max-frame-size = <9000>;
  271. rx-fifo-size = <4096>;
  272. tx-fifo-size = <2048>;
  273. phy-mode = "rgmii";
  274. phy-map = <0x00000001>;
  275. rgmii-device = <&RGMII0>;
  276. rgmii-channel = <0>;
  277. zmii-device = <&ZMII0>;
  278. zmii-channel = <2>;
  279. tah-device = <&TAH0>;
  280. tah-channel = <0>;
  281. };
  282. EMAC3: ethernet@40000e00 {
  283. device_type = "network";
  284. compatible = "ibm,emac-440gx", "ibm,emac4";
  285. interrupt-parent = <&UIC2>;
  286. interrupts = <0x2 0x4 0x3 0x4>;
  287. reg = <0x40000e00 0x00000070>;
  288. local-mac-address = [000000000000]; // Filled in by zImage
  289. mal-device = <&MAL0>;
  290. mal-tx-channel = <3>;
  291. mal-rx-channel = <3>;
  292. cell-index = <3>;
  293. max-frame-size = <9000>;
  294. rx-fifo-size = <4096>;
  295. tx-fifo-size = <2048>;
  296. phy-mode = "rgmii";
  297. phy-map = <0x00000003>;
  298. rgmii-device = <&RGMII0>;
  299. rgmii-channel = <1>;
  300. zmii-device = <&ZMII0>;
  301. zmii-channel = <3>;
  302. tah-device = <&TAH1>;
  303. tah-channel = <0>;
  304. };
  305. GPT0: gpt@40000a00 {
  306. /* FIXME */
  307. reg = <0x40000a00 0x000000d4>;
  308. interrupt-parent = <&UIC0>;
  309. interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
  310. };
  311. };
  312. PCIX0: pci@20ec00000 {
  313. device_type = "pci";
  314. #interrupt-cells = <1>;
  315. #size-cells = <2>;
  316. #address-cells = <3>;
  317. compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
  318. primary;
  319. large-inbound-windows;
  320. enable-msi-hole;
  321. reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
  322. 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
  323. 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
  324. 0x00000002 0x0ec80000 0x00000100 /* Internal registers */
  325. 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
  326. /* Outbound ranges, one memory and one IO,
  327. * later cannot be changed
  328. */
  329. ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
  330. 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
  331. /* Inbound 2GB range starting at 0 */
  332. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  333. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  334. interrupt-map = <
  335. /* IDSEL 1 */
  336. 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8
  337. 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8
  338. 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8
  339. 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8
  340. /* IDSEL 2 */
  341. 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8
  342. 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8
  343. 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8
  344. 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8
  345. >;
  346. };
  347. };
  348. chosen {
  349. linux,stdout-path = "/plb/opb/serial@40000300";
  350. };
  351. };