mpc8544ds.dts 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458
  1. /*
  2. * MPC8544 DS Device Tree Source
  3. *
  4. * Copyright 2007, 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8544DS";
  14. compatible = "MPC8544DS", "MPC85xxDS";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. pci2 = &pci2;
  25. pci3 = &pci3;
  26. };
  27. cpus {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. PowerPC,8544@0 {
  31. device_type = "cpu";
  32. reg = <0x0>;
  33. d-cache-line-size = <32>; // 32 bytes
  34. i-cache-line-size = <32>; // 32 bytes
  35. d-cache-size = <0x8000>; // L1, 32K
  36. i-cache-size = <0x8000>; // L1, 32K
  37. timebase-frequency = <0>;
  38. bus-frequency = <0>;
  39. clock-frequency = <0>;
  40. };
  41. };
  42. memory {
  43. device_type = "memory";
  44. reg = <0x0 0x0>; // Filled by U-Boot
  45. };
  46. soc8544@e0000000 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. device_type = "soc";
  50. ranges = <0x0 0xe0000000 0x100000>;
  51. reg = <0xe0000000 0x1000>; // CCSRBAR 1M
  52. bus-frequency = <0>; // Filled out by uboot.
  53. memory-controller@2000 {
  54. compatible = "fsl,8544-memory-controller";
  55. reg = <0x2000 0x1000>;
  56. interrupt-parent = <&mpic>;
  57. interrupts = <18 2>;
  58. };
  59. l2-cache-controller@20000 {
  60. compatible = "fsl,8544-l2-cache-controller";
  61. reg = <0x20000 0x1000>;
  62. cache-line-size = <32>; // 32 bytes
  63. cache-size = <0x40000>; // L2, 256K
  64. interrupt-parent = <&mpic>;
  65. interrupts = <16 2>;
  66. };
  67. i2c@3000 {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. cell-index = <0>;
  71. compatible = "fsl-i2c";
  72. reg = <0x3000 0x100>;
  73. interrupts = <43 2>;
  74. interrupt-parent = <&mpic>;
  75. dfsrr;
  76. };
  77. i2c@3100 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. cell-index = <1>;
  81. compatible = "fsl-i2c";
  82. reg = <0x3100 0x100>;
  83. interrupts = <43 2>;
  84. interrupt-parent = <&mpic>;
  85. dfsrr;
  86. };
  87. mdio@24520 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. compatible = "fsl,gianfar-mdio";
  91. reg = <0x24520 0x20>;
  92. phy0: ethernet-phy@0 {
  93. interrupt-parent = <&mpic>;
  94. interrupts = <10 1>;
  95. reg = <0x0>;
  96. device_type = "ethernet-phy";
  97. };
  98. phy1: ethernet-phy@1 {
  99. interrupt-parent = <&mpic>;
  100. interrupts = <10 1>;
  101. reg = <0x1>;
  102. device_type = "ethernet-phy";
  103. };
  104. };
  105. dma@21300 {
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
  109. reg = <0x21300 0x4>;
  110. ranges = <0x0 0x21100 0x200>;
  111. cell-index = <0>;
  112. dma-channel@0 {
  113. compatible = "fsl,mpc8544-dma-channel",
  114. "fsl,eloplus-dma-channel";
  115. reg = <0x0 0x80>;
  116. cell-index = <0>;
  117. interrupt-parent = <&mpic>;
  118. interrupts = <20 2>;
  119. };
  120. dma-channel@80 {
  121. compatible = "fsl,mpc8544-dma-channel",
  122. "fsl,eloplus-dma-channel";
  123. reg = <0x80 0x80>;
  124. cell-index = <1>;
  125. interrupt-parent = <&mpic>;
  126. interrupts = <21 2>;
  127. };
  128. dma-channel@100 {
  129. compatible = "fsl,mpc8544-dma-channel",
  130. "fsl,eloplus-dma-channel";
  131. reg = <0x100 0x80>;
  132. cell-index = <2>;
  133. interrupt-parent = <&mpic>;
  134. interrupts = <22 2>;
  135. };
  136. dma-channel@180 {
  137. compatible = "fsl,mpc8544-dma-channel",
  138. "fsl,eloplus-dma-channel";
  139. reg = <0x180 0x80>;
  140. cell-index = <3>;
  141. interrupt-parent = <&mpic>;
  142. interrupts = <23 2>;
  143. };
  144. };
  145. enet0: ethernet@24000 {
  146. cell-index = <0>;
  147. device_type = "network";
  148. model = "TSEC";
  149. compatible = "gianfar";
  150. reg = <0x24000 0x1000>;
  151. local-mac-address = [ 00 00 00 00 00 00 ];
  152. interrupts = <29 2 30 2 34 2>;
  153. interrupt-parent = <&mpic>;
  154. phy-handle = <&phy0>;
  155. phy-connection-type = "rgmii-id";
  156. };
  157. enet1: ethernet@26000 {
  158. cell-index = <1>;
  159. device_type = "network";
  160. model = "TSEC";
  161. compatible = "gianfar";
  162. reg = <0x26000 0x1000>;
  163. local-mac-address = [ 00 00 00 00 00 00 ];
  164. interrupts = <31 2 32 2 33 2>;
  165. interrupt-parent = <&mpic>;
  166. phy-handle = <&phy1>;
  167. phy-connection-type = "rgmii-id";
  168. };
  169. serial0: serial@4500 {
  170. cell-index = <0>;
  171. device_type = "serial";
  172. compatible = "ns16550";
  173. reg = <0x4500 0x100>;
  174. clock-frequency = <0>;
  175. interrupts = <42 2>;
  176. interrupt-parent = <&mpic>;
  177. };
  178. serial1: serial@4600 {
  179. cell-index = <1>;
  180. device_type = "serial";
  181. compatible = "ns16550";
  182. reg = <0x4600 0x100>;
  183. clock-frequency = <0>;
  184. interrupts = <42 2>;
  185. interrupt-parent = <&mpic>;
  186. };
  187. global-utilities@e0000 { //global utilities block
  188. compatible = "fsl,mpc8548-guts";
  189. reg = <0xe0000 0x1000>;
  190. fsl,has-rstcr;
  191. };
  192. mpic: pic@40000 {
  193. clock-frequency = <0>;
  194. interrupt-controller;
  195. #address-cells = <0>;
  196. #interrupt-cells = <2>;
  197. reg = <0x40000 0x40000>;
  198. compatible = "chrp,open-pic";
  199. device_type = "open-pic";
  200. big-endian;
  201. };
  202. msi@41600 {
  203. compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
  204. reg = <0x41600 0x80>;
  205. msi-available-ranges = <0 0x100>;
  206. interrupts = <
  207. 0xe0 0
  208. 0xe1 0
  209. 0xe2 0
  210. 0xe3 0
  211. 0xe4 0
  212. 0xe5 0
  213. 0xe6 0
  214. 0xe7 0>;
  215. interrupt-parent = <&mpic>;
  216. };
  217. };
  218. pci0: pci@e0008000 {
  219. cell-index = <0>;
  220. compatible = "fsl,mpc8540-pci";
  221. device_type = "pci";
  222. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  223. interrupt-map = <
  224. /* IDSEL 0x11 J17 Slot 1 */
  225. 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
  226. 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
  227. 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
  228. 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
  229. /* IDSEL 0x12 J16 Slot 2 */
  230. 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
  231. 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
  232. 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
  233. 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
  234. interrupt-parent = <&mpic>;
  235. interrupts = <24 2>;
  236. bus-range = <0 255>;
  237. ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
  238. 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
  239. clock-frequency = <66666666>;
  240. #interrupt-cells = <1>;
  241. #size-cells = <2>;
  242. #address-cells = <3>;
  243. reg = <0xe0008000 0x1000>;
  244. };
  245. pci1: pcie@e0009000 {
  246. cell-index = <1>;
  247. compatible = "fsl,mpc8548-pcie";
  248. device_type = "pci";
  249. #interrupt-cells = <1>;
  250. #size-cells = <2>;
  251. #address-cells = <3>;
  252. reg = <0xe0009000 0x1000>;
  253. bus-range = <0 255>;
  254. ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  255. 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
  256. clock-frequency = <33333333>;
  257. interrupt-parent = <&mpic>;
  258. interrupts = <26 2>;
  259. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  260. interrupt-map = <
  261. /* IDSEL 0x0 */
  262. 0000 0x0 0x0 0x1 &mpic 0x4 0x1
  263. 0000 0x0 0x0 0x2 &mpic 0x5 0x1
  264. 0000 0x0 0x0 0x3 &mpic 0x6 0x1
  265. 0000 0x0 0x0 0x4 &mpic 0x7 0x1
  266. >;
  267. pcie@0 {
  268. reg = <0x0 0x0 0x0 0x0 0x0>;
  269. #size-cells = <2>;
  270. #address-cells = <3>;
  271. device_type = "pci";
  272. ranges = <0x2000000 0x0 0x80000000
  273. 0x2000000 0x0 0x80000000
  274. 0x0 0x20000000
  275. 0x1000000 0x0 0x0
  276. 0x1000000 0x0 0x0
  277. 0x0 0x10000>;
  278. };
  279. };
  280. pci2: pcie@e000a000 {
  281. cell-index = <2>;
  282. compatible = "fsl,mpc8548-pcie";
  283. device_type = "pci";
  284. #interrupt-cells = <1>;
  285. #size-cells = <2>;
  286. #address-cells = <3>;
  287. reg = <0xe000a000 0x1000>;
  288. bus-range = <0 255>;
  289. ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  290. 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
  291. clock-frequency = <33333333>;
  292. interrupt-parent = <&mpic>;
  293. interrupts = <25 2>;
  294. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  295. interrupt-map = <
  296. /* IDSEL 0x0 */
  297. 0000 0x0 0x0 0x1 &mpic 0x0 0x1
  298. 0000 0x0 0x0 0x2 &mpic 0x1 0x1
  299. 0000 0x0 0x0 0x3 &mpic 0x2 0x1
  300. 0000 0x0 0x0 0x4 &mpic 0x3 0x1
  301. >;
  302. pcie@0 {
  303. reg = <0x0 0x0 0x0 0x0 0x0>;
  304. #size-cells = <2>;
  305. #address-cells = <3>;
  306. device_type = "pci";
  307. ranges = <0x2000000 0x0 0xa0000000
  308. 0x2000000 0x0 0xa0000000
  309. 0x0 0x10000000
  310. 0x1000000 0x0 0x0
  311. 0x1000000 0x0 0x0
  312. 0x0 0x10000>;
  313. };
  314. };
  315. pci3: pcie@e000b000 {
  316. cell-index = <3>;
  317. compatible = "fsl,mpc8548-pcie";
  318. device_type = "pci";
  319. #interrupt-cells = <1>;
  320. #size-cells = <2>;
  321. #address-cells = <3>;
  322. reg = <0xe000b000 0x1000>;
  323. bus-range = <0 255>;
  324. ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
  325. 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
  326. clock-frequency = <33333333>;
  327. interrupt-parent = <&mpic>;
  328. interrupts = <27 2>;
  329. interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
  330. interrupt-map = <
  331. // IDSEL 0x1c USB
  332. 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
  333. 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
  334. 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
  335. 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
  336. // IDSEL 0x1d Audio
  337. 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
  338. // IDSEL 0x1e Legacy
  339. 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
  340. 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
  341. // IDSEL 0x1f IDE/SATA
  342. 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
  343. 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
  344. >;
  345. pcie@0 {
  346. reg = <0x0 0x0 0x0 0x0 0x0>;
  347. #size-cells = <2>;
  348. #address-cells = <3>;
  349. device_type = "pci";
  350. ranges = <0x2000000 0x0 0xb0000000
  351. 0x2000000 0x0 0xb0000000
  352. 0x0 0x100000
  353. 0x1000000 0x0 0x0
  354. 0x1000000 0x0 0x0
  355. 0x0 0x100000>;
  356. uli1575@0 {
  357. reg = <0x0 0x0 0x0 0x0 0x0>;
  358. #size-cells = <2>;
  359. #address-cells = <3>;
  360. ranges = <0x2000000 0x0 0xb0000000
  361. 0x2000000 0x0 0xb0000000
  362. 0x0 0x100000
  363. 0x1000000 0x0 0x0
  364. 0x1000000 0x0 0x0
  365. 0x0 0x100000>;
  366. isa@1e {
  367. device_type = "isa";
  368. #interrupt-cells = <2>;
  369. #size-cells = <1>;
  370. #address-cells = <2>;
  371. reg = <0xf000 0x0 0x0 0x0 0x0>;
  372. ranges = <0x1 0x0
  373. 0x1000000 0x0 0x0
  374. 0x1000>;
  375. interrupt-parent = <&i8259>;
  376. i8259: interrupt-controller@20 {
  377. reg = <0x1 0x20 0x2
  378. 0x1 0xa0 0x2
  379. 0x1 0x4d0 0x2>;
  380. interrupt-controller;
  381. device_type = "interrupt-controller";
  382. #address-cells = <0>;
  383. #interrupt-cells = <2>;
  384. compatible = "chrp,iic";
  385. interrupts = <9 2>;
  386. interrupt-parent = <&mpic>;
  387. };
  388. i8042@60 {
  389. #size-cells = <0>;
  390. #address-cells = <1>;
  391. reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
  392. interrupts = <1 3 12 3>;
  393. interrupt-parent = <&i8259>;
  394. keyboard@0 {
  395. reg = <0x0>;
  396. compatible = "pnpPNP,303";
  397. };
  398. mouse@1 {
  399. reg = <0x1>;
  400. compatible = "pnpPNP,f03";
  401. };
  402. };
  403. rtc@70 {
  404. compatible = "pnpPNP,b00";
  405. reg = <0x1 0x70 0x2>;
  406. };
  407. gpio@400 {
  408. reg = <0x1 0x400 0x80>;
  409. };
  410. };
  411. };
  412. };
  413. };
  414. };