dsp_spos.c 53 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <sound/driver.h>
  21. #include <asm/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/mutex.h>
  28. #include <sound/core.h>
  29. #include <sound/control.h>
  30. #include <sound/info.h>
  31. #include <sound/asoundef.h>
  32. #include <sound/cs46xx.h>
  33. #include "cs46xx_lib.h"
  34. #include "dsp_spos.h"
  35. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  36. struct dsp_scb_descriptor * fg_entry);
  37. static enum wide_opcode wide_opcodes[] = {
  38. WIDE_FOR_BEGIN_LOOP,
  39. WIDE_FOR_BEGIN_LOOP2,
  40. WIDE_COND_GOTO_ADDR,
  41. WIDE_COND_GOTO_CALL,
  42. WIDE_TBEQ_COND_GOTO_ADDR,
  43. WIDE_TBEQ_COND_CALL_ADDR,
  44. WIDE_TBEQ_NCOND_GOTO_ADDR,
  45. WIDE_TBEQ_NCOND_CALL_ADDR,
  46. WIDE_TBEQ_COND_GOTO1_ADDR,
  47. WIDE_TBEQ_COND_CALL1_ADDR,
  48. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  49. WIDE_TBEQ_NCOND_CALL1_ADDR
  50. };
  51. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  52. u32 overlay_begin_address)
  53. {
  54. unsigned int i = 0, j, nreallocated = 0;
  55. u32 hival,loval,address;
  56. u32 mop_operands,mop_type,wide_op;
  57. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  58. snd_assert( ((size % 2) == 0), return -EINVAL);
  59. while (i < size) {
  60. loval = data[i++];
  61. hival = data[i++];
  62. if (ins->code.offset > 0) {
  63. mop_operands = (hival >> 6) & 0x03fff;
  64. mop_type = mop_operands >> 10;
  65. /* check for wide type instruction */
  66. if (mop_type == 0 &&
  67. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  68. (mop_operands & WIDE_INSTR_MASK) != 0) {
  69. wide_op = loval & 0x7f;
  70. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  71. if (wide_opcodes[j] == wide_op) {
  72. /* need to reallocate instruction */
  73. address = (hival & 0x00FFF) << 5;
  74. address |= loval >> 15;
  75. snd_printdd("handle_wideop[1]: %05x:%05x addr %04x\n",hival,loval,address);
  76. if ( !(address & 0x8000) ) {
  77. address += (ins->code.offset / 2) - overlay_begin_address;
  78. } else {
  79. snd_printdd("handle_wideop[1]: ROM symbol not reallocated\n");
  80. }
  81. hival &= 0xFF000;
  82. loval &= 0x07FFF;
  83. hival |= ( (address >> 5) & 0x00FFF);
  84. loval |= ( (address << 15) & 0xF8000);
  85. address = (hival & 0x00FFF) << 5;
  86. address |= loval >> 15;
  87. snd_printdd("handle_wideop:[2] %05x:%05x addr %04x\n",hival,loval,address);
  88. nreallocated ++;
  89. } /* wide_opcodes[j] == wide_op */
  90. } /* for */
  91. } /* mod_type == 0 ... */
  92. } /* ins->code.offset > 0 */
  93. ins->code.data[ins->code.size++] = loval;
  94. ins->code.data[ins->code.size++] = hival;
  95. }
  96. snd_printdd("dsp_spos: %d instructions reallocated\n",nreallocated);
  97. return nreallocated;
  98. }
  99. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  100. {
  101. int i;
  102. for (i = 0;i < module->nsegments; ++i) {
  103. if (module->segments[i].segment_type == seg_type) {
  104. return (module->segments + i);
  105. }
  106. }
  107. return NULL;
  108. };
  109. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  110. {
  111. int index = ins->symbol_table.nsymbols,i;
  112. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  113. if (ins->symbol_table.symbols[i].deleted) {
  114. index = i;
  115. break;
  116. }
  117. }
  118. return index;
  119. }
  120. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  121. {
  122. int i;
  123. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  124. if (module->symbol_table.nsymbols > 0) {
  125. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  126. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  127. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  128. }
  129. }
  130. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  131. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  132. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  133. return -ENOMEM;
  134. }
  135. if (cs46xx_dsp_lookup_symbol(chip,
  136. module->symbol_table.symbols[i].symbol_name,
  137. module->symbol_table.symbols[i].symbol_type) == NULL) {
  138. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  139. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  140. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  141. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  142. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  143. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  144. ins->symbol_table.nsymbols++;
  145. } else {
  146. /* if (0) printk ("dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  147. module->symbol_table.symbols[i].symbol_name); */
  148. }
  149. }
  150. return 0;
  151. }
  152. static struct dsp_symbol_entry *
  153. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  154. {
  155. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  156. struct dsp_symbol_entry * symbol = NULL;
  157. int index;
  158. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  159. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  160. return NULL;
  161. }
  162. if (cs46xx_dsp_lookup_symbol(chip,
  163. symbol_name,
  164. type) != NULL) {
  165. snd_printk(KERN_ERR "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  166. return NULL;
  167. }
  168. index = find_free_symbol_index (ins);
  169. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  170. ins->symbol_table.symbols[index].address = address;
  171. ins->symbol_table.symbols[index].symbol_type = type;
  172. ins->symbol_table.symbols[index].module = NULL;
  173. ins->symbol_table.symbols[index].deleted = 0;
  174. symbol = (ins->symbol_table.symbols + index);
  175. if (index > ins->symbol_table.highest_frag_index)
  176. ins->symbol_table.highest_frag_index = index;
  177. if (index == ins->symbol_table.nsymbols)
  178. ins->symbol_table.nsymbols++; /* no frag. in list */
  179. return symbol;
  180. }
  181. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  182. {
  183. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  184. if (ins == NULL)
  185. return NULL;
  186. /* better to use vmalloc for this big table */
  187. ins->symbol_table.nsymbols = 0;
  188. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  189. DSP_MAX_SYMBOLS);
  190. ins->symbol_table.highest_frag_index = 0;
  191. if (ins->symbol_table.symbols == NULL) {
  192. cs46xx_dsp_spos_destroy(chip);
  193. goto error;
  194. }
  195. ins->code.offset = 0;
  196. ins->code.size = 0;
  197. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  198. if (ins->code.data == NULL) {
  199. cs46xx_dsp_spos_destroy(chip);
  200. goto error;
  201. }
  202. ins->nscb = 0;
  203. ins->ntask = 0;
  204. ins->nmodules = 0;
  205. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  206. if (ins->modules == NULL) {
  207. cs46xx_dsp_spos_destroy(chip);
  208. goto error;
  209. }
  210. /* default SPDIF input sample rate
  211. to 48000 khz */
  212. ins->spdif_in_sample_rate = 48000;
  213. /* maximize volume */
  214. ins->dac_volume_right = 0x8000;
  215. ins->dac_volume_left = 0x8000;
  216. ins->spdif_input_volume_right = 0x8000;
  217. ins->spdif_input_volume_left = 0x8000;
  218. /* set left and right validity bits and
  219. default channel status */
  220. ins->spdif_csuv_default =
  221. ins->spdif_csuv_stream =
  222. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  223. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  224. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  225. /* left and right validity bits */ (1 << 13) | (1 << 12);
  226. return ins;
  227. error:
  228. kfree(ins);
  229. return NULL;
  230. }
  231. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  232. {
  233. int i;
  234. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  235. snd_assert(ins != NULL, return);
  236. mutex_lock(&chip->spos_mutex);
  237. for (i = 0; i < ins->nscb; ++i) {
  238. if (ins->scbs[i].deleted) continue;
  239. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  240. }
  241. kfree(ins->code.data);
  242. vfree(ins->symbol_table.symbols);
  243. kfree(ins->modules);
  244. kfree(ins);
  245. mutex_unlock(&chip->spos_mutex);
  246. }
  247. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  248. {
  249. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  250. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  251. struct dsp_segment_desc * parameter = get_segment_desc (module,SEGTYPE_SP_PARAMETER);
  252. struct dsp_segment_desc * sample = get_segment_desc (module,SEGTYPE_SP_SAMPLE);
  253. u32 doffset, dsize;
  254. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  255. snd_printk(KERN_ERR "dsp_spos: to many modules loaded into DSP\n");
  256. return -ENOMEM;
  257. }
  258. snd_printdd("dsp_spos: loading module %s into DSP\n", module->module_name);
  259. if (ins->nmodules == 0) {
  260. snd_printdd("dsp_spos: clearing parameter area\n");
  261. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  262. }
  263. if (parameter == NULL) {
  264. snd_printdd("dsp_spos: module got no parameter segment\n");
  265. } else {
  266. if (ins->nmodules > 0) {
  267. snd_printk(KERN_WARNING "dsp_spos: WARNING current parameter data may be overwriten!\n");
  268. }
  269. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  270. dsize = parameter->size * 4;
  271. snd_printdd("dsp_spos: downloading parameter data to chip (%08x-%08x)\n",
  272. doffset,doffset + dsize);
  273. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  274. snd_printk(KERN_ERR "dsp_spos: failed to download parameter data to DSP\n");
  275. return -EINVAL;
  276. }
  277. }
  278. if (ins->nmodules == 0) {
  279. snd_printdd("dsp_spos: clearing sample area\n");
  280. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  281. }
  282. if (sample == NULL) {
  283. snd_printdd("dsp_spos: module got no sample segment\n");
  284. } else {
  285. if (ins->nmodules > 0) {
  286. snd_printk(KERN_WARNING "dsp_spos: WARNING current sample data may be overwriten\n");
  287. }
  288. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  289. dsize = sample->size * 4;
  290. snd_printdd("dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  291. doffset,doffset + dsize);
  292. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  293. snd_printk(KERN_ERR "dsp_spos: failed to sample data to DSP\n");
  294. return -EINVAL;
  295. }
  296. }
  297. if (ins->nmodules == 0) {
  298. snd_printdd("dsp_spos: clearing code area\n");
  299. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  300. }
  301. if (code == NULL) {
  302. snd_printdd("dsp_spos: module got no code segment\n");
  303. } else {
  304. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  305. snd_printk(KERN_ERR "dsp_spos: no space available in DSP\n");
  306. return -ENOMEM;
  307. }
  308. module->load_address = ins->code.offset;
  309. module->overlay_begin_address = 0x000;
  310. /* if module has a code segment it must have
  311. symbol table */
  312. snd_assert(module->symbol_table.symbols != NULL ,return -ENOMEM);
  313. if (add_symbols(chip,module)) {
  314. snd_printk(KERN_ERR "dsp_spos: failed to load symbol table\n");
  315. return -ENOMEM;
  316. }
  317. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  318. dsize = code->size * 4;
  319. snd_printdd("dsp_spos: downloading code to chip (%08x-%08x)\n",
  320. doffset,doffset + dsize);
  321. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  322. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  323. snd_printk(KERN_ERR "dsp_spos: failed to download code to DSP\n");
  324. return -EINVAL;
  325. }
  326. ins->code.offset += code->size;
  327. }
  328. /* NOTE: module segments and symbol table must be
  329. statically allocated. Case that module data is
  330. not generated by the ospparser */
  331. ins->modules[ins->nmodules] = *module;
  332. ins->nmodules++;
  333. return 0;
  334. }
  335. struct dsp_symbol_entry *
  336. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  337. {
  338. int i;
  339. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  340. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  341. if (ins->symbol_table.symbols[i].deleted)
  342. continue;
  343. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  344. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  345. return (ins->symbol_table.symbols + i);
  346. }
  347. }
  348. #if 0
  349. printk ("dsp_spos: symbol <%s> type %02x not found\n",
  350. symbol_name,symbol_type);
  351. #endif
  352. return NULL;
  353. }
  354. #ifdef CONFIG_PROC_FS
  355. static struct dsp_symbol_entry *
  356. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  357. {
  358. int i;
  359. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  360. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  361. if (ins->symbol_table.symbols[i].deleted)
  362. continue;
  363. if (ins->symbol_table.symbols[i].address == address &&
  364. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  365. return (ins->symbol_table.symbols + i);
  366. }
  367. }
  368. return NULL;
  369. }
  370. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  371. struct snd_info_buffer *buffer)
  372. {
  373. struct snd_cs46xx *chip = entry->private_data;
  374. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  375. int i;
  376. snd_iprintf(buffer, "SYMBOLS:\n");
  377. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  378. char *module_str = "system";
  379. if (ins->symbol_table.symbols[i].deleted)
  380. continue;
  381. if (ins->symbol_table.symbols[i].module != NULL) {
  382. module_str = ins->symbol_table.symbols[i].module->module_name;
  383. }
  384. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  385. ins->symbol_table.symbols[i].address,
  386. ins->symbol_table.symbols[i].symbol_type,
  387. ins->symbol_table.symbols[i].symbol_name,
  388. module_str);
  389. }
  390. }
  391. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  392. struct snd_info_buffer *buffer)
  393. {
  394. struct snd_cs46xx *chip = entry->private_data;
  395. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  396. int i,j;
  397. mutex_lock(&chip->spos_mutex);
  398. snd_iprintf(buffer, "MODULES:\n");
  399. for ( i = 0; i < ins->nmodules; ++i ) {
  400. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  401. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  402. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  403. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  404. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  405. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  406. desc->segment_type,desc->offset, desc->size);
  407. }
  408. }
  409. mutex_unlock(&chip->spos_mutex);
  410. }
  411. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  412. struct snd_info_buffer *buffer)
  413. {
  414. struct snd_cs46xx *chip = entry->private_data;
  415. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  416. int i, j, col;
  417. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  418. mutex_lock(&chip->spos_mutex);
  419. snd_iprintf(buffer, "TASK TREES:\n");
  420. for ( i = 0; i < ins->ntask; ++i) {
  421. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  422. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  423. u32 val;
  424. if (col == 4) {
  425. snd_iprintf(buffer,"\n");
  426. col = 0;
  427. }
  428. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  429. snd_iprintf(buffer,"%08x ",val);
  430. }
  431. }
  432. snd_iprintf(buffer,"\n");
  433. mutex_unlock(&chip->spos_mutex);
  434. }
  435. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  436. struct snd_info_buffer *buffer)
  437. {
  438. struct snd_cs46xx *chip = entry->private_data;
  439. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  440. int i;
  441. mutex_lock(&chip->spos_mutex);
  442. snd_iprintf(buffer, "SCB's:\n");
  443. for ( i = 0; i < ins->nscb; ++i) {
  444. if (ins->scbs[i].deleted)
  445. continue;
  446. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  447. if (ins->scbs[i].parent_scb_ptr != NULL) {
  448. snd_iprintf(buffer,"parent [%s:%04x] ",
  449. ins->scbs[i].parent_scb_ptr->scb_name,
  450. ins->scbs[i].parent_scb_ptr->address);
  451. } else snd_iprintf(buffer,"parent [none] ");
  452. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  453. ins->scbs[i].sub_list_ptr->scb_name,
  454. ins->scbs[i].sub_list_ptr->address,
  455. ins->scbs[i].next_scb_ptr->scb_name,
  456. ins->scbs[i].next_scb_ptr->address,
  457. ins->scbs[i].task_entry->symbol_name,
  458. ins->scbs[i].task_entry->address);
  459. }
  460. snd_iprintf(buffer,"\n");
  461. mutex_unlock(&chip->spos_mutex);
  462. }
  463. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  464. struct snd_info_buffer *buffer)
  465. {
  466. struct snd_cs46xx *chip = entry->private_data;
  467. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  468. unsigned int i, col = 0;
  469. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  470. struct dsp_symbol_entry * symbol;
  471. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  472. if (col == 4) {
  473. snd_iprintf(buffer,"\n");
  474. col = 0;
  475. }
  476. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  477. col = 0;
  478. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  479. }
  480. if (col == 0) {
  481. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  482. }
  483. snd_iprintf(buffer,"%08X ",readl(dst + i));
  484. }
  485. }
  486. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  487. struct snd_info_buffer *buffer)
  488. {
  489. struct snd_cs46xx *chip = entry->private_data;
  490. int i,col = 0;
  491. void __iomem *dst = chip->region.idx[2].remap_addr;
  492. snd_iprintf(buffer,"PCMREADER:\n");
  493. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  494. if (col == 4) {
  495. snd_iprintf(buffer,"\n");
  496. col = 0;
  497. }
  498. if (col == 0) {
  499. snd_iprintf(buffer, "%04X ",i);
  500. }
  501. snd_iprintf(buffer,"%08X ",readl(dst + i));
  502. }
  503. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  504. col = 0;
  505. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  506. if (col == 4) {
  507. snd_iprintf(buffer,"\n");
  508. col = 0;
  509. }
  510. if (col == 0) {
  511. snd_iprintf(buffer, "%04X ",i);
  512. }
  513. snd_iprintf(buffer,"%08X ",readl(dst + i));
  514. }
  515. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  516. col = 0;
  517. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  518. if (col == 4) {
  519. snd_iprintf(buffer,"\n");
  520. col = 0;
  521. }
  522. if (col == 0) {
  523. snd_iprintf(buffer, "%04X ",i);
  524. }
  525. snd_iprintf(buffer,"%08X ",readl(dst + i));
  526. }
  527. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  528. col = 0;
  529. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  530. if (col == 4) {
  531. snd_iprintf(buffer,"\n");
  532. col = 0;
  533. }
  534. if (col == 0) {
  535. snd_iprintf(buffer, "%04X ",i);
  536. }
  537. snd_iprintf(buffer,"%08X ",readl(dst + i));
  538. }
  539. snd_iprintf(buffer,"\n...\n");
  540. col = 0;
  541. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  542. if (col == 4) {
  543. snd_iprintf(buffer,"\n");
  544. col = 0;
  545. }
  546. if (col == 0) {
  547. snd_iprintf(buffer, "%04X ",i);
  548. }
  549. snd_iprintf(buffer,"%08X ",readl(dst + i));
  550. }
  551. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  552. col = 0;
  553. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  554. if (col == 4) {
  555. snd_iprintf(buffer,"\n");
  556. col = 0;
  557. }
  558. if (col == 0) {
  559. snd_iprintf(buffer, "%04X ",i);
  560. }
  561. snd_iprintf(buffer,"%08X ",readl(dst + i));
  562. }
  563. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  564. col = 0;
  565. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  566. if (col == 4) {
  567. snd_iprintf(buffer,"\n");
  568. col = 0;
  569. }
  570. if (col == 0) {
  571. snd_iprintf(buffer, "%04X ",i);
  572. }
  573. snd_iprintf(buffer,"%08X ",readl(dst + i));
  574. }
  575. #if 0
  576. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  577. col = 0;
  578. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  579. if (col == 4) {
  580. snd_iprintf(buffer,"\n");
  581. col = 0;
  582. }
  583. if (col == 0) {
  584. snd_iprintf(buffer, "%04X ",i);
  585. }
  586. snd_iprintf(buffer,"%08X ",readl(dst + i));
  587. }
  588. #endif
  589. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  590. col = 0;
  591. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  592. if (col == 4) {
  593. snd_iprintf(buffer,"\n");
  594. col = 0;
  595. }
  596. if (col == 0) {
  597. snd_iprintf(buffer, "%04X ",i);
  598. }
  599. snd_iprintf(buffer,"%08X ",readl(dst + i));
  600. }
  601. snd_iprintf(buffer,"\n");
  602. }
  603. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  604. {
  605. struct snd_info_entry *entry;
  606. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  607. int i;
  608. ins->snd_card = card;
  609. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  610. entry->content = SNDRV_INFO_CONTENT_TEXT;
  611. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  612. if (snd_info_register(entry) < 0) {
  613. snd_info_free_entry(entry);
  614. entry = NULL;
  615. }
  616. }
  617. ins->proc_dsp_dir = entry;
  618. if (!ins->proc_dsp_dir)
  619. return -ENOMEM;
  620. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  621. entry->content = SNDRV_INFO_CONTENT_TEXT;
  622. entry->private_data = chip;
  623. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  624. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  625. if (snd_info_register(entry) < 0) {
  626. snd_info_free_entry(entry);
  627. entry = NULL;
  628. }
  629. }
  630. ins->proc_sym_info_entry = entry;
  631. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  632. entry->content = SNDRV_INFO_CONTENT_TEXT;
  633. entry->private_data = chip;
  634. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  635. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  636. if (snd_info_register(entry) < 0) {
  637. snd_info_free_entry(entry);
  638. entry = NULL;
  639. }
  640. }
  641. ins->proc_modules_info_entry = entry;
  642. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  643. entry->content = SNDRV_INFO_CONTENT_TEXT;
  644. entry->private_data = chip;
  645. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  646. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  647. if (snd_info_register(entry) < 0) {
  648. snd_info_free_entry(entry);
  649. entry = NULL;
  650. }
  651. }
  652. ins->proc_parameter_dump_info_entry = entry;
  653. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  654. entry->content = SNDRV_INFO_CONTENT_TEXT;
  655. entry->private_data = chip;
  656. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  657. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  658. if (snd_info_register(entry) < 0) {
  659. snd_info_free_entry(entry);
  660. entry = NULL;
  661. }
  662. }
  663. ins->proc_sample_dump_info_entry = entry;
  664. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  665. entry->content = SNDRV_INFO_CONTENT_TEXT;
  666. entry->private_data = chip;
  667. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  668. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  669. if (snd_info_register(entry) < 0) {
  670. snd_info_free_entry(entry);
  671. entry = NULL;
  672. }
  673. }
  674. ins->proc_task_info_entry = entry;
  675. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  676. entry->content = SNDRV_INFO_CONTENT_TEXT;
  677. entry->private_data = chip;
  678. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  679. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  680. if (snd_info_register(entry) < 0) {
  681. snd_info_free_entry(entry);
  682. entry = NULL;
  683. }
  684. }
  685. ins->proc_scb_info_entry = entry;
  686. mutex_lock(&chip->spos_mutex);
  687. /* register/update SCB's entries on proc */
  688. for (i = 0; i < ins->nscb; ++i) {
  689. if (ins->scbs[i].deleted) continue;
  690. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  691. }
  692. mutex_unlock(&chip->spos_mutex);
  693. return 0;
  694. }
  695. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  696. {
  697. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  698. int i;
  699. snd_info_free_entry(ins->proc_sym_info_entry);
  700. ins->proc_sym_info_entry = NULL;
  701. snd_info_free_entry(ins->proc_modules_info_entry);
  702. ins->proc_modules_info_entry = NULL;
  703. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  704. ins->proc_parameter_dump_info_entry = NULL;
  705. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  706. ins->proc_sample_dump_info_entry = NULL;
  707. snd_info_free_entry(ins->proc_scb_info_entry);
  708. ins->proc_scb_info_entry = NULL;
  709. snd_info_free_entry(ins->proc_task_info_entry);
  710. ins->proc_task_info_entry = NULL;
  711. mutex_lock(&chip->spos_mutex);
  712. for (i = 0; i < ins->nscb; ++i) {
  713. if (ins->scbs[i].deleted) continue;
  714. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  715. }
  716. mutex_unlock(&chip->spos_mutex);
  717. snd_info_free_entry(ins->proc_dsp_dir);
  718. ins->proc_dsp_dir = NULL;
  719. return 0;
  720. }
  721. #endif /* CONFIG_PROC_FS */
  722. static int debug_tree;
  723. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  724. u32 dest, int size)
  725. {
  726. void __iomem *spdst = chip->region.idx[1].remap_addr +
  727. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  728. int i;
  729. for (i = 0; i < size; ++i) {
  730. if (debug_tree) printk ("addr %p, val %08x\n",spdst,task_data[i]);
  731. writel(task_data[i],spdst);
  732. spdst += sizeof(u32);
  733. }
  734. }
  735. static int debug_scb;
  736. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  737. {
  738. void __iomem *spdst = chip->region.idx[1].remap_addr +
  739. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  740. int i;
  741. for (i = 0; i < 0x10; ++i) {
  742. if (debug_scb) printk ("addr %p, val %08x\n",spdst,scb_data[i]);
  743. writel(scb_data[i],spdst);
  744. spdst += sizeof(u32);
  745. }
  746. }
  747. static int find_free_scb_index (struct dsp_spos_instance * ins)
  748. {
  749. int index = ins->nscb, i;
  750. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  751. if (ins->scbs[i].deleted) {
  752. index = i;
  753. break;
  754. }
  755. }
  756. return index;
  757. }
  758. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  759. {
  760. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  761. struct dsp_scb_descriptor * desc = NULL;
  762. int index;
  763. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  764. snd_printk(KERN_ERR "dsp_spos: got no place for other SCB\n");
  765. return NULL;
  766. }
  767. index = find_free_scb_index (ins);
  768. strcpy(ins->scbs[index].scb_name, name);
  769. ins->scbs[index].address = dest;
  770. ins->scbs[index].index = index;
  771. ins->scbs[index].proc_info = NULL;
  772. ins->scbs[index].ref_count = 1;
  773. ins->scbs[index].deleted = 0;
  774. spin_lock_init(&ins->scbs[index].lock);
  775. desc = (ins->scbs + index);
  776. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  777. if (index > ins->scb_highest_frag_index)
  778. ins->scb_highest_frag_index = index;
  779. if (index == ins->nscb)
  780. ins->nscb++;
  781. return desc;
  782. }
  783. static struct dsp_task_descriptor *
  784. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  785. {
  786. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  787. struct dsp_task_descriptor * desc = NULL;
  788. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  789. snd_printk(KERN_ERR "dsp_spos: got no place for other TASK\n");
  790. return NULL;
  791. }
  792. strcpy(ins->tasks[ins->ntask].task_name,name);
  793. ins->tasks[ins->ntask].address = dest;
  794. ins->tasks[ins->ntask].size = size;
  795. /* quick find in list */
  796. ins->tasks[ins->ntask].index = ins->ntask;
  797. desc = (ins->tasks + ins->ntask);
  798. ins->ntask++;
  799. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  800. return desc;
  801. }
  802. struct dsp_scb_descriptor *
  803. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  804. {
  805. struct dsp_scb_descriptor * desc;
  806. desc = _map_scb (chip,name,dest);
  807. if (desc) {
  808. _dsp_create_scb(chip,scb_data,dest);
  809. } else {
  810. snd_printk(KERN_ERR "dsp_spos: failed to map SCB\n");
  811. }
  812. return desc;
  813. }
  814. static struct dsp_task_descriptor *
  815. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  816. u32 dest, int size)
  817. {
  818. struct dsp_task_descriptor * desc;
  819. desc = _map_task_tree (chip,name,dest,size);
  820. if (desc) {
  821. _dsp_create_task_tree(chip,task_data,dest,size);
  822. } else {
  823. snd_printk(KERN_ERR "dsp_spos: failed to map TASK\n");
  824. }
  825. return desc;
  826. }
  827. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  828. {
  829. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  830. struct dsp_symbol_entry * fg_task_tree_header_code;
  831. struct dsp_symbol_entry * task_tree_header_code;
  832. struct dsp_symbol_entry * task_tree_thread;
  833. struct dsp_symbol_entry * null_algorithm;
  834. struct dsp_symbol_entry * magic_snoop_task;
  835. struct dsp_scb_descriptor * timing_master_scb;
  836. struct dsp_scb_descriptor * codec_out_scb;
  837. struct dsp_scb_descriptor * codec_in_scb;
  838. struct dsp_scb_descriptor * src_task_scb;
  839. struct dsp_scb_descriptor * master_mix_scb;
  840. struct dsp_scb_descriptor * rear_mix_scb;
  841. struct dsp_scb_descriptor * record_mix_scb;
  842. struct dsp_scb_descriptor * write_back_scb;
  843. struct dsp_scb_descriptor * vari_decimate_scb;
  844. struct dsp_scb_descriptor * rear_codec_out_scb;
  845. struct dsp_scb_descriptor * clfe_codec_out_scb;
  846. struct dsp_scb_descriptor * magic_snoop_scb;
  847. int fifo_addr, fifo_span, valid_slots;
  848. static struct dsp_spos_control_block sposcb = {
  849. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  850. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  851. /* 2 */ DSP_SPOS_DC,0,
  852. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  853. /* 4 */ 0,0,
  854. /* 5 */ DSP_SPOS_UU,0,
  855. /* 6 */ FG_TASK_HEADER_ADDR,0,
  856. /* 7 */ 0,0,
  857. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  858. /* 9 */ 0,
  859. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  860. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  861. /* C */ DSP_SPOS_DC_DC,
  862. /* D */ DSP_SPOS_DC_DC,
  863. /* E */ DSP_SPOS_DC_DC,
  864. /* F */ DSP_SPOS_DC_DC
  865. };
  866. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  867. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  868. if (null_algorithm == NULL) {
  869. snd_printk(KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  870. return -EIO;
  871. }
  872. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  873. if (fg_task_tree_header_code == NULL) {
  874. snd_printk(KERN_ERR "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  875. return -EIO;
  876. }
  877. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  878. if (task_tree_header_code == NULL) {
  879. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  880. return -EIO;
  881. }
  882. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  883. if (task_tree_thread == NULL) {
  884. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREETHREAD not found\n");
  885. return -EIO;
  886. }
  887. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  888. if (magic_snoop_task == NULL) {
  889. snd_printk(KERN_ERR "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  890. return -EIO;
  891. }
  892. {
  893. /* create the null SCB */
  894. static struct dsp_generic_scb null_scb = {
  895. { 0, 0, 0, 0 },
  896. { 0, 0, 0, 0, 0 },
  897. NULL_SCB_ADDR, NULL_SCB_ADDR,
  898. 0, 0, 0, 0, 0,
  899. {
  900. 0,0,
  901. 0,0,
  902. }
  903. };
  904. null_scb.entry_point = null_algorithm->address;
  905. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  906. ins->the_null_scb->task_entry = null_algorithm;
  907. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  908. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  909. ins->the_null_scb->parent_scb_ptr = NULL;
  910. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  911. }
  912. {
  913. /* setup foreground task tree */
  914. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  915. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  916. DSP_SPOS_DC_DC,
  917. DSP_SPOS_DC_DC,
  918. 0x0000,DSP_SPOS_DC,
  919. DSP_SPOS_DC, DSP_SPOS_DC,
  920. DSP_SPOS_DC_DC,
  921. DSP_SPOS_DC_DC,
  922. DSP_SPOS_DC_DC,
  923. DSP_SPOS_DC,DSP_SPOS_DC },
  924. {
  925. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  926. 0,
  927. FG_TASK_HEADER_ADDR + TCBData,
  928. },
  929. {
  930. 4,0,
  931. 1,0,
  932. 2,SPOSCB_ADDR + HFGFlags,
  933. 0,0,
  934. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  935. },
  936. {
  937. DSP_SPOS_DC,0,
  938. DSP_SPOS_DC,DSP_SPOS_DC,
  939. DSP_SPOS_DC,DSP_SPOS_DC,
  940. DSP_SPOS_DC,DSP_SPOS_DC,
  941. DSP_SPOS_DC,DSP_SPOS_DC,
  942. DSP_SPOS_DCDC,
  943. DSP_SPOS_UU,1,
  944. DSP_SPOS_DCDC,
  945. DSP_SPOS_DCDC,
  946. DSP_SPOS_DCDC,
  947. DSP_SPOS_DCDC,
  948. DSP_SPOS_DCDC,
  949. DSP_SPOS_DCDC,
  950. DSP_SPOS_DCDC,
  951. DSP_SPOS_DCDC,
  952. DSP_SPOS_DCDC,
  953. DSP_SPOS_DCDC,
  954. DSP_SPOS_DCDC,
  955. DSP_SPOS_DCDC,
  956. DSP_SPOS_DCDC,
  957. DSP_SPOS_DCDC,
  958. DSP_SPOS_DCDC,
  959. DSP_SPOS_DCDC,
  960. DSP_SPOS_DCDC,
  961. DSP_SPOS_DCDC,
  962. DSP_SPOS_DCDC,
  963. DSP_SPOS_DCDC,
  964. DSP_SPOS_DCDC,
  965. DSP_SPOS_DCDC,
  966. DSP_SPOS_DCDC,
  967. DSP_SPOS_DCDC,
  968. DSP_SPOS_DCDC,
  969. DSP_SPOS_DCDC,
  970. DSP_SPOS_DCDC,
  971. DSP_SPOS_DCDC
  972. },
  973. {
  974. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  975. 0,0
  976. }
  977. };
  978. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  979. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  980. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  981. }
  982. {
  983. /* setup foreground task tree */
  984. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  985. { DSP_SPOS_DC_DC,
  986. DSP_SPOS_DC_DC,
  987. DSP_SPOS_DC_DC,
  988. DSP_SPOS_DC, DSP_SPOS_DC,
  989. DSP_SPOS_DC, DSP_SPOS_DC,
  990. DSP_SPOS_DC_DC,
  991. DSP_SPOS_DC_DC,
  992. DSP_SPOS_DC_DC,
  993. DSP_SPOS_DC,DSP_SPOS_DC },
  994. {
  995. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  996. 0,
  997. BG_TREE_SCB_ADDR + TCBData,
  998. },
  999. {
  1000. 9999,0,
  1001. 0,1,
  1002. 0,SPOSCB_ADDR + HFGFlags,
  1003. 0,0,
  1004. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1005. },
  1006. {
  1007. DSP_SPOS_DC,0,
  1008. DSP_SPOS_DC,DSP_SPOS_DC,
  1009. DSP_SPOS_DC,DSP_SPOS_DC,
  1010. DSP_SPOS_DC,DSP_SPOS_DC,
  1011. DSP_SPOS_DC,DSP_SPOS_DC,
  1012. DSP_SPOS_DCDC,
  1013. DSP_SPOS_UU,1,
  1014. DSP_SPOS_DCDC,
  1015. DSP_SPOS_DCDC,
  1016. DSP_SPOS_DCDC,
  1017. DSP_SPOS_DCDC,
  1018. DSP_SPOS_DCDC,
  1019. DSP_SPOS_DCDC,
  1020. DSP_SPOS_DCDC,
  1021. DSP_SPOS_DCDC,
  1022. DSP_SPOS_DCDC,
  1023. DSP_SPOS_DCDC,
  1024. DSP_SPOS_DCDC,
  1025. DSP_SPOS_DCDC,
  1026. DSP_SPOS_DCDC,
  1027. DSP_SPOS_DCDC,
  1028. DSP_SPOS_DCDC,
  1029. DSP_SPOS_DCDC,
  1030. DSP_SPOS_DCDC,
  1031. DSP_SPOS_DCDC,
  1032. DSP_SPOS_DCDC,
  1033. DSP_SPOS_DCDC,
  1034. DSP_SPOS_DCDC,
  1035. DSP_SPOS_DCDC,
  1036. DSP_SPOS_DCDC,
  1037. DSP_SPOS_DCDC,
  1038. DSP_SPOS_DCDC,
  1039. DSP_SPOS_DCDC,
  1040. DSP_SPOS_DCDC,
  1041. DSP_SPOS_DCDC
  1042. },
  1043. {
  1044. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1045. 0,0
  1046. }
  1047. };
  1048. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1049. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1050. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1051. }
  1052. /* create timing master SCB */
  1053. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1054. /* create the CODEC output task */
  1055. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1056. MASTERMIX_SCB_ADDR,
  1057. CODECOUT_SCB_ADDR,timing_master_scb,
  1058. SCB_ON_PARENT_SUBLIST_SCB);
  1059. if (!codec_out_scb) goto _fail_end;
  1060. /* create the master mix SCB */
  1061. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1062. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1063. codec_out_scb,
  1064. SCB_ON_PARENT_SUBLIST_SCB);
  1065. ins->master_mix_scb = master_mix_scb;
  1066. if (!master_mix_scb) goto _fail_end;
  1067. /* create codec in */
  1068. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1069. CODEC_INPUT_BUF1,
  1070. CODECIN_SCB_ADDR,codec_out_scb,
  1071. SCB_ON_PARENT_NEXT_SCB);
  1072. if (!codec_in_scb) goto _fail_end;
  1073. ins->codec_in_scb = codec_in_scb;
  1074. /* create write back scb */
  1075. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1076. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1077. WRITEBACK_SCB_ADDR,
  1078. timing_master_scb,
  1079. SCB_ON_PARENT_NEXT_SCB);
  1080. if (!write_back_scb) goto _fail_end;
  1081. {
  1082. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1083. 0x00020000,
  1084. 0x0000ffff
  1085. };
  1086. /* dirty hack ... */
  1087. _dsp_create_task_tree (chip,(u32 *)&mix2_ostream_spb,WRITE_BACK_SPB,2);
  1088. }
  1089. /* input sample converter */
  1090. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1091. VARI_DECIMATE_BUF0,
  1092. VARI_DECIMATE_BUF1,
  1093. VARIDECIMATE_SCB_ADDR,
  1094. write_back_scb,
  1095. SCB_ON_PARENT_SUBLIST_SCB);
  1096. if (!vari_decimate_scb) goto _fail_end;
  1097. /* create the record mixer SCB */
  1098. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1099. MIX_SAMPLE_BUF2,
  1100. RECORD_MIXER_SCB_ADDR,
  1101. vari_decimate_scb,
  1102. SCB_ON_PARENT_SUBLIST_SCB);
  1103. ins->record_mixer_scb = record_mix_scb;
  1104. if (!record_mix_scb) goto _fail_end;
  1105. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1106. snd_assert (chip->nr_ac97_codecs == 1 || chip->nr_ac97_codecs == 2);
  1107. if (chip->nr_ac97_codecs == 1) {
  1108. /* output on slot 5 and 11
  1109. on primary CODEC */
  1110. fifo_addr = 0x20;
  1111. fifo_span = 0x60;
  1112. /* enable slot 5 and 11 */
  1113. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1114. } else {
  1115. /* output on slot 7 and 8
  1116. on secondary CODEC */
  1117. fifo_addr = 0x40;
  1118. fifo_span = 0x10;
  1119. /* enable slot 7 and 8 */
  1120. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1121. }
  1122. /* create CODEC tasklet for rear speakers output*/
  1123. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1124. REAR_MIXER_SCB_ADDR,
  1125. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1126. SCB_ON_PARENT_NEXT_SCB);
  1127. if (!rear_codec_out_scb) goto _fail_end;
  1128. /* create the rear PCM channel mixer SCB */
  1129. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1130. MIX_SAMPLE_BUF3,
  1131. REAR_MIXER_SCB_ADDR,
  1132. rear_codec_out_scb,
  1133. SCB_ON_PARENT_SUBLIST_SCB);
  1134. ins->rear_mix_scb = rear_mix_scb;
  1135. if (!rear_mix_scb) goto _fail_end;
  1136. if (chip->nr_ac97_codecs == 2) {
  1137. /* create CODEC tasklet for rear Center/LFE output
  1138. slot 6 and 9 on seconadry CODEC */
  1139. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1140. CLFE_MIXER_SCB_ADDR,
  1141. CLFE_CODEC_SCB_ADDR,
  1142. rear_codec_out_scb,
  1143. SCB_ON_PARENT_NEXT_SCB);
  1144. if (!clfe_codec_out_scb) goto _fail_end;
  1145. /* create the rear PCM channel mixer SCB */
  1146. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1147. MIX_SAMPLE_BUF4,
  1148. CLFE_MIXER_SCB_ADDR,
  1149. clfe_codec_out_scb,
  1150. SCB_ON_PARENT_SUBLIST_SCB);
  1151. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1152. /* enable slot 6 and 9 */
  1153. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1154. } else {
  1155. clfe_codec_out_scb = rear_codec_out_scb;
  1156. ins->center_lfe_mix_scb = rear_mix_scb;
  1157. }
  1158. /* enable slots depending on CODEC configuration */
  1159. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1160. /* the magic snooper */
  1161. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1162. OUTPUT_SNOOP_BUFFER,
  1163. codec_out_scb,
  1164. clfe_codec_out_scb,
  1165. SCB_ON_PARENT_NEXT_SCB);
  1166. if (!magic_snoop_scb) goto _fail_end;
  1167. ins->ref_snoop_scb = magic_snoop_scb;
  1168. /* SP IO access */
  1169. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1170. magic_snoop_scb,
  1171. SCB_ON_PARENT_NEXT_SCB))
  1172. goto _fail_end;
  1173. /* SPDIF input sampel rate converter */
  1174. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1175. ins->spdif_in_sample_rate,
  1176. SRC_OUTPUT_BUF1,
  1177. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1178. master_mix_scb,
  1179. SCB_ON_PARENT_SUBLIST_SCB,1);
  1180. if (!src_task_scb) goto _fail_end;
  1181. cs46xx_src_unlink(chip,src_task_scb);
  1182. /* NOTE: when we now how to detect the SPDIF input
  1183. sample rate we will use this SRC to adjust it */
  1184. ins->spdif_in_src = src_task_scb;
  1185. cs46xx_dsp_async_init(chip,timing_master_scb);
  1186. return 0;
  1187. _fail_end:
  1188. snd_printk(KERN_ERR "dsp_spos: failed to setup SCB's in DSP\n");
  1189. return -EINVAL;
  1190. }
  1191. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1192. struct dsp_scb_descriptor * fg_entry)
  1193. {
  1194. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1195. struct dsp_symbol_entry * s16_async_codec_input_task;
  1196. struct dsp_symbol_entry * spdifo_task;
  1197. struct dsp_symbol_entry * spdifi_task;
  1198. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1199. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1200. if (s16_async_codec_input_task == NULL) {
  1201. snd_printk(KERN_ERR "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1202. return -EIO;
  1203. }
  1204. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1205. if (spdifo_task == NULL) {
  1206. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFOTASK not found\n");
  1207. return -EIO;
  1208. }
  1209. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1210. if (spdifi_task == NULL) {
  1211. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFITASK not found\n");
  1212. return -EIO;
  1213. }
  1214. {
  1215. /* 0xBC0 */
  1216. struct dsp_spdifoscb spdifo_scb = {
  1217. /* 0 */ DSP_SPOS_UUUU,
  1218. {
  1219. /* 1 */ 0xb0,
  1220. /* 2 */ 0,
  1221. /* 3 */ 0,
  1222. /* 4 */ 0,
  1223. },
  1224. /* NOTE: the SPDIF output task read samples in mono
  1225. format, the AsynchFGTxSCB task writes to buffer
  1226. in stereo format
  1227. */
  1228. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1229. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1230. /* 7 */ 0,0,
  1231. /* 8 */ 0,
  1232. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1233. /* A */ spdifo_task->address,
  1234. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1235. {
  1236. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1237. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1238. },
  1239. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1240. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1241. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1242. };
  1243. /* 0xBB0 */
  1244. struct dsp_spdifiscb spdifi_scb = {
  1245. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1246. /* 1 */ 0,
  1247. /* 2 */ 0,
  1248. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1249. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1250. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1251. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1252. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1253. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1254. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1255. /* A */ spdifi_task->address,
  1256. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1257. /* NOTE: The SPDIF input task write the sample in mono
  1258. format from the HW FIFO, the AsynchFGRxSCB task reads
  1259. them in stereo
  1260. */
  1261. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1262. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1263. /* D */ 0x8048,0,
  1264. /* E */ 0x01f0,0x0001,
  1265. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1266. };
  1267. /* 0xBA0 */
  1268. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1269. /* 0 */ DSP_SPOS_UUUU,
  1270. /* 1 */ 0,
  1271. /* 2 */ 0,
  1272. /* 3 */ 1,4000,
  1273. /* 4 */ 0x0118,0x0001,
  1274. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1275. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1276. /* 7 */ DSP_SPOS_UU,0x3,
  1277. /* 8 */ DSP_SPOS_UUUU,
  1278. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1279. /* A */ s16_async_codec_input_task->address,
  1280. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1281. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1282. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1283. #ifdef UseASER1Input
  1284. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1285. Init. 0000:8042: for ASER1
  1286. 0000:8044: for ASER2 */
  1287. /* D */ 0x8042,0,
  1288. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1289. Init 1 stero:8050 ASER1
  1290. Init 0 mono:8070 ASER2
  1291. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1292. /* E */ 0x0100,0x0001,
  1293. #endif
  1294. #ifdef UseASER2Input
  1295. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1296. Init. 0000:8042: for ASER1
  1297. 0000:8044: for ASER2 */
  1298. /* D */ 0x8044,0,
  1299. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1300. Init 1 stero:8050 ASER1
  1301. Init 0 mono:8070 ASER2
  1302. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1303. /* E */ 0x0110,0x0001,
  1304. #endif
  1305. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1306. AsyncCIOutputBufModulo: The modulo size for
  1307. the output buffer of this task */
  1308. /* F */ 0, /* DSP_SPOS_UUUU */
  1309. };
  1310. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1311. snd_assert(spdifo_scb_desc, return -EIO);
  1312. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1313. snd_assert(spdifi_scb_desc, return -EIO);
  1314. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1315. snd_assert(async_codec_scb_desc, return -EIO);
  1316. async_codec_scb_desc->parent_scb_ptr = NULL;
  1317. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1318. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1319. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1320. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1321. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1322. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1323. spdifi_scb_desc->task_entry = spdifi_task;
  1324. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1325. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1326. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1327. spdifo_scb_desc->task_entry = spdifo_task;
  1328. /* this one is faked, as the parnet of SPDIFO task
  1329. is the FG task tree */
  1330. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1331. /* for proc fs */
  1332. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1333. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1334. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1335. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1336. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1337. }
  1338. return 0;
  1339. }
  1340. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1341. {
  1342. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1343. /* set SPDIF output FIFO slot */
  1344. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1345. /* SPDIF output MASTER ENABLE */
  1346. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1347. /* right and left validate bit */
  1348. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1349. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1350. /* clear fifo pointer */
  1351. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1352. /* monitor state */
  1353. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1354. }
  1355. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1356. {
  1357. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1358. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1359. cs46xx_dsp_disable_spdif_hw (chip);
  1360. udelay(50);
  1361. /* set SPDIF output FIFO slot */
  1362. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1363. /* SPDIF output MASTER ENABLE */
  1364. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1365. /* right and left validate bit */
  1366. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1367. /* monitor state */
  1368. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1369. return 0;
  1370. }
  1371. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1372. {
  1373. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1374. /* turn on amplifier */
  1375. chip->active_ctrl(chip, 1);
  1376. chip->amplifier_ctrl(chip, 1);
  1377. snd_assert (ins->asynch_rx_scb == NULL,return -EINVAL);
  1378. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1379. mutex_lock(&chip->spos_mutex);
  1380. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1381. /* time countdown enable */
  1382. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1383. /* NOTE: 80000005 value is just magic. With all values
  1384. that I've tested this one seem to give the best result.
  1385. Got no explication why. (Benny) */
  1386. /* SPDIF input MASTER ENABLE */
  1387. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1388. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1389. }
  1390. /* create and start the asynchronous receiver SCB */
  1391. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1392. ASYNCRX_SCB_ADDR,
  1393. SPDIFI_SCB_INST,
  1394. SPDIFI_IP_OUTPUT_BUFFER1,
  1395. ins->spdif_in_src,
  1396. SCB_ON_PARENT_SUBLIST_SCB);
  1397. spin_lock_irq(&chip->reg_lock);
  1398. /* reset SPDIF input sample buffer pointer */
  1399. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1400. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1401. /* reset FIFO ptr */
  1402. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1403. cs46xx_src_link(chip,ins->spdif_in_src);
  1404. /* unmute SRC volume */
  1405. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1406. spin_unlock_irq(&chip->reg_lock);
  1407. /* set SPDIF input sample rate and unmute
  1408. NOTE: only 48khz support for SPDIF input this time */
  1409. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1410. /* monitor state */
  1411. ins->spdif_status_in = 1;
  1412. mutex_unlock(&chip->spos_mutex);
  1413. return 0;
  1414. }
  1415. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1416. {
  1417. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1418. snd_assert (ins->asynch_rx_scb != NULL, return -EINVAL);
  1419. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1420. mutex_lock(&chip->spos_mutex);
  1421. /* Remove the asynchronous receiver SCB */
  1422. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1423. ins->asynch_rx_scb = NULL;
  1424. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1425. /* monitor state */
  1426. ins->spdif_status_in = 0;
  1427. mutex_unlock(&chip->spos_mutex);
  1428. /* restore amplifier */
  1429. chip->active_ctrl(chip, -1);
  1430. chip->amplifier_ctrl(chip, -1);
  1431. return 0;
  1432. }
  1433. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1434. {
  1435. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1436. snd_assert (ins->pcm_input == NULL,return -EINVAL);
  1437. snd_assert (ins->ref_snoop_scb != NULL,return -EINVAL);
  1438. mutex_lock(&chip->spos_mutex);
  1439. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1440. "PCMSerialInput_Wave");
  1441. mutex_unlock(&chip->spos_mutex);
  1442. return 0;
  1443. }
  1444. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1445. {
  1446. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1447. snd_assert (ins->pcm_input != NULL,return -EINVAL);
  1448. mutex_lock(&chip->spos_mutex);
  1449. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1450. ins->pcm_input = NULL;
  1451. mutex_unlock(&chip->spos_mutex);
  1452. return 0;
  1453. }
  1454. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1455. {
  1456. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1457. snd_assert (ins->adc_input == NULL,return -EINVAL);
  1458. snd_assert (ins->codec_in_scb != NULL,return -EINVAL);
  1459. mutex_lock(&chip->spos_mutex);
  1460. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1461. "PCMSerialInput_ADC");
  1462. mutex_unlock(&chip->spos_mutex);
  1463. return 0;
  1464. }
  1465. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1466. {
  1467. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1468. snd_assert (ins->adc_input != NULL,return -EINVAL);
  1469. mutex_lock(&chip->spos_mutex);
  1470. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1471. ins->adc_input = NULL;
  1472. mutex_unlock(&chip->spos_mutex);
  1473. return 0;
  1474. }
  1475. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1476. {
  1477. u32 temp;
  1478. int i;
  1479. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1480. a rough guess from looking at the controller spec.) */
  1481. if (address < 0x8000 || address >= 0x9000)
  1482. return -EINVAL;
  1483. /* initialize the SP_IO_WRITE SCB with the data. */
  1484. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1485. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1486. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1487. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1488. /* Poke this location to tell the task to start */
  1489. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1490. /* Verify that the task ran */
  1491. for (i=0; i<25; i++) {
  1492. udelay(125);
  1493. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1494. if (temp == 0x00000000)
  1495. break;
  1496. }
  1497. if (i == 25) {
  1498. snd_printk(KERN_ERR "dsp_spos: SPIOWriteTask not responding\n");
  1499. return -EBUSY;
  1500. }
  1501. return 0;
  1502. }
  1503. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1504. {
  1505. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1506. struct dsp_scb_descriptor * scb;
  1507. mutex_lock(&chip->spos_mutex);
  1508. /* main output */
  1509. scb = ins->master_mix_scb->sub_list_ptr;
  1510. while (scb != ins->the_null_scb) {
  1511. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1512. scb = scb->next_scb_ptr;
  1513. }
  1514. /* rear output */
  1515. scb = ins->rear_mix_scb->sub_list_ptr;
  1516. while (scb != ins->the_null_scb) {
  1517. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1518. scb = scb->next_scb_ptr;
  1519. }
  1520. ins->dac_volume_left = left;
  1521. ins->dac_volume_right = right;
  1522. mutex_unlock(&chip->spos_mutex);
  1523. return 0;
  1524. }
  1525. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1526. {
  1527. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1528. mutex_lock(&chip->spos_mutex);
  1529. if (ins->asynch_rx_scb != NULL)
  1530. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1531. left,right);
  1532. ins->spdif_input_volume_left = left;
  1533. ins->spdif_input_volume_right = right;
  1534. mutex_unlock(&chip->spos_mutex);
  1535. return 0;
  1536. }