cstate.c 4.3 KB

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  1. /*
  2. * arch/i386/kernel/acpi/cstate.c
  3. *
  4. * Copyright (C) 2005 Intel Corporation
  5. * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
  6. * - Added _PDC for SMP C-states on Intel CPUs
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/acpi.h>
  12. #include <linux/cpu.h>
  13. #include <linux/sched.h>
  14. #include <acpi/processor.h>
  15. #include <asm/acpi.h>
  16. /*
  17. * Initialize bm_flags based on the CPU cache properties
  18. * On SMP it depends on cache configuration
  19. * - When cache is not shared among all CPUs, we flush cache
  20. * before entering C3.
  21. * - When cache is shared among all CPUs, we use bm_check
  22. * mechanism as in UP case
  23. *
  24. * This routine is called only after all the CPUs are online
  25. */
  26. void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
  27. unsigned int cpu)
  28. {
  29. struct cpuinfo_x86 *c = cpu_data + cpu;
  30. flags->bm_check = 0;
  31. if (num_online_cpus() == 1)
  32. flags->bm_check = 1;
  33. else if (c->x86_vendor == X86_VENDOR_INTEL) {
  34. /*
  35. * Today all CPUs that support C3 share cache.
  36. * TBD: This needs to look at cache shared map, once
  37. * multi-core detection patch makes to the base.
  38. */
  39. flags->bm_check = 1;
  40. }
  41. }
  42. EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
  43. /* The code below handles cstate entry with monitor-mwait pair on Intel*/
  44. struct cstate_entry {
  45. struct {
  46. unsigned int eax;
  47. unsigned int ecx;
  48. } states[ACPI_PROCESSOR_MAX_POWER];
  49. };
  50. static struct cstate_entry *cpu_cstate_entry; /* per CPU ptr */
  51. static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
  52. #define MWAIT_SUBSTATE_MASK (0xf)
  53. #define MWAIT_SUBSTATE_SIZE (4)
  54. #define CPUID_MWAIT_LEAF (5)
  55. #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
  56. #define CPUID5_ECX_INTERRUPT_BREAK (0x2)
  57. #define MWAIT_ECX_INTERRUPT_BREAK (0x1)
  58. #define NATIVE_CSTATE_BEYOND_HALT (2)
  59. int acpi_processor_ffh_cstate_probe(unsigned int cpu,
  60. struct acpi_processor_cx *cx, struct acpi_power_register *reg)
  61. {
  62. struct cstate_entry *percpu_entry;
  63. struct cpuinfo_x86 *c = cpu_data + cpu;
  64. cpumask_t saved_mask;
  65. int retval;
  66. unsigned int eax, ebx, ecx, edx;
  67. unsigned int edx_part;
  68. unsigned int cstate_type; /* C-state type and not ACPI C-state type */
  69. unsigned int num_cstate_subtype;
  70. if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF )
  71. return -1;
  72. if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
  73. return -1;
  74. percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
  75. percpu_entry->states[cx->index].eax = 0;
  76. percpu_entry->states[cx->index].ecx = 0;
  77. /* Make sure we are running on right CPU */
  78. saved_mask = current->cpus_allowed;
  79. retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
  80. if (retval)
  81. return -1;
  82. cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
  83. /* Check whether this particular cx_type (in CST) is supported or not */
  84. cstate_type = (cx->address >> MWAIT_SUBSTATE_SIZE) + 1;
  85. edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
  86. num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
  87. retval = 0;
  88. if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
  89. retval = -1;
  90. goto out;
  91. }
  92. /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
  93. if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
  94. !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
  95. retval = -1;
  96. goto out;
  97. }
  98. percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
  99. /* Use the hint in CST */
  100. percpu_entry->states[cx->index].eax = cx->address;
  101. if (!mwait_supported[cstate_type]) {
  102. mwait_supported[cstate_type] = 1;
  103. printk(KERN_DEBUG "Monitor-Mwait will be used to enter C-%d "
  104. "state\n", cx->type);
  105. }
  106. out:
  107. set_cpus_allowed(current, saved_mask);
  108. return retval;
  109. }
  110. EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
  111. void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
  112. {
  113. unsigned int cpu = smp_processor_id();
  114. struct cstate_entry *percpu_entry;
  115. percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
  116. mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
  117. percpu_entry->states[cx->index].ecx);
  118. }
  119. EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
  120. static int __init ffh_cstate_init(void)
  121. {
  122. struct cpuinfo_x86 *c = &boot_cpu_data;
  123. if (c->x86_vendor != X86_VENDOR_INTEL)
  124. return -1;
  125. cpu_cstate_entry = alloc_percpu(struct cstate_entry);
  126. return 0;
  127. }
  128. static void __exit ffh_cstate_exit(void)
  129. {
  130. free_percpu(cpu_cstate_entry);
  131. cpu_cstate_entry = NULL;
  132. }
  133. arch_initcall(ffh_cstate_init);
  134. __exitcall(ffh_cstate_exit);