pm.c 4.5 KB

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  1. /*
  2. * PXA250/210 Power Management Routines
  3. *
  4. * Original code for the SA11x0:
  5. * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
  6. *
  7. * Modified for the PXA250 by Nicolas Pitre:
  8. * Copyright (c) 2002 Monta Vista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/suspend.h>
  16. #include <linux/errno.h>
  17. #include <linux/time.h>
  18. #include <asm/hardware.h>
  19. #include <asm/memory.h>
  20. #include <asm/system.h>
  21. #include <asm/arch/pm.h>
  22. #include <asm/arch/pxa-regs.h>
  23. #include <asm/arch/lubbock.h>
  24. #include <asm/mach/time.h>
  25. /*
  26. * Debug macros
  27. */
  28. #undef DEBUG
  29. #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
  30. #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
  31. #define RESTORE_GPLEVEL(n) do { \
  32. GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
  33. GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
  34. } while (0)
  35. /*
  36. * List of global PXA peripheral registers to preserve.
  37. * More ones like CP and general purpose register values are preserved
  38. * with the stack pointer in sleep.S.
  39. */
  40. enum { SLEEP_SAVE_START = 0,
  41. SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
  42. SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
  43. SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
  44. SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
  45. SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
  46. SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
  47. SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
  48. SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
  49. SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
  50. SLEEP_SAVE_PSTR,
  51. SLEEP_SAVE_ICMR,
  52. SLEEP_SAVE_CKEN,
  53. #ifdef CONFIG_PXA27x
  54. SLEEP_SAVE_MDREFR,
  55. SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
  56. SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
  57. #endif
  58. SLEEP_SAVE_CKSUM,
  59. SLEEP_SAVE_SIZE
  60. };
  61. int pxa_pm_enter(suspend_state_t state)
  62. {
  63. unsigned long sleep_save[SLEEP_SAVE_SIZE];
  64. unsigned long checksum = 0;
  65. int i;
  66. extern void pxa_cpu_pm_enter(suspend_state_t state);
  67. #ifdef CONFIG_IWMMXT
  68. /* force any iWMMXt context to ram **/
  69. if (elf_hwcap & HWCAP_IWMMXT)
  70. iwmmxt_task_disable(NULL);
  71. #endif
  72. SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
  73. SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
  74. SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
  75. SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
  76. SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
  77. SAVE(GAFR0_L); SAVE(GAFR0_U);
  78. SAVE(GAFR1_L); SAVE(GAFR1_U);
  79. SAVE(GAFR2_L); SAVE(GAFR2_U);
  80. #ifdef CONFIG_PXA27x
  81. SAVE(MDREFR);
  82. SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
  83. SAVE(GAFR3_L); SAVE(GAFR3_U);
  84. SAVE(PWER); SAVE(PCFR); SAVE(PRER);
  85. SAVE(PFER); SAVE(PKWR);
  86. #endif
  87. SAVE(ICMR);
  88. ICMR = 0;
  89. SAVE(CKEN);
  90. SAVE(PSTR);
  91. /* Note: wake up source are set up in each machine specific files */
  92. /* clear GPIO transition detect bits */
  93. GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
  94. #ifdef CONFIG_PXA27x
  95. GEDR3 = GEDR3;
  96. #endif
  97. /* Clear sleep reset status */
  98. RCSR = RCSR_SMR;
  99. /* before sleeping, calculate and save a checksum */
  100. for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
  101. checksum += sleep_save[i];
  102. sleep_save[SLEEP_SAVE_CKSUM] = checksum;
  103. /* *** go zzz *** */
  104. pxa_cpu_pm_enter(state);
  105. cpu_init();
  106. /* after sleeping, validate the checksum */
  107. checksum = 0;
  108. for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
  109. checksum += sleep_save[i];
  110. /* if invalid, display message and wait for a hardware reset */
  111. if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
  112. #ifdef CONFIG_ARCH_LUBBOCK
  113. LUB_HEXLED = 0xbadbadc5;
  114. #endif
  115. while (1)
  116. pxa_cpu_pm_enter(state);
  117. }
  118. /* ensure not to come back here if it wasn't intended */
  119. PSPR = 0;
  120. /* restore registers */
  121. RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
  122. RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
  123. RESTORE(GAFR0_L); RESTORE(GAFR0_U);
  124. RESTORE(GAFR1_L); RESTORE(GAFR1_U);
  125. RESTORE(GAFR2_L); RESTORE(GAFR2_U);
  126. RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
  127. RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
  128. RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
  129. #ifdef CONFIG_PXA27x
  130. RESTORE(MDREFR);
  131. RESTORE_GPLEVEL(3); RESTORE(GPDR3);
  132. RESTORE(GAFR3_L); RESTORE(GAFR3_U);
  133. RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
  134. RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
  135. RESTORE(PFER); RESTORE(PKWR);
  136. #endif
  137. PSSR = PSSR_RDH | PSSR_PH;
  138. RESTORE(CKEN);
  139. ICLR = 0;
  140. ICCR = 1;
  141. RESTORE(ICMR);
  142. RESTORE(PSTR);
  143. #ifdef DEBUG
  144. printk(KERN_DEBUG "*** made it back from resume\n");
  145. #endif
  146. return 0;
  147. }
  148. EXPORT_SYMBOL_GPL(pxa_pm_enter);
  149. unsigned long sleep_phys_sp(void *sp)
  150. {
  151. return virt_to_phys(sp);
  152. }