head.S 16 KB

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  1. /*
  2. * linux/arch/arm/boot/compressed/head.S
  3. *
  4. * Copyright (C) 1996-2002 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/config.h>
  11. #include <linux/linkage.h>
  12. /*
  13. * Debugging stuff
  14. *
  15. * Note that these macros must not contain any code which is not
  16. * 100% relocatable. Any attempt to do so will result in a crash.
  17. * Please select one of the following when turning on debugging.
  18. */
  19. #ifdef DEBUG
  20. #include <asm/arch/debug-macro.S>
  21. #if defined(CONFIG_DEBUG_ICEDCC)
  22. .macro loadsp, rb
  23. .endm
  24. .macro writeb, ch, rb
  25. mcr p14, 0, \ch, c0, c1, 0
  26. .endm
  27. #else
  28. .macro writeb, ch, rb
  29. senduart \ch, \rb
  30. .endm
  31. #if defined(CONFIG_FOOTBRIDGE) || \
  32. defined(CONFIG_ARCH_RPC) || \
  33. defined(CONFIG_ARCH_INTEGRATOR) || \
  34. defined(CONFIG_ARCH_PXA) || \
  35. defined(CONFIG_ARCH_IXP4XX) || \
  36. defined(CONFIG_ARCH_IXP2000) || \
  37. defined(CONFIG_ARCH_LH7A40X) || \
  38. defined(CONFIG_ARCH_OMAP) || \
  39. defined(CONFIG_MACH_MP1000)
  40. .macro loadsp, rb
  41. addruart \rb
  42. .endm
  43. #elif defined(CONFIG_ARCH_SA1100)
  44. .macro loadsp, rb
  45. mov \rb, #0x80000000 @ physical base address
  46. # if defined(CONFIG_DEBUG_LL_SER3)
  47. add \rb, \rb, #0x00050000 @ Ser3
  48. # else
  49. add \rb, \rb, #0x00010000 @ Ser1
  50. # endif
  51. .endm
  52. #elif defined(CONFIG_ARCH_IOP331)
  53. .macro loadsp, rb
  54. mov \rb, #0xff000000
  55. orr \rb, \rb, #0x00ff0000
  56. orr \rb, \rb, #0x0000f700 @ location of the UART
  57. .endm
  58. #elif defined(CONFIG_ARCH_S3C2410)
  59. .macro loadsp, rb
  60. mov \rb, #0x50000000
  61. add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
  62. .endm
  63. #else
  64. #error no serial architecture defined
  65. #endif
  66. #endif
  67. #endif
  68. .macro kputc,val
  69. mov r0, \val
  70. bl putc
  71. .endm
  72. .macro kphex,val,len
  73. mov r0, \val
  74. mov r1, #\len
  75. bl phex
  76. .endm
  77. .macro debug_reloc_start
  78. #ifdef DEBUG
  79. kputc #'\n'
  80. kphex r6, 8 /* processor id */
  81. kputc #':'
  82. kphex r7, 8 /* architecture id */
  83. kputc #':'
  84. mrc p15, 0, r0, c1, c0
  85. kphex r0, 8 /* control reg */
  86. kputc #'\n'
  87. kphex r5, 8 /* decompressed kernel start */
  88. kputc #'-'
  89. kphex r8, 8 /* decompressed kernel end */
  90. kputc #'>'
  91. kphex r4, 8 /* kernel execution address */
  92. kputc #'\n'
  93. #endif
  94. .endm
  95. .macro debug_reloc_end
  96. #ifdef DEBUG
  97. kphex r5, 8 /* end of kernel */
  98. kputc #'\n'
  99. mov r0, r4
  100. bl memdump /* dump 256 bytes at start of kernel */
  101. #endif
  102. .endm
  103. .section ".start", #alloc, #execinstr
  104. /*
  105. * sort out different calling conventions
  106. */
  107. .align
  108. start:
  109. .type start,#function
  110. .rept 8
  111. mov r0, r0
  112. .endr
  113. b 1f
  114. .word 0x016f2818 @ Magic numbers to help the loader
  115. .word start @ absolute load/run zImage address
  116. .word _edata @ zImage end address
  117. 1: mov r7, r1 @ save architecture ID
  118. mov r8, #0 @ save r0
  119. #ifndef __ARM_ARCH_2__
  120. /*
  121. * Booting from Angel - need to enter SVC mode and disable
  122. * FIQs/IRQs (numeric definitions from angel arm.h source).
  123. * We only do this if we were in user mode on entry.
  124. */
  125. mrs r2, cpsr @ get current mode
  126. tst r2, #3 @ not user?
  127. bne not_angel
  128. mov r0, #0x17 @ angel_SWIreason_EnterSVC
  129. swi 0x123456 @ angel_SWI_ARM
  130. not_angel:
  131. mrs r2, cpsr @ turn off interrupts to
  132. orr r2, r2, #0xc0 @ prevent angel from running
  133. msr cpsr_c, r2
  134. #else
  135. teqp pc, #0x0c000003 @ turn off interrupts
  136. #endif
  137. /*
  138. * Note that some cache flushing and other stuff may
  139. * be needed here - is there an Angel SWI call for this?
  140. */
  141. /*
  142. * some architecture specific code can be inserted
  143. * by the linker here, but it should preserve r7 and r8.
  144. */
  145. .text
  146. adr r0, LC0
  147. ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
  148. subs r0, r0, r1 @ calculate the delta offset
  149. @ if delta is zero, we are
  150. beq not_relocated @ running at the address we
  151. @ were linked at.
  152. /*
  153. * We're running at a different address. We need to fix
  154. * up various pointers:
  155. * r5 - zImage base address
  156. * r6 - GOT start
  157. * ip - GOT end
  158. */
  159. add r5, r5, r0
  160. add r6, r6, r0
  161. add ip, ip, r0
  162. #ifndef CONFIG_ZBOOT_ROM
  163. /*
  164. * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
  165. * we need to fix up pointers into the BSS region.
  166. * r2 - BSS start
  167. * r3 - BSS end
  168. * sp - stack pointer
  169. */
  170. add r2, r2, r0
  171. add r3, r3, r0
  172. add sp, sp, r0
  173. /*
  174. * Relocate all entries in the GOT table.
  175. */
  176. 1: ldr r1, [r6, #0] @ relocate entries in the GOT
  177. add r1, r1, r0 @ table. This fixes up the
  178. str r1, [r6], #4 @ C references.
  179. cmp r6, ip
  180. blo 1b
  181. #else
  182. /*
  183. * Relocate entries in the GOT table. We only relocate
  184. * the entries that are outside the (relocated) BSS region.
  185. */
  186. 1: ldr r1, [r6, #0] @ relocate entries in the GOT
  187. cmp r1, r2 @ entry < bss_start ||
  188. cmphs r3, r1 @ _end < entry
  189. addlo r1, r1, r0 @ table. This fixes up the
  190. str r1, [r6], #4 @ C references.
  191. cmp r6, ip
  192. blo 1b
  193. #endif
  194. not_relocated: mov r0, #0
  195. 1: str r0, [r2], #4 @ clear bss
  196. str r0, [r2], #4
  197. str r0, [r2], #4
  198. str r0, [r2], #4
  199. cmp r2, r3
  200. blo 1b
  201. /*
  202. * The C runtime environment should now be setup
  203. * sufficiently. Turn the cache on, set up some
  204. * pointers, and start decompressing.
  205. */
  206. bl cache_on
  207. mov r1, sp @ malloc space above stack
  208. add r2, sp, #0x10000 @ 64k max
  209. /*
  210. * Check to see if we will overwrite ourselves.
  211. * r4 = final kernel address
  212. * r5 = start of this image
  213. * r2 = end of malloc space (and therefore this image)
  214. * We basically want:
  215. * r4 >= r2 -> OK
  216. * r4 + image length <= r5 -> OK
  217. */
  218. cmp r4, r2
  219. bhs wont_overwrite
  220. add r0, r4, #4096*1024 @ 4MB largest kernel size
  221. cmp r0, r5
  222. bls wont_overwrite
  223. mov r5, r2 @ decompress after malloc space
  224. mov r0, r5
  225. mov r3, r7
  226. bl decompress_kernel
  227. add r0, r0, #127
  228. bic r0, r0, #127 @ align the kernel length
  229. /*
  230. * r0 = decompressed kernel length
  231. * r1-r3 = unused
  232. * r4 = kernel execution address
  233. * r5 = decompressed kernel start
  234. * r6 = processor ID
  235. * r7 = architecture ID
  236. * r8-r14 = unused
  237. */
  238. add r1, r5, r0 @ end of decompressed kernel
  239. adr r2, reloc_start
  240. ldr r3, LC1
  241. add r3, r2, r3
  242. 1: ldmia r2!, {r8 - r13} @ copy relocation code
  243. stmia r1!, {r8 - r13}
  244. ldmia r2!, {r8 - r13}
  245. stmia r1!, {r8 - r13}
  246. cmp r2, r3
  247. blo 1b
  248. bl cache_clean_flush
  249. add pc, r5, r0 @ call relocation code
  250. /*
  251. * We're not in danger of overwriting ourselves. Do this the simple way.
  252. *
  253. * r4 = kernel execution address
  254. * r7 = architecture ID
  255. */
  256. wont_overwrite: mov r0, r4
  257. mov r3, r7
  258. bl decompress_kernel
  259. b call_kernel
  260. .type LC0, #object
  261. LC0: .word LC0 @ r1
  262. .word __bss_start @ r2
  263. .word _end @ r3
  264. .word zreladdr @ r4
  265. .word _start @ r5
  266. .word _got_start @ r6
  267. .word _got_end @ ip
  268. .word user_stack+4096 @ sp
  269. LC1: .word reloc_end - reloc_start
  270. .size LC0, . - LC0
  271. #ifdef CONFIG_ARCH_RPC
  272. .globl params
  273. params: ldr r0, =params_phys
  274. mov pc, lr
  275. .ltorg
  276. .align
  277. #endif
  278. /*
  279. * Turn on the cache. We need to setup some page tables so that we
  280. * can have both the I and D caches on.
  281. *
  282. * We place the page tables 16k down from the kernel execution address,
  283. * and we hope that nothing else is using it. If we're using it, we
  284. * will go pop!
  285. *
  286. * On entry,
  287. * r4 = kernel execution address
  288. * r6 = processor ID
  289. * r7 = architecture number
  290. * r8 = run-time address of "start"
  291. * On exit,
  292. * r1, r2, r3, r8, r9, r12 corrupted
  293. * This routine must preserve:
  294. * r4, r5, r6, r7
  295. */
  296. .align 5
  297. cache_on: mov r3, #8 @ cache_on function
  298. b call_cache_fn
  299. __setup_mmu: sub r3, r4, #16384 @ Page directory size
  300. bic r3, r3, #0xff @ Align the pointer
  301. bic r3, r3, #0x3f00
  302. /*
  303. * Initialise the page tables, turning on the cacheable and bufferable
  304. * bits for the RAM area only.
  305. */
  306. mov r0, r3
  307. mov r8, r0, lsr #18
  308. mov r8, r8, lsl #18 @ start of RAM
  309. add r9, r8, #0x10000000 @ a reasonable RAM size
  310. mov r1, #0x12
  311. orr r1, r1, #3 << 10
  312. add r2, r3, #16384
  313. 1: cmp r1, r8 @ if virt > start of RAM
  314. orrhs r1, r1, #0x0c @ set cacheable, bufferable
  315. cmp r1, r9 @ if virt > end of RAM
  316. bichs r1, r1, #0x0c @ clear cacheable, bufferable
  317. str r1, [r0], #4 @ 1:1 mapping
  318. add r1, r1, #1048576
  319. teq r0, r2
  320. bne 1b
  321. /*
  322. * If ever we are running from Flash, then we surely want the cache
  323. * to be enabled also for our execution instance... We map 2MB of it
  324. * so there is no map overlap problem for up to 1 MB compressed kernel.
  325. * If the execution is in RAM then we would only be duplicating the above.
  326. */
  327. mov r1, #0x1e
  328. orr r1, r1, #3 << 10
  329. mov r2, pc, lsr #20
  330. orr r1, r1, r2, lsl #20
  331. add r0, r3, r2, lsl #2
  332. str r1, [r0], #4
  333. add r1, r1, #1048576
  334. str r1, [r0]
  335. mov pc, lr
  336. __armv4_cache_on:
  337. mov r12, lr
  338. bl __setup_mmu
  339. mov r0, #0
  340. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  341. mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
  342. mrc p15, 0, r0, c1, c0, 0 @ read control reg
  343. orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
  344. orr r0, r0, #0x0030
  345. bl __common_cache_on
  346. mov r0, #0
  347. mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
  348. mov pc, r12
  349. __arm6_cache_on:
  350. mov r12, lr
  351. bl __setup_mmu
  352. mov r0, #0
  353. mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
  354. mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
  355. mov r0, #0x30
  356. bl __common_cache_on
  357. mov r0, #0
  358. mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
  359. mov pc, r12
  360. __common_cache_on:
  361. #ifndef DEBUG
  362. orr r0, r0, #0x000d @ Write buffer, mmu
  363. #endif
  364. mov r1, #-1
  365. mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
  366. mcr p15, 0, r1, c3, c0, 0 @ load domain access control
  367. mcr p15, 0, r0, c1, c0, 0 @ load control register
  368. mov pc, lr
  369. /*
  370. * All code following this line is relocatable. It is relocated by
  371. * the above code to the end of the decompressed kernel image and
  372. * executed there. During this time, we have no stacks.
  373. *
  374. * r0 = decompressed kernel length
  375. * r1-r3 = unused
  376. * r4 = kernel execution address
  377. * r5 = decompressed kernel start
  378. * r6 = processor ID
  379. * r7 = architecture ID
  380. * r8-r14 = unused
  381. */
  382. .align 5
  383. reloc_start: add r8, r5, r0
  384. debug_reloc_start
  385. mov r1, r4
  386. 1:
  387. .rept 4
  388. ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
  389. stmia r1!, {r0, r2, r3, r9 - r13}
  390. .endr
  391. cmp r5, r8
  392. blo 1b
  393. debug_reloc_end
  394. call_kernel: bl cache_clean_flush
  395. bl cache_off
  396. mov r0, #0
  397. mov r1, r7 @ restore architecture number
  398. mov pc, r4 @ call kernel
  399. /*
  400. * Here follow the relocatable cache support functions for the
  401. * various processors. This is a generic hook for locating an
  402. * entry and jumping to an instruction at the specified offset
  403. * from the start of the block. Please note this is all position
  404. * independent code.
  405. *
  406. * r1 = corrupted
  407. * r2 = corrupted
  408. * r3 = block offset
  409. * r6 = corrupted
  410. * r12 = corrupted
  411. */
  412. call_cache_fn: adr r12, proc_types
  413. mrc p15, 0, r6, c0, c0 @ get processor ID
  414. 1: ldr r1, [r12, #0] @ get value
  415. ldr r2, [r12, #4] @ get mask
  416. eor r1, r1, r6 @ (real ^ match)
  417. tst r1, r2 @ & mask
  418. addeq pc, r12, r3 @ call cache function
  419. add r12, r12, #4*5
  420. b 1b
  421. /*
  422. * Table for cache operations. This is basically:
  423. * - CPU ID match
  424. * - CPU ID mask
  425. * - 'cache on' method instruction
  426. * - 'cache off' method instruction
  427. * - 'cache flush' method instruction
  428. *
  429. * We match an entry using: ((real_id ^ match) & mask) == 0
  430. *
  431. * Writethrough caches generally only need 'on' and 'off'
  432. * methods. Writeback caches _must_ have the flush method
  433. * defined.
  434. */
  435. .type proc_types,#object
  436. proc_types:
  437. .word 0x41560600 @ ARM6/610
  438. .word 0xffffffe0
  439. b __arm6_cache_off @ works, but slow
  440. b __arm6_cache_off
  441. mov pc, lr
  442. @ b __arm6_cache_on @ untested
  443. @ b __arm6_cache_off
  444. @ b __armv3_cache_flush
  445. .word 0x00000000 @ old ARM ID
  446. .word 0x0000f000
  447. mov pc, lr
  448. mov pc, lr
  449. mov pc, lr
  450. .word 0x41007000 @ ARM7/710
  451. .word 0xfff8fe00
  452. b __arm7_cache_off
  453. b __arm7_cache_off
  454. mov pc, lr
  455. .word 0x41807200 @ ARM720T (writethrough)
  456. .word 0xffffff00
  457. b __armv4_cache_on
  458. b __armv4_cache_off
  459. mov pc, lr
  460. .word 0x00007000 @ ARM7 IDs
  461. .word 0x0000f000
  462. mov pc, lr
  463. mov pc, lr
  464. mov pc, lr
  465. @ Everything from here on will be the new ID system.
  466. .word 0x4401a100 @ sa110 / sa1100
  467. .word 0xffffffe0
  468. b __armv4_cache_on
  469. b __armv4_cache_off
  470. b __armv4_cache_flush
  471. .word 0x6901b110 @ sa1110
  472. .word 0xfffffff0
  473. b __armv4_cache_on
  474. b __armv4_cache_off
  475. b __armv4_cache_flush
  476. @ These match on the architecture ID
  477. .word 0x00020000 @ ARMv4T
  478. .word 0x000f0000
  479. b __armv4_cache_on
  480. b __armv4_cache_off
  481. b __armv4_cache_flush
  482. .word 0x00050000 @ ARMv5TE
  483. .word 0x000f0000
  484. b __armv4_cache_on
  485. b __armv4_cache_off
  486. b __armv4_cache_flush
  487. .word 0x00060000 @ ARMv5TEJ
  488. .word 0x000f0000
  489. b __armv4_cache_on
  490. b __armv4_cache_off
  491. b __armv4_cache_flush
  492. .word 0x00070000 @ ARMv6
  493. .word 0x000f0000
  494. b __armv4_cache_on
  495. b __armv4_cache_off
  496. b __armv6_cache_flush
  497. .word 0 @ unrecognised type
  498. .word 0
  499. mov pc, lr
  500. mov pc, lr
  501. mov pc, lr
  502. .size proc_types, . - proc_types
  503. /*
  504. * Turn off the Cache and MMU. ARMv3 does not support
  505. * reading the control register, but ARMv4 does.
  506. *
  507. * On entry, r6 = processor ID
  508. * On exit, r0, r1, r2, r3, r12 corrupted
  509. * This routine must preserve: r4, r6, r7
  510. */
  511. .align 5
  512. cache_off: mov r3, #12 @ cache_off function
  513. b call_cache_fn
  514. __armv4_cache_off:
  515. mrc p15, 0, r0, c1, c0
  516. bic r0, r0, #0x000d
  517. mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
  518. mov r0, #0
  519. mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
  520. mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
  521. mov pc, lr
  522. __arm6_cache_off:
  523. mov r0, #0x00000030 @ ARM6 control reg.
  524. b __armv3_cache_off
  525. __arm7_cache_off:
  526. mov r0, #0x00000070 @ ARM7 control reg.
  527. b __armv3_cache_off
  528. __armv3_cache_off:
  529. mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
  530. mov r0, #0
  531. mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
  532. mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
  533. mov pc, lr
  534. /*
  535. * Clean and flush the cache to maintain consistency.
  536. *
  537. * On entry,
  538. * r6 = processor ID
  539. * On exit,
  540. * r1, r2, r3, r11, r12 corrupted
  541. * This routine must preserve:
  542. * r0, r4, r5, r6, r7
  543. */
  544. .align 5
  545. cache_clean_flush:
  546. mov r3, #16
  547. b call_cache_fn
  548. __armv6_cache_flush:
  549. mov r1, #0
  550. mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
  551. mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
  552. mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
  553. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  554. mov pc, lr
  555. __armv4_cache_flush:
  556. mov r2, #64*1024 @ default: 32K dcache size (*2)
  557. mov r11, #32 @ default: 32 byte line size
  558. mrc p15, 0, r3, c0, c0, 1 @ read cache type
  559. teq r3, r6 @ cache ID register present?
  560. beq no_cache_id
  561. mov r1, r3, lsr #18
  562. and r1, r1, #7
  563. mov r2, #1024
  564. mov r2, r2, lsl r1 @ base dcache size *2
  565. tst r3, #1 << 14 @ test M bit
  566. addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
  567. mov r3, r3, lsr #12
  568. and r3, r3, #3
  569. mov r11, #8
  570. mov r11, r11, lsl r3 @ cache line size in bytes
  571. no_cache_id:
  572. bic r1, pc, #63 @ align to longest cache line
  573. add r2, r1, r2
  574. 1: ldr r3, [r1], r11 @ s/w flush D cache
  575. teq r1, r2
  576. bne 1b
  577. mcr p15, 0, r1, c7, c5, 0 @ flush I cache
  578. mcr p15, 0, r1, c7, c6, 0 @ flush D cache
  579. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  580. mov pc, lr
  581. __armv3_cache_flush:
  582. mov r1, #0
  583. mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
  584. mov pc, lr
  585. /*
  586. * Various debugging routines for printing hex characters and
  587. * memory, which again must be relocatable.
  588. */
  589. #ifdef DEBUG
  590. .type phexbuf,#object
  591. phexbuf: .space 12
  592. .size phexbuf, . - phexbuf
  593. phex: adr r3, phexbuf
  594. mov r2, #0
  595. strb r2, [r3, r1]
  596. 1: subs r1, r1, #1
  597. movmi r0, r3
  598. bmi puts
  599. and r2, r0, #15
  600. mov r0, r0, lsr #4
  601. cmp r2, #10
  602. addge r2, r2, #7
  603. add r2, r2, #'0'
  604. strb r2, [r3, r1]
  605. b 1b
  606. puts: loadsp r3
  607. 1: ldrb r2, [r0], #1
  608. teq r2, #0
  609. moveq pc, lr
  610. 2: writeb r2, r3
  611. mov r1, #0x00020000
  612. 3: subs r1, r1, #1
  613. bne 3b
  614. teq r2, #'\n'
  615. moveq r2, #'\r'
  616. beq 2b
  617. teq r0, #0
  618. bne 1b
  619. mov pc, lr
  620. putc:
  621. mov r2, r0
  622. mov r0, #0
  623. loadsp r3
  624. b 2b
  625. memdump: mov r12, r0
  626. mov r10, lr
  627. mov r11, #0
  628. 2: mov r0, r11, lsl #2
  629. add r0, r0, r12
  630. mov r1, #8
  631. bl phex
  632. mov r0, #':'
  633. bl putc
  634. 1: mov r0, #' '
  635. bl putc
  636. ldr r0, [r12, r11, lsl #2]
  637. mov r1, #8
  638. bl phex
  639. and r0, r11, #7
  640. teq r0, #3
  641. moveq r0, #' '
  642. bleq putc
  643. and r0, r11, #7
  644. add r11, r11, #1
  645. teq r0, #7
  646. bne 1b
  647. mov r0, #'\n'
  648. bl putc
  649. cmp r11, #64
  650. blt 2b
  651. mov pc, r10
  652. #endif
  653. reloc_end:
  654. .align
  655. .section ".stack", "w"
  656. user_stack: .space 4096