rts5249.c 8.4 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
  21. */
  22. #include <linux/module.h>
  23. #include <linux/delay.h>
  24. #include <linux/mfd/rtsx_pci.h>
  25. #include "rtsx_pcr.h"
  26. static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  27. {
  28. u8 val;
  29. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  30. return val & 0x0F;
  31. }
  32. static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  33. {
  34. u8 driving_3v3[4][3] = {
  35. {0x11, 0x11, 0x11},
  36. {0x55, 0x55, 0x5C},
  37. {0x99, 0x99, 0x92},
  38. {0x99, 0x99, 0x92},
  39. };
  40. u8 driving_1v8[4][3] = {
  41. {0x3C, 0x3C, 0x3C},
  42. {0xB3, 0xB3, 0xB3},
  43. {0xFE, 0xFE, 0xFE},
  44. {0xC4, 0xC4, 0xC4},
  45. };
  46. u8 (*driving)[3], drive_sel;
  47. if (voltage == OUTPUT_3V3) {
  48. driving = driving_3v3;
  49. drive_sel = pcr->sd30_drive_sel_3v3;
  50. } else {
  51. driving = driving_1v8;
  52. drive_sel = pcr->sd30_drive_sel_1v8;
  53. }
  54. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  55. 0xFF, driving[drive_sel][0]);
  56. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  57. 0xFF, driving[drive_sel][1]);
  58. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  59. 0xFF, driving[drive_sel][2]);
  60. }
  61. static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
  62. {
  63. u32 reg;
  64. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  65. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  66. if (!rtsx_vendor_setting_valid(reg))
  67. return;
  68. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  69. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  70. pcr->card_drive_sel &= 0x3F;
  71. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  72. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  73. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  74. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  75. if (rtsx_reg_check_reverse_socket(reg))
  76. pcr->flags |= PCR_REVERSE_SOCKET;
  77. }
  78. static void rts5249_force_power_down(struct rtsx_pcr *pcr)
  79. {
  80. /* Set relink_time to 0 */
  81. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  82. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  83. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  84. rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  85. }
  86. static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
  87. {
  88. rtsx_pci_init_cmd(pcr);
  89. /* Configure GPIO as output */
  90. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  91. /* Switch LDO3318 source from DV33 to card_3v3 */
  92. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  93. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  94. /* LED shine disabled, set initial shine cycle period */
  95. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  96. /* Configure driving */
  97. rts5249_fill_driving(pcr, OUTPUT_3V3);
  98. if (pcr->flags & PCR_REVERSE_SOCKET)
  99. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  100. AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
  101. else
  102. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  103. AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
  104. return rtsx_pci_send_cmd(pcr, 100);
  105. }
  106. static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
  107. {
  108. int err;
  109. err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
  110. if (err < 0)
  111. return err;
  112. msleep(1);
  113. return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
  114. }
  115. static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
  116. {
  117. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  118. }
  119. static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
  120. {
  121. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  122. }
  123. static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
  124. {
  125. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  126. }
  127. static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
  128. {
  129. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  130. }
  131. static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
  132. {
  133. int err;
  134. rtsx_pci_init_cmd(pcr);
  135. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  136. SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
  137. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  138. LDO3318_PWR_MASK, 0x02);
  139. err = rtsx_pci_send_cmd(pcr, 100);
  140. if (err < 0)
  141. return err;
  142. msleep(5);
  143. rtsx_pci_init_cmd(pcr);
  144. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  145. SD_POWER_MASK, SD_VCC_POWER_ON);
  146. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  147. LDO3318_PWR_MASK, 0x06);
  148. err = rtsx_pci_send_cmd(pcr, 100);
  149. if (err < 0)
  150. return err;
  151. return 0;
  152. }
  153. static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
  154. {
  155. rtsx_pci_init_cmd(pcr);
  156. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  157. SD_POWER_MASK, SD_POWER_OFF);
  158. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  159. LDO3318_PWR_MASK, 0x00);
  160. return rtsx_pci_send_cmd(pcr, 100);
  161. }
  162. static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  163. {
  164. int err;
  165. if (voltage == OUTPUT_3V3) {
  166. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
  167. if (err < 0)
  168. return err;
  169. } else if (voltage == OUTPUT_1V8) {
  170. err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
  171. if (err < 0)
  172. return err;
  173. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
  174. if (err < 0)
  175. return err;
  176. } else {
  177. return -EINVAL;
  178. }
  179. /* set pad drive */
  180. rtsx_pci_init_cmd(pcr);
  181. rts5249_fill_driving(pcr, voltage);
  182. return rtsx_pci_send_cmd(pcr, 100);
  183. }
  184. static const struct pcr_ops rts5249_pcr_ops = {
  185. .fetch_vendor_settings = rts5249_fetch_vendor_settings,
  186. .extra_init_hw = rts5249_extra_init_hw,
  187. .optimize_phy = rts5249_optimize_phy,
  188. .turn_on_led = rts5249_turn_on_led,
  189. .turn_off_led = rts5249_turn_off_led,
  190. .enable_auto_blink = rts5249_enable_auto_blink,
  191. .disable_auto_blink = rts5249_disable_auto_blink,
  192. .card_power_on = rts5249_card_power_on,
  193. .card_power_off = rts5249_card_power_off,
  194. .switch_output_voltage = rts5249_switch_output_voltage,
  195. .force_power_down = rts5249_force_power_down,
  196. };
  197. /* SD Pull Control Enable:
  198. * SD_DAT[3:0] ==> pull up
  199. * SD_CD ==> pull up
  200. * SD_WP ==> pull up
  201. * SD_CMD ==> pull up
  202. * SD_CLK ==> pull down
  203. */
  204. static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
  205. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  206. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  207. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  208. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  209. 0,
  210. };
  211. /* SD Pull Control Disable:
  212. * SD_DAT[3:0] ==> pull down
  213. * SD_CD ==> pull up
  214. * SD_WP ==> pull down
  215. * SD_CMD ==> pull down
  216. * SD_CLK ==> pull down
  217. */
  218. static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
  219. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  220. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  221. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  222. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  223. 0,
  224. };
  225. /* MS Pull Control Enable:
  226. * MS CD ==> pull up
  227. * others ==> pull down
  228. */
  229. static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
  230. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  231. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  232. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  233. 0,
  234. };
  235. /* MS Pull Control Disable:
  236. * MS CD ==> pull up
  237. * others ==> pull down
  238. */
  239. static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
  240. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  241. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  242. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  243. 0,
  244. };
  245. void rts5249_init_params(struct rtsx_pcr *pcr)
  246. {
  247. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  248. pcr->num_slots = 2;
  249. pcr->ops = &rts5249_pcr_ops;
  250. pcr->flags = 0;
  251. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  252. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
  253. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  254. pcr->aspm_en = ASPM_L1_EN;
  255. pcr->ic_version = rts5249_get_ic_version(pcr);
  256. pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
  257. pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
  258. pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
  259. pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
  260. }