sh_dma.h 2.6 KB

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  1. /*
  2. * Header for the new SH dmaengine driver
  3. *
  4. * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef SH_DMA_H
  11. #define SH_DMA_H
  12. #include <linux/dmaengine.h>
  13. #include <linux/list.h>
  14. #include <linux/shdma-base.h>
  15. /* Used by slave DMA clients to request DMA to/from a specific peripheral */
  16. struct sh_dmae_slave {
  17. union {
  18. unsigned int slave_id; /* Set by the platform */
  19. struct shdma_slave shdma_slave;
  20. };
  21. struct device *dma_dev; /* Set by the platform */
  22. const struct sh_dmae_slave_config *config; /* Set by the driver */
  23. };
  24. struct sh_dmae_regs {
  25. u32 sar; /* SAR / source address */
  26. u32 dar; /* DAR / destination address */
  27. u32 tcr; /* TCR / transfer count */
  28. };
  29. struct sh_desc {
  30. struct sh_dmae_regs hw;
  31. struct list_head node;
  32. struct dma_async_tx_descriptor async_tx;
  33. enum dma_transfer_direction direction;
  34. dma_cookie_t cookie;
  35. size_t partial;
  36. int chunks;
  37. int mark;
  38. };
  39. struct sh_dmae_slave_config {
  40. unsigned int slave_id;
  41. dma_addr_t addr;
  42. u32 chcr;
  43. char mid_rid;
  44. };
  45. struct sh_dmae_channel {
  46. unsigned int offset;
  47. unsigned int dmars;
  48. unsigned int dmars_bit;
  49. unsigned int chclr_offset;
  50. };
  51. struct sh_dmae_pdata {
  52. const struct sh_dmae_slave_config *slave;
  53. int slave_num;
  54. const struct sh_dmae_channel *channel;
  55. int channel_num;
  56. unsigned int ts_low_shift;
  57. unsigned int ts_low_mask;
  58. unsigned int ts_high_shift;
  59. unsigned int ts_high_mask;
  60. const unsigned int *ts_shift;
  61. int ts_shift_num;
  62. u16 dmaor_init;
  63. unsigned int chcr_offset;
  64. u32 chcr_ie_bit;
  65. unsigned int dmaor_is_32bit:1;
  66. unsigned int needs_tend_set:1;
  67. unsigned int no_dmars:1;
  68. unsigned int chclr_present:1;
  69. unsigned int slave_only:1;
  70. };
  71. /* DMA register */
  72. #define SAR 0x00
  73. #define DAR 0x04
  74. #define TCR 0x08
  75. #define CHCR 0x0C
  76. #define DMAOR 0x40
  77. #define TEND 0x18 /* USB-DMAC */
  78. /* DMAOR definitions */
  79. #define DMAOR_AE 0x00000004
  80. #define DMAOR_NMIF 0x00000002
  81. #define DMAOR_DME 0x00000001
  82. /* Definitions for the SuperH DMAC */
  83. #define REQ_L 0x00000000
  84. #define REQ_E 0x00080000
  85. #define RACK_H 0x00000000
  86. #define RACK_L 0x00040000
  87. #define ACK_R 0x00000000
  88. #define ACK_W 0x00020000
  89. #define ACK_H 0x00000000
  90. #define ACK_L 0x00010000
  91. #define DM_INC 0x00004000
  92. #define DM_DEC 0x00008000
  93. #define DM_FIX 0x0000c000
  94. #define SM_INC 0x00001000
  95. #define SM_DEC 0x00002000
  96. #define SM_FIX 0x00003000
  97. #define RS_IN 0x00000200
  98. #define RS_OUT 0x00000300
  99. #define TS_BLK 0x00000040
  100. #define TM_BUR 0x00000020
  101. #define CHCR_DE 0x00000001
  102. #define CHCR_TE 0x00000002
  103. #define CHCR_IE 0x00000004
  104. #endif