intel_display.c 176 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/vgaarb.h>
  32. #include "drmP.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "i915_trace.h"
  37. #include "drm_dp_helper.h"
  38. #include "drm_crtc_helper.h"
  39. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  41. static void intel_update_watermarks(struct drm_device *dev);
  42. static void intel_increase_pllclock(struct drm_crtc *crtc);
  43. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  44. typedef struct {
  45. /* given values */
  46. int n;
  47. int m1, m2;
  48. int p1, p2;
  49. /* derived values */
  50. int dot;
  51. int vco;
  52. int m;
  53. int p;
  54. } intel_clock_t;
  55. typedef struct {
  56. int min, max;
  57. } intel_range_t;
  58. typedef struct {
  59. int dot_limit;
  60. int p2_slow, p2_fast;
  61. } intel_p2_t;
  62. #define INTEL_P2_NUM 2
  63. typedef struct intel_limit intel_limit_t;
  64. struct intel_limit {
  65. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  66. intel_p2_t p2;
  67. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  68. int, int, intel_clock_t *);
  69. };
  70. #define I8XX_DOT_MIN 25000
  71. #define I8XX_DOT_MAX 350000
  72. #define I8XX_VCO_MIN 930000
  73. #define I8XX_VCO_MAX 1400000
  74. #define I8XX_N_MIN 3
  75. #define I8XX_N_MAX 16
  76. #define I8XX_M_MIN 96
  77. #define I8XX_M_MAX 140
  78. #define I8XX_M1_MIN 18
  79. #define I8XX_M1_MAX 26
  80. #define I8XX_M2_MIN 6
  81. #define I8XX_M2_MAX 16
  82. #define I8XX_P_MIN 4
  83. #define I8XX_P_MAX 128
  84. #define I8XX_P1_MIN 2
  85. #define I8XX_P1_MAX 33
  86. #define I8XX_P1_LVDS_MIN 1
  87. #define I8XX_P1_LVDS_MAX 6
  88. #define I8XX_P2_SLOW 4
  89. #define I8XX_P2_FAST 2
  90. #define I8XX_P2_LVDS_SLOW 14
  91. #define I8XX_P2_LVDS_FAST 7
  92. #define I8XX_P2_SLOW_LIMIT 165000
  93. #define I9XX_DOT_MIN 20000
  94. #define I9XX_DOT_MAX 400000
  95. #define I9XX_VCO_MIN 1400000
  96. #define I9XX_VCO_MAX 2800000
  97. #define PINEVIEW_VCO_MIN 1700000
  98. #define PINEVIEW_VCO_MAX 3500000
  99. #define I9XX_N_MIN 1
  100. #define I9XX_N_MAX 6
  101. /* Pineview's Ncounter is a ring counter */
  102. #define PINEVIEW_N_MIN 3
  103. #define PINEVIEW_N_MAX 6
  104. #define I9XX_M_MIN 70
  105. #define I9XX_M_MAX 120
  106. #define PINEVIEW_M_MIN 2
  107. #define PINEVIEW_M_MAX 256
  108. #define I9XX_M1_MIN 10
  109. #define I9XX_M1_MAX 22
  110. #define I9XX_M2_MIN 5
  111. #define I9XX_M2_MAX 9
  112. /* Pineview M1 is reserved, and must be 0 */
  113. #define PINEVIEW_M1_MIN 0
  114. #define PINEVIEW_M1_MAX 0
  115. #define PINEVIEW_M2_MIN 0
  116. #define PINEVIEW_M2_MAX 254
  117. #define I9XX_P_SDVO_DAC_MIN 5
  118. #define I9XX_P_SDVO_DAC_MAX 80
  119. #define I9XX_P_LVDS_MIN 7
  120. #define I9XX_P_LVDS_MAX 98
  121. #define PINEVIEW_P_LVDS_MIN 7
  122. #define PINEVIEW_P_LVDS_MAX 112
  123. #define I9XX_P1_MIN 1
  124. #define I9XX_P1_MAX 8
  125. #define I9XX_P2_SDVO_DAC_SLOW 10
  126. #define I9XX_P2_SDVO_DAC_FAST 5
  127. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  128. #define I9XX_P2_LVDS_SLOW 14
  129. #define I9XX_P2_LVDS_FAST 7
  130. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  131. /*The parameter is for SDVO on G4x platform*/
  132. #define G4X_DOT_SDVO_MIN 25000
  133. #define G4X_DOT_SDVO_MAX 270000
  134. #define G4X_VCO_MIN 1750000
  135. #define G4X_VCO_MAX 3500000
  136. #define G4X_N_SDVO_MIN 1
  137. #define G4X_N_SDVO_MAX 4
  138. #define G4X_M_SDVO_MIN 104
  139. #define G4X_M_SDVO_MAX 138
  140. #define G4X_M1_SDVO_MIN 17
  141. #define G4X_M1_SDVO_MAX 23
  142. #define G4X_M2_SDVO_MIN 5
  143. #define G4X_M2_SDVO_MAX 11
  144. #define G4X_P_SDVO_MIN 10
  145. #define G4X_P_SDVO_MAX 30
  146. #define G4X_P1_SDVO_MIN 1
  147. #define G4X_P1_SDVO_MAX 3
  148. #define G4X_P2_SDVO_SLOW 10
  149. #define G4X_P2_SDVO_FAST 10
  150. #define G4X_P2_SDVO_LIMIT 270000
  151. /*The parameter is for HDMI_DAC on G4x platform*/
  152. #define G4X_DOT_HDMI_DAC_MIN 22000
  153. #define G4X_DOT_HDMI_DAC_MAX 400000
  154. #define G4X_N_HDMI_DAC_MIN 1
  155. #define G4X_N_HDMI_DAC_MAX 4
  156. #define G4X_M_HDMI_DAC_MIN 104
  157. #define G4X_M_HDMI_DAC_MAX 138
  158. #define G4X_M1_HDMI_DAC_MIN 16
  159. #define G4X_M1_HDMI_DAC_MAX 23
  160. #define G4X_M2_HDMI_DAC_MIN 5
  161. #define G4X_M2_HDMI_DAC_MAX 11
  162. #define G4X_P_HDMI_DAC_MIN 5
  163. #define G4X_P_HDMI_DAC_MAX 80
  164. #define G4X_P1_HDMI_DAC_MIN 1
  165. #define G4X_P1_HDMI_DAC_MAX 8
  166. #define G4X_P2_HDMI_DAC_SLOW 10
  167. #define G4X_P2_HDMI_DAC_FAST 5
  168. #define G4X_P2_HDMI_DAC_LIMIT 165000
  169. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  170. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  171. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  172. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  173. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  174. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  175. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  176. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  177. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  178. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  179. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  180. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  181. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  182. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  183. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  184. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  185. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  186. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  187. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  188. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  189. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  190. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  191. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  192. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  193. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  194. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  195. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  196. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  197. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  198. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  199. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  200. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  201. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  202. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  203. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  204. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  205. /*The parameter is for DISPLAY PORT on G4x platform*/
  206. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  207. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  208. #define G4X_N_DISPLAY_PORT_MIN 1
  209. #define G4X_N_DISPLAY_PORT_MAX 2
  210. #define G4X_M_DISPLAY_PORT_MIN 97
  211. #define G4X_M_DISPLAY_PORT_MAX 108
  212. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  213. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  214. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  215. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  216. #define G4X_P_DISPLAY_PORT_MIN 10
  217. #define G4X_P_DISPLAY_PORT_MAX 20
  218. #define G4X_P1_DISPLAY_PORT_MIN 1
  219. #define G4X_P1_DISPLAY_PORT_MAX 2
  220. #define G4X_P2_DISPLAY_PORT_SLOW 10
  221. #define G4X_P2_DISPLAY_PORT_FAST 10
  222. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  223. /* Ironlake / Sandybridge */
  224. /* as we calculate clock using (register_value + 2) for
  225. N/M1/M2, so here the range value for them is (actual_value-2).
  226. */
  227. #define IRONLAKE_DOT_MIN 25000
  228. #define IRONLAKE_DOT_MAX 350000
  229. #define IRONLAKE_VCO_MIN 1760000
  230. #define IRONLAKE_VCO_MAX 3510000
  231. #define IRONLAKE_M1_MIN 12
  232. #define IRONLAKE_M1_MAX 22
  233. #define IRONLAKE_M2_MIN 5
  234. #define IRONLAKE_M2_MAX 9
  235. #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
  236. /* We have parameter ranges for different type of outputs. */
  237. /* DAC & HDMI Refclk 120Mhz */
  238. #define IRONLAKE_DAC_N_MIN 1
  239. #define IRONLAKE_DAC_N_MAX 5
  240. #define IRONLAKE_DAC_M_MIN 79
  241. #define IRONLAKE_DAC_M_MAX 127
  242. #define IRONLAKE_DAC_P_MIN 5
  243. #define IRONLAKE_DAC_P_MAX 80
  244. #define IRONLAKE_DAC_P1_MIN 1
  245. #define IRONLAKE_DAC_P1_MAX 8
  246. #define IRONLAKE_DAC_P2_SLOW 10
  247. #define IRONLAKE_DAC_P2_FAST 5
  248. /* LVDS single-channel 120Mhz refclk */
  249. #define IRONLAKE_LVDS_S_N_MIN 1
  250. #define IRONLAKE_LVDS_S_N_MAX 3
  251. #define IRONLAKE_LVDS_S_M_MIN 79
  252. #define IRONLAKE_LVDS_S_M_MAX 118
  253. #define IRONLAKE_LVDS_S_P_MIN 28
  254. #define IRONLAKE_LVDS_S_P_MAX 112
  255. #define IRONLAKE_LVDS_S_P1_MIN 2
  256. #define IRONLAKE_LVDS_S_P1_MAX 8
  257. #define IRONLAKE_LVDS_S_P2_SLOW 14
  258. #define IRONLAKE_LVDS_S_P2_FAST 14
  259. /* LVDS dual-channel 120Mhz refclk */
  260. #define IRONLAKE_LVDS_D_N_MIN 1
  261. #define IRONLAKE_LVDS_D_N_MAX 3
  262. #define IRONLAKE_LVDS_D_M_MIN 79
  263. #define IRONLAKE_LVDS_D_M_MAX 127
  264. #define IRONLAKE_LVDS_D_P_MIN 14
  265. #define IRONLAKE_LVDS_D_P_MAX 56
  266. #define IRONLAKE_LVDS_D_P1_MIN 2
  267. #define IRONLAKE_LVDS_D_P1_MAX 8
  268. #define IRONLAKE_LVDS_D_P2_SLOW 7
  269. #define IRONLAKE_LVDS_D_P2_FAST 7
  270. /* LVDS single-channel 100Mhz refclk */
  271. #define IRONLAKE_LVDS_S_SSC_N_MIN 1
  272. #define IRONLAKE_LVDS_S_SSC_N_MAX 2
  273. #define IRONLAKE_LVDS_S_SSC_M_MIN 79
  274. #define IRONLAKE_LVDS_S_SSC_M_MAX 126
  275. #define IRONLAKE_LVDS_S_SSC_P_MIN 28
  276. #define IRONLAKE_LVDS_S_SSC_P_MAX 112
  277. #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
  278. #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
  279. #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
  280. #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
  281. /* LVDS dual-channel 100Mhz refclk */
  282. #define IRONLAKE_LVDS_D_SSC_N_MIN 1
  283. #define IRONLAKE_LVDS_D_SSC_N_MAX 3
  284. #define IRONLAKE_LVDS_D_SSC_M_MIN 79
  285. #define IRONLAKE_LVDS_D_SSC_M_MAX 126
  286. #define IRONLAKE_LVDS_D_SSC_P_MIN 14
  287. #define IRONLAKE_LVDS_D_SSC_P_MAX 42
  288. #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
  289. #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
  290. #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
  291. #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
  292. /* DisplayPort */
  293. #define IRONLAKE_DP_N_MIN 1
  294. #define IRONLAKE_DP_N_MAX 2
  295. #define IRONLAKE_DP_M_MIN 81
  296. #define IRONLAKE_DP_M_MAX 90
  297. #define IRONLAKE_DP_P_MIN 10
  298. #define IRONLAKE_DP_P_MAX 20
  299. #define IRONLAKE_DP_P2_FAST 10
  300. #define IRONLAKE_DP_P2_SLOW 10
  301. #define IRONLAKE_DP_P2_LIMIT 0
  302. #define IRONLAKE_DP_P1_MIN 1
  303. #define IRONLAKE_DP_P1_MAX 2
  304. /* FDI */
  305. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  306. static bool
  307. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  308. int target, int refclk, intel_clock_t *best_clock);
  309. static bool
  310. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  311. int target, int refclk, intel_clock_t *best_clock);
  312. static bool
  313. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  314. int target, int refclk, intel_clock_t *best_clock);
  315. static bool
  316. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  317. int target, int refclk, intel_clock_t *best_clock);
  318. static inline u32 /* units of 100MHz */
  319. intel_fdi_link_freq(struct drm_device *dev)
  320. {
  321. struct drm_i915_private *dev_priv = dev->dev_private;
  322. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  323. }
  324. static const intel_limit_t intel_limits_i8xx_dvo = {
  325. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  326. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  327. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  328. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  329. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  330. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  331. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  332. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  333. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  334. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  335. .find_pll = intel_find_best_PLL,
  336. };
  337. static const intel_limit_t intel_limits_i8xx_lvds = {
  338. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  339. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  340. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  341. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  342. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  343. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  344. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  345. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  346. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  347. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  348. .find_pll = intel_find_best_PLL,
  349. };
  350. static const intel_limit_t intel_limits_i9xx_sdvo = {
  351. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  352. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  353. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  354. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  355. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  356. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  357. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  358. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  359. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  360. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  361. .find_pll = intel_find_best_PLL,
  362. };
  363. static const intel_limit_t intel_limits_i9xx_lvds = {
  364. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  365. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  366. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  367. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  368. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  369. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  370. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  371. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  372. /* The single-channel range is 25-112Mhz, and dual-channel
  373. * is 80-224Mhz. Prefer single channel as much as possible.
  374. */
  375. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  376. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  377. .find_pll = intel_find_best_PLL,
  378. };
  379. /* below parameter and function is for G4X Chipset Family*/
  380. static const intel_limit_t intel_limits_g4x_sdvo = {
  381. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  382. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  383. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  384. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  385. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  386. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  387. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  388. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  389. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  390. .p2_slow = G4X_P2_SDVO_SLOW,
  391. .p2_fast = G4X_P2_SDVO_FAST
  392. },
  393. .find_pll = intel_g4x_find_best_PLL,
  394. };
  395. static const intel_limit_t intel_limits_g4x_hdmi = {
  396. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  397. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  398. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  399. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  400. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  401. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  402. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  403. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  404. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  405. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  406. .p2_fast = G4X_P2_HDMI_DAC_FAST
  407. },
  408. .find_pll = intel_g4x_find_best_PLL,
  409. };
  410. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  411. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  412. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  413. .vco = { .min = G4X_VCO_MIN,
  414. .max = G4X_VCO_MAX },
  415. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  416. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  417. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  418. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  419. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  420. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  421. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  422. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  423. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  424. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  425. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  426. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  427. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  428. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  429. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  430. },
  431. .find_pll = intel_g4x_find_best_PLL,
  432. };
  433. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  434. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  435. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  436. .vco = { .min = G4X_VCO_MIN,
  437. .max = G4X_VCO_MAX },
  438. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  439. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  440. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  441. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  442. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  443. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  444. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  445. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  446. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  447. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  448. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  449. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  450. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  451. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  452. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  453. },
  454. .find_pll = intel_g4x_find_best_PLL,
  455. };
  456. static const intel_limit_t intel_limits_g4x_display_port = {
  457. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  458. .max = G4X_DOT_DISPLAY_PORT_MAX },
  459. .vco = { .min = G4X_VCO_MIN,
  460. .max = G4X_VCO_MAX},
  461. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  462. .max = G4X_N_DISPLAY_PORT_MAX },
  463. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  464. .max = G4X_M_DISPLAY_PORT_MAX },
  465. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  466. .max = G4X_M1_DISPLAY_PORT_MAX },
  467. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  468. .max = G4X_M2_DISPLAY_PORT_MAX },
  469. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  470. .max = G4X_P_DISPLAY_PORT_MAX },
  471. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  472. .max = G4X_P1_DISPLAY_PORT_MAX},
  473. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  474. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  475. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  476. .find_pll = intel_find_pll_g4x_dp,
  477. };
  478. static const intel_limit_t intel_limits_pineview_sdvo = {
  479. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  480. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  481. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  482. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  483. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  484. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  485. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  486. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  487. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  488. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  489. .find_pll = intel_find_best_PLL,
  490. };
  491. static const intel_limit_t intel_limits_pineview_lvds = {
  492. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  493. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  494. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  495. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  496. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  497. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  498. .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
  499. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  500. /* Pineview only supports single-channel mode. */
  501. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  502. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  503. .find_pll = intel_find_best_PLL,
  504. };
  505. static const intel_limit_t intel_limits_ironlake_dac = {
  506. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  507. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  508. .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
  509. .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
  510. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  511. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  512. .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
  513. .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
  514. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  515. .p2_slow = IRONLAKE_DAC_P2_SLOW,
  516. .p2_fast = IRONLAKE_DAC_P2_FAST },
  517. .find_pll = intel_g4x_find_best_PLL,
  518. };
  519. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  520. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  521. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  522. .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
  523. .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
  524. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  525. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  526. .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
  527. .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
  528. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  529. .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
  530. .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
  531. .find_pll = intel_g4x_find_best_PLL,
  532. };
  533. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  534. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  535. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  536. .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
  537. .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
  538. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  539. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  540. .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
  541. .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
  542. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  543. .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
  544. .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
  545. .find_pll = intel_g4x_find_best_PLL,
  546. };
  547. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  548. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  549. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  550. .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
  551. .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
  552. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  553. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  554. .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
  555. .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
  556. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  557. .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
  558. .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
  559. .find_pll = intel_g4x_find_best_PLL,
  560. };
  561. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  562. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  563. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  564. .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
  565. .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
  566. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  567. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  568. .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
  569. .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
  570. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  571. .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
  572. .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
  573. .find_pll = intel_g4x_find_best_PLL,
  574. };
  575. static const intel_limit_t intel_limits_ironlake_display_port = {
  576. .dot = { .min = IRONLAKE_DOT_MIN,
  577. .max = IRONLAKE_DOT_MAX },
  578. .vco = { .min = IRONLAKE_VCO_MIN,
  579. .max = IRONLAKE_VCO_MAX},
  580. .n = { .min = IRONLAKE_DP_N_MIN,
  581. .max = IRONLAKE_DP_N_MAX },
  582. .m = { .min = IRONLAKE_DP_M_MIN,
  583. .max = IRONLAKE_DP_M_MAX },
  584. .m1 = { .min = IRONLAKE_M1_MIN,
  585. .max = IRONLAKE_M1_MAX },
  586. .m2 = { .min = IRONLAKE_M2_MIN,
  587. .max = IRONLAKE_M2_MAX },
  588. .p = { .min = IRONLAKE_DP_P_MIN,
  589. .max = IRONLAKE_DP_P_MAX },
  590. .p1 = { .min = IRONLAKE_DP_P1_MIN,
  591. .max = IRONLAKE_DP_P1_MAX},
  592. .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
  593. .p2_slow = IRONLAKE_DP_P2_SLOW,
  594. .p2_fast = IRONLAKE_DP_P2_FAST },
  595. .find_pll = intel_find_pll_ironlake_dp,
  596. };
  597. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
  598. {
  599. struct drm_device *dev = crtc->dev;
  600. struct drm_i915_private *dev_priv = dev->dev_private;
  601. const intel_limit_t *limit;
  602. int refclk = 120;
  603. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  604. if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
  605. refclk = 100;
  606. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  607. LVDS_CLKB_POWER_UP) {
  608. /* LVDS dual channel */
  609. if (refclk == 100)
  610. limit = &intel_limits_ironlake_dual_lvds_100m;
  611. else
  612. limit = &intel_limits_ironlake_dual_lvds;
  613. } else {
  614. if (refclk == 100)
  615. limit = &intel_limits_ironlake_single_lvds_100m;
  616. else
  617. limit = &intel_limits_ironlake_single_lvds;
  618. }
  619. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  620. HAS_eDP)
  621. limit = &intel_limits_ironlake_display_port;
  622. else
  623. limit = &intel_limits_ironlake_dac;
  624. return limit;
  625. }
  626. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  627. {
  628. struct drm_device *dev = crtc->dev;
  629. struct drm_i915_private *dev_priv = dev->dev_private;
  630. const intel_limit_t *limit;
  631. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  632. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  633. LVDS_CLKB_POWER_UP)
  634. /* LVDS with dual channel */
  635. limit = &intel_limits_g4x_dual_channel_lvds;
  636. else
  637. /* LVDS with dual channel */
  638. limit = &intel_limits_g4x_single_channel_lvds;
  639. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  640. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  641. limit = &intel_limits_g4x_hdmi;
  642. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  643. limit = &intel_limits_g4x_sdvo;
  644. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  645. limit = &intel_limits_g4x_display_port;
  646. } else /* The option is for other outputs */
  647. limit = &intel_limits_i9xx_sdvo;
  648. return limit;
  649. }
  650. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  651. {
  652. struct drm_device *dev = crtc->dev;
  653. const intel_limit_t *limit;
  654. if (HAS_PCH_SPLIT(dev))
  655. limit = intel_ironlake_limit(crtc);
  656. else if (IS_G4X(dev)) {
  657. limit = intel_g4x_limit(crtc);
  658. } else if (IS_PINEVIEW(dev)) {
  659. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  660. limit = &intel_limits_pineview_lvds;
  661. else
  662. limit = &intel_limits_pineview_sdvo;
  663. } else if (!IS_GEN2(dev)) {
  664. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  665. limit = &intel_limits_i9xx_lvds;
  666. else
  667. limit = &intel_limits_i9xx_sdvo;
  668. } else {
  669. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  670. limit = &intel_limits_i8xx_lvds;
  671. else
  672. limit = &intel_limits_i8xx_dvo;
  673. }
  674. return limit;
  675. }
  676. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  677. static void pineview_clock(int refclk, intel_clock_t *clock)
  678. {
  679. clock->m = clock->m2 + 2;
  680. clock->p = clock->p1 * clock->p2;
  681. clock->vco = refclk * clock->m / clock->n;
  682. clock->dot = clock->vco / clock->p;
  683. }
  684. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  685. {
  686. if (IS_PINEVIEW(dev)) {
  687. pineview_clock(refclk, clock);
  688. return;
  689. }
  690. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  691. clock->p = clock->p1 * clock->p2;
  692. clock->vco = refclk * clock->m / (clock->n + 2);
  693. clock->dot = clock->vco / clock->p;
  694. }
  695. /**
  696. * Returns whether any output on the specified pipe is of the specified type
  697. */
  698. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  699. {
  700. struct drm_device *dev = crtc->dev;
  701. struct drm_mode_config *mode_config = &dev->mode_config;
  702. struct intel_encoder *encoder;
  703. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  704. if (encoder->base.crtc == crtc && encoder->type == type)
  705. return true;
  706. return false;
  707. }
  708. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  709. /**
  710. * Returns whether the given set of divisors are valid for a given refclk with
  711. * the given connectors.
  712. */
  713. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  714. {
  715. const intel_limit_t *limit = intel_limit (crtc);
  716. struct drm_device *dev = crtc->dev;
  717. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  718. INTELPllInvalid ("p1 out of range\n");
  719. if (clock->p < limit->p.min || limit->p.max < clock->p)
  720. INTELPllInvalid ("p out of range\n");
  721. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  722. INTELPllInvalid ("m2 out of range\n");
  723. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  724. INTELPllInvalid ("m1 out of range\n");
  725. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  726. INTELPllInvalid ("m1 <= m2\n");
  727. if (clock->m < limit->m.min || limit->m.max < clock->m)
  728. INTELPllInvalid ("m out of range\n");
  729. if (clock->n < limit->n.min || limit->n.max < clock->n)
  730. INTELPllInvalid ("n out of range\n");
  731. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  732. INTELPllInvalid ("vco out of range\n");
  733. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  734. * connector, etc., rather than just a single range.
  735. */
  736. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  737. INTELPllInvalid ("dot out of range\n");
  738. return true;
  739. }
  740. static bool
  741. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  742. int target, int refclk, intel_clock_t *best_clock)
  743. {
  744. struct drm_device *dev = crtc->dev;
  745. struct drm_i915_private *dev_priv = dev->dev_private;
  746. intel_clock_t clock;
  747. int err = target;
  748. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  749. (I915_READ(LVDS)) != 0) {
  750. /*
  751. * For LVDS, if the panel is on, just rely on its current
  752. * settings for dual-channel. We haven't figured out how to
  753. * reliably set up different single/dual channel state, if we
  754. * even can.
  755. */
  756. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  757. LVDS_CLKB_POWER_UP)
  758. clock.p2 = limit->p2.p2_fast;
  759. else
  760. clock.p2 = limit->p2.p2_slow;
  761. } else {
  762. if (target < limit->p2.dot_limit)
  763. clock.p2 = limit->p2.p2_slow;
  764. else
  765. clock.p2 = limit->p2.p2_fast;
  766. }
  767. memset (best_clock, 0, sizeof (*best_clock));
  768. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  769. clock.m1++) {
  770. for (clock.m2 = limit->m2.min;
  771. clock.m2 <= limit->m2.max; clock.m2++) {
  772. /* m1 is always 0 in Pineview */
  773. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  774. break;
  775. for (clock.n = limit->n.min;
  776. clock.n <= limit->n.max; clock.n++) {
  777. for (clock.p1 = limit->p1.min;
  778. clock.p1 <= limit->p1.max; clock.p1++) {
  779. int this_err;
  780. intel_clock(dev, refclk, &clock);
  781. if (!intel_PLL_is_valid(crtc, &clock))
  782. continue;
  783. this_err = abs(clock.dot - target);
  784. if (this_err < err) {
  785. *best_clock = clock;
  786. err = this_err;
  787. }
  788. }
  789. }
  790. }
  791. }
  792. return (err != target);
  793. }
  794. static bool
  795. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  796. int target, int refclk, intel_clock_t *best_clock)
  797. {
  798. struct drm_device *dev = crtc->dev;
  799. struct drm_i915_private *dev_priv = dev->dev_private;
  800. intel_clock_t clock;
  801. int max_n;
  802. bool found;
  803. /* approximately equals target * 0.00585 */
  804. int err_most = (target >> 8) + (target >> 9);
  805. found = false;
  806. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  807. int lvds_reg;
  808. if (HAS_PCH_SPLIT(dev))
  809. lvds_reg = PCH_LVDS;
  810. else
  811. lvds_reg = LVDS;
  812. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  813. LVDS_CLKB_POWER_UP)
  814. clock.p2 = limit->p2.p2_fast;
  815. else
  816. clock.p2 = limit->p2.p2_slow;
  817. } else {
  818. if (target < limit->p2.dot_limit)
  819. clock.p2 = limit->p2.p2_slow;
  820. else
  821. clock.p2 = limit->p2.p2_fast;
  822. }
  823. memset(best_clock, 0, sizeof(*best_clock));
  824. max_n = limit->n.max;
  825. /* based on hardware requirement, prefer smaller n to precision */
  826. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  827. /* based on hardware requirement, prefere larger m1,m2 */
  828. for (clock.m1 = limit->m1.max;
  829. clock.m1 >= limit->m1.min; clock.m1--) {
  830. for (clock.m2 = limit->m2.max;
  831. clock.m2 >= limit->m2.min; clock.m2--) {
  832. for (clock.p1 = limit->p1.max;
  833. clock.p1 >= limit->p1.min; clock.p1--) {
  834. int this_err;
  835. intel_clock(dev, refclk, &clock);
  836. if (!intel_PLL_is_valid(crtc, &clock))
  837. continue;
  838. this_err = abs(clock.dot - target) ;
  839. if (this_err < err_most) {
  840. *best_clock = clock;
  841. err_most = this_err;
  842. max_n = clock.n;
  843. found = true;
  844. }
  845. }
  846. }
  847. }
  848. }
  849. return found;
  850. }
  851. static bool
  852. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  853. int target, int refclk, intel_clock_t *best_clock)
  854. {
  855. struct drm_device *dev = crtc->dev;
  856. intel_clock_t clock;
  857. /* return directly when it is eDP */
  858. if (HAS_eDP)
  859. return true;
  860. if (target < 200000) {
  861. clock.n = 1;
  862. clock.p1 = 2;
  863. clock.p2 = 10;
  864. clock.m1 = 12;
  865. clock.m2 = 9;
  866. } else {
  867. clock.n = 2;
  868. clock.p1 = 1;
  869. clock.p2 = 10;
  870. clock.m1 = 14;
  871. clock.m2 = 8;
  872. }
  873. intel_clock(dev, refclk, &clock);
  874. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  875. return true;
  876. }
  877. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  878. static bool
  879. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  880. int target, int refclk, intel_clock_t *best_clock)
  881. {
  882. intel_clock_t clock;
  883. if (target < 200000) {
  884. clock.p1 = 2;
  885. clock.p2 = 10;
  886. clock.n = 2;
  887. clock.m1 = 23;
  888. clock.m2 = 8;
  889. } else {
  890. clock.p1 = 1;
  891. clock.p2 = 10;
  892. clock.n = 1;
  893. clock.m1 = 14;
  894. clock.m2 = 2;
  895. }
  896. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  897. clock.p = (clock.p1 * clock.p2);
  898. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  899. clock.vco = 0;
  900. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  901. return true;
  902. }
  903. /**
  904. * intel_wait_for_vblank - wait for vblank on a given pipe
  905. * @dev: drm device
  906. * @pipe: pipe to wait for
  907. *
  908. * Wait for vblank to occur on a given pipe. Needed for various bits of
  909. * mode setting code.
  910. */
  911. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  912. {
  913. struct drm_i915_private *dev_priv = dev->dev_private;
  914. int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
  915. /* Clear existing vblank status. Note this will clear any other
  916. * sticky status fields as well.
  917. *
  918. * This races with i915_driver_irq_handler() with the result
  919. * that either function could miss a vblank event. Here it is not
  920. * fatal, as we will either wait upon the next vblank interrupt or
  921. * timeout. Generally speaking intel_wait_for_vblank() is only
  922. * called during modeset at which time the GPU should be idle and
  923. * should *not* be performing page flips and thus not waiting on
  924. * vblanks...
  925. * Currently, the result of us stealing a vblank from the irq
  926. * handler is that a single frame will be skipped during swapbuffers.
  927. */
  928. I915_WRITE(pipestat_reg,
  929. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  930. /* Wait for vblank interrupt bit to set */
  931. if (wait_for(I915_READ(pipestat_reg) &
  932. PIPE_VBLANK_INTERRUPT_STATUS,
  933. 50))
  934. DRM_DEBUG_KMS("vblank wait timed out\n");
  935. }
  936. /*
  937. * intel_wait_for_pipe_off - wait for pipe to turn off
  938. * @dev: drm device
  939. * @pipe: pipe to wait for
  940. *
  941. * After disabling a pipe, we can't wait for vblank in the usual way,
  942. * spinning on the vblank interrupt status bit, since we won't actually
  943. * see an interrupt when the pipe is disabled.
  944. *
  945. * On Gen4 and above:
  946. * wait for the pipe register state bit to turn off
  947. *
  948. * Otherwise:
  949. * wait for the display line value to settle (it usually
  950. * ends up stopping at the start of the next frame).
  951. *
  952. */
  953. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  954. {
  955. struct drm_i915_private *dev_priv = dev->dev_private;
  956. if (INTEL_INFO(dev)->gen >= 4) {
  957. int reg = PIPECONF(pipe);
  958. /* Wait for the Pipe State to go off */
  959. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  960. 100))
  961. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  962. } else {
  963. u32 last_line;
  964. int reg = PIPEDSL(pipe);
  965. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  966. /* Wait for the display line to settle */
  967. do {
  968. last_line = I915_READ(reg) & DSL_LINEMASK;
  969. mdelay(5);
  970. } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
  971. time_after(timeout, jiffies));
  972. if (time_after(jiffies, timeout))
  973. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  974. }
  975. }
  976. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  977. {
  978. struct drm_device *dev = crtc->dev;
  979. struct drm_i915_private *dev_priv = dev->dev_private;
  980. struct drm_framebuffer *fb = crtc->fb;
  981. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  982. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  983. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  984. int plane, i;
  985. u32 fbc_ctl, fbc_ctl2;
  986. if (fb->pitch == dev_priv->cfb_pitch &&
  987. obj_priv->fence_reg == dev_priv->cfb_fence &&
  988. intel_crtc->plane == dev_priv->cfb_plane &&
  989. I915_READ(FBC_CONTROL) & FBC_CTL_EN)
  990. return;
  991. i8xx_disable_fbc(dev);
  992. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  993. if (fb->pitch < dev_priv->cfb_pitch)
  994. dev_priv->cfb_pitch = fb->pitch;
  995. /* FBC_CTL wants 64B units */
  996. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  997. dev_priv->cfb_fence = obj_priv->fence_reg;
  998. dev_priv->cfb_plane = intel_crtc->plane;
  999. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  1000. /* Clear old tags */
  1001. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  1002. I915_WRITE(FBC_TAG + (i * 4), 0);
  1003. /* Set it up... */
  1004. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  1005. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1006. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  1007. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  1008. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  1009. /* enable it... */
  1010. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  1011. if (IS_I945GM(dev))
  1012. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  1013. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  1014. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  1015. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1016. fbc_ctl |= dev_priv->cfb_fence;
  1017. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1018. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  1019. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  1020. }
  1021. void i8xx_disable_fbc(struct drm_device *dev)
  1022. {
  1023. struct drm_i915_private *dev_priv = dev->dev_private;
  1024. u32 fbc_ctl;
  1025. /* Disable compression */
  1026. fbc_ctl = I915_READ(FBC_CONTROL);
  1027. if ((fbc_ctl & FBC_CTL_EN) == 0)
  1028. return;
  1029. fbc_ctl &= ~FBC_CTL_EN;
  1030. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1031. /* Wait for compressing bit to clear */
  1032. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  1033. DRM_DEBUG_KMS("FBC idle timed out\n");
  1034. return;
  1035. }
  1036. DRM_DEBUG_KMS("disabled FBC\n");
  1037. }
  1038. static bool i8xx_fbc_enabled(struct drm_device *dev)
  1039. {
  1040. struct drm_i915_private *dev_priv = dev->dev_private;
  1041. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  1042. }
  1043. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1044. {
  1045. struct drm_device *dev = crtc->dev;
  1046. struct drm_i915_private *dev_priv = dev->dev_private;
  1047. struct drm_framebuffer *fb = crtc->fb;
  1048. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1049. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  1050. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1051. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1052. unsigned long stall_watermark = 200;
  1053. u32 dpfc_ctl;
  1054. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1055. if (dpfc_ctl & DPFC_CTL_EN) {
  1056. if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
  1057. dev_priv->cfb_fence == obj_priv->fence_reg &&
  1058. dev_priv->cfb_plane == intel_crtc->plane &&
  1059. dev_priv->cfb_y == crtc->y)
  1060. return;
  1061. I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
  1062. POSTING_READ(DPFC_CONTROL);
  1063. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1064. }
  1065. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1066. dev_priv->cfb_fence = obj_priv->fence_reg;
  1067. dev_priv->cfb_plane = intel_crtc->plane;
  1068. dev_priv->cfb_y = crtc->y;
  1069. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  1070. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  1071. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  1072. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  1073. } else {
  1074. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1075. }
  1076. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1077. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1078. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1079. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  1080. /* enable it... */
  1081. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1082. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1083. }
  1084. void g4x_disable_fbc(struct drm_device *dev)
  1085. {
  1086. struct drm_i915_private *dev_priv = dev->dev_private;
  1087. u32 dpfc_ctl;
  1088. /* Disable compression */
  1089. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1090. if (dpfc_ctl & DPFC_CTL_EN) {
  1091. dpfc_ctl &= ~DPFC_CTL_EN;
  1092. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1093. DRM_DEBUG_KMS("disabled FBC\n");
  1094. }
  1095. }
  1096. static bool g4x_fbc_enabled(struct drm_device *dev)
  1097. {
  1098. struct drm_i915_private *dev_priv = dev->dev_private;
  1099. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1100. }
  1101. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1102. {
  1103. struct drm_device *dev = crtc->dev;
  1104. struct drm_i915_private *dev_priv = dev->dev_private;
  1105. struct drm_framebuffer *fb = crtc->fb;
  1106. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1107. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  1108. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1109. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1110. unsigned long stall_watermark = 200;
  1111. u32 dpfc_ctl;
  1112. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1113. if (dpfc_ctl & DPFC_CTL_EN) {
  1114. if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
  1115. dev_priv->cfb_fence == obj_priv->fence_reg &&
  1116. dev_priv->cfb_plane == intel_crtc->plane &&
  1117. dev_priv->cfb_offset == obj_priv->gtt_offset &&
  1118. dev_priv->cfb_y == crtc->y)
  1119. return;
  1120. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
  1121. POSTING_READ(ILK_DPFC_CONTROL);
  1122. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1123. }
  1124. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1125. dev_priv->cfb_fence = obj_priv->fence_reg;
  1126. dev_priv->cfb_plane = intel_crtc->plane;
  1127. dev_priv->cfb_offset = obj_priv->gtt_offset;
  1128. dev_priv->cfb_y = crtc->y;
  1129. dpfc_ctl &= DPFC_RESERVED;
  1130. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  1131. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  1132. dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
  1133. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  1134. } else {
  1135. I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1136. }
  1137. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1138. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1139. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1140. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  1141. I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
  1142. /* enable it... */
  1143. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  1144. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1145. }
  1146. void ironlake_disable_fbc(struct drm_device *dev)
  1147. {
  1148. struct drm_i915_private *dev_priv = dev->dev_private;
  1149. u32 dpfc_ctl;
  1150. /* Disable compression */
  1151. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1152. if (dpfc_ctl & DPFC_CTL_EN) {
  1153. dpfc_ctl &= ~DPFC_CTL_EN;
  1154. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1155. DRM_DEBUG_KMS("disabled FBC\n");
  1156. }
  1157. }
  1158. static bool ironlake_fbc_enabled(struct drm_device *dev)
  1159. {
  1160. struct drm_i915_private *dev_priv = dev->dev_private;
  1161. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  1162. }
  1163. bool intel_fbc_enabled(struct drm_device *dev)
  1164. {
  1165. struct drm_i915_private *dev_priv = dev->dev_private;
  1166. if (!dev_priv->display.fbc_enabled)
  1167. return false;
  1168. return dev_priv->display.fbc_enabled(dev);
  1169. }
  1170. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1171. {
  1172. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1173. if (!dev_priv->display.enable_fbc)
  1174. return;
  1175. dev_priv->display.enable_fbc(crtc, interval);
  1176. }
  1177. void intel_disable_fbc(struct drm_device *dev)
  1178. {
  1179. struct drm_i915_private *dev_priv = dev->dev_private;
  1180. if (!dev_priv->display.disable_fbc)
  1181. return;
  1182. dev_priv->display.disable_fbc(dev);
  1183. }
  1184. /**
  1185. * intel_update_fbc - enable/disable FBC as needed
  1186. * @dev: the drm_device
  1187. *
  1188. * Set up the framebuffer compression hardware at mode set time. We
  1189. * enable it if possible:
  1190. * - plane A only (on pre-965)
  1191. * - no pixel mulitply/line duplication
  1192. * - no alpha buffer discard
  1193. * - no dual wide
  1194. * - framebuffer <= 2048 in width, 1536 in height
  1195. *
  1196. * We can't assume that any compression will take place (worst case),
  1197. * so the compressed buffer has to be the same size as the uncompressed
  1198. * one. It also must reside (along with the line length buffer) in
  1199. * stolen memory.
  1200. *
  1201. * We need to enable/disable FBC on a global basis.
  1202. */
  1203. static void intel_update_fbc(struct drm_device *dev)
  1204. {
  1205. struct drm_i915_private *dev_priv = dev->dev_private;
  1206. struct drm_crtc *crtc = NULL, *tmp_crtc;
  1207. struct intel_crtc *intel_crtc;
  1208. struct drm_framebuffer *fb;
  1209. struct intel_framebuffer *intel_fb;
  1210. struct drm_i915_gem_object *obj_priv;
  1211. DRM_DEBUG_KMS("\n");
  1212. if (!i915_powersave)
  1213. return;
  1214. if (!I915_HAS_FBC(dev))
  1215. return;
  1216. /*
  1217. * If FBC is already on, we just have to verify that we can
  1218. * keep it that way...
  1219. * Need to disable if:
  1220. * - more than one pipe is active
  1221. * - changing FBC params (stride, fence, mode)
  1222. * - new fb is too large to fit in compressed buffer
  1223. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1224. */
  1225. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  1226. if (tmp_crtc->enabled) {
  1227. if (crtc) {
  1228. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  1229. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  1230. goto out_disable;
  1231. }
  1232. crtc = tmp_crtc;
  1233. }
  1234. }
  1235. if (!crtc || crtc->fb == NULL) {
  1236. DRM_DEBUG_KMS("no output, disabling\n");
  1237. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  1238. goto out_disable;
  1239. }
  1240. intel_crtc = to_intel_crtc(crtc);
  1241. fb = crtc->fb;
  1242. intel_fb = to_intel_framebuffer(fb);
  1243. obj_priv = to_intel_bo(intel_fb->obj);
  1244. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1245. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1246. "compression\n");
  1247. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1248. goto out_disable;
  1249. }
  1250. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  1251. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  1252. DRM_DEBUG_KMS("mode incompatible with compression, "
  1253. "disabling\n");
  1254. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1255. goto out_disable;
  1256. }
  1257. if ((crtc->mode.hdisplay > 2048) ||
  1258. (crtc->mode.vdisplay > 1536)) {
  1259. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1260. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1261. goto out_disable;
  1262. }
  1263. if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  1264. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1265. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1266. goto out_disable;
  1267. }
  1268. if (obj_priv->tiling_mode != I915_TILING_X) {
  1269. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1270. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1271. goto out_disable;
  1272. }
  1273. /* If the kernel debugger is active, always disable compression */
  1274. if (in_dbg_master())
  1275. goto out_disable;
  1276. intel_enable_fbc(crtc, 500);
  1277. return;
  1278. out_disable:
  1279. /* Multiple disables should be harmless */
  1280. if (intel_fbc_enabled(dev)) {
  1281. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1282. intel_disable_fbc(dev);
  1283. }
  1284. }
  1285. int
  1286. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1287. struct drm_gem_object *obj,
  1288. bool pipelined)
  1289. {
  1290. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  1291. u32 alignment;
  1292. int ret;
  1293. switch (obj_priv->tiling_mode) {
  1294. case I915_TILING_NONE:
  1295. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1296. alignment = 128 * 1024;
  1297. else if (INTEL_INFO(dev)->gen >= 4)
  1298. alignment = 4 * 1024;
  1299. else
  1300. alignment = 64 * 1024;
  1301. break;
  1302. case I915_TILING_X:
  1303. /* pin() will align the object as required by fence */
  1304. alignment = 0;
  1305. break;
  1306. case I915_TILING_Y:
  1307. /* FIXME: Is this true? */
  1308. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1309. return -EINVAL;
  1310. default:
  1311. BUG();
  1312. }
  1313. ret = i915_gem_object_pin(obj, alignment);
  1314. if (ret)
  1315. return ret;
  1316. ret = i915_gem_object_set_to_display_plane(obj, pipelined);
  1317. if (ret)
  1318. goto err_unpin;
  1319. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1320. * fence, whereas 965+ only requires a fence if using
  1321. * framebuffer compression. For simplicity, we always install
  1322. * a fence as the cost is not that onerous.
  1323. */
  1324. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1325. obj_priv->tiling_mode != I915_TILING_NONE) {
  1326. ret = i915_gem_object_get_fence_reg(obj, false);
  1327. if (ret)
  1328. goto err_unpin;
  1329. }
  1330. return 0;
  1331. err_unpin:
  1332. i915_gem_object_unpin(obj);
  1333. return ret;
  1334. }
  1335. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1336. static int
  1337. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1338. int x, int y)
  1339. {
  1340. struct drm_device *dev = crtc->dev;
  1341. struct drm_i915_private *dev_priv = dev->dev_private;
  1342. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1343. struct intel_framebuffer *intel_fb;
  1344. struct drm_i915_gem_object *obj_priv;
  1345. struct drm_gem_object *obj;
  1346. int plane = intel_crtc->plane;
  1347. unsigned long Start, Offset;
  1348. u32 dspcntr;
  1349. u32 reg;
  1350. switch (plane) {
  1351. case 0:
  1352. case 1:
  1353. break;
  1354. default:
  1355. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1356. return -EINVAL;
  1357. }
  1358. intel_fb = to_intel_framebuffer(fb);
  1359. obj = intel_fb->obj;
  1360. obj_priv = to_intel_bo(obj);
  1361. reg = DSPCNTR(plane);
  1362. dspcntr = I915_READ(reg);
  1363. /* Mask out pixel format bits in case we change it */
  1364. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1365. switch (fb->bits_per_pixel) {
  1366. case 8:
  1367. dspcntr |= DISPPLANE_8BPP;
  1368. break;
  1369. case 16:
  1370. if (fb->depth == 15)
  1371. dspcntr |= DISPPLANE_15_16BPP;
  1372. else
  1373. dspcntr |= DISPPLANE_16BPP;
  1374. break;
  1375. case 24:
  1376. case 32:
  1377. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1378. break;
  1379. default:
  1380. DRM_ERROR("Unknown color depth\n");
  1381. return -EINVAL;
  1382. }
  1383. if (INTEL_INFO(dev)->gen >= 4) {
  1384. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1385. dspcntr |= DISPPLANE_TILED;
  1386. else
  1387. dspcntr &= ~DISPPLANE_TILED;
  1388. }
  1389. if (HAS_PCH_SPLIT(dev))
  1390. /* must disable */
  1391. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1392. I915_WRITE(reg, dspcntr);
  1393. Start = obj_priv->gtt_offset;
  1394. Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
  1395. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1396. Start, Offset, x, y, fb->pitch);
  1397. I915_WRITE(DSPSTRIDE(plane), fb->pitch);
  1398. if (INTEL_INFO(dev)->gen >= 4) {
  1399. I915_WRITE(DSPSURF(plane), Start);
  1400. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1401. I915_WRITE(DSPADDR(plane), Offset);
  1402. } else
  1403. I915_WRITE(DSPADDR(plane), Start + Offset);
  1404. POSTING_READ(reg);
  1405. intel_update_fbc(dev);
  1406. intel_increase_pllclock(crtc);
  1407. return 0;
  1408. }
  1409. static int
  1410. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1411. struct drm_framebuffer *old_fb)
  1412. {
  1413. struct drm_device *dev = crtc->dev;
  1414. struct drm_i915_master_private *master_priv;
  1415. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1416. int ret;
  1417. /* no fb bound */
  1418. if (!crtc->fb) {
  1419. DRM_DEBUG_KMS("No FB bound\n");
  1420. return 0;
  1421. }
  1422. switch (intel_crtc->plane) {
  1423. case 0:
  1424. case 1:
  1425. break;
  1426. default:
  1427. return -EINVAL;
  1428. }
  1429. mutex_lock(&dev->struct_mutex);
  1430. ret = intel_pin_and_fence_fb_obj(dev,
  1431. to_intel_framebuffer(crtc->fb)->obj,
  1432. false);
  1433. if (ret != 0) {
  1434. mutex_unlock(&dev->struct_mutex);
  1435. return ret;
  1436. }
  1437. if (old_fb) {
  1438. struct drm_i915_private *dev_priv = dev->dev_private;
  1439. struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1440. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  1441. wait_event(dev_priv->pending_flip_queue,
  1442. atomic_read(&obj_priv->pending_flip) == 0);
  1443. }
  1444. ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
  1445. if (ret) {
  1446. i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
  1447. mutex_unlock(&dev->struct_mutex);
  1448. return ret;
  1449. }
  1450. if (old_fb)
  1451. i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
  1452. mutex_unlock(&dev->struct_mutex);
  1453. if (!dev->primary->master)
  1454. return 0;
  1455. master_priv = dev->primary->master->driver_priv;
  1456. if (!master_priv->sarea_priv)
  1457. return 0;
  1458. if (intel_crtc->pipe) {
  1459. master_priv->sarea_priv->pipeB_x = x;
  1460. master_priv->sarea_priv->pipeB_y = y;
  1461. } else {
  1462. master_priv->sarea_priv->pipeA_x = x;
  1463. master_priv->sarea_priv->pipeA_y = y;
  1464. }
  1465. return 0;
  1466. }
  1467. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  1468. {
  1469. struct drm_device *dev = crtc->dev;
  1470. struct drm_i915_private *dev_priv = dev->dev_private;
  1471. u32 dpa_ctl;
  1472. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1473. dpa_ctl = I915_READ(DP_A);
  1474. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1475. if (clock < 200000) {
  1476. u32 temp;
  1477. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1478. /* workaround for 160Mhz:
  1479. 1) program 0x4600c bits 15:0 = 0x8124
  1480. 2) program 0x46010 bit 0 = 1
  1481. 3) program 0x46034 bit 24 = 1
  1482. 4) program 0x64000 bit 14 = 1
  1483. */
  1484. temp = I915_READ(0x4600c);
  1485. temp &= 0xffff0000;
  1486. I915_WRITE(0x4600c, temp | 0x8124);
  1487. temp = I915_READ(0x46010);
  1488. I915_WRITE(0x46010, temp | 1);
  1489. temp = I915_READ(0x46034);
  1490. I915_WRITE(0x46034, temp | (1 << 24));
  1491. } else {
  1492. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1493. }
  1494. I915_WRITE(DP_A, dpa_ctl);
  1495. POSTING_READ(DP_A);
  1496. udelay(500);
  1497. }
  1498. /* The FDI link training functions for ILK/Ibexpeak. */
  1499. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1500. {
  1501. struct drm_device *dev = crtc->dev;
  1502. struct drm_i915_private *dev_priv = dev->dev_private;
  1503. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1504. int pipe = intel_crtc->pipe;
  1505. u32 reg, temp, tries;
  1506. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1507. for train result */
  1508. reg = FDI_RX_IMR(pipe);
  1509. temp = I915_READ(reg);
  1510. temp &= ~FDI_RX_SYMBOL_LOCK;
  1511. temp &= ~FDI_RX_BIT_LOCK;
  1512. I915_WRITE(reg, temp);
  1513. I915_READ(reg);
  1514. udelay(150);
  1515. /* enable CPU FDI TX and PCH FDI RX */
  1516. reg = FDI_TX_CTL(pipe);
  1517. temp = I915_READ(reg);
  1518. temp &= ~(7 << 19);
  1519. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1520. temp &= ~FDI_LINK_TRAIN_NONE;
  1521. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1522. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  1523. reg = FDI_RX_CTL(pipe);
  1524. temp = I915_READ(reg);
  1525. temp &= ~FDI_LINK_TRAIN_NONE;
  1526. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1527. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  1528. POSTING_READ(reg);
  1529. udelay(150);
  1530. reg = FDI_RX_IIR(pipe);
  1531. for (tries = 0; tries < 5; tries++) {
  1532. temp = I915_READ(reg);
  1533. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1534. if ((temp & FDI_RX_BIT_LOCK)) {
  1535. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1536. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  1537. break;
  1538. }
  1539. }
  1540. if (tries == 5)
  1541. DRM_ERROR("FDI train 1 fail!\n");
  1542. /* Train 2 */
  1543. reg = FDI_TX_CTL(pipe);
  1544. temp = I915_READ(reg);
  1545. temp &= ~FDI_LINK_TRAIN_NONE;
  1546. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1547. I915_WRITE(reg, temp);
  1548. reg = FDI_RX_CTL(pipe);
  1549. temp = I915_READ(reg);
  1550. temp &= ~FDI_LINK_TRAIN_NONE;
  1551. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1552. I915_WRITE(reg, temp);
  1553. POSTING_READ(reg);
  1554. udelay(150);
  1555. reg = FDI_RX_IIR(pipe);
  1556. for (tries = 0; tries < 5; tries++) {
  1557. temp = I915_READ(reg);
  1558. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1559. if (temp & FDI_RX_SYMBOL_LOCK) {
  1560. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  1561. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1562. break;
  1563. }
  1564. }
  1565. if (tries == 5)
  1566. DRM_ERROR("FDI train 2 fail!\n");
  1567. DRM_DEBUG_KMS("FDI train done\n");
  1568. }
  1569. static const int const snb_b_fdi_train_param [] = {
  1570. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  1571. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  1572. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  1573. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  1574. };
  1575. /* The FDI link training functions for SNB/Cougarpoint. */
  1576. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  1577. {
  1578. struct drm_device *dev = crtc->dev;
  1579. struct drm_i915_private *dev_priv = dev->dev_private;
  1580. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1581. int pipe = intel_crtc->pipe;
  1582. u32 reg, temp, i;
  1583. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1584. for train result */
  1585. reg = FDI_RX_IMR(pipe);
  1586. temp = I915_READ(reg);
  1587. temp &= ~FDI_RX_SYMBOL_LOCK;
  1588. temp &= ~FDI_RX_BIT_LOCK;
  1589. I915_WRITE(reg, temp);
  1590. POSTING_READ(reg);
  1591. udelay(150);
  1592. /* enable CPU FDI TX and PCH FDI RX */
  1593. reg = FDI_TX_CTL(pipe);
  1594. temp = I915_READ(reg);
  1595. temp &= ~(7 << 19);
  1596. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1597. temp &= ~FDI_LINK_TRAIN_NONE;
  1598. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1599. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1600. /* SNB-B */
  1601. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1602. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  1603. reg = FDI_RX_CTL(pipe);
  1604. temp = I915_READ(reg);
  1605. if (HAS_PCH_CPT(dev)) {
  1606. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1607. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1608. } else {
  1609. temp &= ~FDI_LINK_TRAIN_NONE;
  1610. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1611. }
  1612. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  1613. POSTING_READ(reg);
  1614. udelay(150);
  1615. for (i = 0; i < 4; i++ ) {
  1616. reg = FDI_TX_CTL(pipe);
  1617. temp = I915_READ(reg);
  1618. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1619. temp |= snb_b_fdi_train_param[i];
  1620. I915_WRITE(reg, temp);
  1621. POSTING_READ(reg);
  1622. udelay(500);
  1623. reg = FDI_RX_IIR(pipe);
  1624. temp = I915_READ(reg);
  1625. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1626. if (temp & FDI_RX_BIT_LOCK) {
  1627. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  1628. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1629. break;
  1630. }
  1631. }
  1632. if (i == 4)
  1633. DRM_ERROR("FDI train 1 fail!\n");
  1634. /* Train 2 */
  1635. reg = FDI_TX_CTL(pipe);
  1636. temp = I915_READ(reg);
  1637. temp &= ~FDI_LINK_TRAIN_NONE;
  1638. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1639. if (IS_GEN6(dev)) {
  1640. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1641. /* SNB-B */
  1642. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1643. }
  1644. I915_WRITE(reg, temp);
  1645. reg = FDI_RX_CTL(pipe);
  1646. temp = I915_READ(reg);
  1647. if (HAS_PCH_CPT(dev)) {
  1648. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1649. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  1650. } else {
  1651. temp &= ~FDI_LINK_TRAIN_NONE;
  1652. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1653. }
  1654. I915_WRITE(reg, temp);
  1655. POSTING_READ(reg);
  1656. udelay(150);
  1657. for (i = 0; i < 4; i++ ) {
  1658. reg = FDI_TX_CTL(pipe);
  1659. temp = I915_READ(reg);
  1660. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1661. temp |= snb_b_fdi_train_param[i];
  1662. I915_WRITE(reg, temp);
  1663. POSTING_READ(reg);
  1664. udelay(500);
  1665. reg = FDI_RX_IIR(pipe);
  1666. temp = I915_READ(reg);
  1667. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1668. if (temp & FDI_RX_SYMBOL_LOCK) {
  1669. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  1670. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1671. break;
  1672. }
  1673. }
  1674. if (i == 4)
  1675. DRM_ERROR("FDI train 2 fail!\n");
  1676. DRM_DEBUG_KMS("FDI train done.\n");
  1677. }
  1678. static void ironlake_fdi_enable(struct drm_crtc *crtc)
  1679. {
  1680. struct drm_device *dev = crtc->dev;
  1681. struct drm_i915_private *dev_priv = dev->dev_private;
  1682. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1683. int pipe = intel_crtc->pipe;
  1684. u32 reg, temp;
  1685. /* Write the TU size bits so error detection works */
  1686. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  1687. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  1688. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1689. reg = FDI_RX_CTL(pipe);
  1690. temp = I915_READ(reg);
  1691. temp &= ~((0x7 << 19) | (0x7 << 16));
  1692. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1693. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  1694. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  1695. POSTING_READ(reg);
  1696. udelay(200);
  1697. /* Switch from Rawclk to PCDclk */
  1698. temp = I915_READ(reg);
  1699. I915_WRITE(reg, temp | FDI_PCDCLK);
  1700. POSTING_READ(reg);
  1701. udelay(200);
  1702. /* Enable CPU FDI TX PLL, always on for Ironlake */
  1703. reg = FDI_TX_CTL(pipe);
  1704. temp = I915_READ(reg);
  1705. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1706. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  1707. POSTING_READ(reg);
  1708. udelay(100);
  1709. }
  1710. }
  1711. static void intel_flush_display_plane(struct drm_device *dev,
  1712. int plane)
  1713. {
  1714. struct drm_i915_private *dev_priv = dev->dev_private;
  1715. u32 reg = DSPADDR(plane);
  1716. I915_WRITE(reg, I915_READ(reg));
  1717. }
  1718. /*
  1719. * When we disable a pipe, we need to clear any pending scanline wait events
  1720. * to avoid hanging the ring, which we assume we are waiting on.
  1721. */
  1722. static void intel_clear_scanline_wait(struct drm_device *dev)
  1723. {
  1724. struct drm_i915_private *dev_priv = dev->dev_private;
  1725. u32 tmp;
  1726. if (IS_GEN2(dev))
  1727. /* Can't break the hang on i8xx */
  1728. return;
  1729. tmp = I915_READ(PRB0_CTL);
  1730. if (tmp & RING_WAIT) {
  1731. I915_WRITE(PRB0_CTL, tmp);
  1732. POSTING_READ(PRB0_CTL);
  1733. }
  1734. }
  1735. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  1736. {
  1737. struct drm_i915_gem_object *obj_priv;
  1738. struct drm_i915_private *dev_priv;
  1739. if (crtc->fb == NULL)
  1740. return;
  1741. obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
  1742. dev_priv = crtc->dev->dev_private;
  1743. wait_event(dev_priv->pending_flip_queue,
  1744. atomic_read(&obj_priv->pending_flip) == 0);
  1745. }
  1746. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  1747. {
  1748. struct drm_device *dev = crtc->dev;
  1749. struct drm_i915_private *dev_priv = dev->dev_private;
  1750. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1751. int pipe = intel_crtc->pipe;
  1752. int plane = intel_crtc->plane;
  1753. u32 reg, temp;
  1754. if (intel_crtc->active)
  1755. return;
  1756. intel_crtc->active = true;
  1757. intel_update_watermarks(dev);
  1758. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1759. temp = I915_READ(PCH_LVDS);
  1760. if ((temp & LVDS_PORT_EN) == 0)
  1761. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  1762. }
  1763. ironlake_fdi_enable(crtc);
  1764. /* Enable panel fitting for LVDS */
  1765. if (dev_priv->pch_pf_size &&
  1766. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
  1767. || HAS_eDP || intel_pch_has_edp(crtc))) {
  1768. /* Force use of hard-coded filter coefficients
  1769. * as some pre-programmed values are broken,
  1770. * e.g. x201.
  1771. */
  1772. I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
  1773. PF_ENABLE | PF_FILTER_MED_3x3);
  1774. I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
  1775. dev_priv->pch_pf_pos);
  1776. I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
  1777. dev_priv->pch_pf_size);
  1778. }
  1779. /* Enable CPU pipe */
  1780. reg = PIPECONF(pipe);
  1781. temp = I915_READ(reg);
  1782. if ((temp & PIPECONF_ENABLE) == 0) {
  1783. I915_WRITE(reg, temp | PIPECONF_ENABLE);
  1784. POSTING_READ(reg);
  1785. udelay(100);
  1786. }
  1787. /* configure and enable CPU plane */
  1788. reg = DSPCNTR(plane);
  1789. temp = I915_READ(reg);
  1790. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1791. I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
  1792. intel_flush_display_plane(dev, plane);
  1793. }
  1794. /* For PCH output, training FDI link */
  1795. if (IS_GEN6(dev))
  1796. gen6_fdi_link_train(crtc);
  1797. else
  1798. ironlake_fdi_link_train(crtc);
  1799. /* enable PCH DPLL */
  1800. reg = PCH_DPLL(pipe);
  1801. temp = I915_READ(reg);
  1802. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1803. I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
  1804. POSTING_READ(reg);
  1805. udelay(200);
  1806. }
  1807. if (HAS_PCH_CPT(dev)) {
  1808. /* Be sure PCH DPLL SEL is set */
  1809. temp = I915_READ(PCH_DPLL_SEL);
  1810. if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
  1811. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  1812. else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
  1813. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1814. I915_WRITE(PCH_DPLL_SEL, temp);
  1815. }
  1816. /* set transcoder timing */
  1817. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  1818. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  1819. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  1820. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  1821. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  1822. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  1823. /* enable normal train */
  1824. reg = FDI_TX_CTL(pipe);
  1825. temp = I915_READ(reg);
  1826. temp &= ~FDI_LINK_TRAIN_NONE;
  1827. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  1828. I915_WRITE(reg, temp);
  1829. reg = FDI_RX_CTL(pipe);
  1830. temp = I915_READ(reg);
  1831. if (HAS_PCH_CPT(dev)) {
  1832. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1833. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1834. } else {
  1835. temp &= ~FDI_LINK_TRAIN_NONE;
  1836. temp |= FDI_LINK_TRAIN_NONE;
  1837. }
  1838. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1839. /* wait one idle pattern time */
  1840. POSTING_READ(reg);
  1841. udelay(100);
  1842. /* For PCH DP, enable TRANS_DP_CTL */
  1843. if (HAS_PCH_CPT(dev) &&
  1844. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  1845. reg = TRANS_DP_CTL(pipe);
  1846. temp = I915_READ(reg);
  1847. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  1848. TRANS_DP_SYNC_MASK);
  1849. temp |= (TRANS_DP_OUTPUT_ENABLE |
  1850. TRANS_DP_ENH_FRAMING);
  1851. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  1852. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  1853. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  1854. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  1855. switch (intel_trans_dp_port_sel(crtc)) {
  1856. case PCH_DP_B:
  1857. temp |= TRANS_DP_PORT_SEL_B;
  1858. break;
  1859. case PCH_DP_C:
  1860. temp |= TRANS_DP_PORT_SEL_C;
  1861. break;
  1862. case PCH_DP_D:
  1863. temp |= TRANS_DP_PORT_SEL_D;
  1864. break;
  1865. default:
  1866. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  1867. temp |= TRANS_DP_PORT_SEL_B;
  1868. break;
  1869. }
  1870. I915_WRITE(reg, temp);
  1871. }
  1872. /* enable PCH transcoder */
  1873. reg = TRANSCONF(pipe);
  1874. temp = I915_READ(reg);
  1875. /*
  1876. * make the BPC in transcoder be consistent with
  1877. * that in pipeconf reg.
  1878. */
  1879. temp &= ~PIPE_BPC_MASK;
  1880. temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
  1881. I915_WRITE(reg, temp | TRANS_ENABLE);
  1882. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1883. DRM_ERROR("failed to enable transcoder\n");
  1884. intel_crtc_load_lut(crtc);
  1885. intel_update_fbc(dev);
  1886. intel_crtc_update_cursor(crtc, true);
  1887. }
  1888. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  1889. {
  1890. struct drm_device *dev = crtc->dev;
  1891. struct drm_i915_private *dev_priv = dev->dev_private;
  1892. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1893. int pipe = intel_crtc->pipe;
  1894. int plane = intel_crtc->plane;
  1895. u32 reg, temp;
  1896. if (!intel_crtc->active)
  1897. return;
  1898. intel_crtc_wait_for_pending_flips(crtc);
  1899. drm_vblank_off(dev, pipe);
  1900. intel_crtc_update_cursor(crtc, false);
  1901. /* Disable display plane */
  1902. reg = DSPCNTR(plane);
  1903. temp = I915_READ(reg);
  1904. if (temp & DISPLAY_PLANE_ENABLE) {
  1905. I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
  1906. intel_flush_display_plane(dev, plane);
  1907. }
  1908. if (dev_priv->cfb_plane == plane &&
  1909. dev_priv->display.disable_fbc)
  1910. dev_priv->display.disable_fbc(dev);
  1911. /* disable cpu pipe, disable after all planes disabled */
  1912. reg = PIPECONF(pipe);
  1913. temp = I915_READ(reg);
  1914. if (temp & PIPECONF_ENABLE) {
  1915. I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
  1916. /* wait for cpu pipe off, pipe state */
  1917. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
  1918. DRM_ERROR("failed to turn off cpu pipe\n");
  1919. }
  1920. /* Disable PF */
  1921. I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
  1922. I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
  1923. /* disable CPU FDI tx and PCH FDI rx */
  1924. reg = FDI_TX_CTL(pipe);
  1925. temp = I915_READ(reg);
  1926. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  1927. POSTING_READ(reg);
  1928. reg = FDI_RX_CTL(pipe);
  1929. temp = I915_READ(reg);
  1930. temp &= ~(0x7 << 16);
  1931. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  1932. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  1933. POSTING_READ(reg);
  1934. udelay(100);
  1935. /* still set train pattern 1 */
  1936. reg = FDI_TX_CTL(pipe);
  1937. temp = I915_READ(reg);
  1938. temp &= ~FDI_LINK_TRAIN_NONE;
  1939. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1940. I915_WRITE(reg, temp);
  1941. reg = FDI_RX_CTL(pipe);
  1942. temp = I915_READ(reg);
  1943. if (HAS_PCH_CPT(dev)) {
  1944. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1945. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1946. } else {
  1947. temp &= ~FDI_LINK_TRAIN_NONE;
  1948. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1949. }
  1950. /* BPC in FDI rx is consistent with that in PIPECONF */
  1951. temp &= ~(0x07 << 16);
  1952. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  1953. I915_WRITE(reg, temp);
  1954. POSTING_READ(reg);
  1955. udelay(100);
  1956. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1957. temp = I915_READ(PCH_LVDS);
  1958. if (temp & LVDS_PORT_EN) {
  1959. I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
  1960. POSTING_READ(PCH_LVDS);
  1961. udelay(100);
  1962. }
  1963. }
  1964. /* disable PCH transcoder */
  1965. reg = TRANSCONF(plane);
  1966. temp = I915_READ(reg);
  1967. if (temp & TRANS_ENABLE) {
  1968. I915_WRITE(reg, temp & ~TRANS_ENABLE);
  1969. /* wait for PCH transcoder off, transcoder state */
  1970. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1971. DRM_ERROR("failed to disable transcoder\n");
  1972. }
  1973. if (HAS_PCH_CPT(dev)) {
  1974. /* disable TRANS_DP_CTL */
  1975. reg = TRANS_DP_CTL(pipe);
  1976. temp = I915_READ(reg);
  1977. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  1978. I915_WRITE(reg, temp);
  1979. /* disable DPLL_SEL */
  1980. temp = I915_READ(PCH_DPLL_SEL);
  1981. if (pipe == 0)
  1982. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  1983. else
  1984. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1985. I915_WRITE(PCH_DPLL_SEL, temp);
  1986. }
  1987. /* disable PCH DPLL */
  1988. reg = PCH_DPLL(pipe);
  1989. temp = I915_READ(reg);
  1990. I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
  1991. /* Switch from PCDclk to Rawclk */
  1992. reg = FDI_RX_CTL(pipe);
  1993. temp = I915_READ(reg);
  1994. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  1995. /* Disable CPU FDI TX PLL */
  1996. reg = FDI_TX_CTL(pipe);
  1997. temp = I915_READ(reg);
  1998. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  1999. POSTING_READ(reg);
  2000. udelay(100);
  2001. reg = FDI_RX_CTL(pipe);
  2002. temp = I915_READ(reg);
  2003. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2004. /* Wait for the clocks to turn off. */
  2005. POSTING_READ(reg);
  2006. udelay(100);
  2007. intel_crtc->active = false;
  2008. intel_update_watermarks(dev);
  2009. intel_update_fbc(dev);
  2010. intel_clear_scanline_wait(dev);
  2011. }
  2012. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  2013. {
  2014. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2015. int pipe = intel_crtc->pipe;
  2016. int plane = intel_crtc->plane;
  2017. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2018. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2019. */
  2020. switch (mode) {
  2021. case DRM_MODE_DPMS_ON:
  2022. case DRM_MODE_DPMS_STANDBY:
  2023. case DRM_MODE_DPMS_SUSPEND:
  2024. DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
  2025. ironlake_crtc_enable(crtc);
  2026. break;
  2027. case DRM_MODE_DPMS_OFF:
  2028. DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
  2029. ironlake_crtc_disable(crtc);
  2030. break;
  2031. }
  2032. }
  2033. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2034. {
  2035. if (!enable && intel_crtc->overlay) {
  2036. struct drm_device *dev = intel_crtc->base.dev;
  2037. mutex_lock(&dev->struct_mutex);
  2038. (void) intel_overlay_switch_off(intel_crtc->overlay, false);
  2039. mutex_unlock(&dev->struct_mutex);
  2040. }
  2041. /* Let userspace switch the overlay on again. In most cases userspace
  2042. * has to recompute where to put it anyway.
  2043. */
  2044. }
  2045. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  2046. {
  2047. struct drm_device *dev = crtc->dev;
  2048. struct drm_i915_private *dev_priv = dev->dev_private;
  2049. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2050. int pipe = intel_crtc->pipe;
  2051. int plane = intel_crtc->plane;
  2052. u32 reg, temp;
  2053. if (intel_crtc->active)
  2054. return;
  2055. intel_crtc->active = true;
  2056. intel_update_watermarks(dev);
  2057. /* Enable the DPLL */
  2058. reg = DPLL(pipe);
  2059. temp = I915_READ(reg);
  2060. if ((temp & DPLL_VCO_ENABLE) == 0) {
  2061. I915_WRITE(reg, temp);
  2062. /* Wait for the clocks to stabilize. */
  2063. POSTING_READ(reg);
  2064. udelay(150);
  2065. I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
  2066. /* Wait for the clocks to stabilize. */
  2067. POSTING_READ(reg);
  2068. udelay(150);
  2069. I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
  2070. /* Wait for the clocks to stabilize. */
  2071. POSTING_READ(reg);
  2072. udelay(150);
  2073. }
  2074. /* Enable the pipe */
  2075. reg = PIPECONF(pipe);
  2076. temp = I915_READ(reg);
  2077. if ((temp & PIPECONF_ENABLE) == 0)
  2078. I915_WRITE(reg, temp | PIPECONF_ENABLE);
  2079. /* Enable the plane */
  2080. reg = DSPCNTR(plane);
  2081. temp = I915_READ(reg);
  2082. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  2083. I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
  2084. intel_flush_display_plane(dev, plane);
  2085. }
  2086. intel_crtc_load_lut(crtc);
  2087. intel_update_fbc(dev);
  2088. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2089. intel_crtc_dpms_overlay(intel_crtc, true);
  2090. intel_crtc_update_cursor(crtc, true);
  2091. }
  2092. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2093. {
  2094. struct drm_device *dev = crtc->dev;
  2095. struct drm_i915_private *dev_priv = dev->dev_private;
  2096. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2097. int pipe = intel_crtc->pipe;
  2098. int plane = intel_crtc->plane;
  2099. u32 reg, temp;
  2100. if (!intel_crtc->active)
  2101. return;
  2102. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2103. intel_crtc_wait_for_pending_flips(crtc);
  2104. drm_vblank_off(dev, pipe);
  2105. intel_crtc_dpms_overlay(intel_crtc, false);
  2106. intel_crtc_update_cursor(crtc, false);
  2107. if (dev_priv->cfb_plane == plane &&
  2108. dev_priv->display.disable_fbc)
  2109. dev_priv->display.disable_fbc(dev);
  2110. /* Disable display plane */
  2111. reg = DSPCNTR(plane);
  2112. temp = I915_READ(reg);
  2113. if (temp & DISPLAY_PLANE_ENABLE) {
  2114. I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
  2115. /* Flush the plane changes */
  2116. intel_flush_display_plane(dev, plane);
  2117. /* Wait for vblank for the disable to take effect */
  2118. if (IS_GEN2(dev))
  2119. intel_wait_for_vblank(dev, pipe);
  2120. }
  2121. /* Don't disable pipe A or pipe A PLLs if needed */
  2122. if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  2123. goto done;
  2124. /* Next, disable display pipes */
  2125. reg = PIPECONF(pipe);
  2126. temp = I915_READ(reg);
  2127. if (temp & PIPECONF_ENABLE) {
  2128. I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
  2129. /* Wait for the pipe to turn off */
  2130. POSTING_READ(reg);
  2131. intel_wait_for_pipe_off(dev, pipe);
  2132. }
  2133. reg = DPLL(pipe);
  2134. temp = I915_READ(reg);
  2135. if (temp & DPLL_VCO_ENABLE) {
  2136. I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
  2137. /* Wait for the clocks to turn off. */
  2138. POSTING_READ(reg);
  2139. udelay(150);
  2140. }
  2141. done:
  2142. intel_crtc->active = false;
  2143. intel_update_fbc(dev);
  2144. intel_update_watermarks(dev);
  2145. intel_clear_scanline_wait(dev);
  2146. }
  2147. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  2148. {
  2149. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2150. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2151. */
  2152. switch (mode) {
  2153. case DRM_MODE_DPMS_ON:
  2154. case DRM_MODE_DPMS_STANDBY:
  2155. case DRM_MODE_DPMS_SUSPEND:
  2156. i9xx_crtc_enable(crtc);
  2157. break;
  2158. case DRM_MODE_DPMS_OFF:
  2159. i9xx_crtc_disable(crtc);
  2160. break;
  2161. }
  2162. }
  2163. /**
  2164. * Sets the power management mode of the pipe and plane.
  2165. */
  2166. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2167. {
  2168. struct drm_device *dev = crtc->dev;
  2169. struct drm_i915_private *dev_priv = dev->dev_private;
  2170. struct drm_i915_master_private *master_priv;
  2171. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2172. int pipe = intel_crtc->pipe;
  2173. bool enabled;
  2174. if (intel_crtc->dpms_mode == mode)
  2175. return;
  2176. intel_crtc->dpms_mode = mode;
  2177. dev_priv->display.dpms(crtc, mode);
  2178. if (!dev->primary->master)
  2179. return;
  2180. master_priv = dev->primary->master->driver_priv;
  2181. if (!master_priv->sarea_priv)
  2182. return;
  2183. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2184. switch (pipe) {
  2185. case 0:
  2186. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2187. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2188. break;
  2189. case 1:
  2190. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2191. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2192. break;
  2193. default:
  2194. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  2195. break;
  2196. }
  2197. }
  2198. static void intel_crtc_disable(struct drm_crtc *crtc)
  2199. {
  2200. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2201. struct drm_device *dev = crtc->dev;
  2202. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2203. if (crtc->fb) {
  2204. mutex_lock(&dev->struct_mutex);
  2205. i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
  2206. mutex_unlock(&dev->struct_mutex);
  2207. }
  2208. }
  2209. /* Prepare for a mode set.
  2210. *
  2211. * Note we could be a lot smarter here. We need to figure out which outputs
  2212. * will be enabled, which disabled (in short, how the config will changes)
  2213. * and perform the minimum necessary steps to accomplish that, e.g. updating
  2214. * watermarks, FBC configuration, making sure PLLs are programmed correctly,
  2215. * panel fitting is in the proper state, etc.
  2216. */
  2217. static void i9xx_crtc_prepare(struct drm_crtc *crtc)
  2218. {
  2219. i9xx_crtc_disable(crtc);
  2220. }
  2221. static void i9xx_crtc_commit(struct drm_crtc *crtc)
  2222. {
  2223. i9xx_crtc_enable(crtc);
  2224. }
  2225. static void ironlake_crtc_prepare(struct drm_crtc *crtc)
  2226. {
  2227. ironlake_crtc_disable(crtc);
  2228. }
  2229. static void ironlake_crtc_commit(struct drm_crtc *crtc)
  2230. {
  2231. ironlake_crtc_enable(crtc);
  2232. }
  2233. void intel_encoder_prepare (struct drm_encoder *encoder)
  2234. {
  2235. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2236. /* lvds has its own version of prepare see intel_lvds_prepare */
  2237. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2238. }
  2239. void intel_encoder_commit (struct drm_encoder *encoder)
  2240. {
  2241. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2242. /* lvds has its own version of commit see intel_lvds_commit */
  2243. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2244. }
  2245. void intel_encoder_destroy(struct drm_encoder *encoder)
  2246. {
  2247. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2248. drm_encoder_cleanup(encoder);
  2249. kfree(intel_encoder);
  2250. }
  2251. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2252. struct drm_display_mode *mode,
  2253. struct drm_display_mode *adjusted_mode)
  2254. {
  2255. struct drm_device *dev = crtc->dev;
  2256. if (HAS_PCH_SPLIT(dev)) {
  2257. /* FDI link clock is fixed at 2.7G */
  2258. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  2259. return false;
  2260. }
  2261. /* XXX some encoders set the crtcinfo, others don't.
  2262. * Obviously we need some form of conflict resolution here...
  2263. */
  2264. if (adjusted_mode->crtc_htotal == 0)
  2265. drm_mode_set_crtcinfo(adjusted_mode, 0);
  2266. return true;
  2267. }
  2268. static int i945_get_display_clock_speed(struct drm_device *dev)
  2269. {
  2270. return 400000;
  2271. }
  2272. static int i915_get_display_clock_speed(struct drm_device *dev)
  2273. {
  2274. return 333000;
  2275. }
  2276. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2277. {
  2278. return 200000;
  2279. }
  2280. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2281. {
  2282. u16 gcfgc = 0;
  2283. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2284. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2285. return 133000;
  2286. else {
  2287. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2288. case GC_DISPLAY_CLOCK_333_MHZ:
  2289. return 333000;
  2290. default:
  2291. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2292. return 190000;
  2293. }
  2294. }
  2295. }
  2296. static int i865_get_display_clock_speed(struct drm_device *dev)
  2297. {
  2298. return 266000;
  2299. }
  2300. static int i855_get_display_clock_speed(struct drm_device *dev)
  2301. {
  2302. u16 hpllcc = 0;
  2303. /* Assume that the hardware is in the high speed state. This
  2304. * should be the default.
  2305. */
  2306. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2307. case GC_CLOCK_133_200:
  2308. case GC_CLOCK_100_200:
  2309. return 200000;
  2310. case GC_CLOCK_166_250:
  2311. return 250000;
  2312. case GC_CLOCK_100_133:
  2313. return 133000;
  2314. }
  2315. /* Shouldn't happen */
  2316. return 0;
  2317. }
  2318. static int i830_get_display_clock_speed(struct drm_device *dev)
  2319. {
  2320. return 133000;
  2321. }
  2322. struct fdi_m_n {
  2323. u32 tu;
  2324. u32 gmch_m;
  2325. u32 gmch_n;
  2326. u32 link_m;
  2327. u32 link_n;
  2328. };
  2329. static void
  2330. fdi_reduce_ratio(u32 *num, u32 *den)
  2331. {
  2332. while (*num > 0xffffff || *den > 0xffffff) {
  2333. *num >>= 1;
  2334. *den >>= 1;
  2335. }
  2336. }
  2337. #define DATA_N 0x800000
  2338. #define LINK_N 0x80000
  2339. static void
  2340. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2341. int link_clock, struct fdi_m_n *m_n)
  2342. {
  2343. u64 temp;
  2344. m_n->tu = 64; /* default size */
  2345. temp = (u64) DATA_N * pixel_clock;
  2346. temp = div_u64(temp, link_clock);
  2347. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  2348. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  2349. m_n->gmch_n = DATA_N;
  2350. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2351. temp = (u64) LINK_N * pixel_clock;
  2352. m_n->link_m = div_u64(temp, link_clock);
  2353. m_n->link_n = LINK_N;
  2354. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2355. }
  2356. struct intel_watermark_params {
  2357. unsigned long fifo_size;
  2358. unsigned long max_wm;
  2359. unsigned long default_wm;
  2360. unsigned long guard_size;
  2361. unsigned long cacheline_size;
  2362. };
  2363. /* Pineview has different values for various configs */
  2364. static struct intel_watermark_params pineview_display_wm = {
  2365. PINEVIEW_DISPLAY_FIFO,
  2366. PINEVIEW_MAX_WM,
  2367. PINEVIEW_DFT_WM,
  2368. PINEVIEW_GUARD_WM,
  2369. PINEVIEW_FIFO_LINE_SIZE
  2370. };
  2371. static struct intel_watermark_params pineview_display_hplloff_wm = {
  2372. PINEVIEW_DISPLAY_FIFO,
  2373. PINEVIEW_MAX_WM,
  2374. PINEVIEW_DFT_HPLLOFF_WM,
  2375. PINEVIEW_GUARD_WM,
  2376. PINEVIEW_FIFO_LINE_SIZE
  2377. };
  2378. static struct intel_watermark_params pineview_cursor_wm = {
  2379. PINEVIEW_CURSOR_FIFO,
  2380. PINEVIEW_CURSOR_MAX_WM,
  2381. PINEVIEW_CURSOR_DFT_WM,
  2382. PINEVIEW_CURSOR_GUARD_WM,
  2383. PINEVIEW_FIFO_LINE_SIZE,
  2384. };
  2385. static struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2386. PINEVIEW_CURSOR_FIFO,
  2387. PINEVIEW_CURSOR_MAX_WM,
  2388. PINEVIEW_CURSOR_DFT_WM,
  2389. PINEVIEW_CURSOR_GUARD_WM,
  2390. PINEVIEW_FIFO_LINE_SIZE
  2391. };
  2392. static struct intel_watermark_params g4x_wm_info = {
  2393. G4X_FIFO_SIZE,
  2394. G4X_MAX_WM,
  2395. G4X_MAX_WM,
  2396. 2,
  2397. G4X_FIFO_LINE_SIZE,
  2398. };
  2399. static struct intel_watermark_params g4x_cursor_wm_info = {
  2400. I965_CURSOR_FIFO,
  2401. I965_CURSOR_MAX_WM,
  2402. I965_CURSOR_DFT_WM,
  2403. 2,
  2404. G4X_FIFO_LINE_SIZE,
  2405. };
  2406. static struct intel_watermark_params i965_cursor_wm_info = {
  2407. I965_CURSOR_FIFO,
  2408. I965_CURSOR_MAX_WM,
  2409. I965_CURSOR_DFT_WM,
  2410. 2,
  2411. I915_FIFO_LINE_SIZE,
  2412. };
  2413. static struct intel_watermark_params i945_wm_info = {
  2414. I945_FIFO_SIZE,
  2415. I915_MAX_WM,
  2416. 1,
  2417. 2,
  2418. I915_FIFO_LINE_SIZE
  2419. };
  2420. static struct intel_watermark_params i915_wm_info = {
  2421. I915_FIFO_SIZE,
  2422. I915_MAX_WM,
  2423. 1,
  2424. 2,
  2425. I915_FIFO_LINE_SIZE
  2426. };
  2427. static struct intel_watermark_params i855_wm_info = {
  2428. I855GM_FIFO_SIZE,
  2429. I915_MAX_WM,
  2430. 1,
  2431. 2,
  2432. I830_FIFO_LINE_SIZE
  2433. };
  2434. static struct intel_watermark_params i830_wm_info = {
  2435. I830_FIFO_SIZE,
  2436. I915_MAX_WM,
  2437. 1,
  2438. 2,
  2439. I830_FIFO_LINE_SIZE
  2440. };
  2441. static struct intel_watermark_params ironlake_display_wm_info = {
  2442. ILK_DISPLAY_FIFO,
  2443. ILK_DISPLAY_MAXWM,
  2444. ILK_DISPLAY_DFTWM,
  2445. 2,
  2446. ILK_FIFO_LINE_SIZE
  2447. };
  2448. static struct intel_watermark_params ironlake_cursor_wm_info = {
  2449. ILK_CURSOR_FIFO,
  2450. ILK_CURSOR_MAXWM,
  2451. ILK_CURSOR_DFTWM,
  2452. 2,
  2453. ILK_FIFO_LINE_SIZE
  2454. };
  2455. static struct intel_watermark_params ironlake_display_srwm_info = {
  2456. ILK_DISPLAY_SR_FIFO,
  2457. ILK_DISPLAY_MAX_SRWM,
  2458. ILK_DISPLAY_DFT_SRWM,
  2459. 2,
  2460. ILK_FIFO_LINE_SIZE
  2461. };
  2462. static struct intel_watermark_params ironlake_cursor_srwm_info = {
  2463. ILK_CURSOR_SR_FIFO,
  2464. ILK_CURSOR_MAX_SRWM,
  2465. ILK_CURSOR_DFT_SRWM,
  2466. 2,
  2467. ILK_FIFO_LINE_SIZE
  2468. };
  2469. /**
  2470. * intel_calculate_wm - calculate watermark level
  2471. * @clock_in_khz: pixel clock
  2472. * @wm: chip FIFO params
  2473. * @pixel_size: display pixel size
  2474. * @latency_ns: memory latency for the platform
  2475. *
  2476. * Calculate the watermark level (the level at which the display plane will
  2477. * start fetching from memory again). Each chip has a different display
  2478. * FIFO size and allocation, so the caller needs to figure that out and pass
  2479. * in the correct intel_watermark_params structure.
  2480. *
  2481. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  2482. * on the pixel size. When it reaches the watermark level, it'll start
  2483. * fetching FIFO line sized based chunks from memory until the FIFO fills
  2484. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  2485. * will occur, and a display engine hang could result.
  2486. */
  2487. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  2488. struct intel_watermark_params *wm,
  2489. int pixel_size,
  2490. unsigned long latency_ns)
  2491. {
  2492. long entries_required, wm_size;
  2493. /*
  2494. * Note: we need to make sure we don't overflow for various clock &
  2495. * latency values.
  2496. * clocks go from a few thousand to several hundred thousand.
  2497. * latency is usually a few thousand
  2498. */
  2499. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  2500. 1000;
  2501. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  2502. DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
  2503. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  2504. DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
  2505. /* Don't promote wm_size to unsigned... */
  2506. if (wm_size > (long)wm->max_wm)
  2507. wm_size = wm->max_wm;
  2508. if (wm_size <= 0)
  2509. wm_size = wm->default_wm;
  2510. return wm_size;
  2511. }
  2512. struct cxsr_latency {
  2513. int is_desktop;
  2514. int is_ddr3;
  2515. unsigned long fsb_freq;
  2516. unsigned long mem_freq;
  2517. unsigned long display_sr;
  2518. unsigned long display_hpll_disable;
  2519. unsigned long cursor_sr;
  2520. unsigned long cursor_hpll_disable;
  2521. };
  2522. static const struct cxsr_latency cxsr_latency_table[] = {
  2523. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2524. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2525. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2526. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  2527. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  2528. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2529. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2530. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2531. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  2532. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  2533. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2534. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2535. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2536. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  2537. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  2538. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2539. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2540. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2541. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  2542. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  2543. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2544. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2545. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2546. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  2547. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  2548. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2549. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2550. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2551. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  2552. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  2553. };
  2554. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  2555. int is_ddr3,
  2556. int fsb,
  2557. int mem)
  2558. {
  2559. const struct cxsr_latency *latency;
  2560. int i;
  2561. if (fsb == 0 || mem == 0)
  2562. return NULL;
  2563. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2564. latency = &cxsr_latency_table[i];
  2565. if (is_desktop == latency->is_desktop &&
  2566. is_ddr3 == latency->is_ddr3 &&
  2567. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2568. return latency;
  2569. }
  2570. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2571. return NULL;
  2572. }
  2573. static void pineview_disable_cxsr(struct drm_device *dev)
  2574. {
  2575. struct drm_i915_private *dev_priv = dev->dev_private;
  2576. /* deactivate cxsr */
  2577. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  2578. }
  2579. /*
  2580. * Latency for FIFO fetches is dependent on several factors:
  2581. * - memory configuration (speed, channels)
  2582. * - chipset
  2583. * - current MCH state
  2584. * It can be fairly high in some situations, so here we assume a fairly
  2585. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2586. * set this value too high, the FIFO will fetch frequently to stay full)
  2587. * and power consumption (set it too low to save power and we might see
  2588. * FIFO underruns and display "flicker").
  2589. *
  2590. * A value of 5us seems to be a good balance; safe for very low end
  2591. * platforms but not overly aggressive on lower latency configs.
  2592. */
  2593. static const int latency_ns = 5000;
  2594. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2595. {
  2596. struct drm_i915_private *dev_priv = dev->dev_private;
  2597. uint32_t dsparb = I915_READ(DSPARB);
  2598. int size;
  2599. size = dsparb & 0x7f;
  2600. if (plane)
  2601. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  2602. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2603. plane ? "B" : "A", size);
  2604. return size;
  2605. }
  2606. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2607. {
  2608. struct drm_i915_private *dev_priv = dev->dev_private;
  2609. uint32_t dsparb = I915_READ(DSPARB);
  2610. int size;
  2611. size = dsparb & 0x1ff;
  2612. if (plane)
  2613. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  2614. size >>= 1; /* Convert to cachelines */
  2615. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2616. plane ? "B" : "A", size);
  2617. return size;
  2618. }
  2619. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2620. {
  2621. struct drm_i915_private *dev_priv = dev->dev_private;
  2622. uint32_t dsparb = I915_READ(DSPARB);
  2623. int size;
  2624. size = dsparb & 0x7f;
  2625. size >>= 2; /* Convert to cachelines */
  2626. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2627. plane ? "B" : "A",
  2628. size);
  2629. return size;
  2630. }
  2631. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2632. {
  2633. struct drm_i915_private *dev_priv = dev->dev_private;
  2634. uint32_t dsparb = I915_READ(DSPARB);
  2635. int size;
  2636. size = dsparb & 0x7f;
  2637. size >>= 1; /* Convert to cachelines */
  2638. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2639. plane ? "B" : "A", size);
  2640. return size;
  2641. }
  2642. static void pineview_update_wm(struct drm_device *dev, int planea_clock,
  2643. int planeb_clock, int sr_hdisplay, int unused,
  2644. int pixel_size)
  2645. {
  2646. struct drm_i915_private *dev_priv = dev->dev_private;
  2647. const struct cxsr_latency *latency;
  2648. u32 reg;
  2649. unsigned long wm;
  2650. int sr_clock;
  2651. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  2652. dev_priv->fsb_freq, dev_priv->mem_freq);
  2653. if (!latency) {
  2654. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2655. pineview_disable_cxsr(dev);
  2656. return;
  2657. }
  2658. if (!planea_clock || !planeb_clock) {
  2659. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2660. /* Display SR */
  2661. wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
  2662. pixel_size, latency->display_sr);
  2663. reg = I915_READ(DSPFW1);
  2664. reg &= ~DSPFW_SR_MASK;
  2665. reg |= wm << DSPFW_SR_SHIFT;
  2666. I915_WRITE(DSPFW1, reg);
  2667. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  2668. /* cursor SR */
  2669. wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
  2670. pixel_size, latency->cursor_sr);
  2671. reg = I915_READ(DSPFW3);
  2672. reg &= ~DSPFW_CURSOR_SR_MASK;
  2673. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  2674. I915_WRITE(DSPFW3, reg);
  2675. /* Display HPLL off SR */
  2676. wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
  2677. pixel_size, latency->display_hpll_disable);
  2678. reg = I915_READ(DSPFW3);
  2679. reg &= ~DSPFW_HPLL_SR_MASK;
  2680. reg |= wm & DSPFW_HPLL_SR_MASK;
  2681. I915_WRITE(DSPFW3, reg);
  2682. /* cursor HPLL off SR */
  2683. wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
  2684. pixel_size, latency->cursor_hpll_disable);
  2685. reg = I915_READ(DSPFW3);
  2686. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  2687. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  2688. I915_WRITE(DSPFW3, reg);
  2689. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  2690. /* activate cxsr */
  2691. I915_WRITE(DSPFW3,
  2692. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  2693. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  2694. } else {
  2695. pineview_disable_cxsr(dev);
  2696. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  2697. }
  2698. }
  2699. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2700. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2701. int pixel_size)
  2702. {
  2703. struct drm_i915_private *dev_priv = dev->dev_private;
  2704. int total_size, cacheline_size;
  2705. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2706. struct intel_watermark_params planea_params, planeb_params;
  2707. unsigned long line_time_us;
  2708. int sr_clock, sr_entries = 0, entries_required;
  2709. /* Create copies of the base settings for each pipe */
  2710. planea_params = planeb_params = g4x_wm_info;
  2711. /* Grab a couple of global values before we overwrite them */
  2712. total_size = planea_params.fifo_size;
  2713. cacheline_size = planea_params.cacheline_size;
  2714. /*
  2715. * Note: we need to make sure we don't overflow for various clock &
  2716. * latency values.
  2717. * clocks go from a few thousand to several hundred thousand.
  2718. * latency is usually a few thousand
  2719. */
  2720. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2721. 1000;
  2722. entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
  2723. planea_wm = entries_required + planea_params.guard_size;
  2724. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2725. 1000;
  2726. entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
  2727. planeb_wm = entries_required + planeb_params.guard_size;
  2728. cursora_wm = cursorb_wm = 16;
  2729. cursor_sr = 32;
  2730. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2731. /* Calc sr entries for one plane configs */
  2732. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2733. /* self-refresh has much higher latency */
  2734. static const int sr_latency_ns = 12000;
  2735. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2736. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2737. /* Use ns/us then divide to preserve precision */
  2738. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2739. pixel_size * sr_hdisplay;
  2740. sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
  2741. entries_required = (((sr_latency_ns / line_time_us) +
  2742. 1000) / 1000) * pixel_size * 64;
  2743. entries_required = DIV_ROUND_UP(entries_required,
  2744. g4x_cursor_wm_info.cacheline_size);
  2745. cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
  2746. if (cursor_sr > g4x_cursor_wm_info.max_wm)
  2747. cursor_sr = g4x_cursor_wm_info.max_wm;
  2748. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2749. "cursor %d\n", sr_entries, cursor_sr);
  2750. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2751. } else {
  2752. /* Turn off self refresh if both pipes are enabled */
  2753. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2754. & ~FW_BLC_SELF_EN);
  2755. }
  2756. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2757. planea_wm, planeb_wm, sr_entries);
  2758. planea_wm &= 0x3f;
  2759. planeb_wm &= 0x3f;
  2760. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2761. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2762. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2763. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2764. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2765. /* HPLL off in SR has some issues on G4x... disable it */
  2766. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2767. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2768. }
  2769. static void i965_update_wm(struct drm_device *dev, int planea_clock,
  2770. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2771. int pixel_size)
  2772. {
  2773. struct drm_i915_private *dev_priv = dev->dev_private;
  2774. unsigned long line_time_us;
  2775. int sr_clock, sr_entries, srwm = 1;
  2776. int cursor_sr = 16;
  2777. /* Calc sr entries for one plane configs */
  2778. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2779. /* self-refresh has much higher latency */
  2780. static const int sr_latency_ns = 12000;
  2781. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2782. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2783. /* Use ns/us then divide to preserve precision */
  2784. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2785. pixel_size * sr_hdisplay;
  2786. sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
  2787. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2788. srwm = I965_FIFO_SIZE - sr_entries;
  2789. if (srwm < 0)
  2790. srwm = 1;
  2791. srwm &= 0x1ff;
  2792. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2793. pixel_size * 64;
  2794. sr_entries = DIV_ROUND_UP(sr_entries,
  2795. i965_cursor_wm_info.cacheline_size);
  2796. cursor_sr = i965_cursor_wm_info.fifo_size -
  2797. (sr_entries + i965_cursor_wm_info.guard_size);
  2798. if (cursor_sr > i965_cursor_wm_info.max_wm)
  2799. cursor_sr = i965_cursor_wm_info.max_wm;
  2800. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2801. "cursor %d\n", srwm, cursor_sr);
  2802. if (IS_CRESTLINE(dev))
  2803. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2804. } else {
  2805. /* Turn off self refresh if both pipes are enabled */
  2806. if (IS_CRESTLINE(dev))
  2807. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2808. & ~FW_BLC_SELF_EN);
  2809. }
  2810. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  2811. srwm);
  2812. /* 965 has limitations... */
  2813. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
  2814. (8 << 0));
  2815. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2816. /* update cursor SR watermark */
  2817. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2818. }
  2819. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2820. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2821. int pixel_size)
  2822. {
  2823. struct drm_i915_private *dev_priv = dev->dev_private;
  2824. uint32_t fwater_lo;
  2825. uint32_t fwater_hi;
  2826. int total_size, cacheline_size, cwm, srwm = 1;
  2827. int planea_wm, planeb_wm;
  2828. struct intel_watermark_params planea_params, planeb_params;
  2829. unsigned long line_time_us;
  2830. int sr_clock, sr_entries = 0;
  2831. /* Create copies of the base settings for each pipe */
  2832. if (IS_CRESTLINE(dev) || IS_I945GM(dev))
  2833. planea_params = planeb_params = i945_wm_info;
  2834. else if (!IS_GEN2(dev))
  2835. planea_params = planeb_params = i915_wm_info;
  2836. else
  2837. planea_params = planeb_params = i855_wm_info;
  2838. /* Grab a couple of global values before we overwrite them */
  2839. total_size = planea_params.fifo_size;
  2840. cacheline_size = planea_params.cacheline_size;
  2841. /* Update per-plane FIFO sizes */
  2842. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2843. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2844. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2845. pixel_size, latency_ns);
  2846. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2847. pixel_size, latency_ns);
  2848. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2849. /*
  2850. * Overlay gets an aggressive default since video jitter is bad.
  2851. */
  2852. cwm = 2;
  2853. /* Calc sr entries for one plane configs */
  2854. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2855. (!planea_clock || !planeb_clock)) {
  2856. /* self-refresh has much higher latency */
  2857. static const int sr_latency_ns = 6000;
  2858. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2859. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2860. /* Use ns/us then divide to preserve precision */
  2861. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2862. pixel_size * sr_hdisplay;
  2863. sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
  2864. DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
  2865. srwm = total_size - sr_entries;
  2866. if (srwm < 0)
  2867. srwm = 1;
  2868. if (IS_I945G(dev) || IS_I945GM(dev))
  2869. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  2870. else if (IS_I915GM(dev)) {
  2871. /* 915M has a smaller SRWM field */
  2872. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  2873. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  2874. }
  2875. } else {
  2876. /* Turn off self refresh if both pipes are enabled */
  2877. if (IS_I945G(dev) || IS_I945GM(dev)) {
  2878. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2879. & ~FW_BLC_SELF_EN);
  2880. } else if (IS_I915GM(dev)) {
  2881. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  2882. }
  2883. }
  2884. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2885. planea_wm, planeb_wm, cwm, srwm);
  2886. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2887. fwater_hi = (cwm & 0x1f);
  2888. /* Set request length to 8 cachelines per fetch */
  2889. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2890. fwater_hi = fwater_hi | (1 << 8);
  2891. I915_WRITE(FW_BLC, fwater_lo);
  2892. I915_WRITE(FW_BLC2, fwater_hi);
  2893. }
  2894. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2895. int unused2, int unused3, int pixel_size)
  2896. {
  2897. struct drm_i915_private *dev_priv = dev->dev_private;
  2898. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2899. int planea_wm;
  2900. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2901. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2902. pixel_size, latency_ns);
  2903. fwater_lo |= (3<<8) | planea_wm;
  2904. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  2905. I915_WRITE(FW_BLC, fwater_lo);
  2906. }
  2907. #define ILK_LP0_PLANE_LATENCY 700
  2908. #define ILK_LP0_CURSOR_LATENCY 1300
  2909. static bool ironlake_compute_wm0(struct drm_device *dev,
  2910. int pipe,
  2911. int *plane_wm,
  2912. int *cursor_wm)
  2913. {
  2914. struct drm_crtc *crtc;
  2915. int htotal, hdisplay, clock, pixel_size = 0;
  2916. int line_time_us, line_count, entries;
  2917. crtc = intel_get_crtc_for_pipe(dev, pipe);
  2918. if (crtc->fb == NULL || !crtc->enabled)
  2919. return false;
  2920. htotal = crtc->mode.htotal;
  2921. hdisplay = crtc->mode.hdisplay;
  2922. clock = crtc->mode.clock;
  2923. pixel_size = crtc->fb->bits_per_pixel / 8;
  2924. /* Use the small buffer method to calculate plane watermark */
  2925. entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
  2926. entries = DIV_ROUND_UP(entries,
  2927. ironlake_display_wm_info.cacheline_size);
  2928. *plane_wm = entries + ironlake_display_wm_info.guard_size;
  2929. if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
  2930. *plane_wm = ironlake_display_wm_info.max_wm;
  2931. /* Use the large buffer method to calculate cursor watermark */
  2932. line_time_us = ((htotal * 1000) / clock);
  2933. line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
  2934. entries = line_count * 64 * pixel_size;
  2935. entries = DIV_ROUND_UP(entries,
  2936. ironlake_cursor_wm_info.cacheline_size);
  2937. *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
  2938. if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
  2939. *cursor_wm = ironlake_cursor_wm_info.max_wm;
  2940. return true;
  2941. }
  2942. static void ironlake_update_wm(struct drm_device *dev,
  2943. int planea_clock, int planeb_clock,
  2944. int sr_hdisplay, int sr_htotal,
  2945. int pixel_size)
  2946. {
  2947. struct drm_i915_private *dev_priv = dev->dev_private;
  2948. int plane_wm, cursor_wm, enabled;
  2949. int tmp;
  2950. enabled = 0;
  2951. if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
  2952. I915_WRITE(WM0_PIPEA_ILK,
  2953. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  2954. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  2955. " plane %d, " "cursor: %d\n",
  2956. plane_wm, cursor_wm);
  2957. enabled++;
  2958. }
  2959. if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
  2960. I915_WRITE(WM0_PIPEB_ILK,
  2961. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  2962. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  2963. " plane %d, cursor: %d\n",
  2964. plane_wm, cursor_wm);
  2965. enabled++;
  2966. }
  2967. /*
  2968. * Calculate and update the self-refresh watermark only when one
  2969. * display plane is used.
  2970. */
  2971. tmp = 0;
  2972. if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
  2973. unsigned long line_time_us;
  2974. int small, large, plane_fbc;
  2975. int sr_clock, entries;
  2976. int line_count, line_size;
  2977. /* Read the self-refresh latency. The unit is 0.5us */
  2978. int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
  2979. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2980. line_time_us = (sr_htotal * 1000) / sr_clock;
  2981. /* Use ns/us then divide to preserve precision */
  2982. line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
  2983. / 1000;
  2984. line_size = sr_hdisplay * pixel_size;
  2985. /* Use the minimum of the small and large buffer method for primary */
  2986. small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
  2987. large = line_count * line_size;
  2988. entries = DIV_ROUND_UP(min(small, large),
  2989. ironlake_display_srwm_info.cacheline_size);
  2990. plane_fbc = entries * 64;
  2991. plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
  2992. plane_wm = entries + ironlake_display_srwm_info.guard_size;
  2993. if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
  2994. plane_wm = ironlake_display_srwm_info.max_wm;
  2995. /* calculate the self-refresh watermark for display cursor */
  2996. entries = line_count * pixel_size * 64;
  2997. entries = DIV_ROUND_UP(entries,
  2998. ironlake_cursor_srwm_info.cacheline_size);
  2999. cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
  3000. if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
  3001. cursor_wm = ironlake_cursor_srwm_info.max_wm;
  3002. /* configure watermark and enable self-refresh */
  3003. tmp = (WM1_LP_SR_EN |
  3004. (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
  3005. (plane_fbc << WM1_LP_FBC_SHIFT) |
  3006. (plane_wm << WM1_LP_SR_SHIFT) |
  3007. cursor_wm);
  3008. DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
  3009. " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
  3010. }
  3011. I915_WRITE(WM1_LP_ILK, tmp);
  3012. /* XXX setup WM2 and WM3 */
  3013. }
  3014. /**
  3015. * intel_update_watermarks - update FIFO watermark values based on current modes
  3016. *
  3017. * Calculate watermark values for the various WM regs based on current mode
  3018. * and plane configuration.
  3019. *
  3020. * There are several cases to deal with here:
  3021. * - normal (i.e. non-self-refresh)
  3022. * - self-refresh (SR) mode
  3023. * - lines are large relative to FIFO size (buffer can hold up to 2)
  3024. * - lines are small relative to FIFO size (buffer can hold more than 2
  3025. * lines), so need to account for TLB latency
  3026. *
  3027. * The normal calculation is:
  3028. * watermark = dotclock * bytes per pixel * latency
  3029. * where latency is platform & configuration dependent (we assume pessimal
  3030. * values here).
  3031. *
  3032. * The SR calculation is:
  3033. * watermark = (trunc(latency/line time)+1) * surface width *
  3034. * bytes per pixel
  3035. * where
  3036. * line time = htotal / dotclock
  3037. * surface width = hdisplay for normal plane and 64 for cursor
  3038. * and latency is assumed to be high, as above.
  3039. *
  3040. * The final value programmed to the register should always be rounded up,
  3041. * and include an extra 2 entries to account for clock crossings.
  3042. *
  3043. * We don't use the sprite, so we can ignore that. And on Crestline we have
  3044. * to set the non-SR watermarks to 8.
  3045. */
  3046. static void intel_update_watermarks(struct drm_device *dev)
  3047. {
  3048. struct drm_i915_private *dev_priv = dev->dev_private;
  3049. struct drm_crtc *crtc;
  3050. int sr_hdisplay = 0;
  3051. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  3052. int enabled = 0, pixel_size = 0;
  3053. int sr_htotal = 0;
  3054. if (!dev_priv->display.update_wm)
  3055. return;
  3056. /* Get the clock config from both planes */
  3057. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3058. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3059. if (intel_crtc->active) {
  3060. enabled++;
  3061. if (intel_crtc->plane == 0) {
  3062. DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
  3063. intel_crtc->pipe, crtc->mode.clock);
  3064. planea_clock = crtc->mode.clock;
  3065. } else {
  3066. DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
  3067. intel_crtc->pipe, crtc->mode.clock);
  3068. planeb_clock = crtc->mode.clock;
  3069. }
  3070. sr_hdisplay = crtc->mode.hdisplay;
  3071. sr_clock = crtc->mode.clock;
  3072. sr_htotal = crtc->mode.htotal;
  3073. if (crtc->fb)
  3074. pixel_size = crtc->fb->bits_per_pixel / 8;
  3075. else
  3076. pixel_size = 4; /* by default */
  3077. }
  3078. }
  3079. if (enabled <= 0)
  3080. return;
  3081. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  3082. sr_hdisplay, sr_htotal, pixel_size);
  3083. }
  3084. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  3085. struct drm_display_mode *mode,
  3086. struct drm_display_mode *adjusted_mode,
  3087. int x, int y,
  3088. struct drm_framebuffer *old_fb)
  3089. {
  3090. struct drm_device *dev = crtc->dev;
  3091. struct drm_i915_private *dev_priv = dev->dev_private;
  3092. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3093. int pipe = intel_crtc->pipe;
  3094. int plane = intel_crtc->plane;
  3095. u32 fp_reg, dpll_reg;
  3096. int refclk, num_connectors = 0;
  3097. intel_clock_t clock, reduced_clock;
  3098. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  3099. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  3100. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  3101. struct intel_encoder *has_edp_encoder = NULL;
  3102. struct drm_mode_config *mode_config = &dev->mode_config;
  3103. struct intel_encoder *encoder;
  3104. const intel_limit_t *limit;
  3105. int ret;
  3106. struct fdi_m_n m_n = {0};
  3107. u32 reg, temp;
  3108. int target_clock;
  3109. drm_vblank_pre_modeset(dev, pipe);
  3110. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  3111. if (encoder->base.crtc != crtc)
  3112. continue;
  3113. switch (encoder->type) {
  3114. case INTEL_OUTPUT_LVDS:
  3115. is_lvds = true;
  3116. break;
  3117. case INTEL_OUTPUT_SDVO:
  3118. case INTEL_OUTPUT_HDMI:
  3119. is_sdvo = true;
  3120. if (encoder->needs_tv_clock)
  3121. is_tv = true;
  3122. break;
  3123. case INTEL_OUTPUT_DVO:
  3124. is_dvo = true;
  3125. break;
  3126. case INTEL_OUTPUT_TVOUT:
  3127. is_tv = true;
  3128. break;
  3129. case INTEL_OUTPUT_ANALOG:
  3130. is_crt = true;
  3131. break;
  3132. case INTEL_OUTPUT_DISPLAYPORT:
  3133. is_dp = true;
  3134. break;
  3135. case INTEL_OUTPUT_EDP:
  3136. has_edp_encoder = encoder;
  3137. break;
  3138. }
  3139. num_connectors++;
  3140. }
  3141. if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
  3142. refclk = dev_priv->lvds_ssc_freq * 1000;
  3143. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3144. refclk / 1000);
  3145. } else if (!IS_GEN2(dev)) {
  3146. refclk = 96000;
  3147. if (HAS_PCH_SPLIT(dev))
  3148. refclk = 120000; /* 120Mhz refclk */
  3149. } else {
  3150. refclk = 48000;
  3151. }
  3152. /*
  3153. * Returns a set of divisors for the desired target clock with the given
  3154. * refclk, or FALSE. The returned values represent the clock equation:
  3155. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3156. */
  3157. limit = intel_limit(crtc);
  3158. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  3159. if (!ok) {
  3160. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3161. drm_vblank_post_modeset(dev, pipe);
  3162. return -EINVAL;
  3163. }
  3164. /* Ensure that the cursor is valid for the new mode before changing... */
  3165. intel_crtc_update_cursor(crtc, true);
  3166. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3167. has_reduced_clock = limit->find_pll(limit, crtc,
  3168. dev_priv->lvds_downclock,
  3169. refclk,
  3170. &reduced_clock);
  3171. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  3172. /*
  3173. * If the different P is found, it means that we can't
  3174. * switch the display clock by using the FP0/FP1.
  3175. * In such case we will disable the LVDS downclock
  3176. * feature.
  3177. */
  3178. DRM_DEBUG_KMS("Different P is found for "
  3179. "LVDS clock/downclock\n");
  3180. has_reduced_clock = 0;
  3181. }
  3182. }
  3183. /* SDVO TV has fixed PLL values depend on its clock range,
  3184. this mirrors vbios setting. */
  3185. if (is_sdvo && is_tv) {
  3186. if (adjusted_mode->clock >= 100000
  3187. && adjusted_mode->clock < 140500) {
  3188. clock.p1 = 2;
  3189. clock.p2 = 10;
  3190. clock.n = 3;
  3191. clock.m1 = 16;
  3192. clock.m2 = 8;
  3193. } else if (adjusted_mode->clock >= 140500
  3194. && adjusted_mode->clock <= 200000) {
  3195. clock.p1 = 1;
  3196. clock.p2 = 10;
  3197. clock.n = 6;
  3198. clock.m1 = 12;
  3199. clock.m2 = 8;
  3200. }
  3201. }
  3202. /* FDI link */
  3203. if (HAS_PCH_SPLIT(dev)) {
  3204. int lane = 0, link_bw, bpp;
  3205. /* eDP doesn't require FDI link, so just set DP M/N
  3206. according to current link config */
  3207. if (has_edp_encoder) {
  3208. target_clock = mode->clock;
  3209. intel_edp_link_config(has_edp_encoder,
  3210. &lane, &link_bw);
  3211. } else {
  3212. /* DP over FDI requires target mode clock
  3213. instead of link clock */
  3214. if (is_dp)
  3215. target_clock = mode->clock;
  3216. else
  3217. target_clock = adjusted_mode->clock;
  3218. /* FDI is a binary signal running at ~2.7GHz, encoding
  3219. * each output octet as 10 bits. The actual frequency
  3220. * is stored as a divider into a 100MHz clock, and the
  3221. * mode pixel clock is stored in units of 1KHz.
  3222. * Hence the bw of each lane in terms of the mode signal
  3223. * is:
  3224. */
  3225. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  3226. }
  3227. /* determine panel color depth */
  3228. temp = I915_READ(PIPECONF(pipe));
  3229. temp &= ~PIPE_BPC_MASK;
  3230. if (is_lvds) {
  3231. /* the BPC will be 6 if it is 18-bit LVDS panel */
  3232. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
  3233. temp |= PIPE_8BPC;
  3234. else
  3235. temp |= PIPE_6BPC;
  3236. } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
  3237. switch (dev_priv->edp.bpp/3) {
  3238. case 8:
  3239. temp |= PIPE_8BPC;
  3240. break;
  3241. case 10:
  3242. temp |= PIPE_10BPC;
  3243. break;
  3244. case 6:
  3245. temp |= PIPE_6BPC;
  3246. break;
  3247. case 12:
  3248. temp |= PIPE_12BPC;
  3249. break;
  3250. }
  3251. } else
  3252. temp |= PIPE_8BPC;
  3253. I915_WRITE(PIPECONF(pipe), temp);
  3254. switch (temp & PIPE_BPC_MASK) {
  3255. case PIPE_8BPC:
  3256. bpp = 24;
  3257. break;
  3258. case PIPE_10BPC:
  3259. bpp = 30;
  3260. break;
  3261. case PIPE_6BPC:
  3262. bpp = 18;
  3263. break;
  3264. case PIPE_12BPC:
  3265. bpp = 36;
  3266. break;
  3267. default:
  3268. DRM_ERROR("unknown pipe bpc value\n");
  3269. bpp = 24;
  3270. }
  3271. if (!lane) {
  3272. /*
  3273. * Account for spread spectrum to avoid
  3274. * oversubscribing the link. Max center spread
  3275. * is 2.5%; use 5% for safety's sake.
  3276. */
  3277. u32 bps = target_clock * bpp * 21 / 20;
  3278. lane = bps / (link_bw * 8) + 1;
  3279. }
  3280. intel_crtc->fdi_lanes = lane;
  3281. ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
  3282. }
  3283. /* Ironlake: try to setup display ref clock before DPLL
  3284. * enabling. This is only under driver's control after
  3285. * PCH B stepping, previous chipset stepping should be
  3286. * ignoring this setting.
  3287. */
  3288. if (HAS_PCH_SPLIT(dev)) {
  3289. temp = I915_READ(PCH_DREF_CONTROL);
  3290. /* Always enable nonspread source */
  3291. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3292. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3293. temp &= ~DREF_SSC_SOURCE_MASK;
  3294. temp |= DREF_SSC_SOURCE_ENABLE;
  3295. I915_WRITE(PCH_DREF_CONTROL, temp);
  3296. POSTING_READ(PCH_DREF_CONTROL);
  3297. udelay(200);
  3298. if (has_edp_encoder) {
  3299. if (dev_priv->lvds_use_ssc) {
  3300. temp |= DREF_SSC1_ENABLE;
  3301. I915_WRITE(PCH_DREF_CONTROL, temp);
  3302. POSTING_READ(PCH_DREF_CONTROL);
  3303. udelay(200);
  3304. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3305. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3306. } else {
  3307. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3308. }
  3309. I915_WRITE(PCH_DREF_CONTROL, temp);
  3310. }
  3311. }
  3312. if (IS_PINEVIEW(dev)) {
  3313. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  3314. if (has_reduced_clock)
  3315. fp2 = (1 << reduced_clock.n) << 16 |
  3316. reduced_clock.m1 << 8 | reduced_clock.m2;
  3317. } else {
  3318. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  3319. if (has_reduced_clock)
  3320. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  3321. reduced_clock.m2;
  3322. }
  3323. dpll = 0;
  3324. if (!HAS_PCH_SPLIT(dev))
  3325. dpll = DPLL_VGA_MODE_DIS;
  3326. if (!IS_GEN2(dev)) {
  3327. if (is_lvds)
  3328. dpll |= DPLLB_MODE_LVDS;
  3329. else
  3330. dpll |= DPLLB_MODE_DAC_SERIAL;
  3331. if (is_sdvo) {
  3332. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3333. if (pixel_multiplier > 1) {
  3334. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3335. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3336. else if (HAS_PCH_SPLIT(dev))
  3337. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  3338. }
  3339. dpll |= DPLL_DVO_HIGH_SPEED;
  3340. }
  3341. if (is_dp)
  3342. dpll |= DPLL_DVO_HIGH_SPEED;
  3343. /* compute bitmask from p1 value */
  3344. if (IS_PINEVIEW(dev))
  3345. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3346. else {
  3347. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3348. /* also FPA1 */
  3349. if (HAS_PCH_SPLIT(dev))
  3350. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3351. if (IS_G4X(dev) && has_reduced_clock)
  3352. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3353. }
  3354. switch (clock.p2) {
  3355. case 5:
  3356. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3357. break;
  3358. case 7:
  3359. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3360. break;
  3361. case 10:
  3362. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3363. break;
  3364. case 14:
  3365. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3366. break;
  3367. }
  3368. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
  3369. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3370. } else {
  3371. if (is_lvds) {
  3372. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3373. } else {
  3374. if (clock.p1 == 2)
  3375. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3376. else
  3377. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3378. if (clock.p2 == 4)
  3379. dpll |= PLL_P2_DIVIDE_BY_4;
  3380. }
  3381. }
  3382. if (is_sdvo && is_tv)
  3383. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3384. else if (is_tv)
  3385. /* XXX: just matching BIOS for now */
  3386. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3387. dpll |= 3;
  3388. else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
  3389. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3390. else
  3391. dpll |= PLL_REF_INPUT_DREFCLK;
  3392. /* setup pipeconf */
  3393. pipeconf = I915_READ(PIPECONF(pipe));
  3394. /* Set up the display plane register */
  3395. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3396. /* Ironlake's plane is forced to pipe, bit 24 is to
  3397. enable color space conversion */
  3398. if (!HAS_PCH_SPLIT(dev)) {
  3399. if (pipe == 0)
  3400. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3401. else
  3402. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3403. }
  3404. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  3405. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3406. * core speed.
  3407. *
  3408. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3409. * pipe == 0 check?
  3410. */
  3411. if (mode->clock >
  3412. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3413. pipeconf |= PIPECONF_DOUBLE_WIDE;
  3414. else
  3415. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  3416. }
  3417. dspcntr |= DISPLAY_PLANE_ENABLE;
  3418. pipeconf |= PIPECONF_ENABLE;
  3419. dpll |= DPLL_VCO_ENABLE;
  3420. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3421. drm_mode_debug_printmodeline(mode);
  3422. /* assign to Ironlake registers */
  3423. if (HAS_PCH_SPLIT(dev)) {
  3424. fp_reg = PCH_FP0(pipe);
  3425. dpll_reg = PCH_DPLL(pipe);
  3426. } else {
  3427. fp_reg = FP0(pipe);
  3428. dpll_reg = DPLL(pipe);
  3429. }
  3430. if (!has_edp_encoder) {
  3431. I915_WRITE(fp_reg, fp);
  3432. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  3433. POSTING_READ(dpll_reg);
  3434. udelay(150);
  3435. }
  3436. /* enable transcoder DPLL */
  3437. if (HAS_PCH_CPT(dev)) {
  3438. temp = I915_READ(PCH_DPLL_SEL);
  3439. if (pipe == 0)
  3440. temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
  3441. else
  3442. temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
  3443. I915_WRITE(PCH_DPLL_SEL, temp);
  3444. POSTING_READ(PCH_DPLL_SEL);
  3445. udelay(150);
  3446. }
  3447. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3448. * This is an exception to the general rule that mode_set doesn't turn
  3449. * things on.
  3450. */
  3451. if (is_lvds) {
  3452. reg = LVDS;
  3453. if (HAS_PCH_SPLIT(dev))
  3454. reg = PCH_LVDS;
  3455. temp = I915_READ(reg);
  3456. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3457. if (pipe == 1) {
  3458. if (HAS_PCH_CPT(dev))
  3459. temp |= PORT_TRANS_B_SEL_CPT;
  3460. else
  3461. temp |= LVDS_PIPEB_SELECT;
  3462. } else {
  3463. if (HAS_PCH_CPT(dev))
  3464. temp &= ~PORT_TRANS_SEL_MASK;
  3465. else
  3466. temp &= ~LVDS_PIPEB_SELECT;
  3467. }
  3468. /* set the corresponsding LVDS_BORDER bit */
  3469. temp |= dev_priv->lvds_border_bits;
  3470. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3471. * set the DPLLs for dual-channel mode or not.
  3472. */
  3473. if (clock.p2 == 7)
  3474. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3475. else
  3476. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3477. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3478. * appropriately here, but we need to look more thoroughly into how
  3479. * panels behave in the two modes.
  3480. */
  3481. /* set the dithering flag on non-PCH LVDS as needed */
  3482. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  3483. if (dev_priv->lvds_dither)
  3484. temp |= LVDS_ENABLE_DITHER;
  3485. else
  3486. temp &= ~LVDS_ENABLE_DITHER;
  3487. }
  3488. I915_WRITE(reg, temp);
  3489. }
  3490. /* set the dithering flag and clear for anything other than a panel. */
  3491. if (HAS_PCH_SPLIT(dev)) {
  3492. pipeconf &= ~PIPECONF_DITHER_EN;
  3493. pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
  3494. if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
  3495. pipeconf |= PIPECONF_DITHER_EN;
  3496. pipeconf |= PIPECONF_DITHER_TYPE_ST1;
  3497. }
  3498. }
  3499. if (is_dp)
  3500. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3501. else if (HAS_PCH_SPLIT(dev)) {
  3502. /* For non-DP output, clear any trans DP clock recovery setting.*/
  3503. if (pipe == 0) {
  3504. I915_WRITE(TRANSA_DATA_M1, 0);
  3505. I915_WRITE(TRANSA_DATA_N1, 0);
  3506. I915_WRITE(TRANSA_DP_LINK_M1, 0);
  3507. I915_WRITE(TRANSA_DP_LINK_N1, 0);
  3508. } else {
  3509. I915_WRITE(TRANSB_DATA_M1, 0);
  3510. I915_WRITE(TRANSB_DATA_N1, 0);
  3511. I915_WRITE(TRANSB_DP_LINK_M1, 0);
  3512. I915_WRITE(TRANSB_DP_LINK_N1, 0);
  3513. }
  3514. }
  3515. if (!has_edp_encoder) {
  3516. I915_WRITE(fp_reg, fp);
  3517. I915_WRITE(dpll_reg, dpll);
  3518. /* Wait for the clocks to stabilize. */
  3519. POSTING_READ(dpll_reg);
  3520. udelay(150);
  3521. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  3522. temp = 0;
  3523. if (is_sdvo) {
  3524. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3525. if (temp > 1)
  3526. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3527. else
  3528. temp = 0;
  3529. }
  3530. I915_WRITE(DPLL_MD(pipe), temp);
  3531. } else {
  3532. /* write it again -- the BIOS does, after all */
  3533. I915_WRITE(dpll_reg, dpll);
  3534. }
  3535. /* Wait for the clocks to stabilize. */
  3536. POSTING_READ(dpll_reg);
  3537. udelay(150);
  3538. }
  3539. intel_crtc->lowfreq_avail = false;
  3540. if (is_lvds && has_reduced_clock && i915_powersave) {
  3541. I915_WRITE(fp_reg + 4, fp2);
  3542. intel_crtc->lowfreq_avail = true;
  3543. if (HAS_PIPE_CXSR(dev)) {
  3544. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3545. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3546. }
  3547. } else {
  3548. I915_WRITE(fp_reg + 4, fp);
  3549. if (HAS_PIPE_CXSR(dev)) {
  3550. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3551. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3552. }
  3553. }
  3554. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3555. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  3556. /* the chip adds 2 halflines automatically */
  3557. adjusted_mode->crtc_vdisplay -= 1;
  3558. adjusted_mode->crtc_vtotal -= 1;
  3559. adjusted_mode->crtc_vblank_start -= 1;
  3560. adjusted_mode->crtc_vblank_end -= 1;
  3561. adjusted_mode->crtc_vsync_end -= 1;
  3562. adjusted_mode->crtc_vsync_start -= 1;
  3563. } else
  3564. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  3565. I915_WRITE(HTOTAL(pipe),
  3566. (adjusted_mode->crtc_hdisplay - 1) |
  3567. ((adjusted_mode->crtc_htotal - 1) << 16));
  3568. I915_WRITE(HBLANK(pipe),
  3569. (adjusted_mode->crtc_hblank_start - 1) |
  3570. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3571. I915_WRITE(HSYNC(pipe),
  3572. (adjusted_mode->crtc_hsync_start - 1) |
  3573. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3574. I915_WRITE(VTOTAL(pipe),
  3575. (adjusted_mode->crtc_vdisplay - 1) |
  3576. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3577. I915_WRITE(VBLANK(pipe),
  3578. (adjusted_mode->crtc_vblank_start - 1) |
  3579. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3580. I915_WRITE(VSYNC(pipe),
  3581. (adjusted_mode->crtc_vsync_start - 1) |
  3582. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3583. /* pipesrc and dspsize control the size that is scaled from,
  3584. * which should always be the user's requested size.
  3585. */
  3586. if (!HAS_PCH_SPLIT(dev)) {
  3587. I915_WRITE(DSPSIZE(plane),
  3588. ((mode->vdisplay - 1) << 16) |
  3589. (mode->hdisplay - 1));
  3590. I915_WRITE(DSPPOS(plane), 0);
  3591. }
  3592. I915_WRITE(PIPESRC(pipe),
  3593. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3594. if (HAS_PCH_SPLIT(dev)) {
  3595. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  3596. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  3597. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  3598. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  3599. if (has_edp_encoder) {
  3600. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  3601. } else {
  3602. /* enable FDI RX PLL too */
  3603. reg = FDI_RX_CTL(pipe);
  3604. temp = I915_READ(reg);
  3605. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  3606. POSTING_READ(reg);
  3607. udelay(200);
  3608. /* enable FDI TX PLL too */
  3609. reg = FDI_TX_CTL(pipe);
  3610. temp = I915_READ(reg);
  3611. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  3612. /* enable FDI RX PCDCLK */
  3613. reg = FDI_RX_CTL(pipe);
  3614. temp = I915_READ(reg);
  3615. I915_WRITE(reg, temp | FDI_PCDCLK);
  3616. POSTING_READ(reg);
  3617. udelay(200);
  3618. }
  3619. }
  3620. I915_WRITE(PIPECONF(pipe), pipeconf);
  3621. POSTING_READ(PIPECONF(pipe));
  3622. intel_wait_for_vblank(dev, pipe);
  3623. if (IS_IRONLAKE(dev)) {
  3624. /* enable address swizzle for tiling buffer */
  3625. temp = I915_READ(DISP_ARB_CTL);
  3626. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  3627. }
  3628. I915_WRITE(DSPCNTR(plane), dspcntr);
  3629. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  3630. intel_update_watermarks(dev);
  3631. drm_vblank_post_modeset(dev, pipe);
  3632. return ret;
  3633. }
  3634. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  3635. void intel_crtc_load_lut(struct drm_crtc *crtc)
  3636. {
  3637. struct drm_device *dev = crtc->dev;
  3638. struct drm_i915_private *dev_priv = dev->dev_private;
  3639. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3640. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  3641. int i;
  3642. /* The clocks have to be on to load the palette. */
  3643. if (!crtc->enabled)
  3644. return;
  3645. /* use legacy palette for Ironlake */
  3646. if (HAS_PCH_SPLIT(dev))
  3647. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  3648. LGC_PALETTE_B;
  3649. for (i = 0; i < 256; i++) {
  3650. I915_WRITE(palreg + 4 * i,
  3651. (intel_crtc->lut_r[i] << 16) |
  3652. (intel_crtc->lut_g[i] << 8) |
  3653. intel_crtc->lut_b[i]);
  3654. }
  3655. }
  3656. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  3657. {
  3658. struct drm_device *dev = crtc->dev;
  3659. struct drm_i915_private *dev_priv = dev->dev_private;
  3660. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3661. bool visible = base != 0;
  3662. u32 cntl;
  3663. if (intel_crtc->cursor_visible == visible)
  3664. return;
  3665. cntl = I915_READ(CURACNTR);
  3666. if (visible) {
  3667. /* On these chipsets we can only modify the base whilst
  3668. * the cursor is disabled.
  3669. */
  3670. I915_WRITE(CURABASE, base);
  3671. cntl &= ~(CURSOR_FORMAT_MASK);
  3672. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  3673. cntl |= CURSOR_ENABLE |
  3674. CURSOR_GAMMA_ENABLE |
  3675. CURSOR_FORMAT_ARGB;
  3676. } else
  3677. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  3678. I915_WRITE(CURACNTR, cntl);
  3679. intel_crtc->cursor_visible = visible;
  3680. }
  3681. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  3682. {
  3683. struct drm_device *dev = crtc->dev;
  3684. struct drm_i915_private *dev_priv = dev->dev_private;
  3685. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3686. int pipe = intel_crtc->pipe;
  3687. bool visible = base != 0;
  3688. if (intel_crtc->cursor_visible != visible) {
  3689. uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
  3690. if (base) {
  3691. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  3692. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  3693. cntl |= pipe << 28; /* Connect to correct pipe */
  3694. } else {
  3695. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  3696. cntl |= CURSOR_MODE_DISABLE;
  3697. }
  3698. I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
  3699. intel_crtc->cursor_visible = visible;
  3700. }
  3701. /* and commit changes on next vblank */
  3702. I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
  3703. }
  3704. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  3705. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  3706. bool on)
  3707. {
  3708. struct drm_device *dev = crtc->dev;
  3709. struct drm_i915_private *dev_priv = dev->dev_private;
  3710. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3711. int pipe = intel_crtc->pipe;
  3712. int x = intel_crtc->cursor_x;
  3713. int y = intel_crtc->cursor_y;
  3714. u32 base, pos;
  3715. bool visible;
  3716. pos = 0;
  3717. if (on && crtc->enabled && crtc->fb) {
  3718. base = intel_crtc->cursor_addr;
  3719. if (x > (int) crtc->fb->width)
  3720. base = 0;
  3721. if (y > (int) crtc->fb->height)
  3722. base = 0;
  3723. } else
  3724. base = 0;
  3725. if (x < 0) {
  3726. if (x + intel_crtc->cursor_width < 0)
  3727. base = 0;
  3728. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  3729. x = -x;
  3730. }
  3731. pos |= x << CURSOR_X_SHIFT;
  3732. if (y < 0) {
  3733. if (y + intel_crtc->cursor_height < 0)
  3734. base = 0;
  3735. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  3736. y = -y;
  3737. }
  3738. pos |= y << CURSOR_Y_SHIFT;
  3739. visible = base != 0;
  3740. if (!visible && !intel_crtc->cursor_visible)
  3741. return;
  3742. I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
  3743. if (IS_845G(dev) || IS_I865G(dev))
  3744. i845_update_cursor(crtc, base);
  3745. else
  3746. i9xx_update_cursor(crtc, base);
  3747. if (visible)
  3748. intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
  3749. }
  3750. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  3751. struct drm_file *file_priv,
  3752. uint32_t handle,
  3753. uint32_t width, uint32_t height)
  3754. {
  3755. struct drm_device *dev = crtc->dev;
  3756. struct drm_i915_private *dev_priv = dev->dev_private;
  3757. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3758. struct drm_gem_object *bo;
  3759. struct drm_i915_gem_object *obj_priv;
  3760. uint32_t addr;
  3761. int ret;
  3762. DRM_DEBUG_KMS("\n");
  3763. /* if we want to turn off the cursor ignore width and height */
  3764. if (!handle) {
  3765. DRM_DEBUG_KMS("cursor off\n");
  3766. addr = 0;
  3767. bo = NULL;
  3768. mutex_lock(&dev->struct_mutex);
  3769. goto finish;
  3770. }
  3771. /* Currently we only support 64x64 cursors */
  3772. if (width != 64 || height != 64) {
  3773. DRM_ERROR("we currently only support 64x64 cursors\n");
  3774. return -EINVAL;
  3775. }
  3776. bo = drm_gem_object_lookup(dev, file_priv, handle);
  3777. if (!bo)
  3778. return -ENOENT;
  3779. obj_priv = to_intel_bo(bo);
  3780. if (bo->size < width * height * 4) {
  3781. DRM_ERROR("buffer is to small\n");
  3782. ret = -ENOMEM;
  3783. goto fail;
  3784. }
  3785. /* we only need to pin inside GTT if cursor is non-phy */
  3786. mutex_lock(&dev->struct_mutex);
  3787. if (!dev_priv->info->cursor_needs_physical) {
  3788. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  3789. if (ret) {
  3790. DRM_ERROR("failed to pin cursor bo\n");
  3791. goto fail_locked;
  3792. }
  3793. ret = i915_gem_object_set_to_gtt_domain(bo, 0);
  3794. if (ret) {
  3795. DRM_ERROR("failed to move cursor bo into the GTT\n");
  3796. goto fail_unpin;
  3797. }
  3798. addr = obj_priv->gtt_offset;
  3799. } else {
  3800. int align = IS_I830(dev) ? 16 * 1024 : 256;
  3801. ret = i915_gem_attach_phys_object(dev, bo,
  3802. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  3803. align);
  3804. if (ret) {
  3805. DRM_ERROR("failed to attach phys object\n");
  3806. goto fail_locked;
  3807. }
  3808. addr = obj_priv->phys_obj->handle->busaddr;
  3809. }
  3810. if (IS_GEN2(dev))
  3811. I915_WRITE(CURSIZE, (height << 12) | width);
  3812. finish:
  3813. if (intel_crtc->cursor_bo) {
  3814. if (dev_priv->info->cursor_needs_physical) {
  3815. if (intel_crtc->cursor_bo != bo)
  3816. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  3817. } else
  3818. i915_gem_object_unpin(intel_crtc->cursor_bo);
  3819. drm_gem_object_unreference(intel_crtc->cursor_bo);
  3820. }
  3821. mutex_unlock(&dev->struct_mutex);
  3822. intel_crtc->cursor_addr = addr;
  3823. intel_crtc->cursor_bo = bo;
  3824. intel_crtc->cursor_width = width;
  3825. intel_crtc->cursor_height = height;
  3826. intel_crtc_update_cursor(crtc, true);
  3827. return 0;
  3828. fail_unpin:
  3829. i915_gem_object_unpin(bo);
  3830. fail_locked:
  3831. mutex_unlock(&dev->struct_mutex);
  3832. fail:
  3833. drm_gem_object_unreference_unlocked(bo);
  3834. return ret;
  3835. }
  3836. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  3837. {
  3838. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3839. intel_crtc->cursor_x = x;
  3840. intel_crtc->cursor_y = y;
  3841. intel_crtc_update_cursor(crtc, true);
  3842. return 0;
  3843. }
  3844. /** Sets the color ramps on behalf of RandR */
  3845. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  3846. u16 blue, int regno)
  3847. {
  3848. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3849. intel_crtc->lut_r[regno] = red >> 8;
  3850. intel_crtc->lut_g[regno] = green >> 8;
  3851. intel_crtc->lut_b[regno] = blue >> 8;
  3852. }
  3853. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  3854. u16 *blue, int regno)
  3855. {
  3856. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3857. *red = intel_crtc->lut_r[regno] << 8;
  3858. *green = intel_crtc->lut_g[regno] << 8;
  3859. *blue = intel_crtc->lut_b[regno] << 8;
  3860. }
  3861. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  3862. u16 *blue, uint32_t start, uint32_t size)
  3863. {
  3864. int end = (start + size > 256) ? 256 : start + size, i;
  3865. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3866. for (i = start; i < end; i++) {
  3867. intel_crtc->lut_r[i] = red[i] >> 8;
  3868. intel_crtc->lut_g[i] = green[i] >> 8;
  3869. intel_crtc->lut_b[i] = blue[i] >> 8;
  3870. }
  3871. intel_crtc_load_lut(crtc);
  3872. }
  3873. /**
  3874. * Get a pipe with a simple mode set on it for doing load-based monitor
  3875. * detection.
  3876. *
  3877. * It will be up to the load-detect code to adjust the pipe as appropriate for
  3878. * its requirements. The pipe will be connected to no other encoders.
  3879. *
  3880. * Currently this code will only succeed if there is a pipe with no encoders
  3881. * configured for it. In the future, it could choose to temporarily disable
  3882. * some outputs to free up a pipe for its use.
  3883. *
  3884. * \return crtc, or NULL if no pipes are available.
  3885. */
  3886. /* VESA 640x480x72Hz mode to set on the pipe */
  3887. static struct drm_display_mode load_detect_mode = {
  3888. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  3889. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  3890. };
  3891. struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  3892. struct drm_connector *connector,
  3893. struct drm_display_mode *mode,
  3894. int *dpms_mode)
  3895. {
  3896. struct intel_crtc *intel_crtc;
  3897. struct drm_crtc *possible_crtc;
  3898. struct drm_crtc *supported_crtc =NULL;
  3899. struct drm_encoder *encoder = &intel_encoder->base;
  3900. struct drm_crtc *crtc = NULL;
  3901. struct drm_device *dev = encoder->dev;
  3902. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3903. struct drm_crtc_helper_funcs *crtc_funcs;
  3904. int i = -1;
  3905. /*
  3906. * Algorithm gets a little messy:
  3907. * - if the connector already has an assigned crtc, use it (but make
  3908. * sure it's on first)
  3909. * - try to find the first unused crtc that can drive this connector,
  3910. * and use that if we find one
  3911. * - if there are no unused crtcs available, try to use the first
  3912. * one we found that supports the connector
  3913. */
  3914. /* See if we already have a CRTC for this connector */
  3915. if (encoder->crtc) {
  3916. crtc = encoder->crtc;
  3917. /* Make sure the crtc and connector are running */
  3918. intel_crtc = to_intel_crtc(crtc);
  3919. *dpms_mode = intel_crtc->dpms_mode;
  3920. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3921. crtc_funcs = crtc->helper_private;
  3922. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3923. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3924. }
  3925. return crtc;
  3926. }
  3927. /* Find an unused one (if possible) */
  3928. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3929. i++;
  3930. if (!(encoder->possible_crtcs & (1 << i)))
  3931. continue;
  3932. if (!possible_crtc->enabled) {
  3933. crtc = possible_crtc;
  3934. break;
  3935. }
  3936. if (!supported_crtc)
  3937. supported_crtc = possible_crtc;
  3938. }
  3939. /*
  3940. * If we didn't find an unused CRTC, don't use any.
  3941. */
  3942. if (!crtc) {
  3943. return NULL;
  3944. }
  3945. encoder->crtc = crtc;
  3946. connector->encoder = encoder;
  3947. intel_encoder->load_detect_temp = true;
  3948. intel_crtc = to_intel_crtc(crtc);
  3949. *dpms_mode = intel_crtc->dpms_mode;
  3950. if (!crtc->enabled) {
  3951. if (!mode)
  3952. mode = &load_detect_mode;
  3953. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  3954. } else {
  3955. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3956. crtc_funcs = crtc->helper_private;
  3957. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3958. }
  3959. /* Add this connector to the crtc */
  3960. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  3961. encoder_funcs->commit(encoder);
  3962. }
  3963. /* let the connector get through one full cycle before testing */
  3964. intel_wait_for_vblank(dev, intel_crtc->pipe);
  3965. return crtc;
  3966. }
  3967. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  3968. struct drm_connector *connector, int dpms_mode)
  3969. {
  3970. struct drm_encoder *encoder = &intel_encoder->base;
  3971. struct drm_device *dev = encoder->dev;
  3972. struct drm_crtc *crtc = encoder->crtc;
  3973. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3974. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  3975. if (intel_encoder->load_detect_temp) {
  3976. encoder->crtc = NULL;
  3977. connector->encoder = NULL;
  3978. intel_encoder->load_detect_temp = false;
  3979. crtc->enabled = drm_helper_crtc_in_use(crtc);
  3980. drm_helper_disable_unused_functions(dev);
  3981. }
  3982. /* Switch crtc and encoder back off if necessary */
  3983. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  3984. if (encoder->crtc == crtc)
  3985. encoder_funcs->dpms(encoder, dpms_mode);
  3986. crtc_funcs->dpms(crtc, dpms_mode);
  3987. }
  3988. }
  3989. /* Returns the clock of the currently programmed mode of the given pipe. */
  3990. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  3991. {
  3992. struct drm_i915_private *dev_priv = dev->dev_private;
  3993. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3994. int pipe = intel_crtc->pipe;
  3995. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  3996. u32 fp;
  3997. intel_clock_t clock;
  3998. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  3999. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  4000. else
  4001. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  4002. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  4003. if (IS_PINEVIEW(dev)) {
  4004. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  4005. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  4006. } else {
  4007. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  4008. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  4009. }
  4010. if (!IS_GEN2(dev)) {
  4011. if (IS_PINEVIEW(dev))
  4012. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  4013. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  4014. else
  4015. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  4016. DPLL_FPA01_P1_POST_DIV_SHIFT);
  4017. switch (dpll & DPLL_MODE_MASK) {
  4018. case DPLLB_MODE_DAC_SERIAL:
  4019. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  4020. 5 : 10;
  4021. break;
  4022. case DPLLB_MODE_LVDS:
  4023. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  4024. 7 : 14;
  4025. break;
  4026. default:
  4027. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  4028. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  4029. return 0;
  4030. }
  4031. /* XXX: Handle the 100Mhz refclk */
  4032. intel_clock(dev, 96000, &clock);
  4033. } else {
  4034. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  4035. if (is_lvds) {
  4036. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  4037. DPLL_FPA01_P1_POST_DIV_SHIFT);
  4038. clock.p2 = 14;
  4039. if ((dpll & PLL_REF_INPUT_MASK) ==
  4040. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  4041. /* XXX: might not be 66MHz */
  4042. intel_clock(dev, 66000, &clock);
  4043. } else
  4044. intel_clock(dev, 48000, &clock);
  4045. } else {
  4046. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  4047. clock.p1 = 2;
  4048. else {
  4049. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  4050. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  4051. }
  4052. if (dpll & PLL_P2_DIVIDE_BY_4)
  4053. clock.p2 = 4;
  4054. else
  4055. clock.p2 = 2;
  4056. intel_clock(dev, 48000, &clock);
  4057. }
  4058. }
  4059. /* XXX: It would be nice to validate the clocks, but we can't reuse
  4060. * i830PllIsValid() because it relies on the xf86_config connector
  4061. * configuration being accurate, which it isn't necessarily.
  4062. */
  4063. return clock.dot;
  4064. }
  4065. /** Returns the currently programmed mode of the given pipe. */
  4066. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  4067. struct drm_crtc *crtc)
  4068. {
  4069. struct drm_i915_private *dev_priv = dev->dev_private;
  4070. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4071. int pipe = intel_crtc->pipe;
  4072. struct drm_display_mode *mode;
  4073. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  4074. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  4075. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  4076. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  4077. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  4078. if (!mode)
  4079. return NULL;
  4080. mode->clock = intel_crtc_clock_get(dev, crtc);
  4081. mode->hdisplay = (htot & 0xffff) + 1;
  4082. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  4083. mode->hsync_start = (hsync & 0xffff) + 1;
  4084. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  4085. mode->vdisplay = (vtot & 0xffff) + 1;
  4086. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  4087. mode->vsync_start = (vsync & 0xffff) + 1;
  4088. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  4089. drm_mode_set_name(mode);
  4090. drm_mode_set_crtcinfo(mode, 0);
  4091. return mode;
  4092. }
  4093. #define GPU_IDLE_TIMEOUT 500 /* ms */
  4094. /* When this timer fires, we've been idle for awhile */
  4095. static void intel_gpu_idle_timer(unsigned long arg)
  4096. {
  4097. struct drm_device *dev = (struct drm_device *)arg;
  4098. drm_i915_private_t *dev_priv = dev->dev_private;
  4099. dev_priv->busy = false;
  4100. queue_work(dev_priv->wq, &dev_priv->idle_work);
  4101. }
  4102. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  4103. static void intel_crtc_idle_timer(unsigned long arg)
  4104. {
  4105. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  4106. struct drm_crtc *crtc = &intel_crtc->base;
  4107. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  4108. intel_crtc->busy = false;
  4109. queue_work(dev_priv->wq, &dev_priv->idle_work);
  4110. }
  4111. static void intel_increase_pllclock(struct drm_crtc *crtc)
  4112. {
  4113. struct drm_device *dev = crtc->dev;
  4114. drm_i915_private_t *dev_priv = dev->dev_private;
  4115. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4116. int pipe = intel_crtc->pipe;
  4117. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  4118. int dpll = I915_READ(dpll_reg);
  4119. if (HAS_PCH_SPLIT(dev))
  4120. return;
  4121. if (!dev_priv->lvds_downclock_avail)
  4122. return;
  4123. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  4124. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  4125. /* Unlock panel regs */
  4126. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  4127. PANEL_UNLOCK_REGS);
  4128. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  4129. I915_WRITE(dpll_reg, dpll);
  4130. dpll = I915_READ(dpll_reg);
  4131. intel_wait_for_vblank(dev, pipe);
  4132. dpll = I915_READ(dpll_reg);
  4133. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  4134. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  4135. /* ...and lock them again */
  4136. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  4137. }
  4138. /* Schedule downclock */
  4139. mod_timer(&intel_crtc->idle_timer, jiffies +
  4140. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  4141. }
  4142. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  4143. {
  4144. struct drm_device *dev = crtc->dev;
  4145. drm_i915_private_t *dev_priv = dev->dev_private;
  4146. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4147. int pipe = intel_crtc->pipe;
  4148. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  4149. int dpll = I915_READ(dpll_reg);
  4150. if (HAS_PCH_SPLIT(dev))
  4151. return;
  4152. if (!dev_priv->lvds_downclock_avail)
  4153. return;
  4154. /*
  4155. * Since this is called by a timer, we should never get here in
  4156. * the manual case.
  4157. */
  4158. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  4159. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  4160. /* Unlock panel regs */
  4161. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  4162. PANEL_UNLOCK_REGS);
  4163. dpll |= DISPLAY_RATE_SELECT_FPA1;
  4164. I915_WRITE(dpll_reg, dpll);
  4165. dpll = I915_READ(dpll_reg);
  4166. intel_wait_for_vblank(dev, pipe);
  4167. dpll = I915_READ(dpll_reg);
  4168. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  4169. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  4170. /* ...and lock them again */
  4171. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  4172. }
  4173. }
  4174. /**
  4175. * intel_idle_update - adjust clocks for idleness
  4176. * @work: work struct
  4177. *
  4178. * Either the GPU or display (or both) went idle. Check the busy status
  4179. * here and adjust the CRTC and GPU clocks as necessary.
  4180. */
  4181. static void intel_idle_update(struct work_struct *work)
  4182. {
  4183. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  4184. idle_work);
  4185. struct drm_device *dev = dev_priv->dev;
  4186. struct drm_crtc *crtc;
  4187. struct intel_crtc *intel_crtc;
  4188. int enabled = 0;
  4189. if (!i915_powersave)
  4190. return;
  4191. mutex_lock(&dev->struct_mutex);
  4192. i915_update_gfx_val(dev_priv);
  4193. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4194. /* Skip inactive CRTCs */
  4195. if (!crtc->fb)
  4196. continue;
  4197. enabled++;
  4198. intel_crtc = to_intel_crtc(crtc);
  4199. if (!intel_crtc->busy)
  4200. intel_decrease_pllclock(crtc);
  4201. }
  4202. if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
  4203. DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
  4204. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  4205. }
  4206. mutex_unlock(&dev->struct_mutex);
  4207. }
  4208. /**
  4209. * intel_mark_busy - mark the GPU and possibly the display busy
  4210. * @dev: drm device
  4211. * @obj: object we're operating on
  4212. *
  4213. * Callers can use this function to indicate that the GPU is busy processing
  4214. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  4215. * buffer), we'll also mark the display as busy, so we know to increase its
  4216. * clock frequency.
  4217. */
  4218. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  4219. {
  4220. drm_i915_private_t *dev_priv = dev->dev_private;
  4221. struct drm_crtc *crtc = NULL;
  4222. struct intel_framebuffer *intel_fb;
  4223. struct intel_crtc *intel_crtc;
  4224. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  4225. return;
  4226. if (!dev_priv->busy) {
  4227. if (IS_I945G(dev) || IS_I945GM(dev)) {
  4228. u32 fw_blc_self;
  4229. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  4230. fw_blc_self = I915_READ(FW_BLC_SELF);
  4231. fw_blc_self &= ~FW_BLC_SELF_EN;
  4232. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  4233. }
  4234. dev_priv->busy = true;
  4235. } else
  4236. mod_timer(&dev_priv->idle_timer, jiffies +
  4237. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  4238. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4239. if (!crtc->fb)
  4240. continue;
  4241. intel_crtc = to_intel_crtc(crtc);
  4242. intel_fb = to_intel_framebuffer(crtc->fb);
  4243. if (intel_fb->obj == obj) {
  4244. if (!intel_crtc->busy) {
  4245. if (IS_I945G(dev) || IS_I945GM(dev)) {
  4246. u32 fw_blc_self;
  4247. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  4248. fw_blc_self = I915_READ(FW_BLC_SELF);
  4249. fw_blc_self &= ~FW_BLC_SELF_EN;
  4250. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  4251. }
  4252. /* Non-busy -> busy, upclock */
  4253. intel_increase_pllclock(crtc);
  4254. intel_crtc->busy = true;
  4255. } else {
  4256. /* Busy -> busy, put off timer */
  4257. mod_timer(&intel_crtc->idle_timer, jiffies +
  4258. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  4259. }
  4260. }
  4261. }
  4262. }
  4263. static void intel_crtc_destroy(struct drm_crtc *crtc)
  4264. {
  4265. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4266. struct drm_device *dev = crtc->dev;
  4267. struct intel_unpin_work *work;
  4268. unsigned long flags;
  4269. spin_lock_irqsave(&dev->event_lock, flags);
  4270. work = intel_crtc->unpin_work;
  4271. intel_crtc->unpin_work = NULL;
  4272. spin_unlock_irqrestore(&dev->event_lock, flags);
  4273. if (work) {
  4274. cancel_work_sync(&work->work);
  4275. kfree(work);
  4276. }
  4277. drm_crtc_cleanup(crtc);
  4278. kfree(intel_crtc);
  4279. }
  4280. static void intel_unpin_work_fn(struct work_struct *__work)
  4281. {
  4282. struct intel_unpin_work *work =
  4283. container_of(__work, struct intel_unpin_work, work);
  4284. mutex_lock(&work->dev->struct_mutex);
  4285. i915_gem_object_unpin(work->old_fb_obj);
  4286. drm_gem_object_unreference(work->pending_flip_obj);
  4287. drm_gem_object_unreference(work->old_fb_obj);
  4288. mutex_unlock(&work->dev->struct_mutex);
  4289. kfree(work);
  4290. }
  4291. static void do_intel_finish_page_flip(struct drm_device *dev,
  4292. struct drm_crtc *crtc)
  4293. {
  4294. drm_i915_private_t *dev_priv = dev->dev_private;
  4295. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4296. struct intel_unpin_work *work;
  4297. struct drm_i915_gem_object *obj_priv;
  4298. struct drm_pending_vblank_event *e;
  4299. struct timeval now;
  4300. unsigned long flags;
  4301. /* Ignore early vblank irqs */
  4302. if (intel_crtc == NULL)
  4303. return;
  4304. spin_lock_irqsave(&dev->event_lock, flags);
  4305. work = intel_crtc->unpin_work;
  4306. if (work == NULL || !work->pending) {
  4307. spin_unlock_irqrestore(&dev->event_lock, flags);
  4308. return;
  4309. }
  4310. intel_crtc->unpin_work = NULL;
  4311. drm_vblank_put(dev, intel_crtc->pipe);
  4312. if (work->event) {
  4313. e = work->event;
  4314. do_gettimeofday(&now);
  4315. e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
  4316. e->event.tv_sec = now.tv_sec;
  4317. e->event.tv_usec = now.tv_usec;
  4318. list_add_tail(&e->base.link,
  4319. &e->base.file_priv->event_list);
  4320. wake_up_interruptible(&e->base.file_priv->event_wait);
  4321. }
  4322. spin_unlock_irqrestore(&dev->event_lock, flags);
  4323. obj_priv = to_intel_bo(work->pending_flip_obj);
  4324. /* Initial scanout buffer will have a 0 pending flip count */
  4325. if ((atomic_read(&obj_priv->pending_flip) == 0) ||
  4326. atomic_dec_and_test(&obj_priv->pending_flip))
  4327. wake_up(&dev_priv->pending_flip_queue);
  4328. schedule_work(&work->work);
  4329. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  4330. }
  4331. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  4332. {
  4333. drm_i915_private_t *dev_priv = dev->dev_private;
  4334. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  4335. do_intel_finish_page_flip(dev, crtc);
  4336. }
  4337. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  4338. {
  4339. drm_i915_private_t *dev_priv = dev->dev_private;
  4340. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  4341. do_intel_finish_page_flip(dev, crtc);
  4342. }
  4343. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  4344. {
  4345. drm_i915_private_t *dev_priv = dev->dev_private;
  4346. struct intel_crtc *intel_crtc =
  4347. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  4348. unsigned long flags;
  4349. spin_lock_irqsave(&dev->event_lock, flags);
  4350. if (intel_crtc->unpin_work) {
  4351. if ((++intel_crtc->unpin_work->pending) > 1)
  4352. DRM_ERROR("Prepared flip multiple times\n");
  4353. } else {
  4354. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  4355. }
  4356. spin_unlock_irqrestore(&dev->event_lock, flags);
  4357. }
  4358. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  4359. struct drm_framebuffer *fb,
  4360. struct drm_pending_vblank_event *event)
  4361. {
  4362. struct drm_device *dev = crtc->dev;
  4363. struct drm_i915_private *dev_priv = dev->dev_private;
  4364. struct intel_framebuffer *intel_fb;
  4365. struct drm_i915_gem_object *obj_priv;
  4366. struct drm_gem_object *obj;
  4367. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4368. struct intel_unpin_work *work;
  4369. unsigned long flags, offset;
  4370. int pipe = intel_crtc->pipe;
  4371. u32 pf, pipesrc;
  4372. int ret;
  4373. work = kzalloc(sizeof *work, GFP_KERNEL);
  4374. if (work == NULL)
  4375. return -ENOMEM;
  4376. work->event = event;
  4377. work->dev = crtc->dev;
  4378. intel_fb = to_intel_framebuffer(crtc->fb);
  4379. work->old_fb_obj = intel_fb->obj;
  4380. INIT_WORK(&work->work, intel_unpin_work_fn);
  4381. /* We borrow the event spin lock for protecting unpin_work */
  4382. spin_lock_irqsave(&dev->event_lock, flags);
  4383. if (intel_crtc->unpin_work) {
  4384. spin_unlock_irqrestore(&dev->event_lock, flags);
  4385. kfree(work);
  4386. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  4387. return -EBUSY;
  4388. }
  4389. intel_crtc->unpin_work = work;
  4390. spin_unlock_irqrestore(&dev->event_lock, flags);
  4391. intel_fb = to_intel_framebuffer(fb);
  4392. obj = intel_fb->obj;
  4393. mutex_lock(&dev->struct_mutex);
  4394. ret = intel_pin_and_fence_fb_obj(dev, obj, true);
  4395. if (ret)
  4396. goto cleanup_work;
  4397. /* Reference the objects for the scheduled work. */
  4398. drm_gem_object_reference(work->old_fb_obj);
  4399. drm_gem_object_reference(obj);
  4400. crtc->fb = fb;
  4401. ret = drm_vblank_get(dev, intel_crtc->pipe);
  4402. if (ret)
  4403. goto cleanup_objs;
  4404. obj_priv = to_intel_bo(obj);
  4405. atomic_inc(&obj_priv->pending_flip);
  4406. work->pending_flip_obj = obj;
  4407. if (IS_GEN3(dev) || IS_GEN2(dev)) {
  4408. u32 flip_mask;
  4409. /* Can't queue multiple flips, so wait for the previous
  4410. * one to finish before executing the next.
  4411. */
  4412. BEGIN_LP_RING(2);
  4413. if (intel_crtc->plane)
  4414. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  4415. else
  4416. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  4417. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  4418. OUT_RING(MI_NOOP);
  4419. ADVANCE_LP_RING();
  4420. }
  4421. work->enable_stall_check = true;
  4422. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  4423. offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
  4424. BEGIN_LP_RING(4);
  4425. switch(INTEL_INFO(dev)->gen) {
  4426. case 2:
  4427. OUT_RING(MI_DISPLAY_FLIP |
  4428. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4429. OUT_RING(fb->pitch);
  4430. OUT_RING(obj_priv->gtt_offset + offset);
  4431. OUT_RING(MI_NOOP);
  4432. break;
  4433. case 3:
  4434. OUT_RING(MI_DISPLAY_FLIP_I915 |
  4435. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4436. OUT_RING(fb->pitch);
  4437. OUT_RING(obj_priv->gtt_offset + offset);
  4438. OUT_RING(MI_NOOP);
  4439. break;
  4440. case 4:
  4441. case 5:
  4442. /* i965+ uses the linear or tiled offsets from the
  4443. * Display Registers (which do not change across a page-flip)
  4444. * so we need only reprogram the base address.
  4445. */
  4446. OUT_RING(MI_DISPLAY_FLIP |
  4447. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4448. OUT_RING(fb->pitch);
  4449. OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
  4450. /* XXX Enabling the panel-fitter across page-flip is so far
  4451. * untested on non-native modes, so ignore it for now.
  4452. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  4453. */
  4454. pf = 0;
  4455. pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
  4456. OUT_RING(pf | pipesrc);
  4457. break;
  4458. case 6:
  4459. OUT_RING(MI_DISPLAY_FLIP |
  4460. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4461. OUT_RING(fb->pitch | obj_priv->tiling_mode);
  4462. OUT_RING(obj_priv->gtt_offset);
  4463. pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  4464. pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
  4465. OUT_RING(pf | pipesrc);
  4466. break;
  4467. }
  4468. ADVANCE_LP_RING();
  4469. mutex_unlock(&dev->struct_mutex);
  4470. trace_i915_flip_request(intel_crtc->plane, obj);
  4471. return 0;
  4472. cleanup_objs:
  4473. drm_gem_object_unreference(work->old_fb_obj);
  4474. drm_gem_object_unreference(obj);
  4475. cleanup_work:
  4476. mutex_unlock(&dev->struct_mutex);
  4477. spin_lock_irqsave(&dev->event_lock, flags);
  4478. intel_crtc->unpin_work = NULL;
  4479. spin_unlock_irqrestore(&dev->event_lock, flags);
  4480. kfree(work);
  4481. return ret;
  4482. }
  4483. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  4484. .dpms = intel_crtc_dpms,
  4485. .mode_fixup = intel_crtc_mode_fixup,
  4486. .mode_set = intel_crtc_mode_set,
  4487. .mode_set_base = intel_pipe_set_base,
  4488. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  4489. .load_lut = intel_crtc_load_lut,
  4490. .disable = intel_crtc_disable,
  4491. };
  4492. static const struct drm_crtc_funcs intel_crtc_funcs = {
  4493. .cursor_set = intel_crtc_cursor_set,
  4494. .cursor_move = intel_crtc_cursor_move,
  4495. .gamma_set = intel_crtc_gamma_set,
  4496. .set_config = drm_crtc_helper_set_config,
  4497. .destroy = intel_crtc_destroy,
  4498. .page_flip = intel_crtc_page_flip,
  4499. };
  4500. static void intel_crtc_init(struct drm_device *dev, int pipe)
  4501. {
  4502. drm_i915_private_t *dev_priv = dev->dev_private;
  4503. struct intel_crtc *intel_crtc;
  4504. int i;
  4505. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  4506. if (intel_crtc == NULL)
  4507. return;
  4508. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  4509. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  4510. for (i = 0; i < 256; i++) {
  4511. intel_crtc->lut_r[i] = i;
  4512. intel_crtc->lut_g[i] = i;
  4513. intel_crtc->lut_b[i] = i;
  4514. }
  4515. /* Swap pipes & planes for FBC on pre-965 */
  4516. intel_crtc->pipe = pipe;
  4517. intel_crtc->plane = pipe;
  4518. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  4519. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  4520. intel_crtc->plane = !pipe;
  4521. }
  4522. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  4523. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  4524. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  4525. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  4526. intel_crtc->cursor_addr = 0;
  4527. intel_crtc->dpms_mode = -1;
  4528. intel_crtc->active = true; /* force the pipe off on setup_init_config */
  4529. if (HAS_PCH_SPLIT(dev)) {
  4530. intel_helper_funcs.prepare = ironlake_crtc_prepare;
  4531. intel_helper_funcs.commit = ironlake_crtc_commit;
  4532. } else {
  4533. intel_helper_funcs.prepare = i9xx_crtc_prepare;
  4534. intel_helper_funcs.commit = i9xx_crtc_commit;
  4535. }
  4536. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  4537. intel_crtc->busy = false;
  4538. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  4539. (unsigned long)intel_crtc);
  4540. }
  4541. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  4542. struct drm_file *file_priv)
  4543. {
  4544. drm_i915_private_t *dev_priv = dev->dev_private;
  4545. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  4546. struct drm_mode_object *drmmode_obj;
  4547. struct intel_crtc *crtc;
  4548. if (!dev_priv) {
  4549. DRM_ERROR("called with no initialization\n");
  4550. return -EINVAL;
  4551. }
  4552. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  4553. DRM_MODE_OBJECT_CRTC);
  4554. if (!drmmode_obj) {
  4555. DRM_ERROR("no such CRTC id\n");
  4556. return -EINVAL;
  4557. }
  4558. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  4559. pipe_from_crtc_id->pipe = crtc->pipe;
  4560. return 0;
  4561. }
  4562. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  4563. {
  4564. struct intel_encoder *encoder;
  4565. int index_mask = 0;
  4566. int entry = 0;
  4567. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  4568. if (type_mask & encoder->clone_mask)
  4569. index_mask |= (1 << entry);
  4570. entry++;
  4571. }
  4572. return index_mask;
  4573. }
  4574. static void intel_setup_outputs(struct drm_device *dev)
  4575. {
  4576. struct drm_i915_private *dev_priv = dev->dev_private;
  4577. struct intel_encoder *encoder;
  4578. bool dpd_is_edp = false;
  4579. if (IS_MOBILE(dev) && !IS_I830(dev))
  4580. intel_lvds_init(dev);
  4581. if (HAS_PCH_SPLIT(dev)) {
  4582. dpd_is_edp = intel_dpd_is_edp(dev);
  4583. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  4584. intel_dp_init(dev, DP_A);
  4585. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  4586. intel_dp_init(dev, PCH_DP_D);
  4587. }
  4588. intel_crt_init(dev);
  4589. if (HAS_PCH_SPLIT(dev)) {
  4590. int found;
  4591. if (I915_READ(HDMIB) & PORT_DETECTED) {
  4592. /* PCH SDVOB multiplex with HDMIB */
  4593. found = intel_sdvo_init(dev, PCH_SDVOB);
  4594. if (!found)
  4595. intel_hdmi_init(dev, HDMIB);
  4596. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  4597. intel_dp_init(dev, PCH_DP_B);
  4598. }
  4599. if (I915_READ(HDMIC) & PORT_DETECTED)
  4600. intel_hdmi_init(dev, HDMIC);
  4601. if (I915_READ(HDMID) & PORT_DETECTED)
  4602. intel_hdmi_init(dev, HDMID);
  4603. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  4604. intel_dp_init(dev, PCH_DP_C);
  4605. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  4606. intel_dp_init(dev, PCH_DP_D);
  4607. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  4608. bool found = false;
  4609. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4610. DRM_DEBUG_KMS("probing SDVOB\n");
  4611. found = intel_sdvo_init(dev, SDVOB);
  4612. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  4613. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  4614. intel_hdmi_init(dev, SDVOB);
  4615. }
  4616. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  4617. DRM_DEBUG_KMS("probing DP_B\n");
  4618. intel_dp_init(dev, DP_B);
  4619. }
  4620. }
  4621. /* Before G4X SDVOC doesn't have its own detect register */
  4622. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4623. DRM_DEBUG_KMS("probing SDVOC\n");
  4624. found = intel_sdvo_init(dev, SDVOC);
  4625. }
  4626. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  4627. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  4628. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  4629. intel_hdmi_init(dev, SDVOC);
  4630. }
  4631. if (SUPPORTS_INTEGRATED_DP(dev)) {
  4632. DRM_DEBUG_KMS("probing DP_C\n");
  4633. intel_dp_init(dev, DP_C);
  4634. }
  4635. }
  4636. if (SUPPORTS_INTEGRATED_DP(dev) &&
  4637. (I915_READ(DP_D) & DP_DETECTED)) {
  4638. DRM_DEBUG_KMS("probing DP_D\n");
  4639. intel_dp_init(dev, DP_D);
  4640. }
  4641. } else if (IS_GEN2(dev))
  4642. intel_dvo_init(dev);
  4643. if (SUPPORTS_TV(dev))
  4644. intel_tv_init(dev);
  4645. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  4646. encoder->base.possible_crtcs = encoder->crtc_mask;
  4647. encoder->base.possible_clones =
  4648. intel_encoder_clones(dev, encoder->clone_mask);
  4649. }
  4650. }
  4651. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  4652. {
  4653. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4654. drm_framebuffer_cleanup(fb);
  4655. drm_gem_object_unreference_unlocked(intel_fb->obj);
  4656. kfree(intel_fb);
  4657. }
  4658. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  4659. struct drm_file *file_priv,
  4660. unsigned int *handle)
  4661. {
  4662. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4663. struct drm_gem_object *object = intel_fb->obj;
  4664. return drm_gem_handle_create(file_priv, object, handle);
  4665. }
  4666. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  4667. .destroy = intel_user_framebuffer_destroy,
  4668. .create_handle = intel_user_framebuffer_create_handle,
  4669. };
  4670. int intel_framebuffer_init(struct drm_device *dev,
  4671. struct intel_framebuffer *intel_fb,
  4672. struct drm_mode_fb_cmd *mode_cmd,
  4673. struct drm_gem_object *obj)
  4674. {
  4675. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  4676. int ret;
  4677. if (obj_priv->tiling_mode == I915_TILING_Y)
  4678. return -EINVAL;
  4679. if (mode_cmd->pitch & 63)
  4680. return -EINVAL;
  4681. switch (mode_cmd->bpp) {
  4682. case 8:
  4683. case 16:
  4684. case 24:
  4685. case 32:
  4686. break;
  4687. default:
  4688. return -EINVAL;
  4689. }
  4690. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  4691. if (ret) {
  4692. DRM_ERROR("framebuffer init failed %d\n", ret);
  4693. return ret;
  4694. }
  4695. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  4696. intel_fb->obj = obj;
  4697. return 0;
  4698. }
  4699. static struct drm_framebuffer *
  4700. intel_user_framebuffer_create(struct drm_device *dev,
  4701. struct drm_file *filp,
  4702. struct drm_mode_fb_cmd *mode_cmd)
  4703. {
  4704. struct drm_gem_object *obj;
  4705. struct intel_framebuffer *intel_fb;
  4706. int ret;
  4707. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  4708. if (!obj)
  4709. return ERR_PTR(-ENOENT);
  4710. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4711. if (!intel_fb)
  4712. return ERR_PTR(-ENOMEM);
  4713. ret = intel_framebuffer_init(dev, intel_fb,
  4714. mode_cmd, obj);
  4715. if (ret) {
  4716. drm_gem_object_unreference_unlocked(obj);
  4717. kfree(intel_fb);
  4718. return ERR_PTR(ret);
  4719. }
  4720. return &intel_fb->base;
  4721. }
  4722. static const struct drm_mode_config_funcs intel_mode_funcs = {
  4723. .fb_create = intel_user_framebuffer_create,
  4724. .output_poll_changed = intel_fb_output_poll_changed,
  4725. };
  4726. static struct drm_gem_object *
  4727. intel_alloc_context_page(struct drm_device *dev)
  4728. {
  4729. struct drm_gem_object *ctx;
  4730. int ret;
  4731. ctx = i915_gem_alloc_object(dev, 4096);
  4732. if (!ctx) {
  4733. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  4734. return NULL;
  4735. }
  4736. mutex_lock(&dev->struct_mutex);
  4737. ret = i915_gem_object_pin(ctx, 4096);
  4738. if (ret) {
  4739. DRM_ERROR("failed to pin power context: %d\n", ret);
  4740. goto err_unref;
  4741. }
  4742. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  4743. if (ret) {
  4744. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  4745. goto err_unpin;
  4746. }
  4747. mutex_unlock(&dev->struct_mutex);
  4748. return ctx;
  4749. err_unpin:
  4750. i915_gem_object_unpin(ctx);
  4751. err_unref:
  4752. drm_gem_object_unreference(ctx);
  4753. mutex_unlock(&dev->struct_mutex);
  4754. return NULL;
  4755. }
  4756. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  4757. {
  4758. struct drm_i915_private *dev_priv = dev->dev_private;
  4759. u16 rgvswctl;
  4760. rgvswctl = I915_READ16(MEMSWCTL);
  4761. if (rgvswctl & MEMCTL_CMD_STS) {
  4762. DRM_DEBUG("gpu busy, RCS change rejected\n");
  4763. return false; /* still busy with another command */
  4764. }
  4765. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  4766. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  4767. I915_WRITE16(MEMSWCTL, rgvswctl);
  4768. POSTING_READ16(MEMSWCTL);
  4769. rgvswctl |= MEMCTL_CMD_STS;
  4770. I915_WRITE16(MEMSWCTL, rgvswctl);
  4771. return true;
  4772. }
  4773. void ironlake_enable_drps(struct drm_device *dev)
  4774. {
  4775. struct drm_i915_private *dev_priv = dev->dev_private;
  4776. u32 rgvmodectl = I915_READ(MEMMODECTL);
  4777. u8 fmax, fmin, fstart, vstart;
  4778. /* Enable temp reporting */
  4779. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  4780. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  4781. /* 100ms RC evaluation intervals */
  4782. I915_WRITE(RCUPEI, 100000);
  4783. I915_WRITE(RCDNEI, 100000);
  4784. /* Set max/min thresholds to 90ms and 80ms respectively */
  4785. I915_WRITE(RCBMAXAVG, 90000);
  4786. I915_WRITE(RCBMINAVG, 80000);
  4787. I915_WRITE(MEMIHYST, 1);
  4788. /* Set up min, max, and cur for interrupt handling */
  4789. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  4790. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  4791. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  4792. MEMMODE_FSTART_SHIFT;
  4793. fstart = fmax;
  4794. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  4795. PXVFREQ_PX_SHIFT;
  4796. dev_priv->fmax = fstart; /* IPS callback will increase this */
  4797. dev_priv->fstart = fstart;
  4798. dev_priv->max_delay = fmax;
  4799. dev_priv->min_delay = fmin;
  4800. dev_priv->cur_delay = fstart;
  4801. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
  4802. fstart);
  4803. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  4804. /*
  4805. * Interrupts will be enabled in ironlake_irq_postinstall
  4806. */
  4807. I915_WRITE(VIDSTART, vstart);
  4808. POSTING_READ(VIDSTART);
  4809. rgvmodectl |= MEMMODE_SWMODE_EN;
  4810. I915_WRITE(MEMMODECTL, rgvmodectl);
  4811. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  4812. DRM_ERROR("stuck trying to change perf mode\n");
  4813. msleep(1);
  4814. ironlake_set_drps(dev, fstart);
  4815. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  4816. I915_READ(0x112e0);
  4817. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  4818. dev_priv->last_count2 = I915_READ(0x112f4);
  4819. getrawmonotonic(&dev_priv->last_time2);
  4820. }
  4821. void ironlake_disable_drps(struct drm_device *dev)
  4822. {
  4823. struct drm_i915_private *dev_priv = dev->dev_private;
  4824. u16 rgvswctl = I915_READ16(MEMSWCTL);
  4825. /* Ack interrupts, disable EFC interrupt */
  4826. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  4827. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  4828. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  4829. I915_WRITE(DEIIR, DE_PCU_EVENT);
  4830. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  4831. /* Go back to the starting frequency */
  4832. ironlake_set_drps(dev, dev_priv->fstart);
  4833. msleep(1);
  4834. rgvswctl |= MEMCTL_CMD_STS;
  4835. I915_WRITE(MEMSWCTL, rgvswctl);
  4836. msleep(1);
  4837. }
  4838. static unsigned long intel_pxfreq(u32 vidfreq)
  4839. {
  4840. unsigned long freq;
  4841. int div = (vidfreq & 0x3f0000) >> 16;
  4842. int post = (vidfreq & 0x3000) >> 12;
  4843. int pre = (vidfreq & 0x7);
  4844. if (!pre)
  4845. return 0;
  4846. freq = ((div * 133333) / ((1<<post) * pre));
  4847. return freq;
  4848. }
  4849. void intel_init_emon(struct drm_device *dev)
  4850. {
  4851. struct drm_i915_private *dev_priv = dev->dev_private;
  4852. u32 lcfuse;
  4853. u8 pxw[16];
  4854. int i;
  4855. /* Disable to program */
  4856. I915_WRITE(ECR, 0);
  4857. POSTING_READ(ECR);
  4858. /* Program energy weights for various events */
  4859. I915_WRITE(SDEW, 0x15040d00);
  4860. I915_WRITE(CSIEW0, 0x007f0000);
  4861. I915_WRITE(CSIEW1, 0x1e220004);
  4862. I915_WRITE(CSIEW2, 0x04000004);
  4863. for (i = 0; i < 5; i++)
  4864. I915_WRITE(PEW + (i * 4), 0);
  4865. for (i = 0; i < 3; i++)
  4866. I915_WRITE(DEW + (i * 4), 0);
  4867. /* Program P-state weights to account for frequency power adjustment */
  4868. for (i = 0; i < 16; i++) {
  4869. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  4870. unsigned long freq = intel_pxfreq(pxvidfreq);
  4871. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  4872. PXVFREQ_PX_SHIFT;
  4873. unsigned long val;
  4874. val = vid * vid;
  4875. val *= (freq / 1000);
  4876. val *= 255;
  4877. val /= (127*127*900);
  4878. if (val > 0xff)
  4879. DRM_ERROR("bad pxval: %ld\n", val);
  4880. pxw[i] = val;
  4881. }
  4882. /* Render standby states get 0 weight */
  4883. pxw[14] = 0;
  4884. pxw[15] = 0;
  4885. for (i = 0; i < 4; i++) {
  4886. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  4887. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  4888. I915_WRITE(PXW + (i * 4), val);
  4889. }
  4890. /* Adjust magic regs to magic values (more experimental results) */
  4891. I915_WRITE(OGW0, 0);
  4892. I915_WRITE(OGW1, 0);
  4893. I915_WRITE(EG0, 0x00007f00);
  4894. I915_WRITE(EG1, 0x0000000e);
  4895. I915_WRITE(EG2, 0x000e0000);
  4896. I915_WRITE(EG3, 0x68000300);
  4897. I915_WRITE(EG4, 0x42000000);
  4898. I915_WRITE(EG5, 0x00140031);
  4899. I915_WRITE(EG6, 0);
  4900. I915_WRITE(EG7, 0);
  4901. for (i = 0; i < 8; i++)
  4902. I915_WRITE(PXWL + (i * 4), 0);
  4903. /* Enable PMON + select events */
  4904. I915_WRITE(ECR, 0x80000019);
  4905. lcfuse = I915_READ(LCFUSE02);
  4906. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  4907. }
  4908. void intel_init_clock_gating(struct drm_device *dev)
  4909. {
  4910. struct drm_i915_private *dev_priv = dev->dev_private;
  4911. /*
  4912. * Disable clock gating reported to work incorrectly according to the
  4913. * specs, but enable as much else as we can.
  4914. */
  4915. if (HAS_PCH_SPLIT(dev)) {
  4916. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  4917. if (IS_IRONLAKE(dev)) {
  4918. /* Required for FBC */
  4919. dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
  4920. /* Required for CxSR */
  4921. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  4922. I915_WRITE(PCH_3DCGDIS0,
  4923. MARIUNIT_CLOCK_GATE_DISABLE |
  4924. SVSMUNIT_CLOCK_GATE_DISABLE);
  4925. }
  4926. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  4927. /*
  4928. * According to the spec the following bits should be set in
  4929. * order to enable memory self-refresh
  4930. * The bit 22/21 of 0x42004
  4931. * The bit 5 of 0x42020
  4932. * The bit 15 of 0x45000
  4933. */
  4934. if (IS_IRONLAKE(dev)) {
  4935. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4936. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  4937. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  4938. I915_WRITE(ILK_DSPCLK_GATE,
  4939. (I915_READ(ILK_DSPCLK_GATE) |
  4940. ILK_DPARB_CLK_GATE));
  4941. I915_WRITE(DISP_ARB_CTL,
  4942. (I915_READ(DISP_ARB_CTL) |
  4943. DISP_FBC_WM_DIS));
  4944. I915_WRITE(WM3_LP_ILK, 0);
  4945. I915_WRITE(WM2_LP_ILK, 0);
  4946. I915_WRITE(WM1_LP_ILK, 0);
  4947. }
  4948. /*
  4949. * Based on the document from hardware guys the following bits
  4950. * should be set unconditionally in order to enable FBC.
  4951. * The bit 22 of 0x42000
  4952. * The bit 22 of 0x42004
  4953. * The bit 7,8,9 of 0x42020.
  4954. */
  4955. if (IS_IRONLAKE_M(dev)) {
  4956. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  4957. I915_READ(ILK_DISPLAY_CHICKEN1) |
  4958. ILK_FBCQ_DIS);
  4959. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4960. I915_READ(ILK_DISPLAY_CHICKEN2) |
  4961. ILK_DPARB_GATE);
  4962. I915_WRITE(ILK_DSPCLK_GATE,
  4963. I915_READ(ILK_DSPCLK_GATE) |
  4964. ILK_DPFC_DIS1 |
  4965. ILK_DPFC_DIS2 |
  4966. ILK_CLK_FBC);
  4967. }
  4968. return;
  4969. } else if (IS_G4X(dev)) {
  4970. uint32_t dspclk_gate;
  4971. I915_WRITE(RENCLK_GATE_D1, 0);
  4972. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  4973. GS_UNIT_CLOCK_GATE_DISABLE |
  4974. CL_UNIT_CLOCK_GATE_DISABLE);
  4975. I915_WRITE(RAMCLK_GATE_D, 0);
  4976. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  4977. OVRUNIT_CLOCK_GATE_DISABLE |
  4978. OVCUNIT_CLOCK_GATE_DISABLE;
  4979. if (IS_GM45(dev))
  4980. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  4981. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  4982. } else if (IS_CRESTLINE(dev)) {
  4983. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  4984. I915_WRITE(RENCLK_GATE_D2, 0);
  4985. I915_WRITE(DSPCLK_GATE_D, 0);
  4986. I915_WRITE(RAMCLK_GATE_D, 0);
  4987. I915_WRITE16(DEUC, 0);
  4988. } else if (IS_BROADWATER(dev)) {
  4989. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  4990. I965_RCC_CLOCK_GATE_DISABLE |
  4991. I965_RCPB_CLOCK_GATE_DISABLE |
  4992. I965_ISC_CLOCK_GATE_DISABLE |
  4993. I965_FBC_CLOCK_GATE_DISABLE);
  4994. I915_WRITE(RENCLK_GATE_D2, 0);
  4995. } else if (IS_GEN3(dev)) {
  4996. u32 dstate = I915_READ(D_STATE);
  4997. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  4998. DSTATE_DOT_CLOCK_GATING;
  4999. I915_WRITE(D_STATE, dstate);
  5000. } else if (IS_I85X(dev) || IS_I865G(dev)) {
  5001. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  5002. } else if (IS_I830(dev)) {
  5003. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  5004. }
  5005. /*
  5006. * GPU can automatically power down the render unit if given a page
  5007. * to save state.
  5008. */
  5009. if (IS_IRONLAKE_M(dev)) {
  5010. if (dev_priv->renderctx == NULL)
  5011. dev_priv->renderctx = intel_alloc_context_page(dev);
  5012. if (dev_priv->renderctx) {
  5013. struct drm_i915_gem_object *obj_priv;
  5014. obj_priv = to_intel_bo(dev_priv->renderctx);
  5015. if (obj_priv) {
  5016. BEGIN_LP_RING(4);
  5017. OUT_RING(MI_SET_CONTEXT);
  5018. OUT_RING(obj_priv->gtt_offset |
  5019. MI_MM_SPACE_GTT |
  5020. MI_SAVE_EXT_STATE_EN |
  5021. MI_RESTORE_EXT_STATE_EN |
  5022. MI_RESTORE_INHIBIT);
  5023. OUT_RING(MI_NOOP);
  5024. OUT_RING(MI_FLUSH);
  5025. ADVANCE_LP_RING();
  5026. }
  5027. } else
  5028. DRM_DEBUG_KMS("Failed to allocate render context."
  5029. "Disable RC6\n");
  5030. }
  5031. if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
  5032. struct drm_i915_gem_object *obj_priv = NULL;
  5033. if (dev_priv->pwrctx) {
  5034. obj_priv = to_intel_bo(dev_priv->pwrctx);
  5035. } else {
  5036. struct drm_gem_object *pwrctx;
  5037. pwrctx = intel_alloc_context_page(dev);
  5038. if (pwrctx) {
  5039. dev_priv->pwrctx = pwrctx;
  5040. obj_priv = to_intel_bo(pwrctx);
  5041. }
  5042. }
  5043. if (obj_priv) {
  5044. I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
  5045. I915_WRITE(MCHBAR_RENDER_STANDBY,
  5046. I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
  5047. }
  5048. }
  5049. }
  5050. /* Set up chip specific display functions */
  5051. static void intel_init_display(struct drm_device *dev)
  5052. {
  5053. struct drm_i915_private *dev_priv = dev->dev_private;
  5054. /* We always want a DPMS function */
  5055. if (HAS_PCH_SPLIT(dev))
  5056. dev_priv->display.dpms = ironlake_crtc_dpms;
  5057. else
  5058. dev_priv->display.dpms = i9xx_crtc_dpms;
  5059. if (I915_HAS_FBC(dev)) {
  5060. if (IS_IRONLAKE_M(dev)) {
  5061. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  5062. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  5063. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  5064. } else if (IS_GM45(dev)) {
  5065. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  5066. dev_priv->display.enable_fbc = g4x_enable_fbc;
  5067. dev_priv->display.disable_fbc = g4x_disable_fbc;
  5068. } else if (IS_CRESTLINE(dev)) {
  5069. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  5070. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  5071. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  5072. }
  5073. /* 855GM needs testing */
  5074. }
  5075. /* Returns the core display clock speed */
  5076. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  5077. dev_priv->display.get_display_clock_speed =
  5078. i945_get_display_clock_speed;
  5079. else if (IS_I915G(dev))
  5080. dev_priv->display.get_display_clock_speed =
  5081. i915_get_display_clock_speed;
  5082. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  5083. dev_priv->display.get_display_clock_speed =
  5084. i9xx_misc_get_display_clock_speed;
  5085. else if (IS_I915GM(dev))
  5086. dev_priv->display.get_display_clock_speed =
  5087. i915gm_get_display_clock_speed;
  5088. else if (IS_I865G(dev))
  5089. dev_priv->display.get_display_clock_speed =
  5090. i865_get_display_clock_speed;
  5091. else if (IS_I85X(dev))
  5092. dev_priv->display.get_display_clock_speed =
  5093. i855_get_display_clock_speed;
  5094. else /* 852, 830 */
  5095. dev_priv->display.get_display_clock_speed =
  5096. i830_get_display_clock_speed;
  5097. /* For FIFO watermark updates */
  5098. if (HAS_PCH_SPLIT(dev)) {
  5099. if (IS_IRONLAKE(dev)) {
  5100. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  5101. dev_priv->display.update_wm = ironlake_update_wm;
  5102. else {
  5103. DRM_DEBUG_KMS("Failed to get proper latency. "
  5104. "Disable CxSR\n");
  5105. dev_priv->display.update_wm = NULL;
  5106. }
  5107. } else
  5108. dev_priv->display.update_wm = NULL;
  5109. } else if (IS_PINEVIEW(dev)) {
  5110. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  5111. dev_priv->is_ddr3,
  5112. dev_priv->fsb_freq,
  5113. dev_priv->mem_freq)) {
  5114. DRM_INFO("failed to find known CxSR latency "
  5115. "(found ddr%s fsb freq %d, mem freq %d), "
  5116. "disabling CxSR\n",
  5117. (dev_priv->is_ddr3 == 1) ? "3": "2",
  5118. dev_priv->fsb_freq, dev_priv->mem_freq);
  5119. /* Disable CxSR and never update its watermark again */
  5120. pineview_disable_cxsr(dev);
  5121. dev_priv->display.update_wm = NULL;
  5122. } else
  5123. dev_priv->display.update_wm = pineview_update_wm;
  5124. } else if (IS_G4X(dev))
  5125. dev_priv->display.update_wm = g4x_update_wm;
  5126. else if (IS_GEN4(dev))
  5127. dev_priv->display.update_wm = i965_update_wm;
  5128. else if (IS_GEN3(dev)) {
  5129. dev_priv->display.update_wm = i9xx_update_wm;
  5130. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  5131. } else if (IS_I85X(dev)) {
  5132. dev_priv->display.update_wm = i9xx_update_wm;
  5133. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  5134. } else {
  5135. dev_priv->display.update_wm = i830_update_wm;
  5136. if (IS_845G(dev))
  5137. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  5138. else
  5139. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  5140. }
  5141. }
  5142. /*
  5143. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  5144. * resume, or other times. This quirk makes sure that's the case for
  5145. * affected systems.
  5146. */
  5147. static void quirk_pipea_force (struct drm_device *dev)
  5148. {
  5149. struct drm_i915_private *dev_priv = dev->dev_private;
  5150. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  5151. DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
  5152. }
  5153. struct intel_quirk {
  5154. int device;
  5155. int subsystem_vendor;
  5156. int subsystem_device;
  5157. void (*hook)(struct drm_device *dev);
  5158. };
  5159. struct intel_quirk intel_quirks[] = {
  5160. /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
  5161. { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
  5162. /* HP Mini needs pipe A force quirk (LP: #322104) */
  5163. { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
  5164. /* Thinkpad R31 needs pipe A force quirk */
  5165. { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
  5166. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  5167. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  5168. /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
  5169. { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
  5170. /* ThinkPad X40 needs pipe A force quirk */
  5171. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  5172. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  5173. /* 855 & before need to leave pipe A & dpll A up */
  5174. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  5175. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  5176. };
  5177. static void intel_init_quirks(struct drm_device *dev)
  5178. {
  5179. struct pci_dev *d = dev->pdev;
  5180. int i;
  5181. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  5182. struct intel_quirk *q = &intel_quirks[i];
  5183. if (d->device == q->device &&
  5184. (d->subsystem_vendor == q->subsystem_vendor ||
  5185. q->subsystem_vendor == PCI_ANY_ID) &&
  5186. (d->subsystem_device == q->subsystem_device ||
  5187. q->subsystem_device == PCI_ANY_ID))
  5188. q->hook(dev);
  5189. }
  5190. }
  5191. /* Disable the VGA plane that we never use */
  5192. static void i915_disable_vga(struct drm_device *dev)
  5193. {
  5194. struct drm_i915_private *dev_priv = dev->dev_private;
  5195. u8 sr1;
  5196. u32 vga_reg;
  5197. if (HAS_PCH_SPLIT(dev))
  5198. vga_reg = CPU_VGACNTRL;
  5199. else
  5200. vga_reg = VGACNTRL;
  5201. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  5202. outb(1, VGA_SR_INDEX);
  5203. sr1 = inb(VGA_SR_DATA);
  5204. outb(sr1 | 1<<5, VGA_SR_DATA);
  5205. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  5206. udelay(300);
  5207. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  5208. POSTING_READ(vga_reg);
  5209. }
  5210. void intel_modeset_init(struct drm_device *dev)
  5211. {
  5212. struct drm_i915_private *dev_priv = dev->dev_private;
  5213. int i;
  5214. drm_mode_config_init(dev);
  5215. dev->mode_config.min_width = 0;
  5216. dev->mode_config.min_height = 0;
  5217. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  5218. intel_init_quirks(dev);
  5219. intel_init_display(dev);
  5220. if (IS_GEN2(dev)) {
  5221. dev->mode_config.max_width = 2048;
  5222. dev->mode_config.max_height = 2048;
  5223. } else if (IS_GEN3(dev)) {
  5224. dev->mode_config.max_width = 4096;
  5225. dev->mode_config.max_height = 4096;
  5226. } else {
  5227. dev->mode_config.max_width = 8192;
  5228. dev->mode_config.max_height = 8192;
  5229. }
  5230. /* set memory base */
  5231. if (IS_GEN2(dev))
  5232. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  5233. else
  5234. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  5235. if (IS_MOBILE(dev) || !IS_GEN2(dev))
  5236. dev_priv->num_pipe = 2;
  5237. else
  5238. dev_priv->num_pipe = 1;
  5239. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  5240. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  5241. for (i = 0; i < dev_priv->num_pipe; i++) {
  5242. intel_crtc_init(dev, i);
  5243. }
  5244. intel_setup_outputs(dev);
  5245. intel_init_clock_gating(dev);
  5246. /* Just disable it once at startup */
  5247. i915_disable_vga(dev);
  5248. if (IS_IRONLAKE_M(dev)) {
  5249. ironlake_enable_drps(dev);
  5250. intel_init_emon(dev);
  5251. }
  5252. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  5253. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  5254. (unsigned long)dev);
  5255. intel_setup_overlay(dev);
  5256. }
  5257. void intel_modeset_cleanup(struct drm_device *dev)
  5258. {
  5259. struct drm_i915_private *dev_priv = dev->dev_private;
  5260. struct drm_crtc *crtc;
  5261. struct intel_crtc *intel_crtc;
  5262. mutex_lock(&dev->struct_mutex);
  5263. drm_kms_helper_poll_fini(dev);
  5264. intel_fbdev_fini(dev);
  5265. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5266. /* Skip inactive CRTCs */
  5267. if (!crtc->fb)
  5268. continue;
  5269. intel_crtc = to_intel_crtc(crtc);
  5270. intel_increase_pllclock(crtc);
  5271. }
  5272. if (dev_priv->display.disable_fbc)
  5273. dev_priv->display.disable_fbc(dev);
  5274. if (dev_priv->renderctx) {
  5275. struct drm_i915_gem_object *obj_priv;
  5276. obj_priv = to_intel_bo(dev_priv->renderctx);
  5277. I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
  5278. I915_READ(CCID);
  5279. i915_gem_object_unpin(dev_priv->renderctx);
  5280. drm_gem_object_unreference(dev_priv->renderctx);
  5281. }
  5282. if (dev_priv->pwrctx) {
  5283. struct drm_i915_gem_object *obj_priv;
  5284. obj_priv = to_intel_bo(dev_priv->pwrctx);
  5285. I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
  5286. I915_READ(PWRCTXA);
  5287. i915_gem_object_unpin(dev_priv->pwrctx);
  5288. drm_gem_object_unreference(dev_priv->pwrctx);
  5289. }
  5290. if (IS_IRONLAKE_M(dev))
  5291. ironlake_disable_drps(dev);
  5292. mutex_unlock(&dev->struct_mutex);
  5293. /* Disable the irq before mode object teardown, for the irq might
  5294. * enqueue unpin/hotplug work. */
  5295. drm_irq_uninstall(dev);
  5296. cancel_work_sync(&dev_priv->hotplug_work);
  5297. /* Shut off idle work before the crtcs get freed. */
  5298. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5299. intel_crtc = to_intel_crtc(crtc);
  5300. del_timer_sync(&intel_crtc->idle_timer);
  5301. }
  5302. del_timer_sync(&dev_priv->idle_timer);
  5303. cancel_work_sync(&dev_priv->idle_work);
  5304. drm_mode_config_cleanup(dev);
  5305. }
  5306. /*
  5307. * Return which encoder is currently attached for connector.
  5308. */
  5309. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  5310. {
  5311. return &intel_attached_encoder(connector)->base;
  5312. }
  5313. void intel_connector_attach_encoder(struct intel_connector *connector,
  5314. struct intel_encoder *encoder)
  5315. {
  5316. connector->encoder = encoder;
  5317. drm_mode_connector_attach_encoder(&connector->base,
  5318. &encoder->base);
  5319. }
  5320. /*
  5321. * set vga decode state - true == enable VGA decode
  5322. */
  5323. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  5324. {
  5325. struct drm_i915_private *dev_priv = dev->dev_private;
  5326. u16 gmch_ctrl;
  5327. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  5328. if (state)
  5329. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  5330. else
  5331. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  5332. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  5333. return 0;
  5334. }