gart.h 2.4 KB

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  1. #ifndef _ASM_X8664_IOMMU_H
  2. #define _ASM_X8664_IOMMU_H 1
  3. #include <asm/e820.h>
  4. extern void pci_iommu_shutdown(void);
  5. extern void no_iommu_init(void);
  6. extern int force_iommu, no_iommu;
  7. extern int iommu_detected;
  8. extern int agp_amd64_init(void);
  9. #ifdef CONFIG_GART_IOMMU
  10. extern void gart_iommu_init(void);
  11. extern void gart_iommu_shutdown(void);
  12. extern void __init gart_parse_options(char *);
  13. extern void early_gart_iommu_check(void);
  14. extern void gart_iommu_hole_init(void);
  15. extern void set_up_gart_resume(u32, u32);
  16. extern int fallback_aper_order;
  17. extern int fallback_aper_force;
  18. extern int gart_iommu_aperture;
  19. extern int gart_iommu_aperture_allowed;
  20. extern int gart_iommu_aperture_disabled;
  21. extern int fix_aperture;
  22. #else
  23. #define gart_iommu_aperture 0
  24. #define gart_iommu_aperture_allowed 0
  25. #define gart_iommu_aperture_disabled 1
  26. static inline void early_gart_iommu_check(void)
  27. {
  28. }
  29. static inline void gart_iommu_shutdown(void)
  30. {
  31. }
  32. #endif
  33. /* PTE bits. */
  34. #define GPTE_VALID 1
  35. #define GPTE_COHERENT 2
  36. /* Aperture control register bits. */
  37. #define GARTEN (1<<0)
  38. #define DISGARTCPU (1<<4)
  39. #define DISGARTIO (1<<5)
  40. /* GART cache control register bits. */
  41. #define INVGART (1<<0)
  42. #define GARTPTEERR (1<<1)
  43. /* K8 On-cpu GART registers */
  44. #define AMD64_GARTAPERTURECTL 0x90
  45. #define AMD64_GARTAPERTUREBASE 0x94
  46. #define AMD64_GARTTABLEBASE 0x98
  47. #define AMD64_GARTCACHECTL 0x9c
  48. #define AMD64_GARTEN (1<<0)
  49. static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
  50. {
  51. u32 tmp, ctl;
  52. /* address of the mappings table */
  53. addr >>= 12;
  54. tmp = (u32) addr<<4;
  55. tmp &= ~0xf;
  56. pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
  57. /* Enable GART translation for this hammer. */
  58. pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
  59. ctl |= GARTEN;
  60. ctl &= ~(DISGARTCPU | DISGARTIO);
  61. pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  62. }
  63. static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
  64. {
  65. if (!aper_base)
  66. return 0;
  67. if (aper_base + aper_size > 0x100000000ULL) {
  68. printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
  69. return 0;
  70. }
  71. if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
  72. printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
  73. return 0;
  74. }
  75. if (aper_size < min_size) {
  76. printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
  77. aper_size>>20, min_size>>20);
  78. return 0;
  79. }
  80. return 1;
  81. }
  82. #endif