dmaengine.c 29 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. static DEFINE_MUTEX(dma_list_mutex);
  66. static DEFINE_IDR(dma_idr);
  67. static LIST_HEAD(dma_device_list);
  68. static long dmaengine_ref_count;
  69. /* --- sysfs implementation --- */
  70. /**
  71. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  72. * @dev - device node
  73. *
  74. * Must be called under dma_list_mutex
  75. */
  76. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  77. {
  78. struct dma_chan_dev *chan_dev;
  79. chan_dev = container_of(dev, typeof(*chan_dev), device);
  80. return chan_dev->chan;
  81. }
  82. static ssize_t memcpy_count_show(struct device *dev,
  83. struct device_attribute *attr, char *buf)
  84. {
  85. struct dma_chan *chan;
  86. unsigned long count = 0;
  87. int i;
  88. int err;
  89. mutex_lock(&dma_list_mutex);
  90. chan = dev_to_dma_chan(dev);
  91. if (chan) {
  92. for_each_possible_cpu(i)
  93. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  94. err = sprintf(buf, "%lu\n", count);
  95. } else
  96. err = -ENODEV;
  97. mutex_unlock(&dma_list_mutex);
  98. return err;
  99. }
  100. static DEVICE_ATTR_RO(memcpy_count);
  101. static ssize_t bytes_transferred_show(struct device *dev,
  102. struct device_attribute *attr, char *buf)
  103. {
  104. struct dma_chan *chan;
  105. unsigned long count = 0;
  106. int i;
  107. int err;
  108. mutex_lock(&dma_list_mutex);
  109. chan = dev_to_dma_chan(dev);
  110. if (chan) {
  111. for_each_possible_cpu(i)
  112. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  113. err = sprintf(buf, "%lu\n", count);
  114. } else
  115. err = -ENODEV;
  116. mutex_unlock(&dma_list_mutex);
  117. return err;
  118. }
  119. static DEVICE_ATTR_RO(bytes_transferred);
  120. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  121. char *buf)
  122. {
  123. struct dma_chan *chan;
  124. int err;
  125. mutex_lock(&dma_list_mutex);
  126. chan = dev_to_dma_chan(dev);
  127. if (chan)
  128. err = sprintf(buf, "%d\n", chan->client_count);
  129. else
  130. err = -ENODEV;
  131. mutex_unlock(&dma_list_mutex);
  132. return err;
  133. }
  134. static DEVICE_ATTR_RO(in_use);
  135. static struct attribute *dma_dev_attrs[] = {
  136. &dev_attr_memcpy_count.attr,
  137. &dev_attr_bytes_transferred.attr,
  138. &dev_attr_in_use.attr,
  139. NULL,
  140. };
  141. ATTRIBUTE_GROUPS(dma_dev);
  142. static void chan_dev_release(struct device *dev)
  143. {
  144. struct dma_chan_dev *chan_dev;
  145. chan_dev = container_of(dev, typeof(*chan_dev), device);
  146. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  147. mutex_lock(&dma_list_mutex);
  148. idr_remove(&dma_idr, chan_dev->dev_id);
  149. mutex_unlock(&dma_list_mutex);
  150. kfree(chan_dev->idr_ref);
  151. }
  152. kfree(chan_dev);
  153. }
  154. static struct class dma_devclass = {
  155. .name = "dma",
  156. .dev_groups = dma_dev_groups,
  157. .dev_release = chan_dev_release,
  158. };
  159. /* --- client and device registration --- */
  160. #define dma_device_satisfies_mask(device, mask) \
  161. __dma_device_satisfies_mask((device), &(mask))
  162. static int
  163. __dma_device_satisfies_mask(struct dma_device *device,
  164. const dma_cap_mask_t *want)
  165. {
  166. dma_cap_mask_t has;
  167. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  168. DMA_TX_TYPE_END);
  169. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  170. }
  171. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  172. {
  173. return chan->device->dev->driver->owner;
  174. }
  175. /**
  176. * balance_ref_count - catch up the channel reference count
  177. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  178. *
  179. * balance_ref_count must be called under dma_list_mutex
  180. */
  181. static void balance_ref_count(struct dma_chan *chan)
  182. {
  183. struct module *owner = dma_chan_to_owner(chan);
  184. while (chan->client_count < dmaengine_ref_count) {
  185. __module_get(owner);
  186. chan->client_count++;
  187. }
  188. }
  189. /**
  190. * dma_chan_get - try to grab a dma channel's parent driver module
  191. * @chan - channel to grab
  192. *
  193. * Must be called under dma_list_mutex
  194. */
  195. static int dma_chan_get(struct dma_chan *chan)
  196. {
  197. int err = -ENODEV;
  198. struct module *owner = dma_chan_to_owner(chan);
  199. if (chan->client_count) {
  200. __module_get(owner);
  201. err = 0;
  202. } else if (try_module_get(owner))
  203. err = 0;
  204. if (err == 0)
  205. chan->client_count++;
  206. /* allocate upon first client reference */
  207. if (chan->client_count == 1 && err == 0) {
  208. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  209. if (desc_cnt < 0) {
  210. err = desc_cnt;
  211. chan->client_count = 0;
  212. module_put(owner);
  213. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  214. balance_ref_count(chan);
  215. }
  216. return err;
  217. }
  218. /**
  219. * dma_chan_put - drop a reference to a dma channel's parent driver module
  220. * @chan - channel to release
  221. *
  222. * Must be called under dma_list_mutex
  223. */
  224. static void dma_chan_put(struct dma_chan *chan)
  225. {
  226. if (!chan->client_count)
  227. return; /* this channel failed alloc_chan_resources */
  228. chan->client_count--;
  229. module_put(dma_chan_to_owner(chan));
  230. if (chan->client_count == 0)
  231. chan->device->device_free_chan_resources(chan);
  232. }
  233. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  234. {
  235. enum dma_status status;
  236. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  237. dma_async_issue_pending(chan);
  238. do {
  239. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  240. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  241. pr_err("%s: timeout!\n", __func__);
  242. return DMA_ERROR;
  243. }
  244. if (status != DMA_IN_PROGRESS)
  245. break;
  246. cpu_relax();
  247. } while (1);
  248. return status;
  249. }
  250. EXPORT_SYMBOL(dma_sync_wait);
  251. /**
  252. * dma_cap_mask_all - enable iteration over all operation types
  253. */
  254. static dma_cap_mask_t dma_cap_mask_all;
  255. /**
  256. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  257. * @chan - associated channel for this entry
  258. */
  259. struct dma_chan_tbl_ent {
  260. struct dma_chan *chan;
  261. };
  262. /**
  263. * channel_table - percpu lookup table for memory-to-memory offload providers
  264. */
  265. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  266. static int __init dma_channel_table_init(void)
  267. {
  268. enum dma_transaction_type cap;
  269. int err = 0;
  270. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  271. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  272. * but are not associated with an operation so they do not need
  273. * an entry in the channel_table
  274. */
  275. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  276. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  277. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  278. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  279. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  280. if (!channel_table[cap]) {
  281. err = -ENOMEM;
  282. break;
  283. }
  284. }
  285. if (err) {
  286. pr_err("initialization failure\n");
  287. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  288. if (channel_table[cap])
  289. free_percpu(channel_table[cap]);
  290. }
  291. return err;
  292. }
  293. arch_initcall(dma_channel_table_init);
  294. /**
  295. * dma_find_channel - find a channel to carry out the operation
  296. * @tx_type: transaction type
  297. */
  298. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  299. {
  300. return this_cpu_read(channel_table[tx_type]->chan);
  301. }
  302. EXPORT_SYMBOL(dma_find_channel);
  303. /*
  304. * net_dma_find_channel - find a channel for net_dma
  305. * net_dma has alignment requirements
  306. */
  307. struct dma_chan *net_dma_find_channel(void)
  308. {
  309. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  310. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  311. return NULL;
  312. return chan;
  313. }
  314. EXPORT_SYMBOL(net_dma_find_channel);
  315. /**
  316. * dma_issue_pending_all - flush all pending operations across all channels
  317. */
  318. void dma_issue_pending_all(void)
  319. {
  320. struct dma_device *device;
  321. struct dma_chan *chan;
  322. rcu_read_lock();
  323. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  324. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  325. continue;
  326. list_for_each_entry(chan, &device->channels, device_node)
  327. if (chan->client_count)
  328. device->device_issue_pending(chan);
  329. }
  330. rcu_read_unlock();
  331. }
  332. EXPORT_SYMBOL(dma_issue_pending_all);
  333. /**
  334. * nth_chan - returns the nth channel of the given capability
  335. * @cap: capability to match
  336. * @n: nth channel desired
  337. *
  338. * Defaults to returning the channel with the desired capability and the
  339. * lowest reference count when 'n' cannot be satisfied. Must be called
  340. * under dma_list_mutex.
  341. */
  342. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  343. {
  344. struct dma_device *device;
  345. struct dma_chan *chan;
  346. struct dma_chan *ret = NULL;
  347. struct dma_chan *min = NULL;
  348. list_for_each_entry(device, &dma_device_list, global_node) {
  349. if (!dma_has_cap(cap, device->cap_mask) ||
  350. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  351. continue;
  352. list_for_each_entry(chan, &device->channels, device_node) {
  353. if (!chan->client_count)
  354. continue;
  355. if (!min)
  356. min = chan;
  357. else if (chan->table_count < min->table_count)
  358. min = chan;
  359. if (n-- == 0) {
  360. ret = chan;
  361. break; /* done */
  362. }
  363. }
  364. if (ret)
  365. break; /* done */
  366. }
  367. if (!ret)
  368. ret = min;
  369. if (ret)
  370. ret->table_count++;
  371. return ret;
  372. }
  373. /**
  374. * dma_channel_rebalance - redistribute the available channels
  375. *
  376. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  377. * operation type) in the SMP case, and operation isolation (avoid
  378. * multi-tasking channels) in the non-SMP case. Must be called under
  379. * dma_list_mutex.
  380. */
  381. static void dma_channel_rebalance(void)
  382. {
  383. struct dma_chan *chan;
  384. struct dma_device *device;
  385. int cpu;
  386. int cap;
  387. int n;
  388. /* undo the last distribution */
  389. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  390. for_each_possible_cpu(cpu)
  391. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  392. list_for_each_entry(device, &dma_device_list, global_node) {
  393. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  394. continue;
  395. list_for_each_entry(chan, &device->channels, device_node)
  396. chan->table_count = 0;
  397. }
  398. /* don't populate the channel_table if no clients are available */
  399. if (!dmaengine_ref_count)
  400. return;
  401. /* redistribute available channels */
  402. n = 0;
  403. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  404. for_each_online_cpu(cpu) {
  405. if (num_possible_cpus() > 1)
  406. chan = nth_chan(cap, n++);
  407. else
  408. chan = nth_chan(cap, -1);
  409. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  410. }
  411. }
  412. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  413. struct dma_device *dev,
  414. dma_filter_fn fn, void *fn_param)
  415. {
  416. struct dma_chan *chan;
  417. if (!__dma_device_satisfies_mask(dev, mask)) {
  418. pr_debug("%s: wrong capabilities\n", __func__);
  419. return NULL;
  420. }
  421. /* devices with multiple channels need special handling as we need to
  422. * ensure that all channels are either private or public.
  423. */
  424. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  425. list_for_each_entry(chan, &dev->channels, device_node) {
  426. /* some channels are already publicly allocated */
  427. if (chan->client_count)
  428. return NULL;
  429. }
  430. list_for_each_entry(chan, &dev->channels, device_node) {
  431. if (chan->client_count) {
  432. pr_debug("%s: %s busy\n",
  433. __func__, dma_chan_name(chan));
  434. continue;
  435. }
  436. if (fn && !fn(chan, fn_param)) {
  437. pr_debug("%s: %s filter said false\n",
  438. __func__, dma_chan_name(chan));
  439. continue;
  440. }
  441. return chan;
  442. }
  443. return NULL;
  444. }
  445. /**
  446. * dma_request_channel - try to allocate an exclusive channel
  447. * @mask: capabilities that the channel must satisfy
  448. * @fn: optional callback to disposition available channels
  449. * @fn_param: opaque parameter to pass to dma_filter_fn
  450. */
  451. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  452. dma_filter_fn fn, void *fn_param)
  453. {
  454. struct dma_device *device, *_d;
  455. struct dma_chan *chan = NULL;
  456. int err;
  457. /* Find a channel */
  458. mutex_lock(&dma_list_mutex);
  459. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  460. chan = private_candidate(mask, device, fn, fn_param);
  461. if (chan) {
  462. /* Found a suitable channel, try to grab, prep, and
  463. * return it. We first set DMA_PRIVATE to disable
  464. * balance_ref_count as this channel will not be
  465. * published in the general-purpose allocator
  466. */
  467. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  468. device->privatecnt++;
  469. err = dma_chan_get(chan);
  470. if (err == -ENODEV) {
  471. pr_debug("%s: %s module removed\n",
  472. __func__, dma_chan_name(chan));
  473. list_del_rcu(&device->global_node);
  474. } else if (err)
  475. pr_debug("%s: failed to get %s: (%d)\n",
  476. __func__, dma_chan_name(chan), err);
  477. else
  478. break;
  479. if (--device->privatecnt == 0)
  480. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  481. chan = NULL;
  482. }
  483. }
  484. mutex_unlock(&dma_list_mutex);
  485. pr_debug("%s: %s (%s)\n",
  486. __func__,
  487. chan ? "success" : "fail",
  488. chan ? dma_chan_name(chan) : NULL);
  489. return chan;
  490. }
  491. EXPORT_SYMBOL_GPL(__dma_request_channel);
  492. /**
  493. * dma_request_slave_channel - try to allocate an exclusive slave channel
  494. * @dev: pointer to client device structure
  495. * @name: slave channel name
  496. */
  497. struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
  498. {
  499. /* If device-tree is present get slave info from here */
  500. if (dev->of_node)
  501. return of_dma_request_slave_channel(dev->of_node, name);
  502. /* If device was enumerated by ACPI get slave info from here */
  503. if (ACPI_HANDLE(dev))
  504. return acpi_dma_request_slave_chan_by_name(dev, name);
  505. return NULL;
  506. }
  507. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  508. void dma_release_channel(struct dma_chan *chan)
  509. {
  510. mutex_lock(&dma_list_mutex);
  511. WARN_ONCE(chan->client_count != 1,
  512. "chan reference count %d != 1\n", chan->client_count);
  513. dma_chan_put(chan);
  514. /* drop PRIVATE cap enabled by __dma_request_channel() */
  515. if (--chan->device->privatecnt == 0)
  516. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  517. mutex_unlock(&dma_list_mutex);
  518. }
  519. EXPORT_SYMBOL_GPL(dma_release_channel);
  520. /**
  521. * dmaengine_get - register interest in dma_channels
  522. */
  523. void dmaengine_get(void)
  524. {
  525. struct dma_device *device, *_d;
  526. struct dma_chan *chan;
  527. int err;
  528. mutex_lock(&dma_list_mutex);
  529. dmaengine_ref_count++;
  530. /* try to grab channels */
  531. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  532. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  533. continue;
  534. list_for_each_entry(chan, &device->channels, device_node) {
  535. err = dma_chan_get(chan);
  536. if (err == -ENODEV) {
  537. /* module removed before we could use it */
  538. list_del_rcu(&device->global_node);
  539. break;
  540. } else if (err)
  541. pr_debug("%s: failed to get %s: (%d)\n",
  542. __func__, dma_chan_name(chan), err);
  543. }
  544. }
  545. /* if this is the first reference and there were channels
  546. * waiting we need to rebalance to get those channels
  547. * incorporated into the channel table
  548. */
  549. if (dmaengine_ref_count == 1)
  550. dma_channel_rebalance();
  551. mutex_unlock(&dma_list_mutex);
  552. }
  553. EXPORT_SYMBOL(dmaengine_get);
  554. /**
  555. * dmaengine_put - let dma drivers be removed when ref_count == 0
  556. */
  557. void dmaengine_put(void)
  558. {
  559. struct dma_device *device;
  560. struct dma_chan *chan;
  561. mutex_lock(&dma_list_mutex);
  562. dmaengine_ref_count--;
  563. BUG_ON(dmaengine_ref_count < 0);
  564. /* drop channel references */
  565. list_for_each_entry(device, &dma_device_list, global_node) {
  566. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  567. continue;
  568. list_for_each_entry(chan, &device->channels, device_node)
  569. dma_chan_put(chan);
  570. }
  571. mutex_unlock(&dma_list_mutex);
  572. }
  573. EXPORT_SYMBOL(dmaengine_put);
  574. static bool device_has_all_tx_types(struct dma_device *device)
  575. {
  576. /* A device that satisfies this test has channels that will never cause
  577. * an async_tx channel switch event as all possible operation types can
  578. * be handled.
  579. */
  580. #ifdef CONFIG_ASYNC_TX_DMA
  581. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  582. return false;
  583. #endif
  584. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  585. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  586. return false;
  587. #endif
  588. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  589. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  590. return false;
  591. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  592. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  593. return false;
  594. #endif
  595. #endif
  596. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  597. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  598. return false;
  599. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  600. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  601. return false;
  602. #endif
  603. #endif
  604. return true;
  605. }
  606. static int get_dma_id(struct dma_device *device)
  607. {
  608. int rc;
  609. mutex_lock(&dma_list_mutex);
  610. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  611. if (rc >= 0)
  612. device->dev_id = rc;
  613. mutex_unlock(&dma_list_mutex);
  614. return rc < 0 ? rc : 0;
  615. }
  616. /**
  617. * dma_async_device_register - registers DMA devices found
  618. * @device: &dma_device
  619. */
  620. int dma_async_device_register(struct dma_device *device)
  621. {
  622. int chancnt = 0, rc;
  623. struct dma_chan* chan;
  624. atomic_t *idr_ref;
  625. if (!device)
  626. return -ENODEV;
  627. /* validate device routines */
  628. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  629. !device->device_prep_dma_memcpy);
  630. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  631. !device->device_prep_dma_xor);
  632. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  633. !device->device_prep_dma_xor_val);
  634. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  635. !device->device_prep_dma_pq);
  636. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  637. !device->device_prep_dma_pq_val);
  638. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  639. !device->device_prep_dma_interrupt);
  640. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  641. !device->device_prep_dma_sg);
  642. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  643. !device->device_prep_dma_cyclic);
  644. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  645. !device->device_control);
  646. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  647. !device->device_prep_interleaved_dma);
  648. BUG_ON(!device->device_alloc_chan_resources);
  649. BUG_ON(!device->device_free_chan_resources);
  650. BUG_ON(!device->device_tx_status);
  651. BUG_ON(!device->device_issue_pending);
  652. BUG_ON(!device->dev);
  653. /* note: this only matters in the
  654. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  655. */
  656. if (device_has_all_tx_types(device))
  657. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  658. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  659. if (!idr_ref)
  660. return -ENOMEM;
  661. rc = get_dma_id(device);
  662. if (rc != 0) {
  663. kfree(idr_ref);
  664. return rc;
  665. }
  666. atomic_set(idr_ref, 0);
  667. /* represent channels in sysfs. Probably want devs too */
  668. list_for_each_entry(chan, &device->channels, device_node) {
  669. rc = -ENOMEM;
  670. chan->local = alloc_percpu(typeof(*chan->local));
  671. if (chan->local == NULL)
  672. goto err_out;
  673. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  674. if (chan->dev == NULL) {
  675. free_percpu(chan->local);
  676. chan->local = NULL;
  677. goto err_out;
  678. }
  679. chan->chan_id = chancnt++;
  680. chan->dev->device.class = &dma_devclass;
  681. chan->dev->device.parent = device->dev;
  682. chan->dev->chan = chan;
  683. chan->dev->idr_ref = idr_ref;
  684. chan->dev->dev_id = device->dev_id;
  685. atomic_inc(idr_ref);
  686. dev_set_name(&chan->dev->device, "dma%dchan%d",
  687. device->dev_id, chan->chan_id);
  688. rc = device_register(&chan->dev->device);
  689. if (rc) {
  690. free_percpu(chan->local);
  691. chan->local = NULL;
  692. kfree(chan->dev);
  693. atomic_dec(idr_ref);
  694. goto err_out;
  695. }
  696. chan->client_count = 0;
  697. }
  698. device->chancnt = chancnt;
  699. mutex_lock(&dma_list_mutex);
  700. /* take references on public channels */
  701. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  702. list_for_each_entry(chan, &device->channels, device_node) {
  703. /* if clients are already waiting for channels we need
  704. * to take references on their behalf
  705. */
  706. if (dma_chan_get(chan) == -ENODEV) {
  707. /* note we can only get here for the first
  708. * channel as the remaining channels are
  709. * guaranteed to get a reference
  710. */
  711. rc = -ENODEV;
  712. mutex_unlock(&dma_list_mutex);
  713. goto err_out;
  714. }
  715. }
  716. list_add_tail_rcu(&device->global_node, &dma_device_list);
  717. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  718. device->privatecnt++; /* Always private */
  719. dma_channel_rebalance();
  720. mutex_unlock(&dma_list_mutex);
  721. return 0;
  722. err_out:
  723. /* if we never registered a channel just release the idr */
  724. if (atomic_read(idr_ref) == 0) {
  725. mutex_lock(&dma_list_mutex);
  726. idr_remove(&dma_idr, device->dev_id);
  727. mutex_unlock(&dma_list_mutex);
  728. kfree(idr_ref);
  729. return rc;
  730. }
  731. list_for_each_entry(chan, &device->channels, device_node) {
  732. if (chan->local == NULL)
  733. continue;
  734. mutex_lock(&dma_list_mutex);
  735. chan->dev->chan = NULL;
  736. mutex_unlock(&dma_list_mutex);
  737. device_unregister(&chan->dev->device);
  738. free_percpu(chan->local);
  739. }
  740. return rc;
  741. }
  742. EXPORT_SYMBOL(dma_async_device_register);
  743. /**
  744. * dma_async_device_unregister - unregister a DMA device
  745. * @device: &dma_device
  746. *
  747. * This routine is called by dma driver exit routines, dmaengine holds module
  748. * references to prevent it being called while channels are in use.
  749. */
  750. void dma_async_device_unregister(struct dma_device *device)
  751. {
  752. struct dma_chan *chan;
  753. mutex_lock(&dma_list_mutex);
  754. list_del_rcu(&device->global_node);
  755. dma_channel_rebalance();
  756. mutex_unlock(&dma_list_mutex);
  757. list_for_each_entry(chan, &device->channels, device_node) {
  758. WARN_ONCE(chan->client_count,
  759. "%s called while %d clients hold a reference\n",
  760. __func__, chan->client_count);
  761. mutex_lock(&dma_list_mutex);
  762. chan->dev->chan = NULL;
  763. mutex_unlock(&dma_list_mutex);
  764. device_unregister(&chan->dev->device);
  765. free_percpu(chan->local);
  766. }
  767. }
  768. EXPORT_SYMBOL(dma_async_device_unregister);
  769. /**
  770. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  771. * @chan: DMA channel to offload copy to
  772. * @dest: destination address (virtual)
  773. * @src: source address (virtual)
  774. * @len: length
  775. *
  776. * Both @dest and @src must be mappable to a bus address according to the
  777. * DMA mapping API rules for streaming mappings.
  778. * Both @dest and @src must stay memory resident (kernel memory or locked
  779. * user space pages).
  780. */
  781. dma_cookie_t
  782. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  783. void *src, size_t len)
  784. {
  785. struct dma_device *dev = chan->device;
  786. struct dma_async_tx_descriptor *tx;
  787. dma_addr_t dma_dest, dma_src;
  788. dma_cookie_t cookie;
  789. unsigned long flags;
  790. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  791. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  792. flags = DMA_CTRL_ACK |
  793. DMA_COMPL_SRC_UNMAP_SINGLE |
  794. DMA_COMPL_DEST_UNMAP_SINGLE;
  795. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  796. if (!tx) {
  797. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  798. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  799. return -ENOMEM;
  800. }
  801. tx->callback = NULL;
  802. cookie = tx->tx_submit(tx);
  803. preempt_disable();
  804. __this_cpu_add(chan->local->bytes_transferred, len);
  805. __this_cpu_inc(chan->local->memcpy_count);
  806. preempt_enable();
  807. return cookie;
  808. }
  809. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  810. /**
  811. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  812. * @chan: DMA channel to offload copy to
  813. * @page: destination page
  814. * @offset: offset in page to copy to
  815. * @kdata: source address (virtual)
  816. * @len: length
  817. *
  818. * Both @page/@offset and @kdata must be mappable to a bus address according
  819. * to the DMA mapping API rules for streaming mappings.
  820. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  821. * locked user space pages)
  822. */
  823. dma_cookie_t
  824. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  825. unsigned int offset, void *kdata, size_t len)
  826. {
  827. struct dma_device *dev = chan->device;
  828. struct dma_async_tx_descriptor *tx;
  829. dma_addr_t dma_dest, dma_src;
  830. dma_cookie_t cookie;
  831. unsigned long flags;
  832. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  833. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  834. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  835. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  836. if (!tx) {
  837. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  838. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  839. return -ENOMEM;
  840. }
  841. tx->callback = NULL;
  842. cookie = tx->tx_submit(tx);
  843. preempt_disable();
  844. __this_cpu_add(chan->local->bytes_transferred, len);
  845. __this_cpu_inc(chan->local->memcpy_count);
  846. preempt_enable();
  847. return cookie;
  848. }
  849. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  850. /**
  851. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  852. * @chan: DMA channel to offload copy to
  853. * @dest_pg: destination page
  854. * @dest_off: offset in page to copy to
  855. * @src_pg: source page
  856. * @src_off: offset in page to copy from
  857. * @len: length
  858. *
  859. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  860. * address according to the DMA mapping API rules for streaming mappings.
  861. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  862. * (kernel memory or locked user space pages).
  863. */
  864. dma_cookie_t
  865. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  866. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  867. size_t len)
  868. {
  869. struct dma_device *dev = chan->device;
  870. struct dma_async_tx_descriptor *tx;
  871. dma_addr_t dma_dest, dma_src;
  872. dma_cookie_t cookie;
  873. unsigned long flags;
  874. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  875. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  876. DMA_FROM_DEVICE);
  877. flags = DMA_CTRL_ACK;
  878. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  879. if (!tx) {
  880. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  881. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  882. return -ENOMEM;
  883. }
  884. tx->callback = NULL;
  885. cookie = tx->tx_submit(tx);
  886. preempt_disable();
  887. __this_cpu_add(chan->local->bytes_transferred, len);
  888. __this_cpu_inc(chan->local->memcpy_count);
  889. preempt_enable();
  890. return cookie;
  891. }
  892. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  893. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  894. struct dma_chan *chan)
  895. {
  896. tx->chan = chan;
  897. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  898. spin_lock_init(&tx->lock);
  899. #endif
  900. }
  901. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  902. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  903. * @tx: in-flight transaction to wait on
  904. */
  905. enum dma_status
  906. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  907. {
  908. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  909. if (!tx)
  910. return DMA_SUCCESS;
  911. while (tx->cookie == -EBUSY) {
  912. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  913. pr_err("%s timeout waiting for descriptor submission\n",
  914. __func__);
  915. return DMA_ERROR;
  916. }
  917. cpu_relax();
  918. }
  919. return dma_sync_wait(tx->chan, tx->cookie);
  920. }
  921. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  922. /* dma_run_dependencies - helper routine for dma drivers to process
  923. * (start) dependent operations on their target channel
  924. * @tx: transaction with dependencies
  925. */
  926. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  927. {
  928. struct dma_async_tx_descriptor *dep = txd_next(tx);
  929. struct dma_async_tx_descriptor *dep_next;
  930. struct dma_chan *chan;
  931. if (!dep)
  932. return;
  933. /* we'll submit tx->next now, so clear the link */
  934. txd_clear_next(tx);
  935. chan = dep->chan;
  936. /* keep submitting up until a channel switch is detected
  937. * in that case we will be called again as a result of
  938. * processing the interrupt from async_tx_channel_switch
  939. */
  940. for (; dep; dep = dep_next) {
  941. txd_lock(dep);
  942. txd_clear_parent(dep);
  943. dep_next = txd_next(dep);
  944. if (dep_next && dep_next->chan == chan)
  945. txd_clear_next(dep); /* ->next will be submitted */
  946. else
  947. dep_next = NULL; /* submit current dep and terminate */
  948. txd_unlock(dep);
  949. dep->tx_submit(dep);
  950. }
  951. chan->device->device_issue_pending(chan);
  952. }
  953. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  954. static int __init dma_bus_init(void)
  955. {
  956. return class_register(&dma_devclass);
  957. }
  958. arch_initcall(dma_bus_init);