tqm5200.dts 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186
  1. /*
  2. * TQM5200 board Device Tree Source
  3. *
  4. * Copyright (C) 2007 Semihalf
  5. * Marian Balakowicz <m8@semihalf.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /*
  13. * WARNING: Do not depend on this tree layout remaining static just yet.
  14. * The MPC5200 device tree conventions are still in flux
  15. * Keep an eye on the linuxppc-dev mailing list for more details
  16. */
  17. / {
  18. model = "tqc,tqm5200";
  19. compatible = "tqc,tqm5200";
  20. #address-cells = <1>;
  21. #size-cells = <1>;
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. PowerPC,5200@0 {
  26. device_type = "cpu";
  27. reg = <0>;
  28. d-cache-line-size = <20>;
  29. i-cache-line-size = <20>;
  30. d-cache-size = <4000>; // L1, 16K
  31. i-cache-size = <4000>; // L1, 16K
  32. timebase-frequency = <0>; // from bootloader
  33. bus-frequency = <0>; // from bootloader
  34. clock-frequency = <0>; // from bootloader
  35. };
  36. };
  37. memory {
  38. device_type = "memory";
  39. reg = <00000000 04000000>; // 64MB
  40. };
  41. soc5200@f0000000 {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. model = "fsl,mpc5200";
  45. compatible = "fsl,mpc5200";
  46. revision = ""; // from bootloader
  47. device_type = "soc";
  48. ranges = <0 f0000000 0000c000>;
  49. reg = <f0000000 00000100>;
  50. bus-frequency = <0>; // from bootloader
  51. system-frequency = <0>; // from bootloader
  52. cdm@200 {
  53. compatible = "mpc5200-cdm";
  54. reg = <200 38>;
  55. };
  56. mpc5200_pic: pic@500 {
  57. // 5200 interrupts are encoded into two levels;
  58. interrupt-controller;
  59. #interrupt-cells = <3>;
  60. compatible = "mpc5200-pic";
  61. reg = <500 80>;
  62. };
  63. gpt@600 { // General Purpose Timer
  64. compatible = "fsl,mpc5200-gpt";
  65. reg = <600 10>;
  66. interrupts = <1 9 0>;
  67. interrupt-parent = <&mpc5200_pic>;
  68. fsl,has-wdt;
  69. };
  70. gpio@b00 {
  71. compatible = "mpc5200-gpio";
  72. reg = <b00 40>;
  73. interrupts = <1 7 0>;
  74. interrupt-parent = <&mpc5200_pic>;
  75. };
  76. usb@1000 {
  77. compatible = "mpc5200-ohci","ohci-be";
  78. reg = <1000 ff>;
  79. interrupts = <2 6 0>;
  80. interrupt-parent = <&mpc5200_pic>;
  81. };
  82. dma-controller@1200 {
  83. compatible = "mpc5200-bestcomm";
  84. reg = <1200 80>;
  85. interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
  86. 3 4 0 3 5 0 3 6 0 3 7 0
  87. 3 8 0 3 9 0 3 a 0 3 b 0
  88. 3 c 0 3 d 0 3 e 0 3 f 0>;
  89. interrupt-parent = <&mpc5200_pic>;
  90. };
  91. xlb@1f00 {
  92. compatible = "mpc5200-xlb";
  93. reg = <1f00 100>;
  94. };
  95. serial@2000 { // PSC1
  96. device_type = "serial";
  97. compatible = "mpc5200-psc-uart";
  98. port-number = <0>; // Logical port assignment
  99. reg = <2000 100>;
  100. interrupts = <2 1 0>;
  101. interrupt-parent = <&mpc5200_pic>;
  102. };
  103. serial@2200 { // PSC2
  104. device_type = "serial";
  105. compatible = "mpc5200-psc-uart";
  106. port-number = <1>; // Logical port assignment
  107. reg = <2200 100>;
  108. interrupts = <2 2 0>;
  109. interrupt-parent = <&mpc5200_pic>;
  110. };
  111. serial@2400 { // PSC3
  112. device_type = "serial";
  113. compatible = "mpc5200-psc-uart";
  114. port-number = <2>; // Logical port assignment
  115. reg = <2400 100>;
  116. interrupts = <2 3 0>;
  117. interrupt-parent = <&mpc5200_pic>;
  118. };
  119. ethernet@3000 {
  120. device_type = "network";
  121. compatible = "mpc5200-fec";
  122. reg = <3000 800>;
  123. local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */
  124. interrupts = <2 5 0>;
  125. interrupt-parent = <&mpc5200_pic>;
  126. };
  127. ata@3a00 {
  128. compatible = "mpc5200-ata";
  129. reg = <3a00 100>;
  130. interrupts = <2 7 0>;
  131. interrupt-parent = <&mpc5200_pic>;
  132. };
  133. i2c@3d40 {
  134. compatible = "mpc5200-i2c","fsl-i2c";
  135. reg = <3d40 40>;
  136. interrupts = <2 10 0>;
  137. interrupt-parent = <&mpc5200_pic>;
  138. fsl5200-clocking;
  139. };
  140. sram@8000 {
  141. compatible = "mpc5200-sram";
  142. reg = <8000 4000>;
  143. };
  144. };
  145. pci@f0000d00 {
  146. #interrupt-cells = <1>;
  147. #size-cells = <2>;
  148. #address-cells = <3>;
  149. device_type = "pci";
  150. compatible = "fsl,mpc5200-pci";
  151. reg = <f0000d00 100>;
  152. interrupt-map-mask = <f800 0 0 7>;
  153. interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
  154. c000 0 0 2 &mpc5200_pic 0 0 3
  155. c000 0 0 3 &mpc5200_pic 0 0 3
  156. c000 0 0 4 &mpc5200_pic 0 0 3>;
  157. clock-frequency = <0>; // From boot loader
  158. interrupts = <2 8 0 2 9 0 2 a 0>;
  159. interrupt-parent = <&mpc5200_pic>;
  160. bus-range = <0 0>;
  161. ranges = <42000000 0 80000000 80000000 0 10000000
  162. 02000000 0 90000000 90000000 0 10000000
  163. 01000000 0 00000000 a0000000 0 01000000>;
  164. };
  165. };