tifm_sd.c 25 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.8"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
  34. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  35. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  36. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  37. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  38. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  39. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  40. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  41. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  42. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  43. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  44. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  45. #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
  46. #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
  47. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  48. #define TIFM_MMCSD_RSP_R0 0x0000
  49. #define TIFM_MMCSD_RSP_R1 0x0100
  50. #define TIFM_MMCSD_RSP_R2 0x0200
  51. #define TIFM_MMCSD_RSP_R3 0x0300
  52. #define TIFM_MMCSD_RSP_R4 0x0400
  53. #define TIFM_MMCSD_RSP_R5 0x0500
  54. #define TIFM_MMCSD_RSP_R6 0x0600
  55. #define TIFM_MMCSD_RSP_BUSY 0x0800
  56. #define TIFM_MMCSD_CMD_BC 0x0000
  57. #define TIFM_MMCSD_CMD_BCR 0x1000
  58. #define TIFM_MMCSD_CMD_AC 0x2000
  59. #define TIFM_MMCSD_CMD_ADTC 0x3000
  60. enum {
  61. CMD_READY = 0x0001,
  62. FIFO_READY = 0x0002,
  63. BRS_READY = 0x0004,
  64. SCMD_ACTIVE = 0x0008,
  65. SCMD_READY = 0x0010,
  66. CARD_BUSY = 0x0020,
  67. DATA_CARRY = 0x0040
  68. };
  69. struct tifm_sd {
  70. struct tifm_dev *dev;
  71. unsigned short eject:1,
  72. open_drain:1,
  73. no_dma:1;
  74. unsigned short cmd_flags;
  75. unsigned int clk_freq;
  76. unsigned int clk_div;
  77. unsigned long timeout_jiffies;
  78. struct tasklet_struct finish_tasklet;
  79. struct timer_list timer;
  80. struct mmc_request *req;
  81. size_t written_blocks;
  82. size_t buffer_size;
  83. size_t buffer_pos;
  84. };
  85. static char* tifm_sd_data_buffer(struct mmc_data *data)
  86. {
  87. return page_address(data->sg->page) + data->sg->offset;
  88. }
  89. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  90. unsigned int host_status)
  91. {
  92. struct mmc_command *cmd = host->req->cmd;
  93. unsigned int t_val = 0, cnt = 0;
  94. char *buffer;
  95. if (host_status & TIFM_MMCSD_BRS) {
  96. /* in non-dma rx mode BRS fires when fifo is still not empty */
  97. if (host->no_dma && (cmd->data->flags & MMC_DATA_READ)) {
  98. buffer = tifm_sd_data_buffer(host->req->data);
  99. while (host->buffer_size > host->buffer_pos) {
  100. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  101. buffer[host->buffer_pos++] = t_val & 0xff;
  102. buffer[host->buffer_pos++] =
  103. (t_val >> 8) & 0xff;
  104. }
  105. }
  106. return 1;
  107. } else if (host->no_dma) {
  108. buffer = tifm_sd_data_buffer(host->req->data);
  109. if ((cmd->data->flags & MMC_DATA_READ) &&
  110. (host_status & TIFM_MMCSD_AF)) {
  111. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  112. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  113. if (host->buffer_size > host->buffer_pos) {
  114. buffer[host->buffer_pos++] =
  115. t_val & 0xff;
  116. buffer[host->buffer_pos++] =
  117. (t_val >> 8) & 0xff;
  118. }
  119. }
  120. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  121. && (host_status & TIFM_MMCSD_AE)) {
  122. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  123. if (host->buffer_size > host->buffer_pos) {
  124. t_val = buffer[host->buffer_pos++]
  125. & 0x00ff;
  126. t_val |= ((buffer[host->buffer_pos++])
  127. << 8) & 0xff00;
  128. writel(t_val,
  129. sock->addr + SOCK_MMCSD_DATA);
  130. }
  131. }
  132. }
  133. }
  134. return 0;
  135. }
  136. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  137. {
  138. unsigned int rc = 0;
  139. switch (mmc_resp_type(cmd)) {
  140. case MMC_RSP_NONE:
  141. rc |= TIFM_MMCSD_RSP_R0;
  142. break;
  143. case MMC_RSP_R1B:
  144. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  145. case MMC_RSP_R1:
  146. rc |= TIFM_MMCSD_RSP_R1;
  147. break;
  148. case MMC_RSP_R2:
  149. rc |= TIFM_MMCSD_RSP_R2;
  150. break;
  151. case MMC_RSP_R3:
  152. rc |= TIFM_MMCSD_RSP_R3;
  153. break;
  154. default:
  155. BUG();
  156. }
  157. switch (mmc_cmd_type(cmd)) {
  158. case MMC_CMD_BC:
  159. rc |= TIFM_MMCSD_CMD_BC;
  160. break;
  161. case MMC_CMD_BCR:
  162. rc |= TIFM_MMCSD_CMD_BCR;
  163. break;
  164. case MMC_CMD_AC:
  165. rc |= TIFM_MMCSD_CMD_AC;
  166. break;
  167. case MMC_CMD_ADTC:
  168. rc |= TIFM_MMCSD_CMD_ADTC;
  169. break;
  170. default:
  171. BUG();
  172. }
  173. return rc;
  174. }
  175. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  176. {
  177. struct tifm_dev *sock = host->dev;
  178. unsigned int cmd_mask = tifm_sd_op_flags(cmd);
  179. if (host->open_drain)
  180. cmd_mask |= TIFM_MMCSD_ODTO;
  181. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  182. cmd_mask |= TIFM_MMCSD_READ;
  183. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  184. cmd->opcode, cmd->arg, cmd_mask);
  185. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  186. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  187. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  188. }
  189. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  190. {
  191. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  192. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  193. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  194. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  195. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  196. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  197. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  198. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  199. }
  200. static void tifm_sd_check_status(struct tifm_sd *host)
  201. {
  202. struct tifm_dev *sock = host->dev;
  203. struct mmc_command *cmd = host->req->cmd;
  204. if (cmd->error != MMC_ERR_NONE)
  205. goto finish_request;
  206. if (!(host->cmd_flags & CMD_READY))
  207. return;
  208. if (cmd->data) {
  209. if (cmd->data->error != MMC_ERR_NONE) {
  210. if ((host->cmd_flags & SCMD_ACTIVE)
  211. && !(host->cmd_flags & SCMD_READY))
  212. return;
  213. goto finish_request;
  214. }
  215. if (!(host->cmd_flags & BRS_READY))
  216. return;
  217. if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
  218. return;
  219. if (cmd->data->flags & MMC_DATA_WRITE) {
  220. if (host->req->stop) {
  221. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  222. host->cmd_flags |= SCMD_ACTIVE;
  223. writel(TIFM_MMCSD_EOFB
  224. | readl(sock->addr
  225. + SOCK_MMCSD_INT_ENABLE),
  226. sock->addr
  227. + SOCK_MMCSD_INT_ENABLE);
  228. tifm_sd_exec(host, host->req->stop);
  229. return;
  230. } else {
  231. if (!(host->cmd_flags & SCMD_READY)
  232. || (host->cmd_flags & CARD_BUSY))
  233. return;
  234. writel((~TIFM_MMCSD_EOFB)
  235. & readl(sock->addr
  236. + SOCK_MMCSD_INT_ENABLE),
  237. sock->addr
  238. + SOCK_MMCSD_INT_ENABLE);
  239. }
  240. } else {
  241. if (host->cmd_flags & CARD_BUSY)
  242. return;
  243. writel((~TIFM_MMCSD_EOFB)
  244. & readl(sock->addr
  245. + SOCK_MMCSD_INT_ENABLE),
  246. sock->addr + SOCK_MMCSD_INT_ENABLE);
  247. }
  248. } else {
  249. if (host->req->stop) {
  250. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  251. host->cmd_flags |= SCMD_ACTIVE;
  252. tifm_sd_exec(host, host->req->stop);
  253. return;
  254. } else {
  255. if (!(host->cmd_flags & SCMD_READY))
  256. return;
  257. }
  258. }
  259. }
  260. }
  261. finish_request:
  262. tasklet_schedule(&host->finish_tasklet);
  263. }
  264. /* Called from interrupt handler */
  265. static void tifm_sd_data_event(struct tifm_dev *sock)
  266. {
  267. struct tifm_sd *host;
  268. unsigned int fifo_status = 0;
  269. struct mmc_data *r_data = NULL;
  270. spin_lock(&sock->lock);
  271. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  272. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  273. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  274. fifo_status, host->cmd_flags);
  275. if (host->req) {
  276. r_data = host->req->cmd->data;
  277. if (r_data && (fifo_status & TIFM_FIFO_READY)) {
  278. host->cmd_flags |= FIFO_READY;
  279. tifm_sd_check_status(host);
  280. }
  281. }
  282. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  283. spin_unlock(&sock->lock);
  284. }
  285. /* Called from interrupt handler */
  286. static void tifm_sd_card_event(struct tifm_dev *sock)
  287. {
  288. struct tifm_sd *host;
  289. unsigned int host_status = 0;
  290. int cmd_error = MMC_ERR_NONE;
  291. struct mmc_command *cmd = NULL;
  292. unsigned long flags;
  293. spin_lock(&sock->lock);
  294. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  295. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  296. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  297. host_status, host->cmd_flags);
  298. if (host->req) {
  299. cmd = host->req->cmd;
  300. if (host_status & TIFM_MMCSD_ERRMASK) {
  301. writel(host_status & TIFM_MMCSD_ERRMASK,
  302. sock->addr + SOCK_MMCSD_STATUS);
  303. if (host_status & TIFM_MMCSD_CTO)
  304. cmd_error = MMC_ERR_TIMEOUT;
  305. else if (host_status & TIFM_MMCSD_CCRC)
  306. cmd_error = MMC_ERR_BADCRC;
  307. if (cmd->data) {
  308. if (host_status & TIFM_MMCSD_DTO)
  309. cmd->data->error = MMC_ERR_TIMEOUT;
  310. else if (host_status & TIFM_MMCSD_DCRC)
  311. cmd->data->error = MMC_ERR_BADCRC;
  312. }
  313. writel(TIFM_FIFO_INT_SETALL,
  314. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  315. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  316. if (host->req->stop) {
  317. if (host->cmd_flags & SCMD_ACTIVE) {
  318. host->req->stop->error = cmd_error;
  319. host->cmd_flags |= SCMD_READY;
  320. } else {
  321. cmd->error = cmd_error;
  322. host->cmd_flags |= SCMD_ACTIVE;
  323. tifm_sd_exec(host, host->req->stop);
  324. goto done;
  325. }
  326. } else
  327. cmd->error = cmd_error;
  328. } else {
  329. if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
  330. if (!(host->cmd_flags & CMD_READY)) {
  331. host->cmd_flags |= CMD_READY;
  332. tifm_sd_fetch_resp(cmd, sock);
  333. } else if (host->cmd_flags & SCMD_ACTIVE) {
  334. host->cmd_flags |= SCMD_READY;
  335. tifm_sd_fetch_resp(host->req->stop,
  336. sock);
  337. }
  338. }
  339. if (host_status & TIFM_MMCSD_BRS)
  340. host->cmd_flags |= BRS_READY;
  341. }
  342. if (host->no_dma && cmd->data) {
  343. if (host_status & TIFM_MMCSD_AE)
  344. writel(host_status & TIFM_MMCSD_AE,
  345. sock->addr + SOCK_MMCSD_STATUS);
  346. if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
  347. | TIFM_MMCSD_BRS)) {
  348. local_irq_save(flags);
  349. tifm_sd_transfer_data(sock, host, host_status);
  350. local_irq_restore(flags);
  351. host_status &= ~TIFM_MMCSD_AE;
  352. }
  353. }
  354. if (host_status & TIFM_MMCSD_EOFB)
  355. host->cmd_flags &= ~CARD_BUSY;
  356. else if (host_status & TIFM_MMCSD_CB)
  357. host->cmd_flags |= CARD_BUSY;
  358. tifm_sd_check_status(host);
  359. }
  360. done:
  361. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  362. spin_unlock(&sock->lock);
  363. }
  364. static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
  365. {
  366. struct tifm_dev *sock = host->dev;
  367. unsigned int dest_cnt;
  368. /* DMA style IO */
  369. dev_dbg(&sock->dev, "setting dma for %d blocks\n",
  370. cmd->data->blocks);
  371. writel(TIFM_FIFO_INT_SETALL,
  372. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  373. writel(ilog2(cmd->data->blksz) - 2,
  374. sock->addr + SOCK_FIFO_PAGE_SIZE);
  375. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  376. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  377. dest_cnt = (cmd->data->blocks) << 8;
  378. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  379. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  380. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  381. if (cmd->data->flags & MMC_DATA_WRITE) {
  382. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  383. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  384. sock->addr + SOCK_DMA_CONTROL);
  385. } else {
  386. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  387. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  388. }
  389. }
  390. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  391. struct mmc_data *data)
  392. {
  393. struct tifm_dev *sock = host->dev;
  394. unsigned int data_timeout = data->timeout_clks;
  395. if (fixed_timeout)
  396. return;
  397. data_timeout += data->timeout_ns /
  398. ((1000000000UL / host->clk_freq) * host->clk_div);
  399. if (data_timeout < 0xffff) {
  400. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  401. writel((~TIFM_MMCSD_DPE)
  402. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  403. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  404. } else {
  405. data_timeout = (data_timeout >> 10) + 1;
  406. if (data_timeout > 0xffff)
  407. data_timeout = 0; /* set to unlimited */
  408. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  409. writel(TIFM_MMCSD_DPE
  410. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  411. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  412. }
  413. }
  414. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  415. {
  416. struct tifm_sd *host = mmc_priv(mmc);
  417. struct tifm_dev *sock = host->dev;
  418. unsigned long flags;
  419. int sg_count = 0;
  420. struct mmc_data *r_data = mrq->cmd->data;
  421. spin_lock_irqsave(&sock->lock, flags);
  422. if (host->eject) {
  423. spin_unlock_irqrestore(&sock->lock, flags);
  424. goto err_out;
  425. }
  426. if (host->req) {
  427. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  428. spin_unlock_irqrestore(&sock->lock, flags);
  429. goto err_out;
  430. }
  431. if (r_data) {
  432. tifm_sd_set_data_timeout(host, r_data);
  433. if (host->no_dma) {
  434. host->buffer_size = mrq->cmd->data->blocks
  435. * mrq->cmd->data->blksz;
  436. writel(TIFM_MMCSD_BUFINT
  437. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  438. sock->addr + SOCK_MMCSD_INT_ENABLE);
  439. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  440. | (TIFM_MMCSD_FIFO_SIZE - 1),
  441. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  442. host->written_blocks = 0;
  443. host->cmd_flags &= ~CARD_BUSY;
  444. host->buffer_pos = 0;
  445. writel(r_data->blocks - 1,
  446. sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  447. writel(r_data->blksz - 1,
  448. sock->addr + SOCK_MMCSD_BLOCK_LEN);
  449. } else {
  450. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  451. mrq->cmd->flags & MMC_DATA_WRITE
  452. ? PCI_DMA_TODEVICE
  453. : PCI_DMA_FROMDEVICE);
  454. if (sg_count != 1) {
  455. printk(KERN_ERR DRIVER_NAME
  456. ": scatterlist map failed\n");
  457. spin_unlock_irqrestore(&sock->lock, flags);
  458. goto err_out;
  459. }
  460. host->written_blocks = 0;
  461. host->cmd_flags &= ~CARD_BUSY;
  462. tifm_sd_prepare_data(host, mrq->cmd);
  463. }
  464. }
  465. host->req = mrq;
  466. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  467. host->cmd_flags = 0;
  468. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  469. sock->addr + SOCK_CONTROL);
  470. tifm_sd_exec(host, mrq->cmd);
  471. spin_unlock_irqrestore(&sock->lock, flags);
  472. return;
  473. err_out:
  474. if (sg_count > 0)
  475. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  476. (r_data->flags & MMC_DATA_WRITE)
  477. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  478. mrq->cmd->error = MMC_ERR_TIMEOUT;
  479. mmc_request_done(mmc, mrq);
  480. }
  481. static void tifm_sd_end_cmd(unsigned long data)
  482. {
  483. struct tifm_sd *host = (struct tifm_sd*)data;
  484. struct tifm_dev *sock = host->dev;
  485. struct mmc_host *mmc = tifm_get_drvdata(sock);
  486. struct mmc_request *mrq;
  487. struct mmc_data *r_data = NULL;
  488. unsigned long flags;
  489. spin_lock_irqsave(&sock->lock, flags);
  490. del_timer(&host->timer);
  491. mrq = host->req;
  492. host->req = NULL;
  493. if (!mrq) {
  494. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  495. spin_unlock_irqrestore(&sock->lock, flags);
  496. return;
  497. }
  498. r_data = mrq->cmd->data;
  499. if (r_data) {
  500. if (host->no_dma) {
  501. writel((~TIFM_MMCSD_BUFINT) &
  502. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  503. sock->addr + SOCK_MMCSD_INT_ENABLE);
  504. if (r_data->flags & MMC_DATA_WRITE) {
  505. r_data->bytes_xfered = host->written_blocks
  506. * r_data->blksz;
  507. } else {
  508. r_data->bytes_xfered = r_data->blocks -
  509. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS)
  510. - 1;
  511. r_data->bytes_xfered *= r_data->blksz;
  512. r_data->bytes_xfered += r_data->blksz
  513. - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN)
  514. + 1;
  515. }
  516. host->buffer_pos = 0;
  517. host->buffer_size = 0;
  518. } else {
  519. if (r_data->flags & MMC_DATA_WRITE) {
  520. r_data->bytes_xfered = host->written_blocks
  521. * r_data->blksz;
  522. } else {
  523. r_data->bytes_xfered = r_data->blocks -
  524. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  525. r_data->bytes_xfered *= r_data->blksz;
  526. r_data->bytes_xfered += r_data->blksz -
  527. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN)
  528. + 1;
  529. }
  530. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  531. (r_data->flags & MMC_DATA_WRITE)
  532. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  533. }
  534. }
  535. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  536. sock->addr + SOCK_CONTROL);
  537. spin_unlock_irqrestore(&sock->lock, flags);
  538. mmc_request_done(mmc, mrq);
  539. }
  540. static void tifm_sd_abort(unsigned long data)
  541. {
  542. struct tifm_sd *host = (struct tifm_sd*)data;
  543. printk(KERN_ERR DRIVER_NAME
  544. ": card failed to respond for a long period of time\n");
  545. tifm_eject(host->dev);
  546. }
  547. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  548. {
  549. struct tifm_sd *host = mmc_priv(mmc);
  550. struct tifm_dev *sock = host->dev;
  551. unsigned int clk_div1, clk_div2;
  552. unsigned long flags;
  553. spin_lock_irqsave(&sock->lock, flags);
  554. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  555. ios->power_mode);
  556. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  557. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  558. sock->addr + SOCK_MMCSD_CONFIG);
  559. } else {
  560. writel((~TIFM_MMCSD_4BBUS)
  561. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  562. sock->addr + SOCK_MMCSD_CONFIG);
  563. }
  564. if (ios->clock) {
  565. clk_div1 = 20000000 / ios->clock;
  566. if (!clk_div1)
  567. clk_div1 = 1;
  568. clk_div2 = 24000000 / ios->clock;
  569. if (!clk_div2)
  570. clk_div2 = 1;
  571. if ((20000000 / clk_div1) > ios->clock)
  572. clk_div1++;
  573. if ((24000000 / clk_div2) > ios->clock)
  574. clk_div2++;
  575. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  576. host->clk_freq = 20000000;
  577. host->clk_div = clk_div1;
  578. writel((~TIFM_CTRL_FAST_CLK)
  579. & readl(sock->addr + SOCK_CONTROL),
  580. sock->addr + SOCK_CONTROL);
  581. } else {
  582. host->clk_freq = 24000000;
  583. host->clk_div = clk_div2;
  584. writel(TIFM_CTRL_FAST_CLK
  585. | readl(sock->addr + SOCK_CONTROL),
  586. sock->addr + SOCK_CONTROL);
  587. }
  588. } else {
  589. host->clk_div = 0;
  590. }
  591. host->clk_div &= TIFM_MMCSD_CLKMASK;
  592. writel(host->clk_div
  593. | ((~TIFM_MMCSD_CLKMASK)
  594. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  595. sock->addr + SOCK_MMCSD_CONFIG);
  596. host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
  597. /* chip_select : maybe later */
  598. //vdd
  599. //power is set before probe / after remove
  600. spin_unlock_irqrestore(&sock->lock, flags);
  601. }
  602. static int tifm_sd_ro(struct mmc_host *mmc)
  603. {
  604. int rc = 0;
  605. struct tifm_sd *host = mmc_priv(mmc);
  606. struct tifm_dev *sock = host->dev;
  607. unsigned long flags;
  608. spin_lock_irqsave(&sock->lock, flags);
  609. if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
  610. rc = 1;
  611. spin_unlock_irqrestore(&sock->lock, flags);
  612. return rc;
  613. }
  614. static const struct mmc_host_ops tifm_sd_ops = {
  615. .request = tifm_sd_request,
  616. .set_ios = tifm_sd_ios,
  617. .get_ro = tifm_sd_ro
  618. };
  619. static int tifm_sd_initialize_host(struct tifm_sd *host)
  620. {
  621. int rc;
  622. unsigned int host_status = 0;
  623. struct tifm_dev *sock = host->dev;
  624. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  625. mmiowb();
  626. host->clk_div = 61;
  627. host->clk_freq = 20000000;
  628. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  629. writel(host->clk_div | TIFM_MMCSD_POWER,
  630. sock->addr + SOCK_MMCSD_CONFIG);
  631. /* wait up to 0.51 sec for reset */
  632. for (rc = 32; rc <= 256; rc <<= 1) {
  633. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  634. rc = 0;
  635. break;
  636. }
  637. msleep(rc);
  638. }
  639. if (rc) {
  640. printk(KERN_ERR "%s : controller failed to reset\n",
  641. sock->dev.bus_id);
  642. return -ENODEV;
  643. }
  644. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  645. writel(host->clk_div | TIFM_MMCSD_POWER,
  646. sock->addr + SOCK_MMCSD_CONFIG);
  647. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  648. // command timeout fixed to 64 clocks for now
  649. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  650. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  651. for (rc = 16; rc <= 64; rc <<= 1) {
  652. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  653. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  654. if (!(host_status & TIFM_MMCSD_ERRMASK)
  655. && (host_status & TIFM_MMCSD_EOC)) {
  656. rc = 0;
  657. break;
  658. }
  659. msleep(rc);
  660. }
  661. if (rc) {
  662. printk(KERN_ERR
  663. "%s : card not ready - probe failed on initialization\n",
  664. sock->dev.bus_id);
  665. return -ENODEV;
  666. }
  667. writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
  668. | TIFM_MMCSD_ERRMASK,
  669. sock->addr + SOCK_MMCSD_INT_ENABLE);
  670. mmiowb();
  671. return 0;
  672. }
  673. static int tifm_sd_probe(struct tifm_dev *sock)
  674. {
  675. struct mmc_host *mmc;
  676. struct tifm_sd *host;
  677. int rc = -EIO;
  678. if (!(TIFM_SOCK_STATE_OCCUPIED
  679. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  680. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  681. return rc;
  682. }
  683. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  684. if (!mmc)
  685. return -ENOMEM;
  686. host = mmc_priv(mmc);
  687. host->no_dma = no_dma;
  688. tifm_set_drvdata(sock, mmc);
  689. host->dev = sock;
  690. host->timeout_jiffies = msecs_to_jiffies(1000);
  691. tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
  692. (unsigned long)host);
  693. setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
  694. mmc->ops = &tifm_sd_ops;
  695. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  696. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
  697. mmc->f_min = 20000000 / 60;
  698. mmc->f_max = 24000000;
  699. mmc->max_hw_segs = 1;
  700. mmc->max_phys_segs = 1;
  701. // limited by DMA counter - it's safer to stick with
  702. // block counter has 11 bits though
  703. mmc->max_blk_count = 256;
  704. // 2k maximum hw block length
  705. mmc->max_blk_size = 2048;
  706. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  707. mmc->max_seg_size = mmc->max_req_size;
  708. sock->card_event = tifm_sd_card_event;
  709. sock->data_event = tifm_sd_data_event;
  710. rc = tifm_sd_initialize_host(host);
  711. if (!rc)
  712. rc = mmc_add_host(mmc);
  713. if (rc)
  714. goto out_free_mmc;
  715. return 0;
  716. out_free_mmc:
  717. mmc_free_host(mmc);
  718. return rc;
  719. }
  720. static void tifm_sd_remove(struct tifm_dev *sock)
  721. {
  722. struct mmc_host *mmc = tifm_get_drvdata(sock);
  723. struct tifm_sd *host = mmc_priv(mmc);
  724. unsigned long flags;
  725. spin_lock_irqsave(&sock->lock, flags);
  726. host->eject = 1;
  727. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  728. mmiowb();
  729. spin_unlock_irqrestore(&sock->lock, flags);
  730. tasklet_kill(&host->finish_tasklet);
  731. spin_lock_irqsave(&sock->lock, flags);
  732. if (host->req) {
  733. writel(TIFM_FIFO_INT_SETALL,
  734. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  735. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  736. host->req->cmd->error = MMC_ERR_TIMEOUT;
  737. if (host->req->stop)
  738. host->req->stop->error = MMC_ERR_TIMEOUT;
  739. tasklet_schedule(&host->finish_tasklet);
  740. }
  741. spin_unlock_irqrestore(&sock->lock, flags);
  742. mmc_remove_host(mmc);
  743. dev_dbg(&sock->dev, "after remove\n");
  744. /* The meaning of the bit majority in this constant is unknown. */
  745. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  746. sock->addr + SOCK_CONTROL);
  747. mmc_free_host(mmc);
  748. }
  749. #ifdef CONFIG_PM
  750. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  751. {
  752. struct mmc_host *mmc = tifm_get_drvdata(sock);
  753. int rc;
  754. rc = mmc_suspend_host(mmc, state);
  755. /* The meaning of the bit majority in this constant is unknown. */
  756. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  757. sock->addr + SOCK_CONTROL);
  758. return rc;
  759. }
  760. static int tifm_sd_resume(struct tifm_dev *sock)
  761. {
  762. struct mmc_host *mmc = tifm_get_drvdata(sock);
  763. struct tifm_sd *host = mmc_priv(mmc);
  764. int rc;
  765. rc = tifm_sd_initialize_host(host);
  766. dev_dbg(&sock->dev, "resume initialize %d\n", rc);
  767. if (rc)
  768. host->eject = 1;
  769. else
  770. rc = mmc_resume_host(mmc);
  771. return rc;
  772. }
  773. #else
  774. #define tifm_sd_suspend NULL
  775. #define tifm_sd_resume NULL
  776. #endif /* CONFIG_PM */
  777. static struct tifm_device_id tifm_sd_id_tbl[] = {
  778. { TIFM_TYPE_SD }, { }
  779. };
  780. static struct tifm_driver tifm_sd_driver = {
  781. .driver = {
  782. .name = DRIVER_NAME,
  783. .owner = THIS_MODULE
  784. },
  785. .id_table = tifm_sd_id_tbl,
  786. .probe = tifm_sd_probe,
  787. .remove = tifm_sd_remove,
  788. .suspend = tifm_sd_suspend,
  789. .resume = tifm_sd_resume
  790. };
  791. static int __init tifm_sd_init(void)
  792. {
  793. return tifm_register_driver(&tifm_sd_driver);
  794. }
  795. static void __exit tifm_sd_exit(void)
  796. {
  797. tifm_unregister_driver(&tifm_sd_driver);
  798. }
  799. MODULE_AUTHOR("Alex Dubov");
  800. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  801. MODULE_LICENSE("GPL");
  802. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  803. MODULE_VERSION(DRIVER_VERSION);
  804. module_init(tifm_sd_init);
  805. module_exit(tifm_sd_exit);