bfin_dma_5xx.c 23 KB

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  1. /*
  2. * File: arch/blackfin/kernel/bfin_dma_5xx.c
  3. * Based on:
  4. * Author:
  5. *
  6. * Created:
  7. * Description: This file contains the simple DMA Implementation for Blackfin
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/errno.h>
  30. #include <linux/module.h>
  31. #include <linux/sched.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/kernel.h>
  34. #include <linux/param.h>
  35. #include <asm/blackfin.h>
  36. #include <asm/dma.h>
  37. #include <asm/cacheflush.h>
  38. /**************************************************************************
  39. * Global Variables
  40. ***************************************************************************/
  41. static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
  42. /*------------------------------------------------------------------------------
  43. * Set the Buffer Clear bit in the Configuration register of specific DMA
  44. * channel. This will stop the descriptor based DMA operation.
  45. *-----------------------------------------------------------------------------*/
  46. static void clear_dma_buffer(unsigned int channel)
  47. {
  48. dma_ch[channel].regs->cfg |= RESTART;
  49. SSYNC();
  50. dma_ch[channel].regs->cfg &= ~RESTART;
  51. SSYNC();
  52. }
  53. static int __init blackfin_dma_init(void)
  54. {
  55. int i;
  56. printk(KERN_INFO "Blackfin DMA Controller\n");
  57. for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
  58. dma_ch[i].chan_status = DMA_CHANNEL_FREE;
  59. dma_ch[i].regs = dma_io_base_addr[i];
  60. mutex_init(&(dma_ch[i].dmalock));
  61. }
  62. /* Mark MEMDMA Channel 0 as requested since we're using it internally */
  63. dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED;
  64. dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED;
  65. #if defined(CONFIG_DEB_DMA_URGENT)
  66. bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
  67. | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
  68. #endif
  69. return 0;
  70. }
  71. arch_initcall(blackfin_dma_init);
  72. /*------------------------------------------------------------------------------
  73. * Request the specific DMA channel from the system.
  74. *-----------------------------------------------------------------------------*/
  75. int request_dma(unsigned int channel, char *device_id)
  76. {
  77. pr_debug("request_dma() : BEGIN \n");
  78. #if defined(CONFIG_BF561) && ANOMALY_05000182
  79. if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
  80. if (get_cclk() > 500000000) {
  81. printk(KERN_WARNING
  82. "Request IMDMA failed due to ANOMALY 05000182\n");
  83. return -EFAULT;
  84. }
  85. }
  86. #endif
  87. mutex_lock(&(dma_ch[channel].dmalock));
  88. if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
  89. || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
  90. mutex_unlock(&(dma_ch[channel].dmalock));
  91. pr_debug("DMA CHANNEL IN USE \n");
  92. return -EBUSY;
  93. } else {
  94. dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
  95. pr_debug("DMA CHANNEL IS ALLOCATED \n");
  96. }
  97. mutex_unlock(&(dma_ch[channel].dmalock));
  98. #ifdef CONFIG_BF54x
  99. if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
  100. unsigned int per_map;
  101. per_map = dma_ch[channel].regs->peripheral_map & 0xFFF;
  102. if (strncmp(device_id, "BFIN_UART", 9) == 0)
  103. dma_ch[channel].regs->peripheral_map = per_map |
  104. ((channel - CH_UART2_RX + 0xC)<<12);
  105. else
  106. dma_ch[channel].regs->peripheral_map = per_map |
  107. ((channel - CH_UART2_RX + 0x6)<<12);
  108. }
  109. #endif
  110. dma_ch[channel].device_id = device_id;
  111. dma_ch[channel].irq_callback = NULL;
  112. /* This is to be enabled by putting a restriction -
  113. * you have to request DMA, before doing any operations on
  114. * descriptor/channel
  115. */
  116. pr_debug("request_dma() : END \n");
  117. return channel;
  118. }
  119. EXPORT_SYMBOL(request_dma);
  120. int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
  121. {
  122. int ret_irq = 0;
  123. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  124. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  125. if (callback != NULL) {
  126. int ret_val;
  127. ret_irq = channel2irq(channel);
  128. dma_ch[channel].data = data;
  129. ret_val =
  130. request_irq(ret_irq, (void *)callback, IRQF_DISABLED,
  131. dma_ch[channel].device_id, data);
  132. if (ret_val) {
  133. printk(KERN_NOTICE
  134. "Request irq in DMA engine failed.\n");
  135. return -EPERM;
  136. }
  137. dma_ch[channel].irq_callback = callback;
  138. }
  139. return 0;
  140. }
  141. EXPORT_SYMBOL(set_dma_callback);
  142. void free_dma(unsigned int channel)
  143. {
  144. int ret_irq;
  145. pr_debug("freedma() : BEGIN \n");
  146. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  147. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  148. /* Halt the DMA */
  149. disable_dma(channel);
  150. clear_dma_buffer(channel);
  151. if (dma_ch[channel].irq_callback != NULL) {
  152. ret_irq = channel2irq(channel);
  153. free_irq(ret_irq, dma_ch[channel].data);
  154. }
  155. /* Clear the DMA Variable in the Channel */
  156. mutex_lock(&(dma_ch[channel].dmalock));
  157. dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
  158. mutex_unlock(&(dma_ch[channel].dmalock));
  159. pr_debug("freedma() : END \n");
  160. }
  161. EXPORT_SYMBOL(free_dma);
  162. void dma_enable_irq(unsigned int channel)
  163. {
  164. int ret_irq;
  165. pr_debug("dma_enable_irq() : BEGIN \n");
  166. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  167. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  168. ret_irq = channel2irq(channel);
  169. enable_irq(ret_irq);
  170. }
  171. EXPORT_SYMBOL(dma_enable_irq);
  172. void dma_disable_irq(unsigned int channel)
  173. {
  174. int ret_irq;
  175. pr_debug("dma_disable_irq() : BEGIN \n");
  176. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  177. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  178. ret_irq = channel2irq(channel);
  179. disable_irq(ret_irq);
  180. }
  181. EXPORT_SYMBOL(dma_disable_irq);
  182. int dma_channel_active(unsigned int channel)
  183. {
  184. if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) {
  185. return 0;
  186. } else {
  187. return 1;
  188. }
  189. }
  190. EXPORT_SYMBOL(dma_channel_active);
  191. /*------------------------------------------------------------------------------
  192. * stop the specific DMA channel.
  193. *-----------------------------------------------------------------------------*/
  194. void disable_dma(unsigned int channel)
  195. {
  196. pr_debug("stop_dma() : BEGIN \n");
  197. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  198. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  199. dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
  200. SSYNC();
  201. dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
  202. /* Needs to be enabled Later */
  203. pr_debug("stop_dma() : END \n");
  204. return;
  205. }
  206. EXPORT_SYMBOL(disable_dma);
  207. void enable_dma(unsigned int channel)
  208. {
  209. pr_debug("enable_dma() : BEGIN \n");
  210. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  211. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  212. dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
  213. dma_ch[channel].regs->curr_x_count = 0;
  214. dma_ch[channel].regs->curr_y_count = 0;
  215. dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
  216. SSYNC();
  217. pr_debug("enable_dma() : END \n");
  218. return;
  219. }
  220. EXPORT_SYMBOL(enable_dma);
  221. /*------------------------------------------------------------------------------
  222. * Set the Start Address register for the specific DMA channel
  223. * This function can be used for register based DMA,
  224. * to setup the start address
  225. * addr: Starting address of the DMA Data to be transferred.
  226. *-----------------------------------------------------------------------------*/
  227. void set_dma_start_addr(unsigned int channel, unsigned long addr)
  228. {
  229. pr_debug("set_dma_start_addr() : BEGIN \n");
  230. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  231. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  232. dma_ch[channel].regs->start_addr = addr;
  233. SSYNC();
  234. pr_debug("set_dma_start_addr() : END\n");
  235. }
  236. EXPORT_SYMBOL(set_dma_start_addr);
  237. void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
  238. {
  239. pr_debug("set_dma_next_desc_addr() : BEGIN \n");
  240. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  241. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  242. dma_ch[channel].regs->next_desc_ptr = addr;
  243. SSYNC();
  244. pr_debug("set_dma_next_desc_addr() : END\n");
  245. }
  246. EXPORT_SYMBOL(set_dma_next_desc_addr);
  247. void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr)
  248. {
  249. pr_debug("set_dma_curr_desc_addr() : BEGIN \n");
  250. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  251. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  252. dma_ch[channel].regs->curr_desc_ptr = addr;
  253. SSYNC();
  254. pr_debug("set_dma_curr_desc_addr() : END\n");
  255. }
  256. EXPORT_SYMBOL(set_dma_curr_desc_addr);
  257. void set_dma_x_count(unsigned int channel, unsigned short x_count)
  258. {
  259. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  260. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  261. dma_ch[channel].regs->x_count = x_count;
  262. SSYNC();
  263. }
  264. EXPORT_SYMBOL(set_dma_x_count);
  265. void set_dma_y_count(unsigned int channel, unsigned short y_count)
  266. {
  267. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  268. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  269. dma_ch[channel].regs->y_count = y_count;
  270. SSYNC();
  271. }
  272. EXPORT_SYMBOL(set_dma_y_count);
  273. void set_dma_x_modify(unsigned int channel, short x_modify)
  274. {
  275. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  276. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  277. dma_ch[channel].regs->x_modify = x_modify;
  278. SSYNC();
  279. }
  280. EXPORT_SYMBOL(set_dma_x_modify);
  281. void set_dma_y_modify(unsigned int channel, short y_modify)
  282. {
  283. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  284. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  285. dma_ch[channel].regs->y_modify = y_modify;
  286. SSYNC();
  287. }
  288. EXPORT_SYMBOL(set_dma_y_modify);
  289. void set_dma_config(unsigned int channel, unsigned short config)
  290. {
  291. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  292. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  293. dma_ch[channel].regs->cfg = config;
  294. SSYNC();
  295. }
  296. EXPORT_SYMBOL(set_dma_config);
  297. unsigned short
  298. set_bfin_dma_config(char direction, char flow_mode,
  299. char intr_mode, char dma_mode, char width, char syncmode)
  300. {
  301. unsigned short config;
  302. config =
  303. ((direction << 1) | (width << 2) | (dma_mode << 4) |
  304. (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5));
  305. return config;
  306. }
  307. EXPORT_SYMBOL(set_bfin_dma_config);
  308. void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
  309. {
  310. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  311. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  312. dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8);
  313. dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg;
  314. SSYNC();
  315. }
  316. EXPORT_SYMBOL(set_dma_sg);
  317. void set_dma_curr_addr(unsigned int channel, unsigned long addr)
  318. {
  319. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  320. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  321. dma_ch[channel].regs->curr_addr_ptr = addr;
  322. SSYNC();
  323. }
  324. EXPORT_SYMBOL(set_dma_curr_addr);
  325. /*------------------------------------------------------------------------------
  326. * Get the DMA status of a specific DMA channel from the system.
  327. *-----------------------------------------------------------------------------*/
  328. unsigned short get_dma_curr_irqstat(unsigned int channel)
  329. {
  330. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  331. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  332. return dma_ch[channel].regs->irq_status;
  333. }
  334. EXPORT_SYMBOL(get_dma_curr_irqstat);
  335. /*------------------------------------------------------------------------------
  336. * Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt.
  337. *-----------------------------------------------------------------------------*/
  338. void clear_dma_irqstat(unsigned int channel)
  339. {
  340. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  341. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  342. dma_ch[channel].regs->irq_status |= 3;
  343. }
  344. EXPORT_SYMBOL(clear_dma_irqstat);
  345. /*------------------------------------------------------------------------------
  346. * Get current DMA xcount of a specific DMA channel from the system.
  347. *-----------------------------------------------------------------------------*/
  348. unsigned short get_dma_curr_xcount(unsigned int channel)
  349. {
  350. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  351. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  352. return dma_ch[channel].regs->curr_x_count;
  353. }
  354. EXPORT_SYMBOL(get_dma_curr_xcount);
  355. /*------------------------------------------------------------------------------
  356. * Get current DMA ycount of a specific DMA channel from the system.
  357. *-----------------------------------------------------------------------------*/
  358. unsigned short get_dma_curr_ycount(unsigned int channel)
  359. {
  360. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  361. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  362. return dma_ch[channel].regs->curr_y_count;
  363. }
  364. EXPORT_SYMBOL(get_dma_curr_ycount);
  365. unsigned long get_dma_next_desc_ptr(unsigned int channel)
  366. {
  367. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  368. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  369. return dma_ch[channel].regs->next_desc_ptr;
  370. }
  371. EXPORT_SYMBOL(get_dma_next_desc_ptr);
  372. unsigned long get_dma_curr_desc_ptr(unsigned int channel)
  373. {
  374. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  375. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  376. return dma_ch[channel].regs->curr_desc_ptr;
  377. }
  378. EXPORT_SYMBOL(get_dma_curr_desc_ptr);
  379. unsigned long get_dma_curr_addr(unsigned int channel)
  380. {
  381. BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
  382. && channel < MAX_BLACKFIN_DMA_CHANNEL));
  383. return dma_ch[channel].regs->curr_addr_ptr;
  384. }
  385. EXPORT_SYMBOL(get_dma_curr_addr);
  386. #ifdef CONFIG_PM
  387. int blackfin_dma_suspend(void)
  388. {
  389. int i;
  390. #ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */
  391. for (i = 0; i <= CH_MEM_STREAM3_SRC; i++) {
  392. #else
  393. for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
  394. #endif
  395. if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
  396. printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
  397. return -EBUSY;
  398. }
  399. dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
  400. }
  401. return 0;
  402. }
  403. void blackfin_dma_resume(void)
  404. {
  405. int i;
  406. #ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */
  407. for (i = 0; i <= CH_MEM_STREAM3_SRC; i++)
  408. #else
  409. for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++)
  410. #endif
  411. dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
  412. }
  413. #endif
  414. static void *__dma_memcpy(void *dest, const void *src, size_t size)
  415. {
  416. int direction; /* 1 - address decrease, 0 - address increase */
  417. int flag_align; /* 1 - address aligned, 0 - address unaligned */
  418. int flag_2D; /* 1 - 2D DMA needed, 0 - 1D DMA needed */
  419. unsigned long flags;
  420. if (size <= 0)
  421. return NULL;
  422. local_irq_save(flags);
  423. if ((unsigned long)src < memory_end)
  424. blackfin_dcache_flush_range((unsigned int)src,
  425. (unsigned int)(src + size));
  426. if ((unsigned long)dest < memory_end)
  427. blackfin_dcache_invalidate_range((unsigned int)dest,
  428. (unsigned int)(dest + size));
  429. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  430. if ((unsigned long)src < (unsigned long)dest)
  431. direction = 1;
  432. else
  433. direction = 0;
  434. if ((((unsigned long)dest % 2) == 0) && (((unsigned long)src % 2) == 0)
  435. && ((size % 2) == 0))
  436. flag_align = 1;
  437. else
  438. flag_align = 0;
  439. if (size > 0x10000) /* size > 64K */
  440. flag_2D = 1;
  441. else
  442. flag_2D = 0;
  443. /* Setup destination and source start address */
  444. if (direction) {
  445. if (flag_align) {
  446. bfin_write_MDMA_D0_START_ADDR(dest + size - 2);
  447. bfin_write_MDMA_S0_START_ADDR(src + size - 2);
  448. } else {
  449. bfin_write_MDMA_D0_START_ADDR(dest + size - 1);
  450. bfin_write_MDMA_S0_START_ADDR(src + size - 1);
  451. }
  452. } else {
  453. bfin_write_MDMA_D0_START_ADDR(dest);
  454. bfin_write_MDMA_S0_START_ADDR(src);
  455. }
  456. /* Setup destination and source xcount */
  457. if (flag_2D) {
  458. if (flag_align) {
  459. bfin_write_MDMA_D0_X_COUNT(1024 / 2);
  460. bfin_write_MDMA_S0_X_COUNT(1024 / 2);
  461. } else {
  462. bfin_write_MDMA_D0_X_COUNT(1024);
  463. bfin_write_MDMA_S0_X_COUNT(1024);
  464. }
  465. bfin_write_MDMA_D0_Y_COUNT(size >> 10);
  466. bfin_write_MDMA_S0_Y_COUNT(size >> 10);
  467. } else {
  468. if (flag_align) {
  469. bfin_write_MDMA_D0_X_COUNT(size / 2);
  470. bfin_write_MDMA_S0_X_COUNT(size / 2);
  471. } else {
  472. bfin_write_MDMA_D0_X_COUNT(size);
  473. bfin_write_MDMA_S0_X_COUNT(size);
  474. }
  475. }
  476. /* Setup destination and source xmodify and ymodify */
  477. if (direction) {
  478. if (flag_align) {
  479. bfin_write_MDMA_D0_X_MODIFY(-2);
  480. bfin_write_MDMA_S0_X_MODIFY(-2);
  481. if (flag_2D) {
  482. bfin_write_MDMA_D0_Y_MODIFY(-2);
  483. bfin_write_MDMA_S0_Y_MODIFY(-2);
  484. }
  485. } else {
  486. bfin_write_MDMA_D0_X_MODIFY(-1);
  487. bfin_write_MDMA_S0_X_MODIFY(-1);
  488. if (flag_2D) {
  489. bfin_write_MDMA_D0_Y_MODIFY(-1);
  490. bfin_write_MDMA_S0_Y_MODIFY(-1);
  491. }
  492. }
  493. } else {
  494. if (flag_align) {
  495. bfin_write_MDMA_D0_X_MODIFY(2);
  496. bfin_write_MDMA_S0_X_MODIFY(2);
  497. if (flag_2D) {
  498. bfin_write_MDMA_D0_Y_MODIFY(2);
  499. bfin_write_MDMA_S0_Y_MODIFY(2);
  500. }
  501. } else {
  502. bfin_write_MDMA_D0_X_MODIFY(1);
  503. bfin_write_MDMA_S0_X_MODIFY(1);
  504. if (flag_2D) {
  505. bfin_write_MDMA_D0_Y_MODIFY(1);
  506. bfin_write_MDMA_S0_Y_MODIFY(1);
  507. }
  508. }
  509. }
  510. /* Enable source DMA */
  511. if (flag_2D) {
  512. if (flag_align) {
  513. bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16);
  514. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16);
  515. } else {
  516. bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D);
  517. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D);
  518. }
  519. } else {
  520. if (flag_align) {
  521. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
  522. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
  523. } else {
  524. bfin_write_MDMA_S0_CONFIG(DMAEN);
  525. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN);
  526. }
  527. }
  528. SSYNC();
  529. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
  530. ;
  531. bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() |
  532. (DMA_DONE | DMA_ERR));
  533. bfin_write_MDMA_S0_CONFIG(0);
  534. bfin_write_MDMA_D0_CONFIG(0);
  535. local_irq_restore(flags);
  536. return dest;
  537. }
  538. void *dma_memcpy(void *dest, const void *src, size_t size)
  539. {
  540. size_t bulk;
  541. size_t rest;
  542. void * addr;
  543. bulk = (size >> 16) << 16;
  544. rest = size - bulk;
  545. if (bulk)
  546. __dma_memcpy(dest, src, bulk);
  547. addr = __dma_memcpy(dest+bulk, src+bulk, rest);
  548. return addr;
  549. }
  550. EXPORT_SYMBOL(dma_memcpy);
  551. void *safe_dma_memcpy(void *dest, const void *src, size_t size)
  552. {
  553. void *addr;
  554. addr = dma_memcpy(dest, src, size);
  555. return addr;
  556. }
  557. EXPORT_SYMBOL(safe_dma_memcpy);
  558. void dma_outsb(unsigned long addr, const void *buf, unsigned short len)
  559. {
  560. unsigned long flags;
  561. local_irq_save(flags);
  562. blackfin_dcache_flush_range((unsigned int)buf,
  563. (unsigned int)(buf) + len);
  564. bfin_write_MDMA_D0_START_ADDR(addr);
  565. bfin_write_MDMA_D0_X_COUNT(len);
  566. bfin_write_MDMA_D0_X_MODIFY(0);
  567. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  568. bfin_write_MDMA_S0_START_ADDR(buf);
  569. bfin_write_MDMA_S0_X_COUNT(len);
  570. bfin_write_MDMA_S0_X_MODIFY(1);
  571. bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  572. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
  573. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
  574. SSYNC();
  575. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
  576. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  577. bfin_write_MDMA_S0_CONFIG(0);
  578. bfin_write_MDMA_D0_CONFIG(0);
  579. local_irq_restore(flags);
  580. }
  581. EXPORT_SYMBOL(dma_outsb);
  582. void dma_insb(unsigned long addr, void *buf, unsigned short len)
  583. {
  584. unsigned long flags;
  585. blackfin_dcache_invalidate_range((unsigned int)buf,
  586. (unsigned int)(buf) + len);
  587. local_irq_save(flags);
  588. bfin_write_MDMA_D0_START_ADDR(buf);
  589. bfin_write_MDMA_D0_X_COUNT(len);
  590. bfin_write_MDMA_D0_X_MODIFY(1);
  591. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  592. bfin_write_MDMA_S0_START_ADDR(addr);
  593. bfin_write_MDMA_S0_X_COUNT(len);
  594. bfin_write_MDMA_S0_X_MODIFY(0);
  595. bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  596. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
  597. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
  598. SSYNC();
  599. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
  600. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  601. bfin_write_MDMA_S0_CONFIG(0);
  602. bfin_write_MDMA_D0_CONFIG(0);
  603. local_irq_restore(flags);
  604. }
  605. EXPORT_SYMBOL(dma_insb);
  606. void dma_outsw(unsigned long addr, const void *buf, unsigned short len)
  607. {
  608. unsigned long flags;
  609. local_irq_save(flags);
  610. blackfin_dcache_flush_range((unsigned int)buf,
  611. (unsigned int)(buf) + len * sizeof(short));
  612. bfin_write_MDMA_D0_START_ADDR(addr);
  613. bfin_write_MDMA_D0_X_COUNT(len);
  614. bfin_write_MDMA_D0_X_MODIFY(0);
  615. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  616. bfin_write_MDMA_S0_START_ADDR(buf);
  617. bfin_write_MDMA_S0_X_COUNT(len);
  618. bfin_write_MDMA_S0_X_MODIFY(2);
  619. bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  620. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
  621. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
  622. SSYNC();
  623. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
  624. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  625. bfin_write_MDMA_S0_CONFIG(0);
  626. bfin_write_MDMA_D0_CONFIG(0);
  627. local_irq_restore(flags);
  628. }
  629. EXPORT_SYMBOL(dma_outsw);
  630. void dma_insw(unsigned long addr, void *buf, unsigned short len)
  631. {
  632. unsigned long flags;
  633. blackfin_dcache_invalidate_range((unsigned int)buf,
  634. (unsigned int)(buf) + len * sizeof(short));
  635. local_irq_save(flags);
  636. bfin_write_MDMA_D0_START_ADDR(buf);
  637. bfin_write_MDMA_D0_X_COUNT(len);
  638. bfin_write_MDMA_D0_X_MODIFY(2);
  639. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  640. bfin_write_MDMA_S0_START_ADDR(addr);
  641. bfin_write_MDMA_S0_X_COUNT(len);
  642. bfin_write_MDMA_S0_X_MODIFY(0);
  643. bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  644. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
  645. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
  646. SSYNC();
  647. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
  648. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  649. bfin_write_MDMA_S0_CONFIG(0);
  650. bfin_write_MDMA_D0_CONFIG(0);
  651. local_irq_restore(flags);
  652. }
  653. EXPORT_SYMBOL(dma_insw);
  654. void dma_outsl(unsigned long addr, const void *buf, unsigned short len)
  655. {
  656. unsigned long flags;
  657. local_irq_save(flags);
  658. blackfin_dcache_flush_range((unsigned int)buf,
  659. (unsigned int)(buf) + len * sizeof(long));
  660. bfin_write_MDMA_D0_START_ADDR(addr);
  661. bfin_write_MDMA_D0_X_COUNT(len);
  662. bfin_write_MDMA_D0_X_MODIFY(0);
  663. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  664. bfin_write_MDMA_S0_START_ADDR(buf);
  665. bfin_write_MDMA_S0_X_COUNT(len);
  666. bfin_write_MDMA_S0_X_MODIFY(4);
  667. bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  668. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
  669. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
  670. SSYNC();
  671. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
  672. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  673. bfin_write_MDMA_S0_CONFIG(0);
  674. bfin_write_MDMA_D0_CONFIG(0);
  675. local_irq_restore(flags);
  676. }
  677. EXPORT_SYMBOL(dma_outsl);
  678. void dma_insl(unsigned long addr, void *buf, unsigned short len)
  679. {
  680. unsigned long flags;
  681. blackfin_dcache_invalidate_range((unsigned int)buf,
  682. (unsigned int)(buf) + len * sizeof(long));
  683. local_irq_save(flags);
  684. bfin_write_MDMA_D0_START_ADDR(buf);
  685. bfin_write_MDMA_D0_X_COUNT(len);
  686. bfin_write_MDMA_D0_X_MODIFY(4);
  687. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  688. bfin_write_MDMA_S0_START_ADDR(addr);
  689. bfin_write_MDMA_S0_X_COUNT(len);
  690. bfin_write_MDMA_S0_X_MODIFY(0);
  691. bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  692. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
  693. bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
  694. SSYNC();
  695. while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
  696. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  697. bfin_write_MDMA_S0_CONFIG(0);
  698. bfin_write_MDMA_D0_CONFIG(0);
  699. local_irq_restore(flags);
  700. }
  701. EXPORT_SYMBOL(dma_insl);