wm8958-dsp2.c 27 KB

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  1. /*
  2. * wm8958-dsp2.c -- WM8958 DSP2 support
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <trace/events/asoc.h>
  24. #include <linux/mfd/wm8994/core.h>
  25. #include <linux/mfd/wm8994/registers.h>
  26. #include <linux/mfd/wm8994/pdata.h>
  27. #include <linux/mfd/wm8994/gpio.h>
  28. #include "wm8994.h"
  29. #define WM_FW_BLOCK_INFO 0xff
  30. #define WM_FW_BLOCK_PM 0x00
  31. #define WM_FW_BLOCK_X 0x01
  32. #define WM_FW_BLOCK_Y 0x02
  33. #define WM_FW_BLOCK_Z 0x03
  34. #define WM_FW_BLOCK_I 0x06
  35. #define WM_FW_BLOCK_A 0x08
  36. #define WM_FW_BLOCK_C 0x0c
  37. static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
  38. const struct firmware *fw, bool check)
  39. {
  40. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  41. u64 data64;
  42. u32 data32;
  43. const u8 *data;
  44. char *str;
  45. size_t block_len, len;
  46. int ret = 0;
  47. /* Suppress unneeded downloads */
  48. if (wm8994->cur_fw == fw)
  49. return 0;
  50. if (fw->size < 32) {
  51. dev_err(codec->dev, "%s: firmware too short\n", name);
  52. goto err;
  53. }
  54. if (memcmp(fw->data, "WMFW", 4) != 0) {
  55. memcpy(&data32, fw->data, sizeof(data32));
  56. data32 = be32_to_cpu(data32);
  57. dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
  58. name, data32);
  59. goto err;
  60. }
  61. memcpy(&data32, fw->data + 4, sizeof(data32));
  62. len = be32_to_cpu(data32);
  63. memcpy(&data32, fw->data + 8, sizeof(data32));
  64. data32 = be32_to_cpu(data32);
  65. if ((data32 >> 24) & 0xff) {
  66. dev_err(codec->dev, "%s: unsupported firmware version %d\n",
  67. name, (data32 >> 24) & 0xff);
  68. goto err;
  69. }
  70. if ((data32 & 0xffff) != 8958) {
  71. dev_err(codec->dev, "%s: unsupported target device %d\n",
  72. name, data32 & 0xffff);
  73. goto err;
  74. }
  75. if (((data32 >> 16) & 0xff) != 0xc) {
  76. dev_err(codec->dev, "%s: unsupported target core %d\n",
  77. name, (data32 >> 16) & 0xff);
  78. goto err;
  79. }
  80. if (check) {
  81. memcpy(&data64, fw->data + 24, sizeof(u64));
  82. dev_info(codec->dev, "%s timestamp %llx\n",
  83. name, be64_to_cpu(data64));
  84. } else {
  85. snd_soc_write(codec, 0x102, 0x2);
  86. snd_soc_write(codec, 0x900, 0x2);
  87. }
  88. data = fw->data + len;
  89. len = fw->size - len;
  90. while (len) {
  91. if (len < 12) {
  92. dev_err(codec->dev, "%s short data block of %zd\n",
  93. name, len);
  94. goto err;
  95. }
  96. memcpy(&data32, data + 4, sizeof(data32));
  97. block_len = be32_to_cpu(data32);
  98. if (block_len + 8 > len) {
  99. dev_err(codec->dev, "%zd byte block longer than file\n",
  100. block_len);
  101. goto err;
  102. }
  103. if (block_len == 0) {
  104. dev_err(codec->dev, "Zero length block\n");
  105. goto err;
  106. }
  107. memcpy(&data32, data, sizeof(data32));
  108. data32 = be32_to_cpu(data32);
  109. switch ((data32 >> 24) & 0xff) {
  110. case WM_FW_BLOCK_INFO:
  111. /* Informational text */
  112. if (!check)
  113. break;
  114. str = kzalloc(block_len + 1, GFP_KERNEL);
  115. if (str) {
  116. memcpy(str, data + 8, block_len);
  117. dev_info(codec->dev, "%s: %s\n", name, str);
  118. kfree(str);
  119. } else {
  120. dev_err(codec->dev, "Out of memory\n");
  121. }
  122. break;
  123. case WM_FW_BLOCK_PM:
  124. case WM_FW_BLOCK_X:
  125. case WM_FW_BLOCK_Y:
  126. case WM_FW_BLOCK_Z:
  127. case WM_FW_BLOCK_I:
  128. case WM_FW_BLOCK_A:
  129. case WM_FW_BLOCK_C:
  130. dev_dbg(codec->dev, "%s: %zd bytes of %x@%x\n", name,
  131. block_len, (data32 >> 24) & 0xff,
  132. data32 & 0xffffff);
  133. if (check)
  134. break;
  135. data32 &= 0xffffff;
  136. wm8994_bulk_write(codec->control_data,
  137. data32 & 0xffffff,
  138. block_len / 2,
  139. (void *)(data + 8));
  140. break;
  141. default:
  142. dev_warn(codec->dev, "%s: unknown block type %d\n",
  143. name, (data32 >> 24) & 0xff);
  144. break;
  145. }
  146. /* Round up to the next 32 bit word */
  147. block_len += block_len % 4;
  148. data += block_len + 8;
  149. len -= block_len + 8;
  150. }
  151. if (!check) {
  152. dev_dbg(codec->dev, "%s: download done\n", name);
  153. wm8994->cur_fw = fw;
  154. } else {
  155. dev_info(codec->dev, "%s: got firmware\n", name);
  156. }
  157. goto ok;
  158. err:
  159. ret = -EINVAL;
  160. ok:
  161. if (!check) {
  162. snd_soc_write(codec, 0x900, 0x0);
  163. snd_soc_write(codec, 0x102, 0x0);
  164. }
  165. return ret;
  166. }
  167. static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
  168. {
  169. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  170. struct wm8994_pdata *pdata = wm8994->pdata;
  171. int i;
  172. /* If the DSP is already running then noop */
  173. if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  174. return;
  175. /* If we have MBC firmware download it */
  176. if (wm8994->mbc)
  177. wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
  178. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  179. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  180. /* If we've got user supplied MBC settings use them */
  181. if (pdata && pdata->num_mbc_cfgs) {
  182. struct wm8958_mbc_cfg *cfg
  183. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  184. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  185. snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
  186. cfg->coeff_regs[i]);
  187. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  188. snd_soc_write(codec,
  189. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  190. cfg->cutoff_regs[i]);
  191. }
  192. /* Run the DSP */
  193. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  194. WM8958_DSP2_RUNR);
  195. /* And we're off! */
  196. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  197. WM8958_MBC_ENA |
  198. WM8958_MBC_SEL_MASK,
  199. path << WM8958_MBC_SEL_SHIFT |
  200. WM8958_MBC_ENA);
  201. }
  202. static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
  203. {
  204. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  205. struct wm8994_pdata *pdata = wm8994->pdata;
  206. int i, ena;
  207. if (wm8994->mbc_vss)
  208. wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
  209. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  210. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  211. /* If we've got user supplied settings use them */
  212. if (pdata && pdata->num_mbc_cfgs) {
  213. struct wm8958_mbc_cfg *cfg
  214. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  215. for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
  216. snd_soc_write(codec, i + 0x2800,
  217. cfg->combined_regs[i]);
  218. }
  219. if (pdata && pdata->num_vss_cfgs) {
  220. struct wm8958_vss_cfg *cfg
  221. = &pdata->vss_cfgs[wm8994->vss_cfg];
  222. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  223. snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
  224. }
  225. if (pdata && pdata->num_vss_hpf_cfgs) {
  226. struct wm8958_vss_hpf_cfg *cfg
  227. = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
  228. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  229. snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
  230. }
  231. /* Run the DSP */
  232. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  233. WM8958_DSP2_RUNR);
  234. /* Enable the algorithms we've selected */
  235. ena = 0;
  236. if (wm8994->mbc_ena[path])
  237. ena |= 0x8;
  238. if (wm8994->hpf2_ena[path])
  239. ena |= 0x4;
  240. if (wm8994->hpf1_ena[path])
  241. ena |= 0x2;
  242. if (wm8994->vss_ena[path])
  243. ena |= 0x1;
  244. snd_soc_write(codec, 0x2201, ena);
  245. /* Switch the DSP into the data path */
  246. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  247. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  248. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  249. }
  250. static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
  251. {
  252. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  253. struct wm8994_pdata *pdata = wm8994->pdata;
  254. int i;
  255. wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
  256. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  257. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  258. /* If we've got user supplied settings use them */
  259. if (pdata && pdata->num_enh_eq_cfgs) {
  260. struct wm8958_enh_eq_cfg *cfg
  261. = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
  262. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  263. snd_soc_write(codec, i + 0x2200,
  264. cfg->regs[i]);
  265. }
  266. /* Run the DSP */
  267. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  268. WM8958_DSP2_RUNR);
  269. /* Switch the DSP into the data path */
  270. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  271. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  272. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  273. }
  274. static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
  275. {
  276. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  277. int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
  278. int ena, reg, aif;
  279. switch (path) {
  280. case 0:
  281. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  282. aif = 0;
  283. break;
  284. case 1:
  285. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  286. aif = 0;
  287. break;
  288. case 2:
  289. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  290. aif = 1;
  291. break;
  292. default:
  293. BUG();
  294. return;
  295. }
  296. /* Do we have both an active AIF and an active algorithm? */
  297. ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
  298. wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
  299. wm8994->enh_eq_ena[path];
  300. if (!pwr_reg)
  301. ena = 0;
  302. reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
  303. dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  304. path, wm8994->dsp_active, start, pwr_reg, reg);
  305. if (start && ena) {
  306. /* If the DSP is already running then noop */
  307. if (reg & WM8958_DSP2_ENA)
  308. return;
  309. /* If either AIFnCLK is not yet enabled postpone */
  310. if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  311. & WM8994_AIF1CLK_ENA_MASK) &&
  312. !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  313. & WM8994_AIF2CLK_ENA_MASK))
  314. return;
  315. /* Switch the clock over to the appropriate AIF */
  316. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  317. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  318. aif << WM8958_DSP2CLK_SRC_SHIFT |
  319. WM8958_DSP2CLK_ENA);
  320. if (wm8994->enh_eq_ena[path])
  321. wm8958_dsp_start_enh_eq(codec, path);
  322. else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
  323. wm8994->hpf2_ena[path])
  324. wm8958_dsp_start_vss(codec, path);
  325. else if (wm8994->mbc_ena[path])
  326. wm8958_dsp_start_mbc(codec, path);
  327. wm8994->dsp_active = path;
  328. dev_dbg(codec->dev, "DSP running in path %d\n", path);
  329. }
  330. if (!start && wm8994->dsp_active == path) {
  331. /* If the DSP is already stopped then noop */
  332. if (!(reg & WM8958_DSP2_ENA))
  333. return;
  334. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  335. WM8958_MBC_ENA, 0);
  336. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  337. WM8958_DSP2_STOP);
  338. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  339. WM8958_DSP2_ENA, 0);
  340. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  341. WM8958_DSP2CLK_ENA, 0);
  342. wm8994->dsp_active = -1;
  343. dev_dbg(codec->dev, "DSP stopped\n");
  344. }
  345. }
  346. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  347. struct snd_kcontrol *kcontrol, int event)
  348. {
  349. struct snd_soc_codec *codec = w->codec;
  350. int i;
  351. switch (event) {
  352. case SND_SOC_DAPM_POST_PMU:
  353. case SND_SOC_DAPM_PRE_PMU:
  354. for (i = 0; i < 3; i++)
  355. wm8958_dsp_apply(codec, i, 1);
  356. break;
  357. case SND_SOC_DAPM_POST_PMD:
  358. case SND_SOC_DAPM_PRE_PMD:
  359. for (i = 0; i < 3; i++)
  360. wm8958_dsp_apply(codec, i, 0);
  361. break;
  362. }
  363. return 0;
  364. }
  365. /* Check if DSP2 is in use on another AIF */
  366. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  367. {
  368. int i;
  369. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  370. if (i == aif)
  371. continue;
  372. if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
  373. wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
  374. return 1;
  375. }
  376. return 0;
  377. }
  378. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  379. struct snd_ctl_elem_value *ucontrol)
  380. {
  381. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  382. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  383. struct wm8994_pdata *pdata = wm8994->pdata;
  384. int value = ucontrol->value.integer.value[0];
  385. int reg;
  386. /* Don't allow on the fly reconfiguration */
  387. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  388. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  389. return -EBUSY;
  390. if (value >= pdata->num_mbc_cfgs)
  391. return -EINVAL;
  392. wm8994->mbc_cfg = value;
  393. return 0;
  394. }
  395. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  396. struct snd_ctl_elem_value *ucontrol)
  397. {
  398. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  399. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  400. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  401. return 0;
  402. }
  403. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  404. struct snd_ctl_elem_info *uinfo)
  405. {
  406. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  407. uinfo->count = 1;
  408. uinfo->value.integer.min = 0;
  409. uinfo->value.integer.max = 1;
  410. return 0;
  411. }
  412. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  413. struct snd_ctl_elem_value *ucontrol)
  414. {
  415. int mbc = kcontrol->private_value;
  416. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  417. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  418. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  419. return 0;
  420. }
  421. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  422. struct snd_ctl_elem_value *ucontrol)
  423. {
  424. int mbc = kcontrol->private_value;
  425. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  426. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  427. if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
  428. return 0;
  429. if (ucontrol->value.integer.value[0] > 1)
  430. return -EINVAL;
  431. if (wm8958_dsp2_busy(wm8994, mbc)) {
  432. dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
  433. return -EBUSY;
  434. }
  435. if (wm8994->enh_eq_ena[mbc])
  436. return -EBUSY;
  437. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  438. wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
  439. return 0;
  440. }
  441. #define WM8958_MBC_SWITCH(xname, xval) {\
  442. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  443. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  444. .info = wm8958_mbc_info, \
  445. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  446. .private_value = xval }
  447. static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
  448. struct snd_ctl_elem_value *ucontrol)
  449. {
  450. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  451. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  452. struct wm8994_pdata *pdata = wm8994->pdata;
  453. int value = ucontrol->value.integer.value[0];
  454. int reg;
  455. /* Don't allow on the fly reconfiguration */
  456. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  457. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  458. return -EBUSY;
  459. if (value >= pdata->num_vss_cfgs)
  460. return -EINVAL;
  461. wm8994->vss_cfg = value;
  462. return 0;
  463. }
  464. static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
  465. struct snd_ctl_elem_value *ucontrol)
  466. {
  467. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  468. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  469. ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
  470. return 0;
  471. }
  472. static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  473. struct snd_ctl_elem_value *ucontrol)
  474. {
  475. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  476. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  477. struct wm8994_pdata *pdata = wm8994->pdata;
  478. int value = ucontrol->value.integer.value[0];
  479. int reg;
  480. /* Don't allow on the fly reconfiguration */
  481. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  482. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  483. return -EBUSY;
  484. if (value >= pdata->num_vss_hpf_cfgs)
  485. return -EINVAL;
  486. wm8994->vss_hpf_cfg = value;
  487. return 0;
  488. }
  489. static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  490. struct snd_ctl_elem_value *ucontrol)
  491. {
  492. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  493. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  494. ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
  495. return 0;
  496. }
  497. static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
  498. struct snd_ctl_elem_info *uinfo)
  499. {
  500. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  501. uinfo->count = 1;
  502. uinfo->value.integer.min = 0;
  503. uinfo->value.integer.max = 1;
  504. return 0;
  505. }
  506. static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
  507. struct snd_ctl_elem_value *ucontrol)
  508. {
  509. int vss = kcontrol->private_value;
  510. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  511. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  512. ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
  513. return 0;
  514. }
  515. static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
  516. struct snd_ctl_elem_value *ucontrol)
  517. {
  518. int vss = kcontrol->private_value;
  519. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  520. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  521. if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
  522. return 0;
  523. if (ucontrol->value.integer.value[0] > 1)
  524. return -EINVAL;
  525. if (!wm8994->mbc_vss)
  526. return -ENODEV;
  527. if (wm8958_dsp2_busy(wm8994, vss)) {
  528. dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
  529. return -EBUSY;
  530. }
  531. if (wm8994->enh_eq_ena[vss])
  532. return -EBUSY;
  533. wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
  534. wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
  535. return 0;
  536. }
  537. #define WM8958_VSS_SWITCH(xname, xval) {\
  538. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  539. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  540. .info = wm8958_vss_info, \
  541. .get = wm8958_vss_get, .put = wm8958_vss_put, \
  542. .private_value = xval }
  543. static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
  544. struct snd_ctl_elem_info *uinfo)
  545. {
  546. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  547. uinfo->count = 1;
  548. uinfo->value.integer.min = 0;
  549. uinfo->value.integer.max = 1;
  550. return 0;
  551. }
  552. static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
  553. struct snd_ctl_elem_value *ucontrol)
  554. {
  555. int hpf = kcontrol->private_value;
  556. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  557. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  558. if (hpf < 3)
  559. ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
  560. else
  561. ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
  562. return 0;
  563. }
  564. static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
  565. struct snd_ctl_elem_value *ucontrol)
  566. {
  567. int hpf = kcontrol->private_value;
  568. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  569. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  570. if (hpf < 3) {
  571. if (wm8994->hpf1_ena[hpf % 3] ==
  572. ucontrol->value.integer.value[0])
  573. return 0;
  574. } else {
  575. if (wm8994->hpf2_ena[hpf % 3] ==
  576. ucontrol->value.integer.value[0])
  577. return 0;
  578. }
  579. if (ucontrol->value.integer.value[0] > 1)
  580. return -EINVAL;
  581. if (!wm8994->mbc_vss)
  582. return -ENODEV;
  583. if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
  584. dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
  585. return -EBUSY;
  586. }
  587. if (wm8994->enh_eq_ena[hpf % 3])
  588. return -EBUSY;
  589. if (hpf < 3)
  590. wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
  591. else
  592. wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
  593. wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
  594. return 0;
  595. }
  596. #define WM8958_HPF_SWITCH(xname, xval) {\
  597. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  598. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  599. .info = wm8958_hpf_info, \
  600. .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
  601. .private_value = xval }
  602. static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
  603. struct snd_ctl_elem_value *ucontrol)
  604. {
  605. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  606. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  607. struct wm8994_pdata *pdata = wm8994->pdata;
  608. int value = ucontrol->value.integer.value[0];
  609. int reg;
  610. /* Don't allow on the fly reconfiguration */
  611. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  612. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  613. return -EBUSY;
  614. if (value >= pdata->num_enh_eq_cfgs)
  615. return -EINVAL;
  616. wm8994->enh_eq_cfg = value;
  617. return 0;
  618. }
  619. static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
  620. struct snd_ctl_elem_value *ucontrol)
  621. {
  622. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  623. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  624. ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
  625. return 0;
  626. }
  627. static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
  628. struct snd_ctl_elem_info *uinfo)
  629. {
  630. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  631. uinfo->count = 1;
  632. uinfo->value.integer.min = 0;
  633. uinfo->value.integer.max = 1;
  634. return 0;
  635. }
  636. static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
  637. struct snd_ctl_elem_value *ucontrol)
  638. {
  639. int eq = kcontrol->private_value;
  640. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  641. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  642. ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
  643. return 0;
  644. }
  645. static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
  646. struct snd_ctl_elem_value *ucontrol)
  647. {
  648. int eq = kcontrol->private_value;
  649. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  650. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  651. if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
  652. return 0;
  653. if (ucontrol->value.integer.value[0] > 1)
  654. return -EINVAL;
  655. if (!wm8994->enh_eq)
  656. return -ENODEV;
  657. if (wm8958_dsp2_busy(wm8994, eq)) {
  658. dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
  659. return -EBUSY;
  660. }
  661. if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
  662. wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
  663. return -EBUSY;
  664. wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
  665. wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
  666. return 0;
  667. }
  668. #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
  669. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  670. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  671. .info = wm8958_enh_eq_info, \
  672. .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
  673. .private_value = xval }
  674. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  675. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  676. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  677. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  678. };
  679. static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
  680. WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
  681. WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
  682. WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
  683. WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
  684. WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
  685. WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
  686. WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
  687. WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
  688. WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
  689. };
  690. static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
  691. WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
  692. WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
  693. WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
  694. };
  695. static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
  696. {
  697. struct snd_soc_codec *codec = context;
  698. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  699. if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
  700. mutex_lock(&codec->mutex);
  701. wm8994->enh_eq = fw;
  702. mutex_unlock(&codec->mutex);
  703. }
  704. }
  705. static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
  706. {
  707. struct snd_soc_codec *codec = context;
  708. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  709. if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
  710. mutex_lock(&codec->mutex);
  711. wm8994->mbc_vss = fw;
  712. mutex_unlock(&codec->mutex);
  713. }
  714. /* We can't have more than one request outstanding at once so
  715. * we daisy chain.
  716. */
  717. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  718. "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
  719. codec, wm8958_enh_eq_loaded);
  720. }
  721. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  722. {
  723. struct snd_soc_codec *codec = context;
  724. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  725. if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
  726. return;
  727. mutex_lock(&codec->mutex);
  728. wm8994->mbc = fw;
  729. mutex_unlock(&codec->mutex);
  730. /* We can't have more than one request outstanding at once so
  731. * we daisy chain.
  732. */
  733. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  734. "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
  735. codec, wm8958_mbc_vss_loaded);
  736. }
  737. void wm8958_dsp2_init(struct snd_soc_codec *codec)
  738. {
  739. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  740. struct wm8994_pdata *pdata = wm8994->pdata;
  741. int ret, i;
  742. wm8994->dsp_active = -1;
  743. snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
  744. ARRAY_SIZE(wm8958_mbc_snd_controls));
  745. snd_soc_add_controls(codec, wm8958_vss_snd_controls,
  746. ARRAY_SIZE(wm8958_vss_snd_controls));
  747. snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
  748. ARRAY_SIZE(wm8958_enh_eq_snd_controls));
  749. /* We don't *require* firmware and don't want to delay boot */
  750. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  751. "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
  752. codec, wm8958_mbc_loaded);
  753. if (!pdata)
  754. return;
  755. if (pdata->num_mbc_cfgs) {
  756. struct snd_kcontrol_new control[] = {
  757. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  758. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  759. };
  760. /* We need an array of texts for the enum API */
  761. wm8994->mbc_texts = kmalloc(sizeof(char *)
  762. * pdata->num_mbc_cfgs, GFP_KERNEL);
  763. if (!wm8994->mbc_texts) {
  764. dev_err(wm8994->codec->dev,
  765. "Failed to allocate %d MBC config texts\n",
  766. pdata->num_mbc_cfgs);
  767. return;
  768. }
  769. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  770. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  771. wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
  772. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  773. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  774. if (ret != 0)
  775. dev_err(wm8994->codec->dev,
  776. "Failed to add MBC mode controls: %d\n", ret);
  777. }
  778. if (pdata->num_vss_cfgs) {
  779. struct snd_kcontrol_new control[] = {
  780. SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
  781. wm8958_get_vss_enum, wm8958_put_vss_enum),
  782. };
  783. /* We need an array of texts for the enum API */
  784. wm8994->vss_texts = kmalloc(sizeof(char *)
  785. * pdata->num_vss_cfgs, GFP_KERNEL);
  786. if (!wm8994->vss_texts) {
  787. dev_err(wm8994->codec->dev,
  788. "Failed to allocate %d VSS config texts\n",
  789. pdata->num_vss_cfgs);
  790. return;
  791. }
  792. for (i = 0; i < pdata->num_vss_cfgs; i++)
  793. wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
  794. wm8994->vss_enum.max = pdata->num_vss_cfgs;
  795. wm8994->vss_enum.texts = wm8994->vss_texts;
  796. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  797. if (ret != 0)
  798. dev_err(wm8994->codec->dev,
  799. "Failed to add VSS mode controls: %d\n", ret);
  800. }
  801. if (pdata->num_vss_hpf_cfgs) {
  802. struct snd_kcontrol_new control[] = {
  803. SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
  804. wm8958_get_vss_hpf_enum,
  805. wm8958_put_vss_hpf_enum),
  806. };
  807. /* We need an array of texts for the enum API */
  808. wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
  809. * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
  810. if (!wm8994->vss_hpf_texts) {
  811. dev_err(wm8994->codec->dev,
  812. "Failed to allocate %d VSS HPF config texts\n",
  813. pdata->num_vss_hpf_cfgs);
  814. return;
  815. }
  816. for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
  817. wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
  818. wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
  819. wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
  820. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  821. if (ret != 0)
  822. dev_err(wm8994->codec->dev,
  823. "Failed to add VSS HPFmode controls: %d\n",
  824. ret);
  825. }
  826. if (pdata->num_enh_eq_cfgs) {
  827. struct snd_kcontrol_new control[] = {
  828. SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
  829. wm8958_get_enh_eq_enum,
  830. wm8958_put_enh_eq_enum),
  831. };
  832. /* We need an array of texts for the enum API */
  833. wm8994->enh_eq_texts = kmalloc(sizeof(char *)
  834. * pdata->num_enh_eq_cfgs, GFP_KERNEL);
  835. if (!wm8994->enh_eq_texts) {
  836. dev_err(wm8994->codec->dev,
  837. "Failed to allocate %d enhanced EQ config texts\n",
  838. pdata->num_enh_eq_cfgs);
  839. return;
  840. }
  841. for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
  842. wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
  843. wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
  844. wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
  845. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  846. if (ret != 0)
  847. dev_err(wm8994->codec->dev,
  848. "Failed to add enhanced EQ controls: %d\n",
  849. ret);
  850. }
  851. }