gpio-pca953x.c 20 KB

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  1. /*
  2. * PCA953x 4/8/16 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/irq.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/i2c.h>
  20. #include <linux/platform_data/pca953x.h>
  21. #include <linux/slab.h>
  22. #ifdef CONFIG_OF_GPIO
  23. #include <linux/of_platform.h>
  24. #endif
  25. #define PCA953X_INPUT 0
  26. #define PCA953X_OUTPUT 1
  27. #define PCA953X_INVERT 2
  28. #define PCA953X_DIRECTION 3
  29. #define REG_ADDR_AI 0x80
  30. #define PCA957X_IN 0
  31. #define PCA957X_INVRT 1
  32. #define PCA957X_BKEN 2
  33. #define PCA957X_PUPD 3
  34. #define PCA957X_CFG 4
  35. #define PCA957X_OUT 5
  36. #define PCA957X_MSK 6
  37. #define PCA957X_INTS 7
  38. #define PCA_GPIO_MASK 0x00FF
  39. #define PCA_INT 0x0100
  40. #define PCA953X_TYPE 0x1000
  41. #define PCA957X_TYPE 0x2000
  42. static const struct i2c_device_id pca953x_id[] = {
  43. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  44. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  45. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  46. { "pca9536", 4 | PCA953X_TYPE, },
  47. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9556", 8 | PCA953X_TYPE, },
  53. { "pca9557", 8 | PCA953X_TYPE, },
  54. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  55. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  56. { "max7310", 8 | PCA953X_TYPE, },
  57. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  58. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  59. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  60. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  61. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  62. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  63. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  64. { }
  65. };
  66. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  67. #define MAX_BANK 5
  68. #define BANK_SZ 8
  69. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  70. struct pca953x_chip {
  71. unsigned gpio_start;
  72. u8 reg_output[MAX_BANK];
  73. u8 reg_direction[MAX_BANK];
  74. struct mutex i2c_lock;
  75. #ifdef CONFIG_GPIO_PCA953X_IRQ
  76. struct mutex irq_lock;
  77. u8 irq_mask[MAX_BANK];
  78. u8 irq_stat[MAX_BANK];
  79. u8 irq_trig_raise[MAX_BANK];
  80. u8 irq_trig_fall[MAX_BANK];
  81. struct irq_domain *domain;
  82. #endif
  83. struct i2c_client *client;
  84. struct gpio_chip gpio_chip;
  85. const char *const *names;
  86. int chip_type;
  87. };
  88. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  89. int off)
  90. {
  91. int ret;
  92. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  93. int offset = off / BANK_SZ;
  94. ret = i2c_smbus_read_byte_data(chip->client,
  95. (reg << bank_shift) + offset);
  96. *val = ret;
  97. if (ret < 0) {
  98. dev_err(&chip->client->dev, "failed reading register\n");
  99. return ret;
  100. }
  101. return 0;
  102. }
  103. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  104. int off)
  105. {
  106. int ret = 0;
  107. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  108. int offset = off / BANK_SZ;
  109. ret = i2c_smbus_write_byte_data(chip->client,
  110. (reg << bank_shift) + offset, val);
  111. if (ret < 0) {
  112. dev_err(&chip->client->dev, "failed writing register\n");
  113. return ret;
  114. }
  115. return 0;
  116. }
  117. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  118. {
  119. int ret = 0;
  120. if (chip->gpio_chip.ngpio <= 8)
  121. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  122. else if (chip->gpio_chip.ngpio >= 24) {
  123. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  124. ret = i2c_smbus_write_i2c_block_data(chip->client,
  125. (reg << bank_shift) | REG_ADDR_AI,
  126. NBANK(chip), val);
  127. } else {
  128. switch (chip->chip_type) {
  129. case PCA953X_TYPE:
  130. ret = i2c_smbus_write_word_data(chip->client,
  131. reg << 1, (u16) *val);
  132. break;
  133. case PCA957X_TYPE:
  134. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  135. val[0]);
  136. if (ret < 0)
  137. break;
  138. ret = i2c_smbus_write_byte_data(chip->client,
  139. (reg << 1) + 1,
  140. val[1]);
  141. break;
  142. }
  143. }
  144. if (ret < 0) {
  145. dev_err(&chip->client->dev, "failed writing register\n");
  146. return ret;
  147. }
  148. return 0;
  149. }
  150. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  151. {
  152. int ret;
  153. if (chip->gpio_chip.ngpio <= 8) {
  154. ret = i2c_smbus_read_byte_data(chip->client, reg);
  155. *val = ret;
  156. } else if (chip->gpio_chip.ngpio >= 24) {
  157. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  158. ret = i2c_smbus_read_i2c_block_data(chip->client,
  159. (reg << bank_shift) | REG_ADDR_AI,
  160. NBANK(chip), val);
  161. } else {
  162. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  163. val[0] = (u16)ret & 0xFF;
  164. val[1] = (u16)ret >> 8;
  165. }
  166. if (ret < 0) {
  167. dev_err(&chip->client->dev, "failed reading register\n");
  168. return ret;
  169. }
  170. return 0;
  171. }
  172. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  173. {
  174. struct pca953x_chip *chip;
  175. u8 reg_val;
  176. int ret, offset = 0;
  177. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  178. mutex_lock(&chip->i2c_lock);
  179. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  180. switch (chip->chip_type) {
  181. case PCA953X_TYPE:
  182. offset = PCA953X_DIRECTION;
  183. break;
  184. case PCA957X_TYPE:
  185. offset = PCA957X_CFG;
  186. break;
  187. }
  188. ret = pca953x_write_single(chip, offset, reg_val, off);
  189. if (ret)
  190. goto exit;
  191. chip->reg_direction[off / BANK_SZ] = reg_val;
  192. ret = 0;
  193. exit:
  194. mutex_unlock(&chip->i2c_lock);
  195. return ret;
  196. }
  197. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  198. unsigned off, int val)
  199. {
  200. struct pca953x_chip *chip;
  201. u8 reg_val;
  202. int ret, offset = 0;
  203. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  204. mutex_lock(&chip->i2c_lock);
  205. /* set output level */
  206. if (val)
  207. reg_val = chip->reg_output[off / BANK_SZ]
  208. | (1u << (off % BANK_SZ));
  209. else
  210. reg_val = chip->reg_output[off / BANK_SZ]
  211. & ~(1u << (off % BANK_SZ));
  212. switch (chip->chip_type) {
  213. case PCA953X_TYPE:
  214. offset = PCA953X_OUTPUT;
  215. break;
  216. case PCA957X_TYPE:
  217. offset = PCA957X_OUT;
  218. break;
  219. }
  220. ret = pca953x_write_single(chip, offset, reg_val, off);
  221. if (ret)
  222. goto exit;
  223. chip->reg_output[off / BANK_SZ] = reg_val;
  224. /* then direction */
  225. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  226. switch (chip->chip_type) {
  227. case PCA953X_TYPE:
  228. offset = PCA953X_DIRECTION;
  229. break;
  230. case PCA957X_TYPE:
  231. offset = PCA957X_CFG;
  232. break;
  233. }
  234. ret = pca953x_write_single(chip, offset, reg_val, off);
  235. if (ret)
  236. goto exit;
  237. chip->reg_direction[off / BANK_SZ] = reg_val;
  238. ret = 0;
  239. exit:
  240. mutex_unlock(&chip->i2c_lock);
  241. return ret;
  242. }
  243. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  244. {
  245. struct pca953x_chip *chip;
  246. u32 reg_val;
  247. int ret, offset = 0;
  248. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  249. mutex_lock(&chip->i2c_lock);
  250. switch (chip->chip_type) {
  251. case PCA953X_TYPE:
  252. offset = PCA953X_INPUT;
  253. break;
  254. case PCA957X_TYPE:
  255. offset = PCA957X_IN;
  256. break;
  257. }
  258. ret = pca953x_read_single(chip, offset, &reg_val, off);
  259. mutex_unlock(&chip->i2c_lock);
  260. if (ret < 0) {
  261. /* NOTE: diagnostic already emitted; that's all we should
  262. * do unless gpio_*_value_cansleep() calls become different
  263. * from their nonsleeping siblings (and report faults).
  264. */
  265. return 0;
  266. }
  267. return (reg_val & (1u << off)) ? 1 : 0;
  268. }
  269. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  270. {
  271. struct pca953x_chip *chip;
  272. u8 reg_val;
  273. int ret, offset = 0;
  274. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  275. mutex_lock(&chip->i2c_lock);
  276. if (val)
  277. reg_val = chip->reg_output[off / BANK_SZ]
  278. | (1u << (off % BANK_SZ));
  279. else
  280. reg_val = chip->reg_output[off / BANK_SZ]
  281. & ~(1u << (off % BANK_SZ));
  282. switch (chip->chip_type) {
  283. case PCA953X_TYPE:
  284. offset = PCA953X_OUTPUT;
  285. break;
  286. case PCA957X_TYPE:
  287. offset = PCA957X_OUT;
  288. break;
  289. }
  290. ret = pca953x_write_single(chip, offset, reg_val, off);
  291. if (ret)
  292. goto exit;
  293. chip->reg_output[off / BANK_SZ] = reg_val;
  294. exit:
  295. mutex_unlock(&chip->i2c_lock);
  296. }
  297. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  298. {
  299. struct gpio_chip *gc;
  300. gc = &chip->gpio_chip;
  301. gc->direction_input = pca953x_gpio_direction_input;
  302. gc->direction_output = pca953x_gpio_direction_output;
  303. gc->get = pca953x_gpio_get_value;
  304. gc->set = pca953x_gpio_set_value;
  305. gc->can_sleep = 1;
  306. gc->base = chip->gpio_start;
  307. gc->ngpio = gpios;
  308. gc->label = chip->client->name;
  309. gc->dev = &chip->client->dev;
  310. gc->owner = THIS_MODULE;
  311. gc->names = chip->names;
  312. }
  313. #ifdef CONFIG_GPIO_PCA953X_IRQ
  314. static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
  315. {
  316. struct pca953x_chip *chip;
  317. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  318. return irq_create_mapping(chip->domain, off);
  319. }
  320. static void pca953x_irq_mask(struct irq_data *d)
  321. {
  322. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  323. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  324. }
  325. static void pca953x_irq_unmask(struct irq_data *d)
  326. {
  327. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  328. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  329. }
  330. static void pca953x_irq_bus_lock(struct irq_data *d)
  331. {
  332. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  333. mutex_lock(&chip->irq_lock);
  334. }
  335. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  336. {
  337. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  338. u8 new_irqs;
  339. int level, i;
  340. /* Look for any newly setup interrupt */
  341. for (i = 0; i < NBANK(chip); i++) {
  342. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  343. new_irqs &= ~chip->reg_direction[i];
  344. while (new_irqs) {
  345. level = __ffs(new_irqs);
  346. pca953x_gpio_direction_input(&chip->gpio_chip,
  347. level + (BANK_SZ * i));
  348. new_irqs &= ~(1 << level);
  349. }
  350. }
  351. mutex_unlock(&chip->irq_lock);
  352. }
  353. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  354. {
  355. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  356. int bank_nb = d->hwirq / BANK_SZ;
  357. u8 mask = 1 << (d->hwirq % BANK_SZ);
  358. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  359. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  360. d->irq, type);
  361. return -EINVAL;
  362. }
  363. if (type & IRQ_TYPE_EDGE_FALLING)
  364. chip->irq_trig_fall[bank_nb] |= mask;
  365. else
  366. chip->irq_trig_fall[bank_nb] &= ~mask;
  367. if (type & IRQ_TYPE_EDGE_RISING)
  368. chip->irq_trig_raise[bank_nb] |= mask;
  369. else
  370. chip->irq_trig_raise[bank_nb] &= ~mask;
  371. return 0;
  372. }
  373. static struct irq_chip pca953x_irq_chip = {
  374. .name = "pca953x",
  375. .irq_mask = pca953x_irq_mask,
  376. .irq_unmask = pca953x_irq_unmask,
  377. .irq_bus_lock = pca953x_irq_bus_lock,
  378. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  379. .irq_set_type = pca953x_irq_set_type,
  380. };
  381. static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  382. {
  383. u8 cur_stat[MAX_BANK];
  384. u8 old_stat[MAX_BANK];
  385. u8 pendings = 0;
  386. u8 trigger[MAX_BANK], triggers = 0;
  387. int ret, i, offset = 0;
  388. switch (chip->chip_type) {
  389. case PCA953X_TYPE:
  390. offset = PCA953X_INPUT;
  391. break;
  392. case PCA957X_TYPE:
  393. offset = PCA957X_IN;
  394. break;
  395. }
  396. ret = pca953x_read_regs(chip, offset, cur_stat);
  397. if (ret)
  398. return 0;
  399. /* Remove output pins from the equation */
  400. for (i = 0; i < NBANK(chip); i++)
  401. cur_stat[i] &= chip->reg_direction[i];
  402. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  403. for (i = 0; i < NBANK(chip); i++) {
  404. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  405. triggers += trigger[i];
  406. }
  407. if (!triggers)
  408. return 0;
  409. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  410. for (i = 0; i < NBANK(chip); i++) {
  411. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  412. (cur_stat[i] & chip->irq_trig_raise[i]);
  413. pending[i] &= trigger[i];
  414. pendings += pending[i];
  415. }
  416. return pendings;
  417. }
  418. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  419. {
  420. struct pca953x_chip *chip = devid;
  421. u8 pending[MAX_BANK];
  422. u8 level;
  423. int i;
  424. if (!pca953x_irq_pending(chip, pending))
  425. return IRQ_HANDLED;
  426. for (i = 0; i < NBANK(chip); i++) {
  427. while (pending[i]) {
  428. level = __ffs(pending[i]);
  429. handle_nested_irq(irq_find_mapping(chip->domain,
  430. level + (BANK_SZ * i)));
  431. pending[i] &= ~(1 << level);
  432. }
  433. }
  434. return IRQ_HANDLED;
  435. }
  436. static int pca953x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  437. irq_hw_number_t hwirq)
  438. {
  439. irq_clear_status_flags(irq, IRQ_NOREQUEST);
  440. irq_set_chip_data(irq, d->host_data);
  441. irq_set_chip(irq, &pca953x_irq_chip);
  442. irq_set_nested_thread(irq, true);
  443. #ifdef CONFIG_ARM
  444. set_irq_flags(irq, IRQF_VALID);
  445. #else
  446. irq_set_noprobe(irq);
  447. #endif
  448. return 0;
  449. }
  450. static const struct irq_domain_ops pca953x_irq_simple_ops = {
  451. .map = pca953x_gpio_irq_map,
  452. .xlate = irq_domain_xlate_twocell,
  453. };
  454. static int pca953x_irq_setup(struct pca953x_chip *chip,
  455. const struct i2c_device_id *id,
  456. int irq_base)
  457. {
  458. struct i2c_client *client = chip->client;
  459. int ret, i, offset = 0;
  460. if (irq_base != -1
  461. && (id->driver_data & PCA_INT)) {
  462. switch (chip->chip_type) {
  463. case PCA953X_TYPE:
  464. offset = PCA953X_INPUT;
  465. break;
  466. case PCA957X_TYPE:
  467. offset = PCA957X_IN;
  468. break;
  469. }
  470. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  471. if (ret)
  472. return ret;
  473. /*
  474. * There is no way to know which GPIO line generated the
  475. * interrupt. We have to rely on the previous read for
  476. * this purpose.
  477. */
  478. for (i = 0; i < NBANK(chip); i++)
  479. chip->irq_stat[i] &= chip->reg_direction[i];
  480. mutex_init(&chip->irq_lock);
  481. chip->domain = irq_domain_add_simple(client->dev.of_node,
  482. chip->gpio_chip.ngpio,
  483. irq_base,
  484. &pca953x_irq_simple_ops,
  485. chip);
  486. if (!chip->domain)
  487. return -ENODEV;
  488. ret = devm_request_threaded_irq(&client->dev,
  489. client->irq,
  490. NULL,
  491. pca953x_irq_handler,
  492. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  493. dev_name(&client->dev), chip);
  494. if (ret) {
  495. dev_err(&client->dev, "failed to request irq %d\n",
  496. client->irq);
  497. return ret;
  498. }
  499. chip->gpio_chip.to_irq = pca953x_gpio_to_irq;
  500. }
  501. return 0;
  502. }
  503. #else /* CONFIG_GPIO_PCA953X_IRQ */
  504. static int pca953x_irq_setup(struct pca953x_chip *chip,
  505. const struct i2c_device_id *id,
  506. int irq_base)
  507. {
  508. struct i2c_client *client = chip->client;
  509. if (irq_base != -1 && (id->driver_data & PCA_INT))
  510. dev_warn(&client->dev, "interrupt support not compiled in\n");
  511. return 0;
  512. }
  513. #endif
  514. /*
  515. * Handlers for alternative sources of platform_data
  516. */
  517. #ifdef CONFIG_OF_GPIO
  518. /*
  519. * Translate OpenFirmware node properties into platform_data
  520. * WARNING: This is DEPRECATED and will be removed eventually!
  521. */
  522. static void
  523. pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
  524. {
  525. struct device_node *node;
  526. const __be32 *val;
  527. int size;
  528. node = client->dev.of_node;
  529. if (node == NULL)
  530. return;
  531. *gpio_base = -1;
  532. val = of_get_property(node, "linux,gpio-base", &size);
  533. WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
  534. if (val) {
  535. if (size != sizeof(*val))
  536. dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
  537. node->full_name);
  538. else
  539. *gpio_base = be32_to_cpup(val);
  540. }
  541. val = of_get_property(node, "polarity", NULL);
  542. WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__);
  543. if (val)
  544. *invert = *val;
  545. }
  546. #else
  547. static void
  548. pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
  549. {
  550. *gpio_base = -1;
  551. }
  552. #endif
  553. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  554. {
  555. int ret;
  556. u8 val[MAX_BANK];
  557. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  558. if (ret)
  559. goto out;
  560. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  561. chip->reg_direction);
  562. if (ret)
  563. goto out;
  564. /* set platform specific polarity inversion */
  565. if (invert)
  566. memset(val, 0xFF, NBANK(chip));
  567. else
  568. memset(val, 0, NBANK(chip));
  569. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  570. out:
  571. return ret;
  572. }
  573. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  574. {
  575. int ret;
  576. u8 val[MAX_BANK];
  577. /* Let every port in proper state, that could save power */
  578. memset(val, 0, NBANK(chip));
  579. pca953x_write_regs(chip, PCA957X_PUPD, val);
  580. memset(val, 0xFF, NBANK(chip));
  581. pca953x_write_regs(chip, PCA957X_CFG, val);
  582. memset(val, 0, NBANK(chip));
  583. pca953x_write_regs(chip, PCA957X_OUT, val);
  584. ret = pca953x_read_regs(chip, PCA957X_IN, val);
  585. if (ret)
  586. goto out;
  587. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  588. if (ret)
  589. goto out;
  590. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  591. if (ret)
  592. goto out;
  593. /* set platform specific polarity inversion */
  594. if (invert)
  595. memset(val, 0xFF, NBANK(chip));
  596. else
  597. memset(val, 0, NBANK(chip));
  598. pca953x_write_regs(chip, PCA957X_INVRT, val);
  599. /* To enable register 6, 7 to controll pull up and pull down */
  600. memset(val, 0x02, NBANK(chip));
  601. pca953x_write_regs(chip, PCA957X_BKEN, val);
  602. return 0;
  603. out:
  604. return ret;
  605. }
  606. static int pca953x_probe(struct i2c_client *client,
  607. const struct i2c_device_id *id)
  608. {
  609. struct pca953x_platform_data *pdata;
  610. struct pca953x_chip *chip;
  611. int irq_base = 0;
  612. int ret;
  613. u32 invert = 0;
  614. chip = devm_kzalloc(&client->dev,
  615. sizeof(struct pca953x_chip), GFP_KERNEL);
  616. if (chip == NULL)
  617. return -ENOMEM;
  618. pdata = client->dev.platform_data;
  619. if (pdata) {
  620. irq_base = pdata->irq_base;
  621. chip->gpio_start = pdata->gpio_base;
  622. invert = pdata->invert;
  623. chip->names = pdata->names;
  624. } else {
  625. pca953x_get_alt_pdata(client, &chip->gpio_start, &invert);
  626. #ifdef CONFIG_OF_GPIO
  627. /* If I2C node has no interrupts property, disable GPIO interrupts */
  628. if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL)
  629. irq_base = -1;
  630. #endif
  631. }
  632. chip->client = client;
  633. chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
  634. mutex_init(&chip->i2c_lock);
  635. /* initialize cached registers from their original values.
  636. * we can't share this chip with another i2c master.
  637. */
  638. pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
  639. if (chip->chip_type == PCA953X_TYPE)
  640. ret = device_pca953x_init(chip, invert);
  641. else
  642. ret = device_pca957x_init(chip, invert);
  643. if (ret)
  644. return ret;
  645. ret = pca953x_irq_setup(chip, id, irq_base);
  646. if (ret)
  647. return ret;
  648. ret = gpiochip_add(&chip->gpio_chip);
  649. if (ret)
  650. return ret;
  651. if (pdata && pdata->setup) {
  652. ret = pdata->setup(client, chip->gpio_chip.base,
  653. chip->gpio_chip.ngpio, pdata->context);
  654. if (ret < 0)
  655. dev_warn(&client->dev, "setup failed, %d\n", ret);
  656. }
  657. i2c_set_clientdata(client, chip);
  658. return 0;
  659. }
  660. static int pca953x_remove(struct i2c_client *client)
  661. {
  662. struct pca953x_platform_data *pdata = client->dev.platform_data;
  663. struct pca953x_chip *chip = i2c_get_clientdata(client);
  664. int ret = 0;
  665. if (pdata && pdata->teardown) {
  666. ret = pdata->teardown(client, chip->gpio_chip.base,
  667. chip->gpio_chip.ngpio, pdata->context);
  668. if (ret < 0) {
  669. dev_err(&client->dev, "%s failed, %d\n",
  670. "teardown", ret);
  671. return ret;
  672. }
  673. }
  674. ret = gpiochip_remove(&chip->gpio_chip);
  675. if (ret) {
  676. dev_err(&client->dev, "%s failed, %d\n",
  677. "gpiochip_remove()", ret);
  678. return ret;
  679. }
  680. return 0;
  681. }
  682. static const struct of_device_id pca953x_dt_ids[] = {
  683. { .compatible = "nxp,pca9505", },
  684. { .compatible = "nxp,pca9534", },
  685. { .compatible = "nxp,pca9535", },
  686. { .compatible = "nxp,pca9536", },
  687. { .compatible = "nxp,pca9537", },
  688. { .compatible = "nxp,pca9538", },
  689. { .compatible = "nxp,pca9539", },
  690. { .compatible = "nxp,pca9554", },
  691. { .compatible = "nxp,pca9555", },
  692. { .compatible = "nxp,pca9556", },
  693. { .compatible = "nxp,pca9557", },
  694. { .compatible = "nxp,pca9574", },
  695. { .compatible = "nxp,pca9575", },
  696. { .compatible = "maxim,max7310", },
  697. { .compatible = "maxim,max7312", },
  698. { .compatible = "maxim,max7313", },
  699. { .compatible = "maxim,max7315", },
  700. { .compatible = "ti,pca6107", },
  701. { .compatible = "ti,tca6408", },
  702. { .compatible = "ti,tca6416", },
  703. { .compatible = "ti,tca6424", },
  704. { }
  705. };
  706. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  707. static struct i2c_driver pca953x_driver = {
  708. .driver = {
  709. .name = "pca953x",
  710. .of_match_table = pca953x_dt_ids,
  711. },
  712. .probe = pca953x_probe,
  713. .remove = pca953x_remove,
  714. .id_table = pca953x_id,
  715. };
  716. static int __init pca953x_init(void)
  717. {
  718. return i2c_add_driver(&pca953x_driver);
  719. }
  720. /* register after i2c postcore initcall and before
  721. * subsys initcalls that may rely on these GPIOs
  722. */
  723. subsys_initcall(pca953x_init);
  724. static void __exit pca953x_exit(void)
  725. {
  726. i2c_del_driver(&pca953x_driver);
  727. }
  728. module_exit(pca953x_exit);
  729. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  730. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  731. MODULE_LICENSE("GPL");