main.c 37 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
  21. #define IEEE80211_ACTION_CAT_HT 7
  22. #define IEEE80211_ACTION_HT_TXCHWIDTH 0
  23. static char *dev_info = "ath9k";
  24. MODULE_AUTHOR("Atheros Communications");
  25. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27. MODULE_LICENSE("Dual BSD/GPL");
  28. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  29. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  31. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  32. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  33. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  34. { 0 }
  35. };
  36. static int ath_get_channel(struct ath_softc *sc,
  37. struct ieee80211_channel *chan)
  38. {
  39. int i;
  40. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  41. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  42. return i;
  43. }
  44. return -1;
  45. }
  46. static u32 ath_get_extchanmode(struct ath_softc *sc,
  47. struct ieee80211_channel *chan)
  48. {
  49. u32 chanmode = 0;
  50. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  51. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  52. switch (chan->band) {
  53. case IEEE80211_BAND_2GHZ:
  54. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  55. (tx_chan_width == ATH9K_HT_MACMODE_20))
  56. chanmode = CHANNEL_G_HT20;
  57. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  58. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  59. chanmode = CHANNEL_G_HT40PLUS;
  60. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  61. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  62. chanmode = CHANNEL_G_HT40MINUS;
  63. break;
  64. case IEEE80211_BAND_5GHZ:
  65. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  66. (tx_chan_width == ATH9K_HT_MACMODE_20))
  67. chanmode = CHANNEL_A_HT20;
  68. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  69. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  70. chanmode = CHANNEL_A_HT40PLUS;
  71. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  72. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  73. chanmode = CHANNEL_A_HT40MINUS;
  74. break;
  75. default:
  76. break;
  77. }
  78. return chanmode;
  79. }
  80. static int ath_setkey_tkip(struct ath_softc *sc,
  81. struct ieee80211_key_conf *key,
  82. struct ath9k_keyval *hk,
  83. const u8 *addr)
  84. {
  85. u8 *key_rxmic = NULL;
  86. u8 *key_txmic = NULL;
  87. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  88. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  89. if (addr == NULL) {
  90. /* Group key installation */
  91. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  92. return ath_keyset(sc, key->keyidx, hk, addr);
  93. }
  94. if (!sc->sc_splitmic) {
  95. /*
  96. * data key goes at first index,
  97. * the hal handles the MIC keys at index+64.
  98. */
  99. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  100. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  101. return ath_keyset(sc, key->keyidx, hk, addr);
  102. }
  103. /*
  104. * TX key goes at first index, RX key at +32.
  105. * The hal handles the MIC keys at index+64.
  106. */
  107. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  108. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  109. /* Txmic entry failed. No need to proceed further */
  110. DPRINTF(sc, ATH_DBG_KEYCACHE,
  111. "%s Setting TX MIC Key Failed\n", __func__);
  112. return 0;
  113. }
  114. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  115. /* XXX delete tx key on failure? */
  116. return ath_keyset(sc, key->keyidx+32, hk, addr);
  117. }
  118. static int ath_key_config(struct ath_softc *sc,
  119. const u8 *addr,
  120. struct ieee80211_key_conf *key)
  121. {
  122. struct ieee80211_vif *vif;
  123. struct ath9k_keyval hk;
  124. const u8 *mac = NULL;
  125. int ret = 0;
  126. enum ieee80211_if_types opmode;
  127. memset(&hk, 0, sizeof(hk));
  128. switch (key->alg) {
  129. case ALG_WEP:
  130. hk.kv_type = ATH9K_CIPHER_WEP;
  131. break;
  132. case ALG_TKIP:
  133. hk.kv_type = ATH9K_CIPHER_TKIP;
  134. break;
  135. case ALG_CCMP:
  136. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  137. break;
  138. default:
  139. return -EINVAL;
  140. }
  141. hk.kv_len = key->keylen;
  142. memcpy(hk.kv_val, key->key, key->keylen);
  143. if (!sc->sc_vaps[0])
  144. return -EIO;
  145. vif = sc->sc_vaps[0]->av_if_data;
  146. opmode = vif->type;
  147. /*
  148. * Strategy:
  149. * For _M_STA mc tx, we will not setup a key at all since we never
  150. * tx mc.
  151. * _M_STA mc rx, we will use the keyID.
  152. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  153. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  154. * peer node. BUT we will plumb a cleartext key so that we can do
  155. * perSta default key table lookup in software.
  156. */
  157. if (is_broadcast_ether_addr(addr)) {
  158. switch (opmode) {
  159. case IEEE80211_IF_TYPE_STA:
  160. /* default key: could be group WPA key
  161. * or could be static WEP key */
  162. mac = NULL;
  163. break;
  164. case IEEE80211_IF_TYPE_IBSS:
  165. break;
  166. case IEEE80211_IF_TYPE_AP:
  167. break;
  168. default:
  169. ASSERT(0);
  170. break;
  171. }
  172. } else {
  173. mac = addr;
  174. }
  175. if (key->alg == ALG_TKIP)
  176. ret = ath_setkey_tkip(sc, key, &hk, mac);
  177. else
  178. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  179. if (!ret)
  180. return -EIO;
  181. sc->sc_keytype = hk.kv_type;
  182. return 0;
  183. }
  184. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  185. {
  186. #define ATH_MAX_NUM_KEYS 4
  187. int freeslot;
  188. freeslot = (key->keyidx >= ATH_MAX_NUM_KEYS) ? 1 : 0;
  189. ath_key_reset(sc, key->keyidx, freeslot);
  190. #undef ATH_MAX_NUM_KEYS
  191. }
  192. static void setup_ht_cap(struct ieee80211_ht_info *ht_info)
  193. {
  194. /* Until mac80211 includes these fields */
  195. #define IEEE80211_HT_CAP_DSSSCCK40 0x1000
  196. #define IEEE80211_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  197. #define IEEE80211_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  198. ht_info->ht_supported = 1;
  199. ht_info->cap = (u16)IEEE80211_HT_CAP_SUP_WIDTH
  200. |(u16)IEEE80211_HT_CAP_MIMO_PS
  201. |(u16)IEEE80211_HT_CAP_SGI_40
  202. |(u16)IEEE80211_HT_CAP_DSSSCCK40;
  203. ht_info->ampdu_factor = IEEE80211_HT_CAP_MAXRXAMPDU_65536;
  204. ht_info->ampdu_density = IEEE80211_HT_CAP_MPDUDENSITY_8;
  205. /* setup supported mcs set */
  206. memset(ht_info->supp_mcs_set, 0, 16);
  207. ht_info->supp_mcs_set[0] = 0xff;
  208. ht_info->supp_mcs_set[1] = 0xff;
  209. ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
  210. }
  211. static int ath_rate2idx(struct ath_softc *sc, int rate)
  212. {
  213. int i = 0, cur_band, n_rates;
  214. struct ieee80211_hw *hw = sc->hw;
  215. cur_band = hw->conf.channel->band;
  216. n_rates = sc->sbands[cur_band].n_bitrates;
  217. for (i = 0; i < n_rates; i++) {
  218. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  219. break;
  220. }
  221. /*
  222. * NB:mac80211 validates rx rate index against the supported legacy rate
  223. * index only (should be done against ht rates also), return the highest
  224. * legacy rate index for rx rate which does not match any one of the
  225. * supported basic and extended rates to make mac80211 happy.
  226. * The following hack will be cleaned up once the issue with
  227. * the rx rate index validation in mac80211 is fixed.
  228. */
  229. if (i == n_rates)
  230. return n_rates - 1;
  231. return i;
  232. }
  233. static void ath9k_rx_prepare(struct ath_softc *sc,
  234. struct sk_buff *skb,
  235. struct ath_recv_status *status,
  236. struct ieee80211_rx_status *rx_status)
  237. {
  238. struct ieee80211_hw *hw = sc->hw;
  239. struct ieee80211_channel *curchan = hw->conf.channel;
  240. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  241. rx_status->mactime = status->tsf;
  242. rx_status->band = curchan->band;
  243. rx_status->freq = curchan->center_freq;
  244. rx_status->noise = ATH_DEFAULT_NOISE_FLOOR;
  245. rx_status->signal = rx_status->noise + status->rssi;
  246. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  247. rx_status->antenna = status->antenna;
  248. rx_status->qual = status->rssi * 100 / 64;
  249. if (status->flags & ATH_RX_MIC_ERROR)
  250. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  251. if (status->flags & ATH_RX_FCS_ERROR)
  252. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  253. rx_status->flag |= RX_FLAG_TSFT;
  254. }
  255. static u8 parse_mpdudensity(u8 mpdudensity)
  256. {
  257. /*
  258. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  259. * 0 for no restriction
  260. * 1 for 1/4 us
  261. * 2 for 1/2 us
  262. * 3 for 1 us
  263. * 4 for 2 us
  264. * 5 for 4 us
  265. * 6 for 8 us
  266. * 7 for 16 us
  267. */
  268. switch (mpdudensity) {
  269. case 0:
  270. return 0;
  271. case 1:
  272. case 2:
  273. case 3:
  274. /* Our lower layer calculations limit our precision to
  275. 1 microsecond */
  276. return 1;
  277. case 4:
  278. return 2;
  279. case 5:
  280. return 4;
  281. case 6:
  282. return 8;
  283. case 7:
  284. return 16;
  285. default:
  286. return 0;
  287. }
  288. }
  289. static int ath9k_start(struct ieee80211_hw *hw)
  290. {
  291. struct ath_softc *sc = hw->priv;
  292. struct ieee80211_channel *curchan = hw->conf.channel;
  293. int error = 0, pos;
  294. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  295. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  296. /* setup initial channel */
  297. pos = ath_get_channel(sc, curchan);
  298. if (pos == -1) {
  299. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  300. return -EINVAL;
  301. }
  302. sc->sc_ah->ah_channels[pos].chanmode =
  303. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  304. /* open ath_dev */
  305. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  306. if (error) {
  307. DPRINTF(sc, ATH_DBG_FATAL,
  308. "%s: Unable to complete ath_open\n", __func__);
  309. return error;
  310. }
  311. ieee80211_wake_queues(hw);
  312. return 0;
  313. }
  314. static int ath9k_tx(struct ieee80211_hw *hw,
  315. struct sk_buff *skb)
  316. {
  317. struct ath_softc *sc = hw->priv;
  318. int hdrlen, padsize;
  319. /* Add the padding after the header if this is not already done */
  320. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  321. if (hdrlen & 3) {
  322. padsize = hdrlen % 4;
  323. if (skb_headroom(skb) < padsize)
  324. return -1;
  325. skb_push(skb, padsize);
  326. memmove(skb->data, skb->data + padsize, hdrlen);
  327. }
  328. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  329. __func__,
  330. skb);
  331. if (ath_tx_start(sc, skb) != 0) {
  332. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  333. dev_kfree_skb_any(skb);
  334. /* FIXME: Check for proper return value from ATH_DEV */
  335. return 0;
  336. }
  337. return 0;
  338. }
  339. static void ath9k_stop(struct ieee80211_hw *hw)
  340. {
  341. struct ath_softc *sc = hw->priv;
  342. int error;
  343. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  344. error = ath_suspend(sc);
  345. if (error)
  346. DPRINTF(sc, ATH_DBG_CONFIG,
  347. "%s: Device is no longer present\n", __func__);
  348. ieee80211_stop_queues(hw);
  349. }
  350. static int ath9k_add_interface(struct ieee80211_hw *hw,
  351. struct ieee80211_if_init_conf *conf)
  352. {
  353. struct ath_softc *sc = hw->priv;
  354. int error, ic_opmode = 0;
  355. /* Support only vap for now */
  356. if (sc->sc_nvaps)
  357. return -ENOBUFS;
  358. switch (conf->type) {
  359. case IEEE80211_IF_TYPE_STA:
  360. ic_opmode = ATH9K_M_STA;
  361. break;
  362. case IEEE80211_IF_TYPE_IBSS:
  363. ic_opmode = ATH9K_M_IBSS;
  364. break;
  365. case IEEE80211_IF_TYPE_AP:
  366. ic_opmode = ATH9K_M_HOSTAP;
  367. break;
  368. default:
  369. DPRINTF(sc, ATH_DBG_FATAL,
  370. "%s: Interface type %d not yet supported\n",
  371. __func__, conf->type);
  372. return -EOPNOTSUPP;
  373. }
  374. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  375. __func__,
  376. ic_opmode);
  377. error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
  378. if (error) {
  379. DPRINTF(sc, ATH_DBG_FATAL,
  380. "%s: Unable to attach vap, error: %d\n",
  381. __func__, error);
  382. return error;
  383. }
  384. return 0;
  385. }
  386. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  387. struct ieee80211_if_init_conf *conf)
  388. {
  389. struct ath_softc *sc = hw->priv;
  390. struct ath_vap *avp;
  391. int error;
  392. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  393. avp = sc->sc_vaps[0];
  394. if (avp == NULL) {
  395. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  396. __func__);
  397. return;
  398. }
  399. #ifdef CONFIG_SLOW_ANT_DIV
  400. ath_slow_ant_div_stop(&sc->sc_antdiv);
  401. #endif
  402. /* Update ratectrl */
  403. ath_rate_newstate(sc, avp);
  404. /* Reclaim beacon resources */
  405. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  406. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  407. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  408. ath_beacon_return(sc, avp);
  409. }
  410. /* Set interrupt mask */
  411. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  412. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
  413. sc->sc_flags &= ~SC_OP_BEACONS;
  414. error = ath_vap_detach(sc, 0);
  415. if (error)
  416. DPRINTF(sc, ATH_DBG_FATAL,
  417. "%s: Unable to detach vap, error: %d\n",
  418. __func__, error);
  419. }
  420. static int ath9k_config(struct ieee80211_hw *hw,
  421. struct ieee80211_conf *conf)
  422. {
  423. struct ath_softc *sc = hw->priv;
  424. struct ieee80211_channel *curchan = hw->conf.channel;
  425. int pos;
  426. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  427. __func__,
  428. curchan->center_freq);
  429. pos = ath_get_channel(sc, curchan);
  430. if (pos == -1) {
  431. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  432. return -EINVAL;
  433. }
  434. sc->sc_ah->ah_channels[pos].chanmode =
  435. (curchan->band == IEEE80211_BAND_2GHZ) ?
  436. CHANNEL_G : CHANNEL_A;
  437. if (sc->sc_curaid && hw->conf.ht_conf.ht_supported)
  438. sc->sc_ah->ah_channels[pos].chanmode =
  439. ath_get_extchanmode(sc, curchan);
  440. sc->sc_config.txpowlimit = 2 * conf->power_level;
  441. /* set h/w channel */
  442. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  443. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  444. __func__);
  445. return 0;
  446. }
  447. static int ath9k_config_interface(struct ieee80211_hw *hw,
  448. struct ieee80211_vif *vif,
  449. struct ieee80211_if_conf *conf)
  450. {
  451. struct ath_softc *sc = hw->priv;
  452. struct ath_hal *ah = sc->sc_ah;
  453. struct ath_vap *avp;
  454. u32 rfilt = 0;
  455. int error, i;
  456. DECLARE_MAC_BUF(mac);
  457. avp = sc->sc_vaps[0];
  458. if (avp == NULL) {
  459. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  460. __func__);
  461. return -EINVAL;
  462. }
  463. /* TODO: Need to decide which hw opmode to use for multi-interface
  464. * cases */
  465. if (vif->type == IEEE80211_IF_TYPE_AP &&
  466. ah->ah_opmode != ATH9K_M_HOSTAP) {
  467. ah->ah_opmode = ATH9K_M_HOSTAP;
  468. ath9k_hw_setopmode(ah);
  469. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  470. /* Request full reset to get hw opmode changed properly */
  471. sc->sc_flags |= SC_OP_FULL_RESET;
  472. }
  473. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  474. !is_zero_ether_addr(conf->bssid)) {
  475. switch (vif->type) {
  476. case IEEE80211_IF_TYPE_STA:
  477. case IEEE80211_IF_TYPE_IBSS:
  478. /* Update ratectrl about the new state */
  479. ath_rate_newstate(sc, avp);
  480. /* Set BSSID */
  481. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  482. sc->sc_curaid = 0;
  483. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  484. sc->sc_curaid);
  485. /* Set aggregation protection mode parameters */
  486. sc->sc_config.ath_aggr_prot = 0;
  487. /*
  488. * Reset our TSF so that its value is lower than the
  489. * beacon that we are trying to catch.
  490. * Only then hw will update its TSF register with the
  491. * new beacon. Reset the TSF before setting the BSSID
  492. * to avoid allowing in any frames that would update
  493. * our TSF only to have us clear it
  494. * immediately thereafter.
  495. */
  496. ath9k_hw_reset_tsf(sc->sc_ah);
  497. /* Disable BMISS interrupt when we're not associated */
  498. ath9k_hw_set_interrupts(sc->sc_ah,
  499. sc->sc_imask &
  500. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  501. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  502. DPRINTF(sc, ATH_DBG_CONFIG,
  503. "%s: RX filter 0x%x bssid %s aid 0x%x\n",
  504. __func__, rfilt,
  505. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  506. /* need to reconfigure the beacon */
  507. sc->sc_flags &= ~SC_OP_BEACONS ;
  508. break;
  509. default:
  510. break;
  511. }
  512. }
  513. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  514. (vif->type == IEEE80211_IF_TYPE_IBSS)) {
  515. /*
  516. * Allocate and setup the beacon frame.
  517. *
  518. * Stop any previous beacon DMA. This may be
  519. * necessary, for example, when an ibss merge
  520. * causes reconfiguration; we may be called
  521. * with beacon transmission active.
  522. */
  523. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  524. error = ath_beacon_alloc(sc, 0);
  525. if (error != 0)
  526. return error;
  527. ath_beacon_sync(sc, 0);
  528. }
  529. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  530. (vif->type == IEEE80211_IF_TYPE_AP)) {
  531. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  532. error = ath_beacon_alloc(sc, 0);
  533. if (error != 0)
  534. return error;
  535. ath_beacon_config(sc, 0);
  536. sc->sc_flags |= SC_OP_BEACONS;
  537. }
  538. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  539. if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
  540. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  541. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  542. ath9k_hw_keysetmac(sc->sc_ah,
  543. (u16)i,
  544. sc->sc_curbssid);
  545. }
  546. /* Only legacy IBSS for now */
  547. if (vif->type == IEEE80211_IF_TYPE_IBSS)
  548. ath_update_chainmask(sc, 0);
  549. return 0;
  550. }
  551. #define SUPPORTED_FILTERS \
  552. (FIF_PROMISC_IN_BSS | \
  553. FIF_ALLMULTI | \
  554. FIF_CONTROL | \
  555. FIF_OTHER_BSS | \
  556. FIF_BCN_PRBRESP_PROMISC | \
  557. FIF_FCSFAIL)
  558. /* FIXME: sc->sc_full_reset ? */
  559. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  560. unsigned int changed_flags,
  561. unsigned int *total_flags,
  562. int mc_count,
  563. struct dev_mc_list *mclist)
  564. {
  565. struct ath_softc *sc = hw->priv;
  566. u32 rfilt;
  567. changed_flags &= SUPPORTED_FILTERS;
  568. *total_flags &= SUPPORTED_FILTERS;
  569. sc->rx_filter = *total_flags;
  570. rfilt = ath_calcrxfilter(sc);
  571. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  572. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  573. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  574. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  575. }
  576. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  577. __func__, sc->rx_filter);
  578. }
  579. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  580. struct ieee80211_vif *vif,
  581. enum sta_notify_cmd cmd,
  582. const u8 *addr)
  583. {
  584. struct ath_softc *sc = hw->priv;
  585. struct ath_node *an;
  586. unsigned long flags;
  587. DECLARE_MAC_BUF(mac);
  588. spin_lock_irqsave(&sc->node_lock, flags);
  589. an = ath_node_find(sc, (u8 *) addr);
  590. spin_unlock_irqrestore(&sc->node_lock, flags);
  591. switch (cmd) {
  592. case STA_NOTIFY_ADD:
  593. spin_lock_irqsave(&sc->node_lock, flags);
  594. if (!an) {
  595. ath_node_attach(sc, (u8 *)addr, 0);
  596. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n",
  597. __func__,
  598. print_mac(mac, addr));
  599. } else {
  600. ath_node_get(sc, (u8 *)addr);
  601. }
  602. spin_unlock_irqrestore(&sc->node_lock, flags);
  603. break;
  604. case STA_NOTIFY_REMOVE:
  605. if (!an)
  606. DPRINTF(sc, ATH_DBG_FATAL,
  607. "%s: Removal of a non-existent node\n",
  608. __func__);
  609. else {
  610. ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
  611. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n",
  612. __func__,
  613. print_mac(mac, addr));
  614. }
  615. break;
  616. default:
  617. break;
  618. }
  619. }
  620. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  621. u16 queue,
  622. const struct ieee80211_tx_queue_params *params)
  623. {
  624. struct ath_softc *sc = hw->priv;
  625. struct ath9k_tx_queue_info qi;
  626. int ret = 0, qnum;
  627. if (queue >= WME_NUM_AC)
  628. return 0;
  629. qi.tqi_aifs = params->aifs;
  630. qi.tqi_cwmin = params->cw_min;
  631. qi.tqi_cwmax = params->cw_max;
  632. qi.tqi_burstTime = params->txop;
  633. qnum = ath_get_hal_qnum(queue, sc);
  634. DPRINTF(sc, ATH_DBG_CONFIG,
  635. "%s: Configure tx [queue/halq] [%d/%d], "
  636. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  637. __func__,
  638. queue,
  639. qnum,
  640. params->aifs,
  641. params->cw_min,
  642. params->cw_max,
  643. params->txop);
  644. ret = ath_txq_update(sc, qnum, &qi);
  645. if (ret)
  646. DPRINTF(sc, ATH_DBG_FATAL,
  647. "%s: TXQ Update failed\n", __func__);
  648. return ret;
  649. }
  650. static int ath9k_set_key(struct ieee80211_hw *hw,
  651. enum set_key_cmd cmd,
  652. const u8 *local_addr,
  653. const u8 *addr,
  654. struct ieee80211_key_conf *key)
  655. {
  656. struct ath_softc *sc = hw->priv;
  657. int ret = 0;
  658. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  659. switch (cmd) {
  660. case SET_KEY:
  661. ret = ath_key_config(sc, addr, key);
  662. if (!ret) {
  663. set_bit(key->keyidx, sc->sc_keymap);
  664. key->hw_key_idx = key->keyidx;
  665. /* push IV and Michael MIC generation to stack */
  666. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  667. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  668. }
  669. break;
  670. case DISABLE_KEY:
  671. ath_key_delete(sc, key);
  672. clear_bit(key->keyidx, sc->sc_keymap);
  673. sc->sc_keytype = ATH9K_CIPHER_CLR;
  674. break;
  675. default:
  676. ret = -EINVAL;
  677. }
  678. return ret;
  679. }
  680. static void ath9k_ht_conf(struct ath_softc *sc,
  681. struct ieee80211_bss_conf *bss_conf)
  682. {
  683. #define IEEE80211_HT_CAP_40MHZ_INTOLERANT BIT(14)
  684. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  685. if (bss_conf->assoc_ht) {
  686. ht_info->ext_chan_offset =
  687. bss_conf->ht_bss_conf->bss_cap &
  688. IEEE80211_HT_IE_CHA_SEC_OFFSET;
  689. if (!(bss_conf->ht_conf->cap &
  690. IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
  691. (bss_conf->ht_bss_conf->bss_cap &
  692. IEEE80211_HT_IE_CHA_WIDTH))
  693. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  694. else
  695. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  696. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  697. ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
  698. bss_conf->ht_conf->ampdu_factor);
  699. ht_info->mpdudensity =
  700. parse_mpdudensity(bss_conf->ht_conf->ampdu_density);
  701. }
  702. #undef IEEE80211_HT_CAP_40MHZ_INTOLERANT
  703. }
  704. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  705. struct ieee80211_bss_conf *bss_conf)
  706. {
  707. struct ieee80211_hw *hw = sc->hw;
  708. struct ieee80211_channel *curchan = hw->conf.channel;
  709. struct ath_vap *avp;
  710. int pos;
  711. DECLARE_MAC_BUF(mac);
  712. if (bss_conf->assoc) {
  713. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  714. __func__,
  715. bss_conf->aid);
  716. avp = sc->sc_vaps[0];
  717. if (avp == NULL) {
  718. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  719. __func__);
  720. return;
  721. }
  722. /* New association, store aid */
  723. if (avp->av_opmode == ATH9K_M_STA) {
  724. sc->sc_curaid = bss_conf->aid;
  725. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  726. sc->sc_curaid);
  727. }
  728. /* Configure the beacon */
  729. ath_beacon_config(sc, 0);
  730. sc->sc_flags |= SC_OP_BEACONS;
  731. /* Reset rssi stats */
  732. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  733. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  734. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  735. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  736. /* Update chainmask */
  737. ath_update_chainmask(sc, bss_conf->assoc_ht);
  738. DPRINTF(sc, ATH_DBG_CONFIG,
  739. "%s: bssid %s aid 0x%x\n",
  740. __func__,
  741. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  742. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  743. __func__,
  744. curchan->center_freq);
  745. pos = ath_get_channel(sc, curchan);
  746. if (pos == -1) {
  747. DPRINTF(sc, ATH_DBG_FATAL,
  748. "%s: Invalid channel\n", __func__);
  749. return;
  750. }
  751. if (hw->conf.ht_conf.ht_supported)
  752. sc->sc_ah->ah_channels[pos].chanmode =
  753. ath_get_extchanmode(sc, curchan);
  754. else
  755. sc->sc_ah->ah_channels[pos].chanmode =
  756. (curchan->band == IEEE80211_BAND_2GHZ) ?
  757. CHANNEL_G : CHANNEL_A;
  758. /* set h/w channel */
  759. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  760. DPRINTF(sc, ATH_DBG_FATAL,
  761. "%s: Unable to set channel\n",
  762. __func__);
  763. ath_rate_newstate(sc, avp);
  764. /* Update ratectrl about the new state */
  765. ath_rc_node_update(hw, avp->rc_node);
  766. } else {
  767. DPRINTF(sc, ATH_DBG_CONFIG,
  768. "%s: Bss Info DISSOC\n", __func__);
  769. sc->sc_curaid = 0;
  770. }
  771. }
  772. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  773. struct ieee80211_vif *vif,
  774. struct ieee80211_bss_conf *bss_conf,
  775. u32 changed)
  776. {
  777. struct ath_softc *sc = hw->priv;
  778. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  779. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  780. __func__,
  781. bss_conf->use_short_preamble);
  782. if (bss_conf->use_short_preamble)
  783. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  784. else
  785. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  786. }
  787. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  788. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  789. __func__,
  790. bss_conf->use_cts_prot);
  791. if (bss_conf->use_cts_prot &&
  792. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  793. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  794. else
  795. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  796. }
  797. if (changed & BSS_CHANGED_HT) {
  798. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
  799. __func__,
  800. bss_conf->assoc_ht);
  801. ath9k_ht_conf(sc, bss_conf);
  802. }
  803. if (changed & BSS_CHANGED_ASSOC) {
  804. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  805. __func__,
  806. bss_conf->assoc);
  807. ath9k_bss_assoc_info(sc, bss_conf);
  808. }
  809. }
  810. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  811. {
  812. u64 tsf;
  813. struct ath_softc *sc = hw->priv;
  814. struct ath_hal *ah = sc->sc_ah;
  815. tsf = ath9k_hw_gettsf64(ah);
  816. return tsf;
  817. }
  818. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  819. {
  820. struct ath_softc *sc = hw->priv;
  821. struct ath_hal *ah = sc->sc_ah;
  822. ath9k_hw_reset_tsf(ah);
  823. }
  824. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  825. enum ieee80211_ampdu_mlme_action action,
  826. const u8 *addr,
  827. u16 tid,
  828. u16 *ssn)
  829. {
  830. struct ath_softc *sc = hw->priv;
  831. int ret = 0;
  832. switch (action) {
  833. case IEEE80211_AMPDU_RX_START:
  834. ret = ath_rx_aggr_start(sc, addr, tid, ssn);
  835. if (ret < 0)
  836. DPRINTF(sc, ATH_DBG_FATAL,
  837. "%s: Unable to start RX aggregation\n",
  838. __func__);
  839. break;
  840. case IEEE80211_AMPDU_RX_STOP:
  841. ret = ath_rx_aggr_stop(sc, addr, tid);
  842. if (ret < 0)
  843. DPRINTF(sc, ATH_DBG_FATAL,
  844. "%s: Unable to stop RX aggregation\n",
  845. __func__);
  846. break;
  847. case IEEE80211_AMPDU_TX_START:
  848. ret = ath_tx_aggr_start(sc, addr, tid, ssn);
  849. if (ret < 0)
  850. DPRINTF(sc, ATH_DBG_FATAL,
  851. "%s: Unable to start TX aggregation\n",
  852. __func__);
  853. else
  854. ieee80211_start_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
  855. break;
  856. case IEEE80211_AMPDU_TX_STOP:
  857. ret = ath_tx_aggr_stop(sc, addr, tid);
  858. if (ret < 0)
  859. DPRINTF(sc, ATH_DBG_FATAL,
  860. "%s: Unable to stop TX aggregation\n",
  861. __func__);
  862. ieee80211_stop_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
  863. break;
  864. default:
  865. DPRINTF(sc, ATH_DBG_FATAL,
  866. "%s: Unknown AMPDU action\n", __func__);
  867. }
  868. return ret;
  869. }
  870. static struct ieee80211_ops ath9k_ops = {
  871. .tx = ath9k_tx,
  872. .start = ath9k_start,
  873. .stop = ath9k_stop,
  874. .add_interface = ath9k_add_interface,
  875. .remove_interface = ath9k_remove_interface,
  876. .config = ath9k_config,
  877. .config_interface = ath9k_config_interface,
  878. .configure_filter = ath9k_configure_filter,
  879. .get_stats = NULL,
  880. .sta_notify = ath9k_sta_notify,
  881. .conf_tx = ath9k_conf_tx,
  882. .get_tx_stats = NULL,
  883. .bss_info_changed = ath9k_bss_info_changed,
  884. .set_tim = NULL,
  885. .set_key = ath9k_set_key,
  886. .hw_scan = NULL,
  887. .get_tkip_seq = NULL,
  888. .set_rts_threshold = NULL,
  889. .set_frag_threshold = NULL,
  890. .set_retry_limit = NULL,
  891. .get_tsf = ath9k_get_tsf,
  892. .reset_tsf = ath9k_reset_tsf,
  893. .tx_last_beacon = NULL,
  894. .ampdu_action = ath9k_ampdu_action
  895. };
  896. void ath_get_beaconconfig(struct ath_softc *sc,
  897. int if_id,
  898. struct ath_beacon_config *conf)
  899. {
  900. struct ieee80211_hw *hw = sc->hw;
  901. /* fill in beacon config data */
  902. conf->beacon_interval = hw->conf.beacon_int;
  903. conf->listen_interval = 100;
  904. conf->dtim_count = 1;
  905. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  906. }
  907. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  908. struct ath_xmit_status *tx_status, struct ath_node *an)
  909. {
  910. struct ieee80211_hw *hw = sc->hw;
  911. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  912. DPRINTF(sc, ATH_DBG_XMIT,
  913. "%s: TX complete: skb: %p\n", __func__, skb);
  914. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  915. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  916. /* free driver's private data area of tx_info */
  917. if (tx_info->driver_data[0] != NULL)
  918. kfree(tx_info->driver_data[0]);
  919. tx_info->driver_data[0] = NULL;
  920. }
  921. if (tx_status->flags & ATH_TX_BAR) {
  922. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  923. tx_status->flags &= ~ATH_TX_BAR;
  924. }
  925. if (tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY)) {
  926. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  927. /* Frame was not ACKed, but an ACK was expected */
  928. tx_info->status.excessive_retries = 1;
  929. }
  930. } else {
  931. /* Frame was ACKed */
  932. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  933. }
  934. tx_info->status.retry_count = tx_status->retries;
  935. ieee80211_tx_status(hw, skb);
  936. if (an)
  937. ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
  938. }
  939. int ath__rx_indicate(struct ath_softc *sc,
  940. struct sk_buff *skb,
  941. struct ath_recv_status *status,
  942. u16 keyix)
  943. {
  944. struct ieee80211_hw *hw = sc->hw;
  945. struct ath_node *an = NULL;
  946. struct ieee80211_rx_status rx_status;
  947. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  948. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  949. int padsize;
  950. enum ATH_RX_TYPE st;
  951. /* see if any padding is done by the hw and remove it */
  952. if (hdrlen & 3) {
  953. padsize = hdrlen % 4;
  954. memmove(skb->data + padsize, skb->data, hdrlen);
  955. skb_pull(skb, padsize);
  956. }
  957. /* remove FCS before passing up to protocol stack */
  958. skb_trim(skb, (skb->len - FCS_LEN));
  959. /* Prepare rx status */
  960. ath9k_rx_prepare(sc, skb, status, &rx_status);
  961. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  962. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  963. rx_status.flag |= RX_FLAG_DECRYPTED;
  964. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  965. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  966. && skb->len >= hdrlen + 4) {
  967. keyix = skb->data[hdrlen + 3] >> 6;
  968. if (test_bit(keyix, sc->sc_keymap))
  969. rx_status.flag |= RX_FLAG_DECRYPTED;
  970. }
  971. spin_lock_bh(&sc->node_lock);
  972. an = ath_node_find(sc, hdr->addr2);
  973. spin_unlock_bh(&sc->node_lock);
  974. if (an) {
  975. ath_rx_input(sc, an,
  976. hw->conf.ht_conf.ht_supported,
  977. skb, status, &st);
  978. }
  979. if (!an || (st != ATH_RX_CONSUMED))
  980. __ieee80211_rx(hw, skb, &rx_status);
  981. return 0;
  982. }
  983. int ath_rx_subframe(struct ath_node *an,
  984. struct sk_buff *skb,
  985. struct ath_recv_status *status)
  986. {
  987. struct ath_softc *sc = an->an_sc;
  988. struct ieee80211_hw *hw = sc->hw;
  989. struct ieee80211_rx_status rx_status;
  990. /* Prepare rx status */
  991. ath9k_rx_prepare(sc, skb, status, &rx_status);
  992. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  993. rx_status.flag |= RX_FLAG_DECRYPTED;
  994. __ieee80211_rx(hw, skb, &rx_status);
  995. return 0;
  996. }
  997. enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
  998. {
  999. return sc->sc_ht_info.tx_chan_width;
  1000. }
  1001. static int ath_detach(struct ath_softc *sc)
  1002. {
  1003. struct ieee80211_hw *hw = sc->hw;
  1004. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  1005. /* Unregister hw */
  1006. ieee80211_unregister_hw(hw);
  1007. /* unregister Rate control */
  1008. ath_rate_control_unregister();
  1009. /* tx/rx cleanup */
  1010. ath_rx_cleanup(sc);
  1011. ath_tx_cleanup(sc);
  1012. /* Deinit */
  1013. ath_deinit(sc);
  1014. return 0;
  1015. }
  1016. static int ath_attach(u16 devid,
  1017. struct ath_softc *sc)
  1018. {
  1019. struct ieee80211_hw *hw = sc->hw;
  1020. int error = 0;
  1021. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  1022. error = ath_init(devid, sc);
  1023. if (error != 0)
  1024. return error;
  1025. /* Init nodes */
  1026. INIT_LIST_HEAD(&sc->node_list);
  1027. spin_lock_init(&sc->node_lock);
  1028. /* get mac address from hardware and set in mac80211 */
  1029. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  1030. /* setup channels and rates */
  1031. sc->sbands[IEEE80211_BAND_2GHZ].channels =
  1032. sc->channels[IEEE80211_BAND_2GHZ];
  1033. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  1034. sc->rates[IEEE80211_BAND_2GHZ];
  1035. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  1036. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  1037. /* Setup HT capabilities for 2.4Ghz*/
  1038. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
  1039. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1040. &sc->sbands[IEEE80211_BAND_2GHZ];
  1041. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
  1042. sc->sbands[IEEE80211_BAND_5GHZ].channels =
  1043. sc->channels[IEEE80211_BAND_5GHZ];
  1044. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  1045. sc->rates[IEEE80211_BAND_5GHZ];
  1046. sc->sbands[IEEE80211_BAND_5GHZ].band =
  1047. IEEE80211_BAND_5GHZ;
  1048. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  1049. /* Setup HT capabilities for 5Ghz*/
  1050. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
  1051. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1052. &sc->sbands[IEEE80211_BAND_5GHZ];
  1053. }
  1054. /* FIXME: Have to figure out proper hw init values later */
  1055. hw->queues = 4;
  1056. hw->ampdu_queues = 1;
  1057. /* Register rate control */
  1058. hw->rate_control_algorithm = "ath9k_rate_control";
  1059. error = ath_rate_control_register();
  1060. if (error != 0) {
  1061. DPRINTF(sc, ATH_DBG_FATAL,
  1062. "%s: Unable to register rate control "
  1063. "algorithm:%d\n", __func__, error);
  1064. ath_rate_control_unregister();
  1065. goto bad;
  1066. }
  1067. error = ieee80211_register_hw(hw);
  1068. if (error != 0) {
  1069. ath_rate_control_unregister();
  1070. goto bad;
  1071. }
  1072. /* initialize tx/rx engine */
  1073. error = ath_tx_init(sc, ATH_TXBUF);
  1074. if (error != 0)
  1075. goto bad1;
  1076. error = ath_rx_init(sc, ATH_RXBUF);
  1077. if (error != 0)
  1078. goto bad1;
  1079. return 0;
  1080. bad1:
  1081. ath_detach(sc);
  1082. bad:
  1083. return error;
  1084. }
  1085. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1086. {
  1087. void __iomem *mem;
  1088. struct ath_softc *sc;
  1089. struct ieee80211_hw *hw;
  1090. const char *athname;
  1091. u8 csz;
  1092. u32 val;
  1093. int ret = 0;
  1094. if (pci_enable_device(pdev))
  1095. return -EIO;
  1096. /* XXX 32-bit addressing only */
  1097. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1098. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1099. ret = -ENODEV;
  1100. goto bad;
  1101. }
  1102. /*
  1103. * Cache line size is used to size and align various
  1104. * structures used to communicate with the hardware.
  1105. */
  1106. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1107. if (csz == 0) {
  1108. /*
  1109. * Linux 2.4.18 (at least) writes the cache line size
  1110. * register as a 16-bit wide register which is wrong.
  1111. * We must have this setup properly for rx buffer
  1112. * DMA to work so force a reasonable value here if it
  1113. * comes up zero.
  1114. */
  1115. csz = L1_CACHE_BYTES / sizeof(u32);
  1116. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1117. }
  1118. /*
  1119. * The default setting of latency timer yields poor results,
  1120. * set it to the value used by other systems. It may be worth
  1121. * tweaking this setting more.
  1122. */
  1123. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1124. pci_set_master(pdev);
  1125. /*
  1126. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1127. * PCI Tx retries from interfering with C3 CPU state.
  1128. */
  1129. pci_read_config_dword(pdev, 0x40, &val);
  1130. if ((val & 0x0000ff00) != 0)
  1131. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1132. ret = pci_request_region(pdev, 0, "ath9k");
  1133. if (ret) {
  1134. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1135. ret = -ENODEV;
  1136. goto bad;
  1137. }
  1138. mem = pci_iomap(pdev, 0, 0);
  1139. if (!mem) {
  1140. printk(KERN_ERR "PCI memory map error\n") ;
  1141. ret = -EIO;
  1142. goto bad1;
  1143. }
  1144. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1145. if (hw == NULL) {
  1146. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1147. goto bad2;
  1148. }
  1149. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1150. IEEE80211_HW_NOISE_DBM;
  1151. SET_IEEE80211_DEV(hw, &pdev->dev);
  1152. pci_set_drvdata(pdev, hw);
  1153. sc = hw->priv;
  1154. sc->hw = hw;
  1155. sc->pdev = pdev;
  1156. sc->mem = mem;
  1157. if (ath_attach(id->device, sc) != 0) {
  1158. ret = -ENODEV;
  1159. goto bad3;
  1160. }
  1161. /* setup interrupt service routine */
  1162. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1163. printk(KERN_ERR "%s: request_irq failed\n",
  1164. wiphy_name(hw->wiphy));
  1165. ret = -EIO;
  1166. goto bad4;
  1167. }
  1168. athname = ath9k_hw_probe(id->vendor, id->device);
  1169. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1170. wiphy_name(hw->wiphy),
  1171. athname ? athname : "Atheros ???",
  1172. (unsigned long)mem, pdev->irq);
  1173. return 0;
  1174. bad4:
  1175. ath_detach(sc);
  1176. bad3:
  1177. ieee80211_free_hw(hw);
  1178. bad2:
  1179. pci_iounmap(pdev, mem);
  1180. bad1:
  1181. pci_release_region(pdev, 0);
  1182. bad:
  1183. pci_disable_device(pdev);
  1184. return ret;
  1185. }
  1186. static void ath_pci_remove(struct pci_dev *pdev)
  1187. {
  1188. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1189. struct ath_softc *sc = hw->priv;
  1190. if (pdev->irq)
  1191. free_irq(pdev->irq, sc);
  1192. ath_detach(sc);
  1193. pci_iounmap(pdev, sc->mem);
  1194. pci_release_region(pdev, 0);
  1195. pci_disable_device(pdev);
  1196. ieee80211_free_hw(hw);
  1197. }
  1198. #ifdef CONFIG_PM
  1199. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1200. {
  1201. pci_save_state(pdev);
  1202. pci_disable_device(pdev);
  1203. pci_set_power_state(pdev, 3);
  1204. return 0;
  1205. }
  1206. static int ath_pci_resume(struct pci_dev *pdev)
  1207. {
  1208. u32 val;
  1209. int err;
  1210. err = pci_enable_device(pdev);
  1211. if (err)
  1212. return err;
  1213. pci_restore_state(pdev);
  1214. /*
  1215. * Suspend/Resume resets the PCI configuration space, so we have to
  1216. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1217. * PCI Tx retries from interfering with C3 CPU state
  1218. */
  1219. pci_read_config_dword(pdev, 0x40, &val);
  1220. if ((val & 0x0000ff00) != 0)
  1221. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1222. return 0;
  1223. }
  1224. #endif /* CONFIG_PM */
  1225. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1226. static struct pci_driver ath_pci_driver = {
  1227. .name = "ath9k",
  1228. .id_table = ath_pci_id_table,
  1229. .probe = ath_pci_probe,
  1230. .remove = ath_pci_remove,
  1231. #ifdef CONFIG_PM
  1232. .suspend = ath_pci_suspend,
  1233. .resume = ath_pci_resume,
  1234. #endif /* CONFIG_PM */
  1235. };
  1236. static int __init init_ath_pci(void)
  1237. {
  1238. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1239. if (pci_register_driver(&ath_pci_driver) < 0) {
  1240. printk(KERN_ERR
  1241. "ath_pci: No devices found, driver not installed.\n");
  1242. pci_unregister_driver(&ath_pci_driver);
  1243. return -ENODEV;
  1244. }
  1245. return 0;
  1246. }
  1247. module_init(init_ath_pci);
  1248. static void __exit exit_ath_pci(void)
  1249. {
  1250. pci_unregister_driver(&ath_pci_driver);
  1251. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1252. }
  1253. module_exit(exit_ath_pci);