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linux-vybrid_pu...
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arch
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powerpc
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include
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asm
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pte-book3e.h

pte-book3e.h 2.2 KB
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  1. #ifndef _ASM_POWERPC_PTE_BOOK3E_H
    2. 

  2. #define _ASM_POWERPC_PTE_BOOK3E_H
    3. 

  3. #ifdef __KERNEL__
    4. 

  4. 

  5. /* PTE bit definitions for processors compliant to the Book3E
    6. 

  6.  * architecture 2.06 or later. The position of the PTE bits
    7. 

  7.  * matches the HW definition of the optional Embedded Page Table
    8. 

  8.  * category.
    9. 

  9.  */
    10. 

  10. 

  11. /* Architected bits */
    12. 

  12. #define _PAGE_PRESENT	0x000001 /* software: pte contains a translation */
    13. 

  13. #define _PAGE_FILE	0x000002 /* (!present only) software: pte holds file offset */
    14. 

  14. #define _PAGE_SW1	0x000002
    15. 

  15. #define _PAGE_BAP_SR	0x000004
    16. 

  16. #define _PAGE_BAP_UR	0x000008
    17. 

  17. #define _PAGE_BAP_SW	0x000010
    18. 

  18. #define _PAGE_BAP_UW	0x000020
    19. 

  19. #define _PAGE_BAP_SX	0x000040
    20. 

  20. #define _PAGE_BAP_UX	0x000080
    21. 

  21. #define _PAGE_PSIZE_MSK	0x000f00
    22. 

  22. #define _PAGE_PSIZE_4K	0x000200
    23. 

  23. #define _PAGE_PSIZE_64K	0x000600
    24. 

  24. #define _PAGE_PSIZE_1M	0x000a00
    25. 

  25. #define _PAGE_PSIZE_16M	0x000e00
    26. 

  26. #define _PAGE_DIRTY	0x001000 /* C: page changed */
    27. 

  27. #define _PAGE_SW0	0x002000
    28. 

  28. #define _PAGE_U3	0x004000
    29. 

  29. #define _PAGE_U2	0x008000
    30. 

  30. #define _PAGE_U1	0x010000
    31. 

  31. #define _PAGE_U0	0x020000
    32. 

  32. #define _PAGE_ACCESSED	0x040000
    33. 

  33. #define _PAGE_LENDIAN	0x080000
    34. 

  34. #define _PAGE_GUARDED	0x100000
    35. 

  35. #define _PAGE_COHERENT	0x200000 /* M: enforce memory coherence */
    36. 

  36. #define _PAGE_NO_CACHE	0x400000 /* I: cache inhibit */
    37. 

  37. #define _PAGE_WRITETHRU	0x800000 /* W: cache write-through */
    38. 

  38. 

  39. /* "Higher level" linux bit combinations */
    40. 

  40. #define _PAGE_EXEC	_PAGE_BAP_SX /* Can be executed from potentially */
    41. 

  41. #define _PAGE_HWEXEC	_PAGE_BAP_UX /* .. and was cache cleaned */
    42. 

  42. #define _PAGE_RW	(_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
    43. 

  43. #define _PAGE_KERNEL_RW	(_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
    44. 

  44. #define _PAGE_KERNEL_RO	(_PAGE_BAP_SR)
    45. 

  45. #define _PAGE_USER	(_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
    46. 

  46. 

  47. #define _PAGE_HASHPTE	0
    48. 

  48. #define _PAGE_BUSY	0
    49. 

  49. 

  50. #define _PAGE_SPECIAL	_PAGE_SW0
    51. 

  51. 

  52. /* Flags to be preserved on PTE modifications */
    53. 

  53. #define _PAGE_HPTEFLAGS	_PAGE_BUSY
    54. 

  54. 

  55. /* Base page size */
    56. 

  56. #ifdef CONFIG_PPC_64K_PAGES
    57. 

  57. #define _PAGE_PSIZE	_PAGE_PSIZE_64K
    58. 

  58. #define PTE_RPN_SHIFT	(28)
    59. 

  59. #else
    60. 

  60. #define _PAGE_PSIZE	_PAGE_PSIZE_4K
    61. 

  61. #define	PTE_RPN_SHIFT	(24)
    62. 

  62. #endif
    63. 

  63. 

  64. /* On 32-bit, we never clear the top part of the PTE */
    65. 

  65. #ifdef CONFIG_PPC32
    66. 

  66. #define _PTE_NONE_MASK	0xffffffff00000000ULL
    67. 

  67. #endif
    68. 

  68. 

  69. #endif /* __KERNEL__ */
    70. 

  70. #endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
    71.