iwl-4965.c 142 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-4965.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. /* module parameters */
  45. static struct iwl_mod_params iwl4965_mod_params = {
  46. .num_of_queues = IWL_MAX_NUM_QUEUES,
  47. .enable_qos = 1,
  48. .amsdu_size_8K = 1,
  49. /* the rest are 0 by default */
  50. };
  51. static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
  52. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  53. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  54. IWL_RATE_SISO_##s##M_PLCP, \
  55. IWL_RATE_MIMO_##s##M_PLCP, \
  56. IWL_RATE_##r##M_IEEE, \
  57. IWL_RATE_##ip##M_INDEX, \
  58. IWL_RATE_##in##M_INDEX, \
  59. IWL_RATE_##rp##M_INDEX, \
  60. IWL_RATE_##rn##M_INDEX, \
  61. IWL_RATE_##pp##M_INDEX, \
  62. IWL_RATE_##np##M_INDEX }
  63. /*
  64. * Parameter order:
  65. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  66. *
  67. * If there isn't a valid next or previous rate then INV is used which
  68. * maps to IWL_RATE_INVALID
  69. *
  70. */
  71. const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
  72. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  73. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  74. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  75. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  76. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  77. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  78. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  79. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  80. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  81. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  82. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  83. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  84. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  85. };
  86. #ifdef CONFIG_IWL4965_HT
  87. static const u16 default_tid_to_tx_fifo[] = {
  88. IWL_TX_FIFO_AC1,
  89. IWL_TX_FIFO_AC0,
  90. IWL_TX_FIFO_AC0,
  91. IWL_TX_FIFO_AC1,
  92. IWL_TX_FIFO_AC2,
  93. IWL_TX_FIFO_AC2,
  94. IWL_TX_FIFO_AC3,
  95. IWL_TX_FIFO_AC3,
  96. IWL_TX_FIFO_NONE,
  97. IWL_TX_FIFO_NONE,
  98. IWL_TX_FIFO_NONE,
  99. IWL_TX_FIFO_NONE,
  100. IWL_TX_FIFO_NONE,
  101. IWL_TX_FIFO_NONE,
  102. IWL_TX_FIFO_NONE,
  103. IWL_TX_FIFO_NONE,
  104. IWL_TX_FIFO_AC3
  105. };
  106. #endif /*CONFIG_IWL4965_HT */
  107. /* check contents of special bootstrap uCode SRAM */
  108. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  109. {
  110. __le32 *image = priv->ucode_boot.v_addr;
  111. u32 len = priv->ucode_boot.len;
  112. u32 reg;
  113. u32 val;
  114. IWL_DEBUG_INFO("Begin verify bsm\n");
  115. /* verify BSM SRAM contents */
  116. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  117. for (reg = BSM_SRAM_LOWER_BOUND;
  118. reg < BSM_SRAM_LOWER_BOUND + len;
  119. reg += sizeof(u32), image++) {
  120. val = iwl_read_prph(priv, reg);
  121. if (val != le32_to_cpu(*image)) {
  122. IWL_ERROR("BSM uCode verification failed at "
  123. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  124. BSM_SRAM_LOWER_BOUND,
  125. reg - BSM_SRAM_LOWER_BOUND, len,
  126. val, le32_to_cpu(*image));
  127. return -EIO;
  128. }
  129. }
  130. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  131. return 0;
  132. }
  133. /**
  134. * iwl4965_load_bsm - Load bootstrap instructions
  135. *
  136. * BSM operation:
  137. *
  138. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  139. * in special SRAM that does not power down during RFKILL. When powering back
  140. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  141. * the bootstrap program into the on-board processor, and starts it.
  142. *
  143. * The bootstrap program loads (via DMA) instructions and data for a new
  144. * program from host DRAM locations indicated by the host driver in the
  145. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  146. * automatically.
  147. *
  148. * When initializing the NIC, the host driver points the BSM to the
  149. * "initialize" uCode image. This uCode sets up some internal data, then
  150. * notifies host via "initialize alive" that it is complete.
  151. *
  152. * The host then replaces the BSM_DRAM_* pointer values to point to the
  153. * normal runtime uCode instructions and a backup uCode data cache buffer
  154. * (filled initially with starting data values for the on-board processor),
  155. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  156. * which begins normal operation.
  157. *
  158. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  159. * the backup data cache in DRAM before SRAM is powered down.
  160. *
  161. * When powering back up, the BSM loads the bootstrap program. This reloads
  162. * the runtime uCode instructions and the backup data cache into SRAM,
  163. * and re-launches the runtime uCode from where it left off.
  164. */
  165. static int iwl4965_load_bsm(struct iwl_priv *priv)
  166. {
  167. __le32 *image = priv->ucode_boot.v_addr;
  168. u32 len = priv->ucode_boot.len;
  169. dma_addr_t pinst;
  170. dma_addr_t pdata;
  171. u32 inst_len;
  172. u32 data_len;
  173. int i;
  174. u32 done;
  175. u32 reg_offset;
  176. int ret;
  177. IWL_DEBUG_INFO("Begin load bsm\n");
  178. /* make sure bootstrap program is no larger than BSM's SRAM size */
  179. if (len > IWL_MAX_BSM_SIZE)
  180. return -EINVAL;
  181. /* Tell bootstrap uCode where to find the "Initialize" uCode
  182. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  183. * NOTE: iwl4965_initialize_alive_start() will replace these values,
  184. * after the "initialize" uCode has run, to point to
  185. * runtime/protocol instructions and backup data cache. */
  186. pinst = priv->ucode_init.p_addr >> 4;
  187. pdata = priv->ucode_init_data.p_addr >> 4;
  188. inst_len = priv->ucode_init.len;
  189. data_len = priv->ucode_init_data.len;
  190. ret = iwl_grab_nic_access(priv);
  191. if (ret)
  192. return ret;
  193. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  194. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  195. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  196. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  197. /* Fill BSM memory with bootstrap instructions */
  198. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  199. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  200. reg_offset += sizeof(u32), image++)
  201. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  202. ret = iwl4965_verify_bsm(priv);
  203. if (ret) {
  204. iwl_release_nic_access(priv);
  205. return ret;
  206. }
  207. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  208. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  209. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  210. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  211. /* Load bootstrap code into instruction SRAM now,
  212. * to prepare to load "initialize" uCode */
  213. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  214. /* Wait for load of bootstrap uCode to finish */
  215. for (i = 0; i < 100; i++) {
  216. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  217. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  218. break;
  219. udelay(10);
  220. }
  221. if (i < 100)
  222. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  223. else {
  224. IWL_ERROR("BSM write did not complete!\n");
  225. return -EIO;
  226. }
  227. /* Enable future boot loads whenever power management unit triggers it
  228. * (e.g. when powering back up after power-save shutdown) */
  229. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  230. iwl_release_nic_access(priv);
  231. return 0;
  232. }
  233. static int iwl4965_init_drv(struct iwl_priv *priv)
  234. {
  235. int ret;
  236. int i;
  237. priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
  238. priv->retry_rate = 1;
  239. priv->ibss_beacon = NULL;
  240. spin_lock_init(&priv->lock);
  241. spin_lock_init(&priv->power_data.lock);
  242. spin_lock_init(&priv->sta_lock);
  243. spin_lock_init(&priv->hcmd_lock);
  244. spin_lock_init(&priv->lq_mngr.lock);
  245. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  246. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  247. INIT_LIST_HEAD(&priv->free_frames);
  248. mutex_init(&priv->mutex);
  249. /* Clear the driver's (not device's) station table */
  250. iwlcore_clear_stations_table(priv);
  251. priv->data_retry_limit = -1;
  252. priv->ieee_channels = NULL;
  253. priv->ieee_rates = NULL;
  254. priv->band = IEEE80211_BAND_2GHZ;
  255. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  256. priv->use_ant_b_for_management_frame = 1; /* start with ant B */
  257. priv->valid_antenna = 0x7; /* assume all 3 connected */
  258. priv->ps_mode = IWL_MIMO_PS_NONE;
  259. /* Choose which receivers/antennas to use */
  260. iwl4965_set_rxon_chain(priv);
  261. iwlcore_reset_qos(priv);
  262. priv->qos_data.qos_active = 0;
  263. priv->qos_data.qos_cap.val = 0;
  264. iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  265. priv->rates_mask = IWL_RATES_MASK;
  266. /* If power management is turned on, default to AC mode */
  267. priv->power_mode = IWL_POWER_AC;
  268. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  269. ret = iwl_init_channel_map(priv);
  270. if (ret) {
  271. IWL_ERROR("initializing regulatory failed: %d\n", ret);
  272. goto err;
  273. }
  274. ret = iwl4965_init_geos(priv);
  275. if (ret) {
  276. IWL_ERROR("initializing geos failed: %d\n", ret);
  277. goto err_free_channel_map;
  278. }
  279. ret = ieee80211_register_hw(priv->hw);
  280. if (ret) {
  281. IWL_ERROR("Failed to register network device (error %d)\n",
  282. ret);
  283. goto err_free_geos;
  284. }
  285. priv->hw->conf.beacon_int = 100;
  286. priv->mac80211_registered = 1;
  287. return 0;
  288. err_free_geos:
  289. iwl4965_free_geos(priv);
  290. err_free_channel_map:
  291. iwl_free_channel_map(priv);
  292. err:
  293. return ret;
  294. }
  295. static int is_fat_channel(__le32 rxon_flags)
  296. {
  297. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  298. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  299. }
  300. static u8 is_single_stream(struct iwl_priv *priv)
  301. {
  302. #ifdef CONFIG_IWL4965_HT
  303. if (!priv->current_ht_config.is_ht ||
  304. (priv->current_ht_config.supp_mcs_set[1] == 0) ||
  305. (priv->ps_mode == IWL_MIMO_PS_STATIC))
  306. return 1;
  307. #else
  308. return 1;
  309. #endif /*CONFIG_IWL4965_HT */
  310. return 0;
  311. }
  312. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  313. {
  314. int idx = 0;
  315. /* 4965 HT rate format */
  316. if (rate_n_flags & RATE_MCS_HT_MSK) {
  317. idx = (rate_n_flags & 0xff);
  318. if (idx >= IWL_RATE_MIMO_6M_PLCP)
  319. idx = idx - IWL_RATE_MIMO_6M_PLCP;
  320. idx += IWL_FIRST_OFDM_RATE;
  321. /* skip 9M not supported in ht*/
  322. if (idx >= IWL_RATE_9M_INDEX)
  323. idx += 1;
  324. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  325. return idx;
  326. /* 4965 legacy rate format, search for match in table */
  327. } else {
  328. for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
  329. if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
  330. return idx;
  331. }
  332. return -1;
  333. }
  334. /**
  335. * translate ucode response to mac80211 tx status control values
  336. */
  337. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  338. struct ieee80211_tx_control *control)
  339. {
  340. int rate_index;
  341. control->antenna_sel_tx =
  342. ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
  343. if (rate_n_flags & RATE_MCS_HT_MSK)
  344. control->flags |= IEEE80211_TXCTL_OFDM_HT;
  345. if (rate_n_flags & RATE_MCS_GF_MSK)
  346. control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
  347. if (rate_n_flags & RATE_MCS_FAT_MSK)
  348. control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
  349. if (rate_n_flags & RATE_MCS_DUP_MSK)
  350. control->flags |= IEEE80211_TXCTL_DUP_DATA;
  351. if (rate_n_flags & RATE_MCS_SGI_MSK)
  352. control->flags |= IEEE80211_TXCTL_SHORT_GI;
  353. /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
  354. * IEEE80211_BAND_2GHZ band as it contains all the rates */
  355. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  356. if (rate_index == -1)
  357. control->tx_rate = NULL;
  358. else
  359. control->tx_rate =
  360. &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
  361. }
  362. /*
  363. * Determine how many receiver/antenna chains to use.
  364. * More provides better reception via diversity. Fewer saves power.
  365. * MIMO (dual stream) requires at least 2, but works better with 3.
  366. * This does not determine *which* chains to use, just how many.
  367. */
  368. static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
  369. u8 *idle_state, u8 *rx_state)
  370. {
  371. u8 is_single = is_single_stream(priv);
  372. u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
  373. /* # of Rx chains to use when expecting MIMO. */
  374. if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
  375. *rx_state = 2;
  376. else
  377. *rx_state = 3;
  378. /* # Rx chains when idling and maybe trying to save power */
  379. switch (priv->ps_mode) {
  380. case IWL_MIMO_PS_STATIC:
  381. case IWL_MIMO_PS_DYNAMIC:
  382. *idle_state = (is_cam) ? 2 : 1;
  383. break;
  384. case IWL_MIMO_PS_NONE:
  385. *idle_state = (is_cam) ? *rx_state : 1;
  386. break;
  387. default:
  388. *idle_state = 1;
  389. break;
  390. }
  391. return 0;
  392. }
  393. int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
  394. {
  395. int rc;
  396. unsigned long flags;
  397. spin_lock_irqsave(&priv->lock, flags);
  398. rc = iwl_grab_nic_access(priv);
  399. if (rc) {
  400. spin_unlock_irqrestore(&priv->lock, flags);
  401. return rc;
  402. }
  403. /* stop Rx DMA */
  404. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  405. rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  406. (1 << 24), 1000);
  407. if (rc < 0)
  408. IWL_ERROR("Can't stop Rx DMA.\n");
  409. iwl_release_nic_access(priv);
  410. spin_unlock_irqrestore(&priv->lock, flags);
  411. return 0;
  412. }
  413. u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
  414. {
  415. int i;
  416. int start = 0;
  417. int ret = IWL_INVALID_STATION;
  418. unsigned long flags;
  419. DECLARE_MAC_BUF(mac);
  420. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
  421. (priv->iw_mode == IEEE80211_IF_TYPE_AP))
  422. start = IWL_STA_ID;
  423. if (is_broadcast_ether_addr(addr))
  424. return priv->hw_setting.bcast_sta_id;
  425. spin_lock_irqsave(&priv->sta_lock, flags);
  426. for (i = start; i < priv->hw_setting.max_stations; i++)
  427. if ((priv->stations[i].used) &&
  428. (!compare_ether_addr
  429. (priv->stations[i].sta.sta.addr, addr))) {
  430. ret = i;
  431. goto out;
  432. }
  433. IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
  434. print_mac(mac, addr), priv->num_stations);
  435. out:
  436. spin_unlock_irqrestore(&priv->sta_lock, flags);
  437. return ret;
  438. }
  439. static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
  440. {
  441. int ret;
  442. unsigned long flags;
  443. spin_lock_irqsave(&priv->lock, flags);
  444. ret = iwl_grab_nic_access(priv);
  445. if (ret) {
  446. spin_unlock_irqrestore(&priv->lock, flags);
  447. return ret;
  448. }
  449. if (!pwr_max) {
  450. u32 val;
  451. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  452. &val);
  453. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
  454. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  455. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  456. ~APMG_PS_CTRL_MSK_PWR_SRC);
  457. } else
  458. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  459. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  460. ~APMG_PS_CTRL_MSK_PWR_SRC);
  461. iwl_release_nic_access(priv);
  462. spin_unlock_irqrestore(&priv->lock, flags);
  463. return ret;
  464. }
  465. static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
  466. {
  467. int rc;
  468. unsigned long flags;
  469. unsigned int rb_size;
  470. spin_lock_irqsave(&priv->lock, flags);
  471. rc = iwl_grab_nic_access(priv);
  472. if (rc) {
  473. spin_unlock_irqrestore(&priv->lock, flags);
  474. return rc;
  475. }
  476. if (priv->cfg->mod_params->amsdu_size_8K)
  477. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  478. else
  479. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  480. /* Stop Rx DMA */
  481. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  482. /* Reset driver's Rx queue write index */
  483. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  484. /* Tell device where to find RBD circular buffer in DRAM */
  485. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  486. rxq->dma_addr >> 8);
  487. /* Tell device where in DRAM to update its Rx status */
  488. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  489. (priv->hw_setting.shared_phys +
  490. offsetof(struct iwl4965_shared, val0)) >> 4);
  491. /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
  492. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  493. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  494. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  495. rb_size |
  496. /*0x10 << 4 | */
  497. (RX_QUEUE_SIZE_LOG <<
  498. FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
  499. /*
  500. * iwl_write32(priv,CSR_INT_COAL_REG,0);
  501. */
  502. iwl_release_nic_access(priv);
  503. spin_unlock_irqrestore(&priv->lock, flags);
  504. return 0;
  505. }
  506. /* Tell 4965 where to find the "keep warm" buffer */
  507. static int iwl4965_kw_init(struct iwl_priv *priv)
  508. {
  509. unsigned long flags;
  510. int rc;
  511. spin_lock_irqsave(&priv->lock, flags);
  512. rc = iwl_grab_nic_access(priv);
  513. if (rc)
  514. goto out;
  515. iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
  516. priv->kw.dma_addr >> 4);
  517. iwl_release_nic_access(priv);
  518. out:
  519. spin_unlock_irqrestore(&priv->lock, flags);
  520. return rc;
  521. }
  522. static int iwl4965_kw_alloc(struct iwl_priv *priv)
  523. {
  524. struct pci_dev *dev = priv->pci_dev;
  525. struct iwl4965_kw *kw = &priv->kw;
  526. kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
  527. kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
  528. if (!kw->v_addr)
  529. return -ENOMEM;
  530. return 0;
  531. }
  532. /**
  533. * iwl4965_kw_free - Free the "keep warm" buffer
  534. */
  535. static void iwl4965_kw_free(struct iwl_priv *priv)
  536. {
  537. struct pci_dev *dev = priv->pci_dev;
  538. struct iwl4965_kw *kw = &priv->kw;
  539. if (kw->v_addr) {
  540. pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
  541. memset(kw, 0, sizeof(*kw));
  542. }
  543. }
  544. /**
  545. * iwl4965_txq_ctx_reset - Reset TX queue context
  546. * Destroys all DMA structures and initialise them again
  547. *
  548. * @param priv
  549. * @return error code
  550. */
  551. static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
  552. {
  553. int rc = 0;
  554. int txq_id, slots_num;
  555. unsigned long flags;
  556. iwl4965_kw_free(priv);
  557. /* Free all tx/cmd queues and keep-warm buffer */
  558. iwl4965_hw_txq_ctx_free(priv);
  559. /* Alloc keep-warm buffer */
  560. rc = iwl4965_kw_alloc(priv);
  561. if (rc) {
  562. IWL_ERROR("Keep Warm allocation failed");
  563. goto error_kw;
  564. }
  565. spin_lock_irqsave(&priv->lock, flags);
  566. rc = iwl_grab_nic_access(priv);
  567. if (unlikely(rc)) {
  568. IWL_ERROR("TX reset failed");
  569. spin_unlock_irqrestore(&priv->lock, flags);
  570. goto error_reset;
  571. }
  572. /* Turn off all Tx DMA channels */
  573. iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
  574. iwl_release_nic_access(priv);
  575. spin_unlock_irqrestore(&priv->lock, flags);
  576. /* Tell 4965 where to find the keep-warm buffer */
  577. rc = iwl4965_kw_init(priv);
  578. if (rc) {
  579. IWL_ERROR("kw_init failed\n");
  580. goto error_reset;
  581. }
  582. /* Alloc and init all (default 16) Tx queues,
  583. * including the command queue (#4) */
  584. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  585. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  586. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  587. rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  588. txq_id);
  589. if (rc) {
  590. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  591. goto error;
  592. }
  593. }
  594. return rc;
  595. error:
  596. iwl4965_hw_txq_ctx_free(priv);
  597. error_reset:
  598. iwl4965_kw_free(priv);
  599. error_kw:
  600. return rc;
  601. }
  602. int iwl4965_hw_nic_init(struct iwl_priv *priv)
  603. {
  604. int rc;
  605. unsigned long flags;
  606. struct iwl4965_rx_queue *rxq = &priv->rxq;
  607. u8 rev_id;
  608. u32 val;
  609. u8 val_link;
  610. iwl4965_power_init_handle(priv);
  611. /* nic_init */
  612. spin_lock_irqsave(&priv->lock, flags);
  613. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  614. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  615. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  616. rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
  617. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  618. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  619. if (rc < 0) {
  620. spin_unlock_irqrestore(&priv->lock, flags);
  621. IWL_DEBUG_INFO("Failed to init the card\n");
  622. return rc;
  623. }
  624. rc = iwl_grab_nic_access(priv);
  625. if (rc) {
  626. spin_unlock_irqrestore(&priv->lock, flags);
  627. return rc;
  628. }
  629. iwl_read_prph(priv, APMG_CLK_CTRL_REG);
  630. iwl_write_prph(priv, APMG_CLK_CTRL_REG,
  631. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  632. iwl_read_prph(priv, APMG_CLK_CTRL_REG);
  633. udelay(20);
  634. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  635. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  636. iwl_release_nic_access(priv);
  637. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  638. spin_unlock_irqrestore(&priv->lock, flags);
  639. /* Determine HW type */
  640. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  641. if (rc)
  642. return rc;
  643. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  644. iwl4965_nic_set_pwr_src(priv, 1);
  645. spin_lock_irqsave(&priv->lock, flags);
  646. if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
  647. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  648. /* Enable No Snoop field */
  649. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  650. val & ~(1 << 11));
  651. }
  652. spin_unlock_irqrestore(&priv->lock, flags);
  653. if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
  654. IWL_ERROR("Older EEPROM detected! Aborting.\n");
  655. return -EINVAL;
  656. }
  657. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  658. /* disable L1 entry -- workaround for pre-B1 */
  659. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  660. spin_lock_irqsave(&priv->lock, flags);
  661. /* set CSR_HW_CONFIG_REG for uCode use */
  662. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  663. CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
  664. CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  665. CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
  666. rc = iwl_grab_nic_access(priv);
  667. if (rc < 0) {
  668. spin_unlock_irqrestore(&priv->lock, flags);
  669. IWL_DEBUG_INFO("Failed to init the card\n");
  670. return rc;
  671. }
  672. iwl_read_prph(priv, APMG_PS_CTRL_REG);
  673. iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
  674. udelay(5);
  675. iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
  676. iwl_release_nic_access(priv);
  677. spin_unlock_irqrestore(&priv->lock, flags);
  678. iwl4965_hw_card_show_info(priv);
  679. /* end nic_init */
  680. /* Allocate the RX queue, or reset if it is already allocated */
  681. if (!rxq->bd) {
  682. rc = iwl4965_rx_queue_alloc(priv);
  683. if (rc) {
  684. IWL_ERROR("Unable to initialize Rx queue\n");
  685. return -ENOMEM;
  686. }
  687. } else
  688. iwl4965_rx_queue_reset(priv, rxq);
  689. iwl4965_rx_replenish(priv);
  690. iwl4965_rx_init(priv, rxq);
  691. spin_lock_irqsave(&priv->lock, flags);
  692. rxq->need_update = 1;
  693. iwl4965_rx_queue_update_write_ptr(priv, rxq);
  694. spin_unlock_irqrestore(&priv->lock, flags);
  695. /* Allocate and init all Tx and Command queues */
  696. rc = iwl4965_txq_ctx_reset(priv);
  697. if (rc)
  698. return rc;
  699. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  700. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  701. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  702. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  703. set_bit(STATUS_INIT, &priv->status);
  704. return 0;
  705. }
  706. int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
  707. {
  708. int rc = 0;
  709. u32 reg_val;
  710. unsigned long flags;
  711. spin_lock_irqsave(&priv->lock, flags);
  712. /* set stop master bit */
  713. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  714. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  715. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  716. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  717. IWL_DEBUG_INFO("Card in power save, master is already "
  718. "stopped\n");
  719. else {
  720. rc = iwl_poll_bit(priv, CSR_RESET,
  721. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  722. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  723. if (rc < 0) {
  724. spin_unlock_irqrestore(&priv->lock, flags);
  725. return rc;
  726. }
  727. }
  728. spin_unlock_irqrestore(&priv->lock, flags);
  729. IWL_DEBUG_INFO("stop master\n");
  730. return rc;
  731. }
  732. /**
  733. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  734. */
  735. void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
  736. {
  737. int txq_id;
  738. unsigned long flags;
  739. /* Stop each Tx DMA channel, and wait for it to be idle */
  740. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  741. spin_lock_irqsave(&priv->lock, flags);
  742. if (iwl_grab_nic_access(priv)) {
  743. spin_unlock_irqrestore(&priv->lock, flags);
  744. continue;
  745. }
  746. iwl_write_direct32(priv,
  747. IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
  748. iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
  749. IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  750. (txq_id), 200);
  751. iwl_release_nic_access(priv);
  752. spin_unlock_irqrestore(&priv->lock, flags);
  753. }
  754. /* Deallocate memory for all Tx queues */
  755. iwl4965_hw_txq_ctx_free(priv);
  756. }
  757. int iwl4965_hw_nic_reset(struct iwl_priv *priv)
  758. {
  759. int rc = 0;
  760. unsigned long flags;
  761. iwl4965_hw_nic_stop_master(priv);
  762. spin_lock_irqsave(&priv->lock, flags);
  763. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  764. udelay(10);
  765. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  766. rc = iwl_poll_bit(priv, CSR_RESET,
  767. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  768. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  769. udelay(10);
  770. rc = iwl_grab_nic_access(priv);
  771. if (!rc) {
  772. iwl_write_prph(priv, APMG_CLK_EN_REG,
  773. APMG_CLK_VAL_DMA_CLK_RQT |
  774. APMG_CLK_VAL_BSM_CLK_RQT);
  775. udelay(10);
  776. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  777. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  778. iwl_release_nic_access(priv);
  779. }
  780. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  781. wake_up_interruptible(&priv->wait_command_queue);
  782. spin_unlock_irqrestore(&priv->lock, flags);
  783. return rc;
  784. }
  785. #define REG_RECALIB_PERIOD (60)
  786. /**
  787. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  788. *
  789. * This callback is provided in order to queue the statistics_work
  790. * in work_queue context (v. softirq)
  791. *
  792. * This timer function is continually reset to execute within
  793. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  794. * was received. We need to ensure we receive the statistics in order
  795. * to update the temperature used for calibrating the TXPOWER. However,
  796. * we can't send the statistics command from softirq context (which
  797. * is the context which timers run at) so we have to queue off the
  798. * statistics_work to actually send the command to the hardware.
  799. */
  800. static void iwl4965_bg_statistics_periodic(unsigned long data)
  801. {
  802. struct iwl_priv *priv = (struct iwl_priv *)data;
  803. queue_work(priv->workqueue, &priv->statistics_work);
  804. }
  805. /**
  806. * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
  807. *
  808. * This is queued by iwl4965_bg_statistics_periodic.
  809. */
  810. static void iwl4965_bg_statistics_work(struct work_struct *work)
  811. {
  812. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  813. statistics_work);
  814. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  815. return;
  816. mutex_lock(&priv->mutex);
  817. iwl4965_send_statistics_request(priv);
  818. mutex_unlock(&priv->mutex);
  819. }
  820. #define CT_LIMIT_CONST 259
  821. #define TM_CT_KILL_THRESHOLD 110
  822. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  823. {
  824. struct iwl4965_ct_kill_config cmd;
  825. u32 R1, R2, R3;
  826. u32 temp_th;
  827. u32 crit_temperature;
  828. unsigned long flags;
  829. int ret = 0;
  830. spin_lock_irqsave(&priv->lock, flags);
  831. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  832. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  833. spin_unlock_irqrestore(&priv->lock, flags);
  834. if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
  835. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  836. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  837. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  838. } else {
  839. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  840. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  841. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  842. }
  843. temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
  844. crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
  845. cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
  846. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  847. sizeof(cmd), &cmd);
  848. if (ret)
  849. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  850. else
  851. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
  852. }
  853. #ifdef CONFIG_IWL4965_SENSITIVITY
  854. /* "false alarms" are signals that our DSP tries to lock onto,
  855. * but then determines that they are either noise, or transmissions
  856. * from a distant wireless network (also "noise", really) that get
  857. * "stepped on" by stronger transmissions within our own network.
  858. * This algorithm attempts to set a sensitivity level that is high
  859. * enough to receive all of our own network traffic, but not so
  860. * high that our DSP gets too busy trying to lock onto non-network
  861. * activity/noise. */
  862. static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
  863. u32 norm_fa,
  864. u32 rx_enable_time,
  865. struct statistics_general_data *rx_info)
  866. {
  867. u32 max_nrg_cck = 0;
  868. int i = 0;
  869. u8 max_silence_rssi = 0;
  870. u32 silence_ref = 0;
  871. u8 silence_rssi_a = 0;
  872. u8 silence_rssi_b = 0;
  873. u8 silence_rssi_c = 0;
  874. u32 val;
  875. /* "false_alarms" values below are cross-multiplications to assess the
  876. * numbers of false alarms within the measured period of actual Rx
  877. * (Rx is off when we're txing), vs the min/max expected false alarms
  878. * (some should be expected if rx is sensitive enough) in a
  879. * hypothetical listening period of 200 time units (TU), 204.8 msec:
  880. *
  881. * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
  882. *
  883. * */
  884. u32 false_alarms = norm_fa * 200 * 1024;
  885. u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
  886. u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
  887. struct iwl4965_sensitivity_data *data = NULL;
  888. data = &(priv->sensitivity_data);
  889. data->nrg_auto_corr_silence_diff = 0;
  890. /* Find max silence rssi among all 3 receivers.
  891. * This is background noise, which may include transmissions from other
  892. * networks, measured during silence before our network's beacon */
  893. silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
  894. ALL_BAND_FILTER) >> 8);
  895. silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
  896. ALL_BAND_FILTER) >> 8);
  897. silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
  898. ALL_BAND_FILTER) >> 8);
  899. val = max(silence_rssi_b, silence_rssi_c);
  900. max_silence_rssi = max(silence_rssi_a, (u8) val);
  901. /* Store silence rssi in 20-beacon history table */
  902. data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
  903. data->nrg_silence_idx++;
  904. if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
  905. data->nrg_silence_idx = 0;
  906. /* Find max silence rssi across 20 beacon history */
  907. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
  908. val = data->nrg_silence_rssi[i];
  909. silence_ref = max(silence_ref, val);
  910. }
  911. IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
  912. silence_rssi_a, silence_rssi_b, silence_rssi_c,
  913. silence_ref);
  914. /* Find max rx energy (min value!) among all 3 receivers,
  915. * measured during beacon frame.
  916. * Save it in 10-beacon history table. */
  917. i = data->nrg_energy_idx;
  918. val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
  919. data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
  920. data->nrg_energy_idx++;
  921. if (data->nrg_energy_idx >= 10)
  922. data->nrg_energy_idx = 0;
  923. /* Find min rx energy (max value) across 10 beacon history.
  924. * This is the minimum signal level that we want to receive well.
  925. * Add backoff (margin so we don't miss slightly lower energy frames).
  926. * This establishes an upper bound (min value) for energy threshold. */
  927. max_nrg_cck = data->nrg_value[0];
  928. for (i = 1; i < 10; i++)
  929. max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
  930. max_nrg_cck += 6;
  931. IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
  932. rx_info->beacon_energy_a, rx_info->beacon_energy_b,
  933. rx_info->beacon_energy_c, max_nrg_cck - 6);
  934. /* Count number of consecutive beacons with fewer-than-desired
  935. * false alarms. */
  936. if (false_alarms < min_false_alarms)
  937. data->num_in_cck_no_fa++;
  938. else
  939. data->num_in_cck_no_fa = 0;
  940. IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
  941. data->num_in_cck_no_fa);
  942. /* If we got too many false alarms this time, reduce sensitivity */
  943. if (false_alarms > max_false_alarms) {
  944. IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
  945. false_alarms, max_false_alarms);
  946. IWL_DEBUG_CALIB("... reducing sensitivity\n");
  947. data->nrg_curr_state = IWL_FA_TOO_MANY;
  948. if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
  949. /* Store for "fewer than desired" on later beacon */
  950. data->nrg_silence_ref = silence_ref;
  951. /* increase energy threshold (reduce nrg value)
  952. * to decrease sensitivity */
  953. if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
  954. data->nrg_th_cck = data->nrg_th_cck
  955. - NRG_STEP_CCK;
  956. }
  957. /* increase auto_corr values to decrease sensitivity */
  958. if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
  959. data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
  960. else {
  961. val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
  962. data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
  963. }
  964. val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
  965. data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
  966. /* Else if we got fewer than desired, increase sensitivity */
  967. } else if (false_alarms < min_false_alarms) {
  968. data->nrg_curr_state = IWL_FA_TOO_FEW;
  969. /* Compare silence level with silence level for most recent
  970. * healthy number or too many false alarms */
  971. data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
  972. (s32)silence_ref;
  973. IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
  974. false_alarms, min_false_alarms,
  975. data->nrg_auto_corr_silence_diff);
  976. /* Increase value to increase sensitivity, but only if:
  977. * 1a) previous beacon did *not* have *too many* false alarms
  978. * 1b) AND there's a significant difference in Rx levels
  979. * from a previous beacon with too many, or healthy # FAs
  980. * OR 2) We've seen a lot of beacons (100) with too few
  981. * false alarms */
  982. if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
  983. ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
  984. (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
  985. IWL_DEBUG_CALIB("... increasing sensitivity\n");
  986. /* Increase nrg value to increase sensitivity */
  987. val = data->nrg_th_cck + NRG_STEP_CCK;
  988. data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
  989. /* Decrease auto_corr values to increase sensitivity */
  990. val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
  991. data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
  992. val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
  993. data->auto_corr_cck_mrc =
  994. max((u32)AUTO_CORR_MIN_CCK_MRC, val);
  995. } else
  996. IWL_DEBUG_CALIB("... but not changing sensitivity\n");
  997. /* Else we got a healthy number of false alarms, keep status quo */
  998. } else {
  999. IWL_DEBUG_CALIB(" FA in safe zone\n");
  1000. data->nrg_curr_state = IWL_FA_GOOD_RANGE;
  1001. /* Store for use in "fewer than desired" with later beacon */
  1002. data->nrg_silence_ref = silence_ref;
  1003. /* If previous beacon had too many false alarms,
  1004. * give it some extra margin by reducing sensitivity again
  1005. * (but don't go below measured energy of desired Rx) */
  1006. if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
  1007. IWL_DEBUG_CALIB("... increasing margin\n");
  1008. data->nrg_th_cck -= NRG_MARGIN;
  1009. }
  1010. }
  1011. /* Make sure the energy threshold does not go above the measured
  1012. * energy of the desired Rx signals (reduced by backoff margin),
  1013. * or else we might start missing Rx frames.
  1014. * Lower value is higher energy, so we use max()!
  1015. */
  1016. data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
  1017. IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
  1018. data->nrg_prev_state = data->nrg_curr_state;
  1019. return 0;
  1020. }
  1021. static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
  1022. u32 norm_fa,
  1023. u32 rx_enable_time)
  1024. {
  1025. u32 val;
  1026. u32 false_alarms = norm_fa * 200 * 1024;
  1027. u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
  1028. u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
  1029. struct iwl4965_sensitivity_data *data = NULL;
  1030. data = &(priv->sensitivity_data);
  1031. /* If we got too many false alarms this time, reduce sensitivity */
  1032. if (false_alarms > max_false_alarms) {
  1033. IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
  1034. false_alarms, max_false_alarms);
  1035. val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
  1036. data->auto_corr_ofdm =
  1037. min((u32)AUTO_CORR_MAX_OFDM, val);
  1038. val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
  1039. data->auto_corr_ofdm_mrc =
  1040. min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
  1041. val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
  1042. data->auto_corr_ofdm_x1 =
  1043. min((u32)AUTO_CORR_MAX_OFDM_X1, val);
  1044. val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
  1045. data->auto_corr_ofdm_mrc_x1 =
  1046. min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
  1047. }
  1048. /* Else if we got fewer than desired, increase sensitivity */
  1049. else if (false_alarms < min_false_alarms) {
  1050. IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
  1051. false_alarms, min_false_alarms);
  1052. val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
  1053. data->auto_corr_ofdm =
  1054. max((u32)AUTO_CORR_MIN_OFDM, val);
  1055. val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
  1056. data->auto_corr_ofdm_mrc =
  1057. max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
  1058. val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
  1059. data->auto_corr_ofdm_x1 =
  1060. max((u32)AUTO_CORR_MIN_OFDM_X1, val);
  1061. val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
  1062. data->auto_corr_ofdm_mrc_x1 =
  1063. max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
  1064. }
  1065. else
  1066. IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
  1067. min_false_alarms, false_alarms, max_false_alarms);
  1068. return 0;
  1069. }
  1070. static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
  1071. struct iwl_cmd *cmd, struct sk_buff *skb)
  1072. {
  1073. /* We didn't cache the SKB; let the caller free it */
  1074. return 1;
  1075. }
  1076. /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
  1077. static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
  1078. {
  1079. struct iwl4965_sensitivity_cmd cmd ;
  1080. struct iwl4965_sensitivity_data *data = NULL;
  1081. struct iwl_host_cmd cmd_out = {
  1082. .id = SENSITIVITY_CMD,
  1083. .len = sizeof(struct iwl4965_sensitivity_cmd),
  1084. .meta.flags = flags,
  1085. .data = &cmd,
  1086. };
  1087. int ret;
  1088. data = &(priv->sensitivity_data);
  1089. memset(&cmd, 0, sizeof(cmd));
  1090. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
  1091. cpu_to_le16((u16)data->auto_corr_ofdm);
  1092. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
  1093. cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
  1094. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
  1095. cpu_to_le16((u16)data->auto_corr_ofdm_x1);
  1096. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
  1097. cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
  1098. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
  1099. cpu_to_le16((u16)data->auto_corr_cck);
  1100. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
  1101. cpu_to_le16((u16)data->auto_corr_cck_mrc);
  1102. cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
  1103. cpu_to_le16((u16)data->nrg_th_cck);
  1104. cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
  1105. cpu_to_le16((u16)data->nrg_th_ofdm);
  1106. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
  1107. __constant_cpu_to_le16(190);
  1108. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
  1109. __constant_cpu_to_le16(390);
  1110. cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
  1111. __constant_cpu_to_le16(62);
  1112. IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
  1113. data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
  1114. data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
  1115. data->nrg_th_ofdm);
  1116. IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
  1117. data->auto_corr_cck, data->auto_corr_cck_mrc,
  1118. data->nrg_th_cck);
  1119. /* Update uCode's "work" table, and copy it to DSP */
  1120. cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
  1121. if (flags & CMD_ASYNC)
  1122. cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
  1123. /* Don't send command to uCode if nothing has changed */
  1124. if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
  1125. sizeof(u16)*HD_TABLE_SIZE)) {
  1126. IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
  1127. return 0;
  1128. }
  1129. /* Copy table for comparison next time */
  1130. memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
  1131. sizeof(u16)*HD_TABLE_SIZE);
  1132. ret = iwl_send_cmd(priv, &cmd_out);
  1133. if (ret)
  1134. IWL_ERROR("SENSITIVITY_CMD failed\n");
  1135. return ret;
  1136. }
  1137. void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
  1138. {
  1139. struct iwl4965_sensitivity_data *data = NULL;
  1140. int i;
  1141. int ret = 0;
  1142. IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
  1143. if (force)
  1144. memset(&(priv->sensitivity_tbl[0]), 0,
  1145. sizeof(u16)*HD_TABLE_SIZE);
  1146. /* Clear driver's sensitivity algo data */
  1147. data = &(priv->sensitivity_data);
  1148. memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
  1149. data->num_in_cck_no_fa = 0;
  1150. data->nrg_curr_state = IWL_FA_TOO_MANY;
  1151. data->nrg_prev_state = IWL_FA_TOO_MANY;
  1152. data->nrg_silence_ref = 0;
  1153. data->nrg_silence_idx = 0;
  1154. data->nrg_energy_idx = 0;
  1155. for (i = 0; i < 10; i++)
  1156. data->nrg_value[i] = 0;
  1157. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
  1158. data->nrg_silence_rssi[i] = 0;
  1159. data->auto_corr_ofdm = 90;
  1160. data->auto_corr_ofdm_mrc = 170;
  1161. data->auto_corr_ofdm_x1 = 105;
  1162. data->auto_corr_ofdm_mrc_x1 = 220;
  1163. data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
  1164. data->auto_corr_cck_mrc = 200;
  1165. data->nrg_th_cck = 100;
  1166. data->nrg_th_ofdm = 100;
  1167. data->last_bad_plcp_cnt_ofdm = 0;
  1168. data->last_fa_cnt_ofdm = 0;
  1169. data->last_bad_plcp_cnt_cck = 0;
  1170. data->last_fa_cnt_cck = 0;
  1171. /* Clear prior Sensitivity command data to force send to uCode */
  1172. if (force)
  1173. memset(&(priv->sensitivity_tbl[0]), 0,
  1174. sizeof(u16)*HD_TABLE_SIZE);
  1175. ret |= iwl4965_sensitivity_write(priv, flags);
  1176. IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
  1177. return;
  1178. }
  1179. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  1180. * Called after every association, but this runs only once!
  1181. * ... once chain noise is calibrated the first time, it's good forever. */
  1182. void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  1183. {
  1184. struct iwl4965_chain_noise_data *data = NULL;
  1185. data = &(priv->chain_noise_data);
  1186. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  1187. struct iwl4965_calibration_cmd cmd;
  1188. memset(&cmd, 0, sizeof(cmd));
  1189. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1190. cmd.diff_gain_a = 0;
  1191. cmd.diff_gain_b = 0;
  1192. cmd.diff_gain_c = 0;
  1193. iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
  1194. sizeof(cmd), &cmd, NULL);
  1195. msleep(4);
  1196. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  1197. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  1198. }
  1199. return;
  1200. }
  1201. /*
  1202. * Accumulate 20 beacons of signal and noise statistics for each of
  1203. * 3 receivers/antennas/rx-chains, then figure out:
  1204. * 1) Which antennas are connected.
  1205. * 2) Differential rx gain settings to balance the 3 receivers.
  1206. */
  1207. static void iwl4965_noise_calibration(struct iwl_priv *priv,
  1208. struct iwl4965_notif_statistics *stat_resp)
  1209. {
  1210. struct iwl4965_chain_noise_data *data = NULL;
  1211. int ret = 0;
  1212. u32 chain_noise_a;
  1213. u32 chain_noise_b;
  1214. u32 chain_noise_c;
  1215. u32 chain_sig_a;
  1216. u32 chain_sig_b;
  1217. u32 chain_sig_c;
  1218. u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1219. u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1220. u32 max_average_sig;
  1221. u16 max_average_sig_antenna_i;
  1222. u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
  1223. u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
  1224. u16 i = 0;
  1225. u16 chan_num = INITIALIZATION_VALUE;
  1226. u32 band = INITIALIZATION_VALUE;
  1227. u32 active_chains = 0;
  1228. unsigned long flags;
  1229. struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
  1230. data = &(priv->chain_noise_data);
  1231. /* Accumulate just the first 20 beacons after the first association,
  1232. * then we're done forever. */
  1233. if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
  1234. if (data->state == IWL_CHAIN_NOISE_ALIVE)
  1235. IWL_DEBUG_CALIB("Wait for noise calib reset\n");
  1236. return;
  1237. }
  1238. spin_lock_irqsave(&priv->lock, flags);
  1239. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1240. IWL_DEBUG_CALIB(" << Interference data unavailable\n");
  1241. spin_unlock_irqrestore(&priv->lock, flags);
  1242. return;
  1243. }
  1244. band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
  1245. chan_num = le16_to_cpu(priv->staging_rxon.channel);
  1246. /* Make sure we accumulate data for just the associated channel
  1247. * (even if scanning). */
  1248. if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
  1249. ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
  1250. (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
  1251. IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
  1252. chan_num, band);
  1253. spin_unlock_irqrestore(&priv->lock, flags);
  1254. return;
  1255. }
  1256. /* Accumulate beacon statistics values across 20 beacons */
  1257. chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
  1258. IN_BAND_FILTER;
  1259. chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
  1260. IN_BAND_FILTER;
  1261. chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
  1262. IN_BAND_FILTER;
  1263. chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
  1264. chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
  1265. chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
  1266. spin_unlock_irqrestore(&priv->lock, flags);
  1267. data->beacon_count++;
  1268. data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
  1269. data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
  1270. data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
  1271. data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
  1272. data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
  1273. data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
  1274. IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
  1275. data->beacon_count);
  1276. IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
  1277. chain_sig_a, chain_sig_b, chain_sig_c);
  1278. IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
  1279. chain_noise_a, chain_noise_b, chain_noise_c);
  1280. /* If this is the 20th beacon, determine:
  1281. * 1) Disconnected antennas (using signal strengths)
  1282. * 2) Differential gain (using silence noise) to balance receivers */
  1283. if (data->beacon_count == CAL_NUM_OF_BEACONS) {
  1284. /* Analyze signal for disconnected antenna */
  1285. average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
  1286. average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
  1287. average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
  1288. if (average_sig[0] >= average_sig[1]) {
  1289. max_average_sig = average_sig[0];
  1290. max_average_sig_antenna_i = 0;
  1291. active_chains = (1 << max_average_sig_antenna_i);
  1292. } else {
  1293. max_average_sig = average_sig[1];
  1294. max_average_sig_antenna_i = 1;
  1295. active_chains = (1 << max_average_sig_antenna_i);
  1296. }
  1297. if (average_sig[2] >= max_average_sig) {
  1298. max_average_sig = average_sig[2];
  1299. max_average_sig_antenna_i = 2;
  1300. active_chains = (1 << max_average_sig_antenna_i);
  1301. }
  1302. IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
  1303. average_sig[0], average_sig[1], average_sig[2]);
  1304. IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
  1305. max_average_sig, max_average_sig_antenna_i);
  1306. /* Compare signal strengths for all 3 receivers. */
  1307. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1308. if (i != max_average_sig_antenna_i) {
  1309. s32 rssi_delta = (max_average_sig -
  1310. average_sig[i]);
  1311. /* If signal is very weak, compared with
  1312. * strongest, mark it as disconnected. */
  1313. if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
  1314. data->disconn_array[i] = 1;
  1315. else
  1316. active_chains |= (1 << i);
  1317. IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
  1318. "disconn_array[i] = %d\n",
  1319. i, rssi_delta, data->disconn_array[i]);
  1320. }
  1321. }
  1322. /*If both chains A & B are disconnected -
  1323. * connect B and leave A as is */
  1324. if (data->disconn_array[CHAIN_A] &&
  1325. data->disconn_array[CHAIN_B]) {
  1326. data->disconn_array[CHAIN_B] = 0;
  1327. active_chains |= (1 << CHAIN_B);
  1328. IWL_DEBUG_CALIB("both A & B chains are disconnected! "
  1329. "W/A - declare B as connected\n");
  1330. }
  1331. IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
  1332. active_chains);
  1333. /* Save for use within RXON, TX, SCAN commands, etc. */
  1334. priv->valid_antenna = active_chains;
  1335. /* Analyze noise for rx balance */
  1336. average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
  1337. average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
  1338. average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
  1339. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1340. if (!(data->disconn_array[i]) &&
  1341. (average_noise[i] <= min_average_noise)) {
  1342. /* This means that chain i is active and has
  1343. * lower noise values so far: */
  1344. min_average_noise = average_noise[i];
  1345. min_average_noise_antenna_i = i;
  1346. }
  1347. }
  1348. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  1349. IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
  1350. average_noise[0], average_noise[1],
  1351. average_noise[2]);
  1352. IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
  1353. min_average_noise, min_average_noise_antenna_i);
  1354. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1355. s32 delta_g = 0;
  1356. if (!(data->disconn_array[i]) &&
  1357. (data->delta_gain_code[i] ==
  1358. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  1359. delta_g = average_noise[i] - min_average_noise;
  1360. data->delta_gain_code[i] = (u8)((delta_g *
  1361. 10) / 15);
  1362. if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
  1363. data->delta_gain_code[i])
  1364. data->delta_gain_code[i] =
  1365. CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
  1366. data->delta_gain_code[i] =
  1367. (data->delta_gain_code[i] | (1 << 2));
  1368. } else
  1369. data->delta_gain_code[i] = 0;
  1370. }
  1371. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  1372. data->delta_gain_code[0],
  1373. data->delta_gain_code[1],
  1374. data->delta_gain_code[2]);
  1375. /* Differential gain gets sent to uCode only once */
  1376. if (!data->radio_write) {
  1377. struct iwl4965_calibration_cmd cmd;
  1378. data->radio_write = 1;
  1379. memset(&cmd, 0, sizeof(cmd));
  1380. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1381. cmd.diff_gain_a = data->delta_gain_code[0];
  1382. cmd.diff_gain_b = data->delta_gain_code[1];
  1383. cmd.diff_gain_c = data->delta_gain_code[2];
  1384. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1385. sizeof(cmd), &cmd);
  1386. if (ret)
  1387. IWL_DEBUG_CALIB("fail sending cmd "
  1388. "REPLY_PHY_CALIBRATION_CMD \n");
  1389. /* TODO we might want recalculate
  1390. * rx_chain in rxon cmd */
  1391. /* Mark so we run this algo only once! */
  1392. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  1393. }
  1394. data->chain_noise_a = 0;
  1395. data->chain_noise_b = 0;
  1396. data->chain_noise_c = 0;
  1397. data->chain_signal_a = 0;
  1398. data->chain_signal_b = 0;
  1399. data->chain_signal_c = 0;
  1400. data->beacon_count = 0;
  1401. }
  1402. return;
  1403. }
  1404. static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
  1405. struct iwl4965_notif_statistics *resp)
  1406. {
  1407. u32 rx_enable_time;
  1408. u32 fa_cck;
  1409. u32 fa_ofdm;
  1410. u32 bad_plcp_cck;
  1411. u32 bad_plcp_ofdm;
  1412. u32 norm_fa_ofdm;
  1413. u32 norm_fa_cck;
  1414. struct iwl4965_sensitivity_data *data = NULL;
  1415. struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
  1416. struct statistics_rx *statistics = &(resp->rx);
  1417. unsigned long flags;
  1418. struct statistics_general_data statis;
  1419. int ret;
  1420. data = &(priv->sensitivity_data);
  1421. if (!iwl_is_associated(priv)) {
  1422. IWL_DEBUG_CALIB("<< - not associated\n");
  1423. return;
  1424. }
  1425. spin_lock_irqsave(&priv->lock, flags);
  1426. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1427. IWL_DEBUG_CALIB("<< invalid data.\n");
  1428. spin_unlock_irqrestore(&priv->lock, flags);
  1429. return;
  1430. }
  1431. /* Extract Statistics: */
  1432. rx_enable_time = le32_to_cpu(rx_info->channel_load);
  1433. fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
  1434. fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
  1435. bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
  1436. bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
  1437. statis.beacon_silence_rssi_a =
  1438. le32_to_cpu(statistics->general.beacon_silence_rssi_a);
  1439. statis.beacon_silence_rssi_b =
  1440. le32_to_cpu(statistics->general.beacon_silence_rssi_b);
  1441. statis.beacon_silence_rssi_c =
  1442. le32_to_cpu(statistics->general.beacon_silence_rssi_c);
  1443. statis.beacon_energy_a =
  1444. le32_to_cpu(statistics->general.beacon_energy_a);
  1445. statis.beacon_energy_b =
  1446. le32_to_cpu(statistics->general.beacon_energy_b);
  1447. statis.beacon_energy_c =
  1448. le32_to_cpu(statistics->general.beacon_energy_c);
  1449. spin_unlock_irqrestore(&priv->lock, flags);
  1450. IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
  1451. if (!rx_enable_time) {
  1452. IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
  1453. return;
  1454. }
  1455. /* These statistics increase monotonically, and do not reset
  1456. * at each beacon. Calculate difference from last value, or just
  1457. * use the new statistics value if it has reset or wrapped around. */
  1458. if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
  1459. data->last_bad_plcp_cnt_cck = bad_plcp_cck;
  1460. else {
  1461. bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
  1462. data->last_bad_plcp_cnt_cck += bad_plcp_cck;
  1463. }
  1464. if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
  1465. data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
  1466. else {
  1467. bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
  1468. data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
  1469. }
  1470. if (data->last_fa_cnt_ofdm > fa_ofdm)
  1471. data->last_fa_cnt_ofdm = fa_ofdm;
  1472. else {
  1473. fa_ofdm -= data->last_fa_cnt_ofdm;
  1474. data->last_fa_cnt_ofdm += fa_ofdm;
  1475. }
  1476. if (data->last_fa_cnt_cck > fa_cck)
  1477. data->last_fa_cnt_cck = fa_cck;
  1478. else {
  1479. fa_cck -= data->last_fa_cnt_cck;
  1480. data->last_fa_cnt_cck += fa_cck;
  1481. }
  1482. /* Total aborted signal locks */
  1483. norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
  1484. norm_fa_cck = fa_cck + bad_plcp_cck;
  1485. IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
  1486. bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
  1487. iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
  1488. iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
  1489. ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
  1490. return;
  1491. }
  1492. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  1493. {
  1494. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1495. sensitivity_work);
  1496. mutex_lock(&priv->mutex);
  1497. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1498. test_bit(STATUS_SCANNING, &priv->status)) {
  1499. mutex_unlock(&priv->mutex);
  1500. return;
  1501. }
  1502. if (priv->start_calib) {
  1503. iwl4965_noise_calibration(priv, &priv->statistics);
  1504. if (priv->sensitivity_data.state ==
  1505. IWL_SENS_CALIB_NEED_REINIT) {
  1506. iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
  1507. priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
  1508. } else
  1509. iwl4965_sensitivity_calibration(priv,
  1510. &priv->statistics);
  1511. }
  1512. mutex_unlock(&priv->mutex);
  1513. return;
  1514. }
  1515. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  1516. static void iwl4965_bg_txpower_work(struct work_struct *work)
  1517. {
  1518. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1519. txpower_work);
  1520. /* If a scan happened to start before we got here
  1521. * then just return; the statistics notification will
  1522. * kick off another scheduled work to compensate for
  1523. * any temperature delta we missed here. */
  1524. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1525. test_bit(STATUS_SCANNING, &priv->status))
  1526. return;
  1527. mutex_lock(&priv->mutex);
  1528. /* Regardless of if we are assocaited, we must reconfigure the
  1529. * TX power since frames can be sent on non-radar channels while
  1530. * not associated */
  1531. iwl4965_hw_reg_send_txpower(priv);
  1532. /* Update last_temperature to keep is_calib_needed from running
  1533. * when it isn't needed... */
  1534. priv->last_temperature = priv->temperature;
  1535. mutex_unlock(&priv->mutex);
  1536. }
  1537. /*
  1538. * Acquire priv->lock before calling this function !
  1539. */
  1540. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  1541. {
  1542. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  1543. (index & 0xff) | (txq_id << 8));
  1544. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  1545. }
  1546. /**
  1547. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  1548. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  1549. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  1550. *
  1551. * NOTE: Acquire priv->lock before calling this function !
  1552. */
  1553. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  1554. struct iwl4965_tx_queue *txq,
  1555. int tx_fifo_id, int scd_retry)
  1556. {
  1557. int txq_id = txq->q.id;
  1558. /* Find out whether to activate Tx queue */
  1559. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  1560. /* Set up and activate */
  1561. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  1562. (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  1563. (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
  1564. (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
  1565. (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  1566. SCD_QUEUE_STTS_REG_MSK);
  1567. txq->sched_retry = scd_retry;
  1568. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  1569. active ? "Activate" : "Deactivate",
  1570. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  1571. }
  1572. static const u16 default_queue_to_tx_fifo[] = {
  1573. IWL_TX_FIFO_AC3,
  1574. IWL_TX_FIFO_AC2,
  1575. IWL_TX_FIFO_AC1,
  1576. IWL_TX_FIFO_AC0,
  1577. IWL_CMD_FIFO_NUM,
  1578. IWL_TX_FIFO_HCCA_1,
  1579. IWL_TX_FIFO_HCCA_2
  1580. };
  1581. static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
  1582. {
  1583. set_bit(txq_id, &priv->txq_ctx_active_msk);
  1584. }
  1585. static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
  1586. {
  1587. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  1588. }
  1589. int iwl4965_alive_notify(struct iwl_priv *priv)
  1590. {
  1591. u32 a;
  1592. int i = 0;
  1593. unsigned long flags;
  1594. int ret;
  1595. spin_lock_irqsave(&priv->lock, flags);
  1596. #ifdef CONFIG_IWL4965_SENSITIVITY
  1597. memset(&(priv->sensitivity_data), 0,
  1598. sizeof(struct iwl4965_sensitivity_data));
  1599. memset(&(priv->chain_noise_data), 0,
  1600. sizeof(struct iwl4965_chain_noise_data));
  1601. for (i = 0; i < NUM_RX_CHAINS; i++)
  1602. priv->chain_noise_data.delta_gain_code[i] =
  1603. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  1604. #endif /* CONFIG_IWL4965_SENSITIVITY*/
  1605. ret = iwl_grab_nic_access(priv);
  1606. if (ret) {
  1607. spin_unlock_irqrestore(&priv->lock, flags);
  1608. return ret;
  1609. }
  1610. /* Clear 4965's internal Tx Scheduler data base */
  1611. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  1612. a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
  1613. for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1614. iwl_write_targ_mem(priv, a, 0);
  1615. for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1616. iwl_write_targ_mem(priv, a, 0);
  1617. for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
  1618. iwl_write_targ_mem(priv, a, 0);
  1619. /* Tel 4965 where to find Tx byte count tables */
  1620. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  1621. (priv->hw_setting.shared_phys +
  1622. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  1623. /* Disable chain mode for all queues */
  1624. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  1625. /* Initialize each Tx queue (including the command queue) */
  1626. for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
  1627. /* TFD circular buffer read/write indexes */
  1628. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  1629. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1630. /* Max Tx Window size for Scheduler-ACK mode */
  1631. iwl_write_targ_mem(priv, priv->scd_base_addr +
  1632. SCD_CONTEXT_QUEUE_OFFSET(i),
  1633. (SCD_WIN_SIZE <<
  1634. SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1635. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1636. /* Frame limit */
  1637. iwl_write_targ_mem(priv, priv->scd_base_addr +
  1638. SCD_CONTEXT_QUEUE_OFFSET(i) +
  1639. sizeof(u32),
  1640. (SCD_FRAME_LIMIT <<
  1641. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1642. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1643. }
  1644. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  1645. (1 << priv->hw_setting.max_txq_num) - 1);
  1646. /* Activate all Tx DMA/FIFO channels */
  1647. iwl_write_prph(priv, IWL49_SCD_TXFACT,
  1648. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  1649. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  1650. /* Map each Tx/cmd queue to its corresponding fifo */
  1651. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1652. int ac = default_queue_to_tx_fifo[i];
  1653. iwl4965_txq_ctx_activate(priv, i);
  1654. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1655. }
  1656. iwl_release_nic_access(priv);
  1657. spin_unlock_irqrestore(&priv->lock, flags);
  1658. return ret;
  1659. }
  1660. /**
  1661. * iwl4965_hw_set_hw_setting
  1662. *
  1663. * Called when initializing driver
  1664. */
  1665. int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
  1666. {
  1667. int ret = 0;
  1668. if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
  1669. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  1670. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  1671. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  1672. ret = -EINVAL;
  1673. goto out;
  1674. }
  1675. /* Allocate area for Tx byte count tables and Rx queue status */
  1676. priv->hw_setting.shared_virt =
  1677. pci_alloc_consistent(priv->pci_dev,
  1678. sizeof(struct iwl4965_shared),
  1679. &priv->hw_setting.shared_phys);
  1680. if (!priv->hw_setting.shared_virt) {
  1681. ret = -ENOMEM;
  1682. goto out;
  1683. }
  1684. memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
  1685. priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
  1686. priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
  1687. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  1688. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1689. if (priv->cfg->mod_params->amsdu_size_8K)
  1690. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1691. else
  1692. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1693. priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
  1694. priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
  1695. priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
  1696. priv->hw_setting.tx_ant_num = 2;
  1697. out:
  1698. return ret;
  1699. }
  1700. /**
  1701. * iwl4965_hw_txq_ctx_free - Free TXQ Context
  1702. *
  1703. * Destroy all TX DMA queues and structures
  1704. */
  1705. void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
  1706. {
  1707. int txq_id;
  1708. /* Tx queues */
  1709. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  1710. iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
  1711. /* Keep-warm buffer */
  1712. iwl4965_kw_free(priv);
  1713. }
  1714. /**
  1715. * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  1716. *
  1717. * Does NOT advance any TFD circular buffer read/write indexes
  1718. * Does NOT free the TFD itself (which is within circular buffer)
  1719. */
  1720. int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
  1721. {
  1722. struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
  1723. struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
  1724. struct pci_dev *dev = priv->pci_dev;
  1725. int i;
  1726. int counter = 0;
  1727. int index, is_odd;
  1728. /* Host command buffers stay mapped in memory, nothing to clean */
  1729. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  1730. return 0;
  1731. /* Sanity check on number of chunks */
  1732. counter = IWL_GET_BITS(*bd, num_tbs);
  1733. if (counter > MAX_NUM_OF_TBS) {
  1734. IWL_ERROR("Too many chunks: %i\n", counter);
  1735. /* @todo issue fatal error, it is quite serious situation */
  1736. return 0;
  1737. }
  1738. /* Unmap chunks, if any.
  1739. * TFD info for odd chunks is different format than for even chunks. */
  1740. for (i = 0; i < counter; i++) {
  1741. index = i / 2;
  1742. is_odd = i & 0x1;
  1743. if (is_odd)
  1744. pci_unmap_single(
  1745. dev,
  1746. IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
  1747. (IWL_GET_BITS(bd->pa[index],
  1748. tb2_addr_hi20) << 16),
  1749. IWL_GET_BITS(bd->pa[index], tb2_len),
  1750. PCI_DMA_TODEVICE);
  1751. else if (i > 0)
  1752. pci_unmap_single(dev,
  1753. le32_to_cpu(bd->pa[index].tb1_addr),
  1754. IWL_GET_BITS(bd->pa[index], tb1_len),
  1755. PCI_DMA_TODEVICE);
  1756. /* Free SKB, if any, for this chunk */
  1757. if (txq->txb[txq->q.read_ptr].skb[i]) {
  1758. struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
  1759. dev_kfree_skb(skb);
  1760. txq->txb[txq->q.read_ptr].skb[i] = NULL;
  1761. }
  1762. }
  1763. return 0;
  1764. }
  1765. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  1766. {
  1767. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  1768. return -EINVAL;
  1769. }
  1770. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  1771. {
  1772. s32 sign = 1;
  1773. if (num < 0) {
  1774. sign = -sign;
  1775. num = -num;
  1776. }
  1777. if (denom < 0) {
  1778. sign = -sign;
  1779. denom = -denom;
  1780. }
  1781. *res = 1;
  1782. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  1783. return 1;
  1784. }
  1785. /**
  1786. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  1787. *
  1788. * Determines power supply voltage compensation for txpower calculations.
  1789. * Returns number of 1/2-dB steps to subtract from gain table index,
  1790. * to compensate for difference between power supply voltage during
  1791. * factory measurements, vs. current power supply voltage.
  1792. *
  1793. * Voltage indication is higher for lower voltage.
  1794. * Lower voltage requires more gain (lower gain table index).
  1795. */
  1796. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  1797. s32 current_voltage)
  1798. {
  1799. s32 comp = 0;
  1800. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  1801. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  1802. return 0;
  1803. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  1804. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  1805. if (current_voltage > eeprom_voltage)
  1806. comp *= 2;
  1807. if ((comp < -2) || (comp > 2))
  1808. comp = 0;
  1809. return comp;
  1810. }
  1811. static const struct iwl_channel_info *
  1812. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  1813. enum ieee80211_band band, u16 channel)
  1814. {
  1815. const struct iwl_channel_info *ch_info;
  1816. ch_info = iwl_get_channel_info(priv, band, channel);
  1817. if (!is_channel_valid(ch_info))
  1818. return NULL;
  1819. return ch_info;
  1820. }
  1821. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  1822. {
  1823. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  1824. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  1825. return CALIB_CH_GROUP_5;
  1826. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  1827. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  1828. return CALIB_CH_GROUP_1;
  1829. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  1830. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  1831. return CALIB_CH_GROUP_2;
  1832. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  1833. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  1834. return CALIB_CH_GROUP_3;
  1835. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  1836. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  1837. return CALIB_CH_GROUP_4;
  1838. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  1839. return -1;
  1840. }
  1841. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  1842. {
  1843. s32 b = -1;
  1844. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  1845. if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
  1846. continue;
  1847. if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
  1848. && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
  1849. break;
  1850. }
  1851. return b;
  1852. }
  1853. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  1854. {
  1855. s32 val;
  1856. if (x2 == x1)
  1857. return y1;
  1858. else {
  1859. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1860. return val + y2;
  1861. }
  1862. }
  1863. /**
  1864. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  1865. *
  1866. * Interpolates factory measurements from the two sample channels within a
  1867. * sub-band, to apply to channel of interest. Interpolation is proportional to
  1868. * differences in channel frequencies, which is proportional to differences
  1869. * in channel number.
  1870. */
  1871. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1872. struct iwl4965_eeprom_calib_ch_info *chan_info)
  1873. {
  1874. s32 s = -1;
  1875. u32 c;
  1876. u32 m;
  1877. const struct iwl4965_eeprom_calib_measure *m1;
  1878. const struct iwl4965_eeprom_calib_measure *m2;
  1879. struct iwl4965_eeprom_calib_measure *omeas;
  1880. u32 ch_i1;
  1881. u32 ch_i2;
  1882. s = iwl4965_get_sub_band(priv, channel);
  1883. if (s >= EEPROM_TX_POWER_BANDS) {
  1884. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1885. return -1;
  1886. }
  1887. ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
  1888. ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
  1889. chan_info->ch_num = (u8) channel;
  1890. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1891. channel, s, ch_i1, ch_i2);
  1892. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1893. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1894. m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
  1895. measurements[c][m]);
  1896. m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
  1897. measurements[c][m]);
  1898. omeas = &(chan_info->measurements[c][m]);
  1899. omeas->actual_pow =
  1900. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1901. m1->actual_pow,
  1902. ch_i2,
  1903. m2->actual_pow);
  1904. omeas->gain_idx =
  1905. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1906. m1->gain_idx, ch_i2,
  1907. m2->gain_idx);
  1908. omeas->temperature =
  1909. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1910. m1->temperature,
  1911. ch_i2,
  1912. m2->temperature);
  1913. omeas->pa_det =
  1914. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1915. m1->pa_det, ch_i2,
  1916. m2->pa_det);
  1917. IWL_DEBUG_TXPOWER
  1918. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1919. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1920. IWL_DEBUG_TXPOWER
  1921. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1922. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1923. IWL_DEBUG_TXPOWER
  1924. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1925. m1->pa_det, m2->pa_det, omeas->pa_det);
  1926. IWL_DEBUG_TXPOWER
  1927. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1928. m1->temperature, m2->temperature,
  1929. omeas->temperature);
  1930. }
  1931. }
  1932. return 0;
  1933. }
  1934. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1935. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1936. static s32 back_off_table[] = {
  1937. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1938. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1939. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1940. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1941. 10 /* CCK */
  1942. };
  1943. /* Thermal compensation values for txpower for various frequency ranges ...
  1944. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1945. static struct iwl4965_txpower_comp_entry {
  1946. s32 degrees_per_05db_a;
  1947. s32 degrees_per_05db_a_denom;
  1948. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1949. {9, 2}, /* group 0 5.2, ch 34-43 */
  1950. {4, 1}, /* group 1 5.2, ch 44-70 */
  1951. {4, 1}, /* group 2 5.2, ch 71-124 */
  1952. {4, 1}, /* group 3 5.2, ch 125-200 */
  1953. {3, 1} /* group 4 2.4, ch all */
  1954. };
  1955. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1956. {
  1957. if (!band) {
  1958. if ((rate_power_index & 7) <= 4)
  1959. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1960. }
  1961. return MIN_TX_GAIN_INDEX;
  1962. }
  1963. struct gain_entry {
  1964. u8 dsp;
  1965. u8 radio;
  1966. };
  1967. static const struct gain_entry gain_table[2][108] = {
  1968. /* 5.2GHz power gain index table */
  1969. {
  1970. {123, 0x3F}, /* highest txpower */
  1971. {117, 0x3F},
  1972. {110, 0x3F},
  1973. {104, 0x3F},
  1974. {98, 0x3F},
  1975. {110, 0x3E},
  1976. {104, 0x3E},
  1977. {98, 0x3E},
  1978. {110, 0x3D},
  1979. {104, 0x3D},
  1980. {98, 0x3D},
  1981. {110, 0x3C},
  1982. {104, 0x3C},
  1983. {98, 0x3C},
  1984. {110, 0x3B},
  1985. {104, 0x3B},
  1986. {98, 0x3B},
  1987. {110, 0x3A},
  1988. {104, 0x3A},
  1989. {98, 0x3A},
  1990. {110, 0x39},
  1991. {104, 0x39},
  1992. {98, 0x39},
  1993. {110, 0x38},
  1994. {104, 0x38},
  1995. {98, 0x38},
  1996. {110, 0x37},
  1997. {104, 0x37},
  1998. {98, 0x37},
  1999. {110, 0x36},
  2000. {104, 0x36},
  2001. {98, 0x36},
  2002. {110, 0x35},
  2003. {104, 0x35},
  2004. {98, 0x35},
  2005. {110, 0x34},
  2006. {104, 0x34},
  2007. {98, 0x34},
  2008. {110, 0x33},
  2009. {104, 0x33},
  2010. {98, 0x33},
  2011. {110, 0x32},
  2012. {104, 0x32},
  2013. {98, 0x32},
  2014. {110, 0x31},
  2015. {104, 0x31},
  2016. {98, 0x31},
  2017. {110, 0x30},
  2018. {104, 0x30},
  2019. {98, 0x30},
  2020. {110, 0x25},
  2021. {104, 0x25},
  2022. {98, 0x25},
  2023. {110, 0x24},
  2024. {104, 0x24},
  2025. {98, 0x24},
  2026. {110, 0x23},
  2027. {104, 0x23},
  2028. {98, 0x23},
  2029. {110, 0x22},
  2030. {104, 0x18},
  2031. {98, 0x18},
  2032. {110, 0x17},
  2033. {104, 0x17},
  2034. {98, 0x17},
  2035. {110, 0x16},
  2036. {104, 0x16},
  2037. {98, 0x16},
  2038. {110, 0x15},
  2039. {104, 0x15},
  2040. {98, 0x15},
  2041. {110, 0x14},
  2042. {104, 0x14},
  2043. {98, 0x14},
  2044. {110, 0x13},
  2045. {104, 0x13},
  2046. {98, 0x13},
  2047. {110, 0x12},
  2048. {104, 0x08},
  2049. {98, 0x08},
  2050. {110, 0x07},
  2051. {104, 0x07},
  2052. {98, 0x07},
  2053. {110, 0x06},
  2054. {104, 0x06},
  2055. {98, 0x06},
  2056. {110, 0x05},
  2057. {104, 0x05},
  2058. {98, 0x05},
  2059. {110, 0x04},
  2060. {104, 0x04},
  2061. {98, 0x04},
  2062. {110, 0x03},
  2063. {104, 0x03},
  2064. {98, 0x03},
  2065. {110, 0x02},
  2066. {104, 0x02},
  2067. {98, 0x02},
  2068. {110, 0x01},
  2069. {104, 0x01},
  2070. {98, 0x01},
  2071. {110, 0x00},
  2072. {104, 0x00},
  2073. {98, 0x00},
  2074. {93, 0x00},
  2075. {88, 0x00},
  2076. {83, 0x00},
  2077. {78, 0x00},
  2078. },
  2079. /* 2.4GHz power gain index table */
  2080. {
  2081. {110, 0x3f}, /* highest txpower */
  2082. {104, 0x3f},
  2083. {98, 0x3f},
  2084. {110, 0x3e},
  2085. {104, 0x3e},
  2086. {98, 0x3e},
  2087. {110, 0x3d},
  2088. {104, 0x3d},
  2089. {98, 0x3d},
  2090. {110, 0x3c},
  2091. {104, 0x3c},
  2092. {98, 0x3c},
  2093. {110, 0x3b},
  2094. {104, 0x3b},
  2095. {98, 0x3b},
  2096. {110, 0x3a},
  2097. {104, 0x3a},
  2098. {98, 0x3a},
  2099. {110, 0x39},
  2100. {104, 0x39},
  2101. {98, 0x39},
  2102. {110, 0x38},
  2103. {104, 0x38},
  2104. {98, 0x38},
  2105. {110, 0x37},
  2106. {104, 0x37},
  2107. {98, 0x37},
  2108. {110, 0x36},
  2109. {104, 0x36},
  2110. {98, 0x36},
  2111. {110, 0x35},
  2112. {104, 0x35},
  2113. {98, 0x35},
  2114. {110, 0x34},
  2115. {104, 0x34},
  2116. {98, 0x34},
  2117. {110, 0x33},
  2118. {104, 0x33},
  2119. {98, 0x33},
  2120. {110, 0x32},
  2121. {104, 0x32},
  2122. {98, 0x32},
  2123. {110, 0x31},
  2124. {104, 0x31},
  2125. {98, 0x31},
  2126. {110, 0x30},
  2127. {104, 0x30},
  2128. {98, 0x30},
  2129. {110, 0x6},
  2130. {104, 0x6},
  2131. {98, 0x6},
  2132. {110, 0x5},
  2133. {104, 0x5},
  2134. {98, 0x5},
  2135. {110, 0x4},
  2136. {104, 0x4},
  2137. {98, 0x4},
  2138. {110, 0x3},
  2139. {104, 0x3},
  2140. {98, 0x3},
  2141. {110, 0x2},
  2142. {104, 0x2},
  2143. {98, 0x2},
  2144. {110, 0x1},
  2145. {104, 0x1},
  2146. {98, 0x1},
  2147. {110, 0x0},
  2148. {104, 0x0},
  2149. {98, 0x0},
  2150. {97, 0},
  2151. {96, 0},
  2152. {95, 0},
  2153. {94, 0},
  2154. {93, 0},
  2155. {92, 0},
  2156. {91, 0},
  2157. {90, 0},
  2158. {89, 0},
  2159. {88, 0},
  2160. {87, 0},
  2161. {86, 0},
  2162. {85, 0},
  2163. {84, 0},
  2164. {83, 0},
  2165. {82, 0},
  2166. {81, 0},
  2167. {80, 0},
  2168. {79, 0},
  2169. {78, 0},
  2170. {77, 0},
  2171. {76, 0},
  2172. {75, 0},
  2173. {74, 0},
  2174. {73, 0},
  2175. {72, 0},
  2176. {71, 0},
  2177. {70, 0},
  2178. {69, 0},
  2179. {68, 0},
  2180. {67, 0},
  2181. {66, 0},
  2182. {65, 0},
  2183. {64, 0},
  2184. {63, 0},
  2185. {62, 0},
  2186. {61, 0},
  2187. {60, 0},
  2188. {59, 0},
  2189. }
  2190. };
  2191. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  2192. u8 is_fat, u8 ctrl_chan_high,
  2193. struct iwl4965_tx_power_db *tx_power_tbl)
  2194. {
  2195. u8 saturation_power;
  2196. s32 target_power;
  2197. s32 user_target_power;
  2198. s32 power_limit;
  2199. s32 current_temp;
  2200. s32 reg_limit;
  2201. s32 current_regulatory;
  2202. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  2203. int i;
  2204. int c;
  2205. const struct iwl_channel_info *ch_info = NULL;
  2206. struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
  2207. const struct iwl4965_eeprom_calib_measure *measurement;
  2208. s16 voltage;
  2209. s32 init_voltage;
  2210. s32 voltage_compensation;
  2211. s32 degrees_per_05db_num;
  2212. s32 degrees_per_05db_denom;
  2213. s32 factory_temp;
  2214. s32 temperature_comp[2];
  2215. s32 factory_gain_index[2];
  2216. s32 factory_actual_pwr[2];
  2217. s32 power_index;
  2218. /* Sanity check requested level (dBm) */
  2219. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  2220. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  2221. priv->user_txpower_limit);
  2222. return -EINVAL;
  2223. }
  2224. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  2225. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  2226. priv->user_txpower_limit);
  2227. return -EINVAL;
  2228. }
  2229. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  2230. * are used for indexing into txpower table) */
  2231. user_target_power = 2 * priv->user_txpower_limit;
  2232. /* Get current (RXON) channel, band, width */
  2233. ch_info =
  2234. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  2235. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  2236. is_fat);
  2237. if (!ch_info)
  2238. return -EINVAL;
  2239. /* get txatten group, used to select 1) thermal txpower adjustment
  2240. * and 2) mimo txpower balance between Tx chains. */
  2241. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  2242. if (txatten_grp < 0)
  2243. return -EINVAL;
  2244. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  2245. channel, txatten_grp);
  2246. if (is_fat) {
  2247. if (ctrl_chan_high)
  2248. channel -= 2;
  2249. else
  2250. channel += 2;
  2251. }
  2252. /* hardware txpower limits ...
  2253. * saturation (clipping distortion) txpowers are in half-dBm */
  2254. if (band)
  2255. saturation_power = priv->eeprom.calib_info.saturation_power24;
  2256. else
  2257. saturation_power = priv->eeprom.calib_info.saturation_power52;
  2258. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  2259. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  2260. if (band)
  2261. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  2262. else
  2263. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  2264. }
  2265. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  2266. * max_power_avg values are in dBm, convert * 2 */
  2267. if (is_fat)
  2268. reg_limit = ch_info->fat_max_power_avg * 2;
  2269. else
  2270. reg_limit = ch_info->max_power_avg * 2;
  2271. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  2272. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  2273. if (band)
  2274. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  2275. else
  2276. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  2277. }
  2278. /* Interpolate txpower calibration values for this channel,
  2279. * based on factory calibration tests on spaced channels. */
  2280. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  2281. /* calculate tx gain adjustment based on power supply voltage */
  2282. voltage = priv->eeprom.calib_info.voltage;
  2283. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  2284. voltage_compensation =
  2285. iwl4965_get_voltage_compensation(voltage, init_voltage);
  2286. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  2287. init_voltage,
  2288. voltage, voltage_compensation);
  2289. /* get current temperature (Celsius) */
  2290. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  2291. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  2292. current_temp = KELVIN_TO_CELSIUS(current_temp);
  2293. /* select thermal txpower adjustment params, based on channel group
  2294. * (same frequency group used for mimo txatten adjustment) */
  2295. degrees_per_05db_num =
  2296. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  2297. degrees_per_05db_denom =
  2298. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  2299. /* get per-chain txpower values from factory measurements */
  2300. for (c = 0; c < 2; c++) {
  2301. measurement = &ch_eeprom_info.measurements[c][1];
  2302. /* txgain adjustment (in half-dB steps) based on difference
  2303. * between factory and current temperature */
  2304. factory_temp = measurement->temperature;
  2305. iwl4965_math_div_round((current_temp - factory_temp) *
  2306. degrees_per_05db_denom,
  2307. degrees_per_05db_num,
  2308. &temperature_comp[c]);
  2309. factory_gain_index[c] = measurement->gain_idx;
  2310. factory_actual_pwr[c] = measurement->actual_pow;
  2311. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  2312. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  2313. "curr tmp %d, comp %d steps\n",
  2314. factory_temp, current_temp,
  2315. temperature_comp[c]);
  2316. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  2317. factory_gain_index[c],
  2318. factory_actual_pwr[c]);
  2319. }
  2320. /* for each of 33 bit-rates (including 1 for CCK) */
  2321. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  2322. u8 is_mimo_rate;
  2323. union iwl4965_tx_power_dual_stream tx_power;
  2324. /* for mimo, reduce each chain's txpower by half
  2325. * (3dB, 6 steps), so total output power is regulatory
  2326. * compliant. */
  2327. if (i & 0x8) {
  2328. current_regulatory = reg_limit -
  2329. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  2330. is_mimo_rate = 1;
  2331. } else {
  2332. current_regulatory = reg_limit;
  2333. is_mimo_rate = 0;
  2334. }
  2335. /* find txpower limit, either hardware or regulatory */
  2336. power_limit = saturation_power - back_off_table[i];
  2337. if (power_limit > current_regulatory)
  2338. power_limit = current_regulatory;
  2339. /* reduce user's txpower request if necessary
  2340. * for this rate on this channel */
  2341. target_power = user_target_power;
  2342. if (target_power > power_limit)
  2343. target_power = power_limit;
  2344. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  2345. i, saturation_power - back_off_table[i],
  2346. current_regulatory, user_target_power,
  2347. target_power);
  2348. /* for each of 2 Tx chains (radio transmitters) */
  2349. for (c = 0; c < 2; c++) {
  2350. s32 atten_value;
  2351. if (is_mimo_rate)
  2352. atten_value =
  2353. (s32)le32_to_cpu(priv->card_alive_init.
  2354. tx_atten[txatten_grp][c]);
  2355. else
  2356. atten_value = 0;
  2357. /* calculate index; higher index means lower txpower */
  2358. power_index = (u8) (factory_gain_index[c] -
  2359. (target_power -
  2360. factory_actual_pwr[c]) -
  2361. temperature_comp[c] -
  2362. voltage_compensation +
  2363. atten_value);
  2364. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  2365. power_index); */
  2366. if (power_index < get_min_power_index(i, band))
  2367. power_index = get_min_power_index(i, band);
  2368. /* adjust 5 GHz index to support negative indexes */
  2369. if (!band)
  2370. power_index += 9;
  2371. /* CCK, rate 32, reduce txpower for CCK */
  2372. if (i == POWER_TABLE_CCK_ENTRY)
  2373. power_index +=
  2374. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  2375. /* stay within the table! */
  2376. if (power_index > 107) {
  2377. IWL_WARNING("txpower index %d > 107\n",
  2378. power_index);
  2379. power_index = 107;
  2380. }
  2381. if (power_index < 0) {
  2382. IWL_WARNING("txpower index %d < 0\n",
  2383. power_index);
  2384. power_index = 0;
  2385. }
  2386. /* fill txpower command for this rate/chain */
  2387. tx_power.s.radio_tx_gain[c] =
  2388. gain_table[band][power_index].radio;
  2389. tx_power.s.dsp_predis_atten[c] =
  2390. gain_table[band][power_index].dsp;
  2391. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  2392. "gain 0x%02x dsp %d\n",
  2393. c, atten_value, power_index,
  2394. tx_power.s.radio_tx_gain[c],
  2395. tx_power.s.dsp_predis_atten[c]);
  2396. }/* for each chain */
  2397. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  2398. }/* for each rate */
  2399. return 0;
  2400. }
  2401. /**
  2402. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  2403. *
  2404. * Uses the active RXON for channel, band, and characteristics (fat, high)
  2405. * The power limit is taken from priv->user_txpower_limit.
  2406. */
  2407. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  2408. {
  2409. struct iwl4965_txpowertable_cmd cmd = { 0 };
  2410. int ret;
  2411. u8 band = 0;
  2412. u8 is_fat = 0;
  2413. u8 ctrl_chan_high = 0;
  2414. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2415. /* If this gets hit a lot, switch it to a BUG() and catch
  2416. * the stack trace to find out who is calling this during
  2417. * a scan. */
  2418. IWL_WARNING("TX Power requested while scanning!\n");
  2419. return -EAGAIN;
  2420. }
  2421. band = priv->band == IEEE80211_BAND_2GHZ;
  2422. is_fat = is_fat_channel(priv->active_rxon.flags);
  2423. if (is_fat &&
  2424. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2425. ctrl_chan_high = 1;
  2426. cmd.band = band;
  2427. cmd.channel = priv->active_rxon.channel;
  2428. ret = iwl4965_fill_txpower_tbl(priv, band,
  2429. le16_to_cpu(priv->active_rxon.channel),
  2430. is_fat, ctrl_chan_high, &cmd.tx_power);
  2431. if (ret)
  2432. goto out;
  2433. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  2434. out:
  2435. return ret;
  2436. }
  2437. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  2438. {
  2439. int rc;
  2440. u8 band = 0;
  2441. u8 is_fat = 0;
  2442. u8 ctrl_chan_high = 0;
  2443. struct iwl4965_channel_switch_cmd cmd = { 0 };
  2444. const struct iwl_channel_info *ch_info;
  2445. band = priv->band == IEEE80211_BAND_2GHZ;
  2446. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  2447. is_fat = is_fat_channel(priv->staging_rxon.flags);
  2448. if (is_fat &&
  2449. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2450. ctrl_chan_high = 1;
  2451. cmd.band = band;
  2452. cmd.expect_beacon = 0;
  2453. cmd.channel = cpu_to_le16(channel);
  2454. cmd.rxon_flags = priv->active_rxon.flags;
  2455. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  2456. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  2457. if (ch_info)
  2458. cmd.expect_beacon = is_channel_radar(ch_info);
  2459. else
  2460. cmd.expect_beacon = 1;
  2461. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  2462. ctrl_chan_high, &cmd.tx_power);
  2463. if (rc) {
  2464. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  2465. return rc;
  2466. }
  2467. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  2468. return rc;
  2469. }
  2470. #define RTS_HCCA_RETRY_LIMIT 3
  2471. #define RTS_DFAULT_RETRY_LIMIT 60
  2472. void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
  2473. struct iwl_cmd *cmd,
  2474. struct ieee80211_tx_control *ctrl,
  2475. struct ieee80211_hdr *hdr, int sta_id,
  2476. int is_hcca)
  2477. {
  2478. struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
  2479. u8 rts_retry_limit = 0;
  2480. u8 data_retry_limit = 0;
  2481. u16 fc = le16_to_cpu(hdr->frame_control);
  2482. u8 rate_plcp;
  2483. u16 rate_flags = 0;
  2484. int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
  2485. rate_plcp = iwl4965_rates[rate_idx].plcp;
  2486. rts_retry_limit = (is_hcca) ?
  2487. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  2488. if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
  2489. rate_flags |= RATE_MCS_CCK_MSK;
  2490. if (ieee80211_is_probe_response(fc)) {
  2491. data_retry_limit = 3;
  2492. if (data_retry_limit < rts_retry_limit)
  2493. rts_retry_limit = data_retry_limit;
  2494. } else
  2495. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  2496. if (priv->data_retry_limit != -1)
  2497. data_retry_limit = priv->data_retry_limit;
  2498. if (ieee80211_is_data(fc)) {
  2499. tx->initial_rate_index = 0;
  2500. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  2501. } else {
  2502. switch (fc & IEEE80211_FCTL_STYPE) {
  2503. case IEEE80211_STYPE_AUTH:
  2504. case IEEE80211_STYPE_DEAUTH:
  2505. case IEEE80211_STYPE_ASSOC_REQ:
  2506. case IEEE80211_STYPE_REASSOC_REQ:
  2507. if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
  2508. tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2509. tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
  2510. }
  2511. break;
  2512. default:
  2513. break;
  2514. }
  2515. /* Alternate between antenna A and B for successive frames */
  2516. if (priv->use_ant_b_for_management_frame) {
  2517. priv->use_ant_b_for_management_frame = 0;
  2518. rate_flags |= RATE_MCS_ANT_B_MSK;
  2519. } else {
  2520. priv->use_ant_b_for_management_frame = 1;
  2521. rate_flags |= RATE_MCS_ANT_A_MSK;
  2522. }
  2523. }
  2524. tx->rts_retry_limit = rts_retry_limit;
  2525. tx->data_retry_limit = data_retry_limit;
  2526. tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
  2527. }
  2528. int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
  2529. {
  2530. struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
  2531. return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
  2532. }
  2533. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  2534. {
  2535. return priv->temperature;
  2536. }
  2537. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  2538. struct iwl4965_frame *frame, u8 rate)
  2539. {
  2540. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  2541. unsigned int frame_size;
  2542. tx_beacon_cmd = &frame->u.beacon;
  2543. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2544. tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
  2545. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2546. frame_size = iwl4965_fill_beacon_frame(priv,
  2547. tx_beacon_cmd->frame,
  2548. iwl4965_broadcast_addr,
  2549. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2550. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2551. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2552. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  2553. tx_beacon_cmd->tx.rate_n_flags =
  2554. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  2555. else
  2556. tx_beacon_cmd->tx.rate_n_flags =
  2557. iwl4965_hw_set_rate_n_flags(rate, 0);
  2558. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2559. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  2560. return (sizeof(*tx_beacon_cmd) + frame_size);
  2561. }
  2562. /*
  2563. * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
  2564. * given Tx queue, and enable the DMA channel used for that queue.
  2565. *
  2566. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  2567. * channels supported in hardware.
  2568. */
  2569. int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
  2570. {
  2571. int rc;
  2572. unsigned long flags;
  2573. int txq_id = txq->q.id;
  2574. spin_lock_irqsave(&priv->lock, flags);
  2575. rc = iwl_grab_nic_access(priv);
  2576. if (rc) {
  2577. spin_unlock_irqrestore(&priv->lock, flags);
  2578. return rc;
  2579. }
  2580. /* Circular buffer (TFD queue in DRAM) physical base address */
  2581. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  2582. txq->q.dma_addr >> 8);
  2583. /* Enable DMA channel, using same id as for TFD queue */
  2584. iwl_write_direct32(
  2585. priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  2586. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  2587. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
  2588. iwl_release_nic_access(priv);
  2589. spin_unlock_irqrestore(&priv->lock, flags);
  2590. return 0;
  2591. }
  2592. int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
  2593. dma_addr_t addr, u16 len)
  2594. {
  2595. int index, is_odd;
  2596. struct iwl4965_tfd_frame *tfd = ptr;
  2597. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  2598. /* Each TFD can point to a maximum 20 Tx buffers */
  2599. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  2600. IWL_ERROR("Error can not send more than %d chunks\n",
  2601. MAX_NUM_OF_TBS);
  2602. return -EINVAL;
  2603. }
  2604. index = num_tbs / 2;
  2605. is_odd = num_tbs & 0x1;
  2606. if (!is_odd) {
  2607. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  2608. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  2609. iwl_get_dma_hi_address(addr));
  2610. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  2611. } else {
  2612. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  2613. (u32) (addr & 0xffff));
  2614. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  2615. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  2616. }
  2617. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  2618. return 0;
  2619. }
  2620. static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
  2621. {
  2622. u16 hw_version = priv->eeprom.board_revision_4965;
  2623. IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
  2624. ((hw_version >> 8) & 0x0F),
  2625. ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
  2626. IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
  2627. priv->eeprom.board_pba_number_4965);
  2628. }
  2629. #define IWL_TX_CRC_SIZE 4
  2630. #define IWL_TX_DELIMITER_SIZE 4
  2631. /**
  2632. * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
  2633. */
  2634. int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv,
  2635. struct iwl4965_tx_queue *txq, u16 byte_cnt)
  2636. {
  2637. int len;
  2638. int txq_id = txq->q.id;
  2639. struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
  2640. if (txq->need_update == 0)
  2641. return 0;
  2642. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  2643. /* Set up byte count within first 256 entries */
  2644. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2645. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  2646. /* If within first 64 entries, duplicate at end */
  2647. if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
  2648. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2649. tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
  2650. byte_cnt, len);
  2651. return 0;
  2652. }
  2653. /**
  2654. * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  2655. *
  2656. * Selects how many and which Rx receivers/antennas/chains to use.
  2657. * This should not be used for scan command ... it puts data in wrong place.
  2658. */
  2659. void iwl4965_set_rxon_chain(struct iwl_priv *priv)
  2660. {
  2661. u8 is_single = is_single_stream(priv);
  2662. u8 idle_state, rx_state;
  2663. priv->staging_rxon.rx_chain = 0;
  2664. rx_state = idle_state = 3;
  2665. /* Tell uCode which antennas are actually connected.
  2666. * Before first association, we assume all antennas are connected.
  2667. * Just after first association, iwl4965_noise_calibration()
  2668. * checks which antennas actually *are* connected. */
  2669. priv->staging_rxon.rx_chain |=
  2670. cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
  2671. /* How many receivers should we use? */
  2672. iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
  2673. priv->staging_rxon.rx_chain |=
  2674. cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
  2675. priv->staging_rxon.rx_chain |=
  2676. cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
  2677. if (!is_single && (rx_state >= 2) &&
  2678. !test_bit(STATUS_POWER_PMI, &priv->status))
  2679. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2680. else
  2681. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2682. IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
  2683. }
  2684. /**
  2685. * sign_extend - Sign extend a value using specified bit as sign-bit
  2686. *
  2687. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  2688. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  2689. *
  2690. * @param oper value to sign extend
  2691. * @param index 0 based bit index (0<=index<32) to sign bit
  2692. */
  2693. static s32 sign_extend(u32 oper, int index)
  2694. {
  2695. u8 shift = 31 - index;
  2696. return (s32)(oper << shift) >> shift;
  2697. }
  2698. /**
  2699. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  2700. * @statistics: Provides the temperature reading from the uCode
  2701. *
  2702. * A return of <0 indicates bogus data in the statistics
  2703. */
  2704. int iwl4965_get_temperature(const struct iwl_priv *priv)
  2705. {
  2706. s32 temperature;
  2707. s32 vt;
  2708. s32 R1, R2, R3;
  2709. u32 R4;
  2710. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  2711. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  2712. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  2713. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  2714. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  2715. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  2716. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  2717. } else {
  2718. IWL_DEBUG_TEMP("Running temperature calibration\n");
  2719. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  2720. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  2721. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  2722. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  2723. }
  2724. /*
  2725. * Temperature is only 23 bits, so sign extend out to 32.
  2726. *
  2727. * NOTE If we haven't received a statistics notification yet
  2728. * with an updated temperature, use R4 provided to us in the
  2729. * "initialize" ALIVE response.
  2730. */
  2731. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  2732. vt = sign_extend(R4, 23);
  2733. else
  2734. vt = sign_extend(
  2735. le32_to_cpu(priv->statistics.general.temperature), 23);
  2736. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  2737. R1, R2, R3, vt);
  2738. if (R3 == R1) {
  2739. IWL_ERROR("Calibration conflict R1 == R3\n");
  2740. return -1;
  2741. }
  2742. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  2743. * Add offset to center the adjustment around 0 degrees Centigrade. */
  2744. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  2745. temperature /= (R3 - R1);
  2746. temperature = (temperature * 97) / 100 +
  2747. TEMPERATURE_CALIB_KELVIN_OFFSET;
  2748. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  2749. KELVIN_TO_CELSIUS(temperature));
  2750. return temperature;
  2751. }
  2752. /* Adjust Txpower only if temperature variance is greater than threshold. */
  2753. #define IWL_TEMPERATURE_THRESHOLD 3
  2754. /**
  2755. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  2756. *
  2757. * If the temperature changed has changed sufficiently, then a recalibration
  2758. * is needed.
  2759. *
  2760. * Assumes caller will replace priv->last_temperature once calibration
  2761. * executed.
  2762. */
  2763. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  2764. {
  2765. int temp_diff;
  2766. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  2767. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  2768. return 0;
  2769. }
  2770. temp_diff = priv->temperature - priv->last_temperature;
  2771. /* get absolute value */
  2772. if (temp_diff < 0) {
  2773. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  2774. temp_diff = -temp_diff;
  2775. } else if (temp_diff == 0)
  2776. IWL_DEBUG_POWER("Same temp, \n");
  2777. else
  2778. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  2779. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  2780. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  2781. return 0;
  2782. }
  2783. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  2784. return 1;
  2785. }
  2786. /* Calculate noise level, based on measurements during network silence just
  2787. * before arriving beacon. This measurement can be done only if we know
  2788. * exactly when to expect beacons, therefore only when we're associated. */
  2789. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  2790. {
  2791. struct statistics_rx_non_phy *rx_info
  2792. = &(priv->statistics.rx.general);
  2793. int num_active_rx = 0;
  2794. int total_silence = 0;
  2795. int bcn_silence_a =
  2796. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  2797. int bcn_silence_b =
  2798. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  2799. int bcn_silence_c =
  2800. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  2801. if (bcn_silence_a) {
  2802. total_silence += bcn_silence_a;
  2803. num_active_rx++;
  2804. }
  2805. if (bcn_silence_b) {
  2806. total_silence += bcn_silence_b;
  2807. num_active_rx++;
  2808. }
  2809. if (bcn_silence_c) {
  2810. total_silence += bcn_silence_c;
  2811. num_active_rx++;
  2812. }
  2813. /* Average among active antennas */
  2814. if (num_active_rx)
  2815. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  2816. else
  2817. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2818. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  2819. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  2820. priv->last_rx_noise);
  2821. }
  2822. void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
  2823. {
  2824. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  2825. int change;
  2826. s32 temp;
  2827. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  2828. (int)sizeof(priv->statistics), pkt->len);
  2829. change = ((priv->statistics.general.temperature !=
  2830. pkt->u.stats.general.temperature) ||
  2831. ((priv->statistics.flag &
  2832. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  2833. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  2834. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  2835. set_bit(STATUS_STATISTICS, &priv->status);
  2836. /* Reschedule the statistics timer to occur in
  2837. * REG_RECALIB_PERIOD seconds to ensure we get a
  2838. * thermal update even if the uCode doesn't give
  2839. * us one */
  2840. mod_timer(&priv->statistics_periodic, jiffies +
  2841. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  2842. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2843. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  2844. iwl4965_rx_calc_noise(priv);
  2845. #ifdef CONFIG_IWL4965_SENSITIVITY
  2846. queue_work(priv->workqueue, &priv->sensitivity_work);
  2847. #endif
  2848. }
  2849. iwl_leds_background(priv);
  2850. /* If the hardware hasn't reported a change in
  2851. * temperature then don't bother computing a
  2852. * calibrated temperature value */
  2853. if (!change)
  2854. return;
  2855. temp = iwl4965_get_temperature(priv);
  2856. if (temp < 0)
  2857. return;
  2858. if (priv->temperature != temp) {
  2859. if (priv->temperature)
  2860. IWL_DEBUG_TEMP("Temperature changed "
  2861. "from %dC to %dC\n",
  2862. KELVIN_TO_CELSIUS(priv->temperature),
  2863. KELVIN_TO_CELSIUS(temp));
  2864. else
  2865. IWL_DEBUG_TEMP("Temperature "
  2866. "initialized to %dC\n",
  2867. KELVIN_TO_CELSIUS(temp));
  2868. }
  2869. priv->temperature = temp;
  2870. set_bit(STATUS_TEMPERATURE, &priv->status);
  2871. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2872. iwl4965_is_temp_calib_needed(priv))
  2873. queue_work(priv->workqueue, &priv->txpower_work);
  2874. }
  2875. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  2876. struct sk_buff *skb,
  2877. struct iwl4965_rx_phy_res *rx_start,
  2878. struct ieee80211_rx_status *stats,
  2879. u32 ampdu_status)
  2880. {
  2881. s8 signal = stats->ssi;
  2882. s8 noise = 0;
  2883. int rate = stats->rate_idx;
  2884. u64 tsf = stats->mactime;
  2885. __le16 antenna;
  2886. __le16 phy_flags_hw = rx_start->phy_flags;
  2887. struct iwl4965_rt_rx_hdr {
  2888. struct ieee80211_radiotap_header rt_hdr;
  2889. __le64 rt_tsf; /* TSF */
  2890. u8 rt_flags; /* radiotap packet flags */
  2891. u8 rt_rate; /* rate in 500kb/s */
  2892. __le16 rt_channelMHz; /* channel in MHz */
  2893. __le16 rt_chbitmask; /* channel bitfield */
  2894. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  2895. s8 rt_dbmnoise;
  2896. u8 rt_antenna; /* antenna number */
  2897. } __attribute__ ((packed)) *iwl4965_rt;
  2898. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  2899. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  2900. if (net_ratelimit())
  2901. printk(KERN_ERR "not enough headroom [%d] for "
  2902. "radiotap head [%zd]\n",
  2903. skb_headroom(skb), sizeof(*iwl4965_rt));
  2904. return;
  2905. }
  2906. /* put radiotap header in front of 802.11 header and data */
  2907. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  2908. /* initialise radiotap header */
  2909. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2910. iwl4965_rt->rt_hdr.it_pad = 0;
  2911. /* total header + data */
  2912. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  2913. &iwl4965_rt->rt_hdr.it_len);
  2914. /* Indicate all the fields we add to the radiotap header */
  2915. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2916. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2917. (1 << IEEE80211_RADIOTAP_RATE) |
  2918. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2919. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2920. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2921. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  2922. &iwl4965_rt->rt_hdr.it_present);
  2923. /* Zero the flags, we'll add to them as we go */
  2924. iwl4965_rt->rt_flags = 0;
  2925. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  2926. iwl4965_rt->rt_dbmsignal = signal;
  2927. iwl4965_rt->rt_dbmnoise = noise;
  2928. /* Convert the channel frequency and set the flags */
  2929. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  2930. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2931. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2932. IEEE80211_CHAN_5GHZ),
  2933. &iwl4965_rt->rt_chbitmask);
  2934. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2935. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  2936. IEEE80211_CHAN_2GHZ),
  2937. &iwl4965_rt->rt_chbitmask);
  2938. else /* 802.11g */
  2939. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2940. IEEE80211_CHAN_2GHZ),
  2941. &iwl4965_rt->rt_chbitmask);
  2942. if (rate == -1)
  2943. iwl4965_rt->rt_rate = 0;
  2944. else
  2945. iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
  2946. /*
  2947. * "antenna number"
  2948. *
  2949. * It seems that the antenna field in the phy flags value
  2950. * is actually a bitfield. This is undefined by radiotap,
  2951. * it wants an actual antenna number but I always get "7"
  2952. * for most legacy frames I receive indicating that the
  2953. * same frame was received on all three RX chains.
  2954. *
  2955. * I think this field should be removed in favour of a
  2956. * new 802.11n radiotap field "RX chains" that is defined
  2957. * as a bitmask.
  2958. */
  2959. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  2960. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  2961. /* set the preamble flag if appropriate */
  2962. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2963. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2964. stats->flag |= RX_FLAG_RADIOTAP;
  2965. }
  2966. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  2967. {
  2968. /* 0 - mgmt, 1 - cnt, 2 - data */
  2969. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  2970. priv->rx_stats[idx].cnt++;
  2971. priv->rx_stats[idx].bytes += len;
  2972. }
  2973. static u32 iwl4965_translate_rx_status(u32 decrypt_in)
  2974. {
  2975. u32 decrypt_out = 0;
  2976. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  2977. RX_RES_STATUS_STATION_FOUND)
  2978. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  2979. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  2980. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  2981. /* packet was not encrypted */
  2982. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2983. RX_RES_STATUS_SEC_TYPE_NONE)
  2984. return decrypt_out;
  2985. /* packet was encrypted with unknown alg */
  2986. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2987. RX_RES_STATUS_SEC_TYPE_ERR)
  2988. return decrypt_out;
  2989. /* decryption was not done in HW */
  2990. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  2991. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  2992. return decrypt_out;
  2993. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  2994. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2995. /* alg is CCM: check MIC only */
  2996. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  2997. /* Bad MIC */
  2998. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2999. else
  3000. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  3001. break;
  3002. case RX_RES_STATUS_SEC_TYPE_TKIP:
  3003. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  3004. /* Bad TTAK */
  3005. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  3006. break;
  3007. }
  3008. /* fall through if TTAK OK */
  3009. default:
  3010. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  3011. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  3012. else
  3013. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  3014. break;
  3015. };
  3016. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  3017. decrypt_in, decrypt_out);
  3018. return decrypt_out;
  3019. }
  3020. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  3021. int include_phy,
  3022. struct iwl4965_rx_mem_buffer *rxb,
  3023. struct ieee80211_rx_status *stats)
  3024. {
  3025. struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
  3026. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3027. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  3028. struct ieee80211_hdr *hdr;
  3029. u16 len;
  3030. __le32 *rx_end;
  3031. unsigned int skblen;
  3032. u32 ampdu_status;
  3033. u32 ampdu_status_legacy;
  3034. if (!include_phy && priv->last_phy_res[0])
  3035. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3036. if (!rx_start) {
  3037. IWL_ERROR("MPDU frame without a PHY data\n");
  3038. return;
  3039. }
  3040. if (include_phy) {
  3041. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  3042. rx_start->cfg_phy_cnt);
  3043. len = le16_to_cpu(rx_start->byte_count);
  3044. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  3045. sizeof(struct iwl4965_rx_phy_res) +
  3046. rx_start->cfg_phy_cnt + len);
  3047. } else {
  3048. struct iwl4965_rx_mpdu_res_start *amsdu =
  3049. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3050. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  3051. sizeof(struct iwl4965_rx_mpdu_res_start));
  3052. len = le16_to_cpu(amsdu->byte_count);
  3053. rx_start->byte_count = amsdu->byte_count;
  3054. rx_end = (__le32 *) (((u8 *) hdr) + len);
  3055. }
  3056. if (len > priv->hw_setting.max_pkt_size || len < 16) {
  3057. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  3058. return;
  3059. }
  3060. ampdu_status = le32_to_cpu(*rx_end);
  3061. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  3062. if (!include_phy) {
  3063. /* New status scheme, need to translate */
  3064. ampdu_status_legacy = ampdu_status;
  3065. ampdu_status = iwl4965_translate_rx_status(ampdu_status);
  3066. }
  3067. /* start from MAC */
  3068. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  3069. skb_put(rxb->skb, len); /* end where data ends */
  3070. /* We only process data packets if the interface is open */
  3071. if (unlikely(!priv->is_open)) {
  3072. IWL_DEBUG_DROP_LIMIT
  3073. ("Dropping packet while interface is not open.\n");
  3074. return;
  3075. }
  3076. stats->flag = 0;
  3077. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  3078. if (priv->cfg->mod_params->hw_crypto)
  3079. iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
  3080. if (priv->add_radiotap)
  3081. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  3082. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  3083. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  3084. priv->alloc_rxb_skb--;
  3085. rxb->skb = NULL;
  3086. }
  3087. /* Calc max signal level (dBm) among 3 possible receivers */
  3088. static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
  3089. {
  3090. /* data from PHY/DSP regarding signal strength, etc.,
  3091. * contents are always there, not configurable by host. */
  3092. struct iwl4965_rx_non_cfg_phy *ncphy =
  3093. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  3094. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  3095. >> IWL_AGC_DB_POS;
  3096. u32 valid_antennae =
  3097. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  3098. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  3099. u8 max_rssi = 0;
  3100. u32 i;
  3101. /* Find max rssi among 3 possible receivers.
  3102. * These values are measured by the digital signal processor (DSP).
  3103. * They should stay fairly constant even as the signal strength varies,
  3104. * if the radio's automatic gain control (AGC) is working right.
  3105. * AGC value (see below) will provide the "interesting" info. */
  3106. for (i = 0; i < 3; i++)
  3107. if (valid_antennae & (1 << i))
  3108. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  3109. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  3110. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  3111. max_rssi, agc);
  3112. /* dBm = max_rssi dB - agc dB - constant.
  3113. * Higher AGC (higher radio gain) means lower signal. */
  3114. return (max_rssi - agc - IWL_RSSI_OFFSET);
  3115. }
  3116. #ifdef CONFIG_IWL4965_HT
  3117. void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
  3118. struct ieee80211_ht_info *ht_info,
  3119. enum ieee80211_band band)
  3120. {
  3121. ht_info->cap = 0;
  3122. memset(ht_info->supp_mcs_set, 0, 16);
  3123. ht_info->ht_supported = 1;
  3124. if (band == IEEE80211_BAND_5GHZ) {
  3125. ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
  3126. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
  3127. ht_info->supp_mcs_set[4] = 0x01;
  3128. }
  3129. ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
  3130. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
  3131. ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
  3132. (IWL_MIMO_PS_NONE << 2));
  3133. if (priv->cfg->mod_params->amsdu_size_8K)
  3134. ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
  3135. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  3136. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  3137. ht_info->supp_mcs_set[0] = 0xFF;
  3138. ht_info->supp_mcs_set[1] = 0xFF;
  3139. }
  3140. #endif /* CONFIG_IWL4965_HT */
  3141. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  3142. {
  3143. unsigned long flags;
  3144. spin_lock_irqsave(&priv->sta_lock, flags);
  3145. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  3146. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  3147. priv->stations[sta_id].sta.sta.modify_mask = 0;
  3148. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3149. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3150. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3151. }
  3152. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  3153. {
  3154. /* FIXME: need locking over ps_status ??? */
  3155. u8 sta_id = iwl4965_hw_find_station(priv, addr);
  3156. if (sta_id != IWL_INVALID_STATION) {
  3157. u8 sta_awake = priv->stations[sta_id].
  3158. ps_status == STA_PS_STATUS_WAKE;
  3159. if (sta_awake && ps_bit)
  3160. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  3161. else if (!sta_awake && !ps_bit) {
  3162. iwl4965_sta_modify_ps_wake(priv, sta_id);
  3163. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  3164. }
  3165. }
  3166. }
  3167. #ifdef CONFIG_IWLWIFI_DEBUG
  3168. /**
  3169. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  3170. *
  3171. * You may hack this function to show different aspects of received frames,
  3172. * including selective frame dumps.
  3173. * group100 parameter selects whether to show 1 out of 100 good frames.
  3174. *
  3175. * TODO: This was originally written for 3945, need to audit for
  3176. * proper operation with 4965.
  3177. */
  3178. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  3179. struct iwl4965_rx_packet *pkt,
  3180. struct ieee80211_hdr *header, int group100)
  3181. {
  3182. u32 to_us;
  3183. u32 print_summary = 0;
  3184. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  3185. u32 hundred = 0;
  3186. u32 dataframe = 0;
  3187. u16 fc;
  3188. u16 seq_ctl;
  3189. u16 channel;
  3190. u16 phy_flags;
  3191. int rate_sym;
  3192. u16 length;
  3193. u16 status;
  3194. u16 bcn_tmr;
  3195. u32 tsf_low;
  3196. u64 tsf;
  3197. u8 rssi;
  3198. u8 agc;
  3199. u16 sig_avg;
  3200. u16 noise_diff;
  3201. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  3202. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  3203. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  3204. u8 *data = IWL_RX_DATA(pkt);
  3205. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  3206. return;
  3207. /* MAC header */
  3208. fc = le16_to_cpu(header->frame_control);
  3209. seq_ctl = le16_to_cpu(header->seq_ctrl);
  3210. /* metadata */
  3211. channel = le16_to_cpu(rx_hdr->channel);
  3212. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  3213. rate_sym = rx_hdr->rate;
  3214. length = le16_to_cpu(rx_hdr->len);
  3215. /* end-of-frame status and timestamp */
  3216. status = le32_to_cpu(rx_end->status);
  3217. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  3218. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  3219. tsf = le64_to_cpu(rx_end->timestamp);
  3220. /* signal statistics */
  3221. rssi = rx_stats->rssi;
  3222. agc = rx_stats->agc;
  3223. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  3224. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  3225. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  3226. /* if data frame is to us and all is good,
  3227. * (optionally) print summary for only 1 out of every 100 */
  3228. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  3229. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  3230. dataframe = 1;
  3231. if (!group100)
  3232. print_summary = 1; /* print each frame */
  3233. else if (priv->framecnt_to_us < 100) {
  3234. priv->framecnt_to_us++;
  3235. print_summary = 0;
  3236. } else {
  3237. priv->framecnt_to_us = 0;
  3238. print_summary = 1;
  3239. hundred = 1;
  3240. }
  3241. } else {
  3242. /* print summary for all other frames */
  3243. print_summary = 1;
  3244. }
  3245. if (print_summary) {
  3246. char *title;
  3247. int rate_idx;
  3248. u32 bitrate;
  3249. if (hundred)
  3250. title = "100Frames";
  3251. else if (fc & IEEE80211_FCTL_RETRY)
  3252. title = "Retry";
  3253. else if (ieee80211_is_assoc_response(fc))
  3254. title = "AscRsp";
  3255. else if (ieee80211_is_reassoc_response(fc))
  3256. title = "RasRsp";
  3257. else if (ieee80211_is_probe_response(fc)) {
  3258. title = "PrbRsp";
  3259. print_dump = 1; /* dump frame contents */
  3260. } else if (ieee80211_is_beacon(fc)) {
  3261. title = "Beacon";
  3262. print_dump = 1; /* dump frame contents */
  3263. } else if (ieee80211_is_atim(fc))
  3264. title = "ATIM";
  3265. else if (ieee80211_is_auth(fc))
  3266. title = "Auth";
  3267. else if (ieee80211_is_deauth(fc))
  3268. title = "DeAuth";
  3269. else if (ieee80211_is_disassoc(fc))
  3270. title = "DisAssoc";
  3271. else
  3272. title = "Frame";
  3273. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  3274. if (unlikely(rate_idx == -1))
  3275. bitrate = 0;
  3276. else
  3277. bitrate = iwl4965_rates[rate_idx].ieee / 2;
  3278. /* print frame summary.
  3279. * MAC addresses show just the last byte (for brevity),
  3280. * but you can hack it to show more, if you'd like to. */
  3281. if (dataframe)
  3282. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  3283. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  3284. title, fc, header->addr1[5],
  3285. length, rssi, channel, bitrate);
  3286. else {
  3287. /* src/dst addresses assume managed mode */
  3288. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  3289. "src=0x%02x, rssi=%u, tim=%lu usec, "
  3290. "phy=0x%02x, chnl=%d\n",
  3291. title, fc, header->addr1[5],
  3292. header->addr3[5], rssi,
  3293. tsf_low - priv->scan_start_tsf,
  3294. phy_flags, channel);
  3295. }
  3296. }
  3297. if (print_dump)
  3298. iwl_print_hex_dump(IWL_DL_RX, data, length);
  3299. }
  3300. #else
  3301. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  3302. struct iwl4965_rx_packet *pkt,
  3303. struct ieee80211_hdr *header,
  3304. int group100)
  3305. {
  3306. }
  3307. #endif
  3308. /* Called for REPLY_RX (legacy ABG frames), or
  3309. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  3310. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  3311. struct iwl4965_rx_mem_buffer *rxb)
  3312. {
  3313. struct ieee80211_hdr *header;
  3314. struct ieee80211_rx_status rx_status;
  3315. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3316. /* Use phy data (Rx signal strength, etc.) contained within
  3317. * this rx packet for legacy frames,
  3318. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  3319. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  3320. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3321. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  3322. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3323. __le32 *rx_end;
  3324. unsigned int len = 0;
  3325. u16 fc;
  3326. u8 network_packet;
  3327. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  3328. rx_status.freq =
  3329. ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
  3330. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  3331. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  3332. rx_status.rate_idx =
  3333. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  3334. if (rx_status.band == IEEE80211_BAND_5GHZ)
  3335. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  3336. rx_status.antenna = 0;
  3337. rx_status.flag = 0;
  3338. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  3339. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  3340. rx_start->cfg_phy_cnt);
  3341. return;
  3342. }
  3343. if (!include_phy) {
  3344. if (priv->last_phy_res[0])
  3345. rx_start = (struct iwl4965_rx_phy_res *)
  3346. &priv->last_phy_res[1];
  3347. else
  3348. rx_start = NULL;
  3349. }
  3350. if (!rx_start) {
  3351. IWL_ERROR("MPDU frame without a PHY data\n");
  3352. return;
  3353. }
  3354. if (include_phy) {
  3355. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  3356. + rx_start->cfg_phy_cnt);
  3357. len = le16_to_cpu(rx_start->byte_count);
  3358. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  3359. sizeof(struct iwl4965_rx_phy_res) + len);
  3360. } else {
  3361. struct iwl4965_rx_mpdu_res_start *amsdu =
  3362. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3363. header = (void *)(pkt->u.raw +
  3364. sizeof(struct iwl4965_rx_mpdu_res_start));
  3365. len = le16_to_cpu(amsdu->byte_count);
  3366. rx_end = (__le32 *) (pkt->u.raw +
  3367. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  3368. }
  3369. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  3370. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  3371. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  3372. le32_to_cpu(*rx_end));
  3373. return;
  3374. }
  3375. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  3376. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  3377. rx_status.ssi = iwl4965_calc_rssi(rx_start);
  3378. /* Meaningful noise values are available only from beacon statistics,
  3379. * which are gathered only when associated, and indicate noise
  3380. * only for the associated network channel ...
  3381. * Ignore these noise values while scanning (other channels) */
  3382. if (iwl_is_associated(priv) &&
  3383. !test_bit(STATUS_SCANNING, &priv->status)) {
  3384. rx_status.noise = priv->last_rx_noise;
  3385. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
  3386. rx_status.noise);
  3387. } else {
  3388. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3389. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
  3390. }
  3391. /* Reset beacon noise level if not associated. */
  3392. if (!iwl_is_associated(priv))
  3393. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3394. /* Set "1" to report good data frames in groups of 100 */
  3395. /* FIXME: need to optimze the call: */
  3396. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  3397. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  3398. rx_status.ssi, rx_status.noise, rx_status.signal,
  3399. (unsigned long long)rx_status.mactime);
  3400. network_packet = iwl4965_is_network_packet(priv, header);
  3401. if (network_packet) {
  3402. priv->last_rx_rssi = rx_status.ssi;
  3403. priv->last_beacon_time = priv->ucode_beacon_time;
  3404. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  3405. }
  3406. fc = le16_to_cpu(header->frame_control);
  3407. switch (fc & IEEE80211_FCTL_FTYPE) {
  3408. case IEEE80211_FTYPE_MGMT:
  3409. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3410. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3411. header->addr2);
  3412. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  3413. break;
  3414. case IEEE80211_FTYPE_CTL:
  3415. #ifdef CONFIG_IWL4965_HT
  3416. switch (fc & IEEE80211_FCTL_STYPE) {
  3417. case IEEE80211_STYPE_BACK_REQ:
  3418. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  3419. iwl4965_handle_data_packet(priv, 0, include_phy,
  3420. rxb, &rx_status);
  3421. break;
  3422. default:
  3423. break;
  3424. }
  3425. #endif
  3426. break;
  3427. case IEEE80211_FTYPE_DATA: {
  3428. DECLARE_MAC_BUF(mac1);
  3429. DECLARE_MAC_BUF(mac2);
  3430. DECLARE_MAC_BUF(mac3);
  3431. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3432. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3433. header->addr2);
  3434. if (unlikely(!network_packet))
  3435. IWL_DEBUG_DROP("Dropping (non network): "
  3436. "%s, %s, %s\n",
  3437. print_mac(mac1, header->addr1),
  3438. print_mac(mac2, header->addr2),
  3439. print_mac(mac3, header->addr3));
  3440. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  3441. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  3442. print_mac(mac1, header->addr1),
  3443. print_mac(mac2, header->addr2),
  3444. print_mac(mac3, header->addr3));
  3445. else
  3446. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  3447. &rx_status);
  3448. break;
  3449. }
  3450. default:
  3451. break;
  3452. }
  3453. }
  3454. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  3455. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  3456. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  3457. struct iwl4965_rx_mem_buffer *rxb)
  3458. {
  3459. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3460. priv->last_phy_res[0] = 1;
  3461. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  3462. sizeof(struct iwl4965_rx_phy_res));
  3463. }
  3464. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  3465. struct iwl4965_rx_mem_buffer *rxb)
  3466. {
  3467. #ifdef CONFIG_IWL4965_SENSITIVITY
  3468. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3469. struct iwl4965_missed_beacon_notif *missed_beacon;
  3470. missed_beacon = &pkt->u.missed_beacon;
  3471. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  3472. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  3473. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  3474. le32_to_cpu(missed_beacon->total_missed_becons),
  3475. le32_to_cpu(missed_beacon->num_recvd_beacons),
  3476. le32_to_cpu(missed_beacon->num_expected_beacons));
  3477. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  3478. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
  3479. queue_work(priv->workqueue, &priv->sensitivity_work);
  3480. }
  3481. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  3482. }
  3483. #ifdef CONFIG_IWL4965_HT
  3484. /**
  3485. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  3486. */
  3487. static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  3488. int sta_id, int tid)
  3489. {
  3490. unsigned long flags;
  3491. /* Remove "disable" flag, to enable Tx for this TID */
  3492. spin_lock_irqsave(&priv->sta_lock, flags);
  3493. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  3494. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  3495. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3496. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3497. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3498. }
  3499. /**
  3500. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  3501. *
  3502. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  3503. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  3504. */
  3505. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  3506. struct iwl4965_ht_agg *agg,
  3507. struct iwl4965_compressed_ba_resp*
  3508. ba_resp)
  3509. {
  3510. int i, sh, ack;
  3511. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  3512. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3513. u64 bitmap;
  3514. int successes = 0;
  3515. struct ieee80211_tx_status *tx_status;
  3516. if (unlikely(!agg->wait_for_ba)) {
  3517. IWL_ERROR("Received BA when not expected\n");
  3518. return -EINVAL;
  3519. }
  3520. /* Mark that the expected block-ack response arrived */
  3521. agg->wait_for_ba = 0;
  3522. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  3523. /* Calculate shift to align block-ack bits with our Tx window bits */
  3524. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  3525. if (sh < 0) /* tbw something is wrong with indices */
  3526. sh += 0x100;
  3527. /* don't use 64-bit values for now */
  3528. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  3529. if (agg->frame_count > (64 - sh)) {
  3530. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  3531. return -1;
  3532. }
  3533. /* check for success or failure according to the
  3534. * transmitted bitmap and block-ack bitmap */
  3535. bitmap &= agg->bitmap;
  3536. /* For each frame attempted in aggregation,
  3537. * update driver's record of tx frame's status. */
  3538. for (i = 0; i < agg->frame_count ; i++) {
  3539. ack = bitmap & (1 << i);
  3540. successes += !!ack;
  3541. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  3542. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  3543. agg->start_idx + i);
  3544. }
  3545. tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
  3546. tx_status->flags = IEEE80211_TX_STATUS_ACK;
  3547. tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
  3548. tx_status->ampdu_ack_map = successes;
  3549. tx_status->ampdu_ack_len = agg->frame_count;
  3550. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
  3551. &tx_status->control);
  3552. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  3553. return 0;
  3554. }
  3555. /**
  3556. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  3557. */
  3558. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  3559. u16 txq_id)
  3560. {
  3561. /* Simply stop the queue, but don't change any configuration;
  3562. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  3563. iwl_write_prph(priv,
  3564. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  3565. (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  3566. (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  3567. }
  3568. /**
  3569. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3570. * priv->lock must be held by the caller
  3571. */
  3572. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  3573. u16 ssn_idx, u8 tx_fifo)
  3574. {
  3575. int ret = 0;
  3576. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  3577. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3578. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3579. return -EINVAL;
  3580. }
  3581. ret = iwl_grab_nic_access(priv);
  3582. if (ret)
  3583. return ret;
  3584. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3585. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3586. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3587. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3588. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3589. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3590. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  3591. iwl4965_txq_ctx_deactivate(priv, txq_id);
  3592. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  3593. iwl_release_nic_access(priv);
  3594. return 0;
  3595. }
  3596. int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
  3597. u8 tid, int txq_id)
  3598. {
  3599. struct iwl4965_queue *q = &priv->txq[txq_id].q;
  3600. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  3601. struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  3602. switch (priv->stations[sta_id].tid[tid].agg.state) {
  3603. case IWL_EMPTYING_HW_QUEUE_DELBA:
  3604. /* We are reclaiming the last packet of the */
  3605. /* aggregated HW queue */
  3606. if (txq_id == tid_data->agg.txq_id &&
  3607. q->read_ptr == q->write_ptr) {
  3608. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  3609. int tx_fifo = default_tid_to_tx_fifo[tid];
  3610. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  3611. iwl4965_tx_queue_agg_disable(priv, txq_id,
  3612. ssn, tx_fifo);
  3613. tid_data->agg.state = IWL_AGG_OFF;
  3614. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3615. }
  3616. break;
  3617. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  3618. /* We are reclaiming the last packet of the queue */
  3619. if (tid_data->tfds_in_queue == 0) {
  3620. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  3621. tid_data->agg.state = IWL_AGG_ON;
  3622. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3623. }
  3624. break;
  3625. }
  3626. return 0;
  3627. }
  3628. /**
  3629. * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
  3630. * @index -- current index
  3631. * @n_bd -- total number of entries in queue (s/b power of 2)
  3632. */
  3633. static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
  3634. {
  3635. return (index == 0) ? n_bd - 1 : index - 1;
  3636. }
  3637. /**
  3638. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  3639. *
  3640. * Handles block-acknowledge notification from device, which reports success
  3641. * of frames sent via aggregation.
  3642. */
  3643. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  3644. struct iwl4965_rx_mem_buffer *rxb)
  3645. {
  3646. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3647. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  3648. int index;
  3649. struct iwl4965_tx_queue *txq = NULL;
  3650. struct iwl4965_ht_agg *agg;
  3651. DECLARE_MAC_BUF(mac);
  3652. /* "flow" corresponds to Tx queue */
  3653. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3654. /* "ssn" is start of block-ack Tx window, corresponds to index
  3655. * (in Tx queue's circular buffer) of first TFD/frame in window */
  3656. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  3657. if (scd_flow >= ARRAY_SIZE(priv->txq)) {
  3658. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  3659. return;
  3660. }
  3661. txq = &priv->txq[scd_flow];
  3662. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  3663. /* Find index just before block-ack window */
  3664. index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  3665. /* TODO: Need to get this copy more safely - now good for debug */
  3666. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  3667. "sta_id = %d\n",
  3668. agg->wait_for_ba,
  3669. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  3670. ba_resp->sta_id);
  3671. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  3672. "%d, scd_ssn = %d\n",
  3673. ba_resp->tid,
  3674. ba_resp->seq_ctl,
  3675. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  3676. ba_resp->scd_flow,
  3677. ba_resp->scd_ssn);
  3678. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  3679. agg->start_idx,
  3680. (unsigned long long)agg->bitmap);
  3681. /* Update driver's record of ACK vs. not for each frame in window */
  3682. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  3683. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  3684. * block-ack window (we assume that they've been successfully
  3685. * transmitted ... if not, it's too late anyway). */
  3686. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  3687. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  3688. priv->stations[ba_resp->sta_id].
  3689. tid[ba_resp->tid].tfds_in_queue -= freed;
  3690. if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
  3691. priv->mac80211_registered &&
  3692. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  3693. ieee80211_wake_queue(priv->hw, scd_flow);
  3694. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  3695. ba_resp->tid, scd_flow);
  3696. }
  3697. }
  3698. /**
  3699. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  3700. */
  3701. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  3702. u16 txq_id)
  3703. {
  3704. u32 tbl_dw_addr;
  3705. u32 tbl_dw;
  3706. u16 scd_q2ratid;
  3707. scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  3708. tbl_dw_addr = priv->scd_base_addr +
  3709. SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  3710. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  3711. if (txq_id & 0x1)
  3712. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  3713. else
  3714. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  3715. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  3716. return 0;
  3717. }
  3718. /**
  3719. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  3720. *
  3721. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  3722. * i.e. it must be one of the higher queues used for aggregation
  3723. */
  3724. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  3725. int tx_fifo, int sta_id, int tid,
  3726. u16 ssn_idx)
  3727. {
  3728. unsigned long flags;
  3729. int rc;
  3730. u16 ra_tid;
  3731. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  3732. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3733. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3734. ra_tid = BUILD_RAxTID(sta_id, tid);
  3735. /* Modify device's station table to Tx this TID */
  3736. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  3737. spin_lock_irqsave(&priv->lock, flags);
  3738. rc = iwl_grab_nic_access(priv);
  3739. if (rc) {
  3740. spin_unlock_irqrestore(&priv->lock, flags);
  3741. return rc;
  3742. }
  3743. /* Stop this Tx queue before configuring it */
  3744. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3745. /* Map receiver-address / traffic-ID to this queue */
  3746. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  3747. /* Set this queue as a chain-building queue */
  3748. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3749. /* Place first TFD at index corresponding to start sequence number.
  3750. * Assumes that ssn_idx is valid (!= 0xFFF) */
  3751. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3752. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3753. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3754. /* Set up Tx window size and frame limit for this queue */
  3755. iwl_write_targ_mem(priv,
  3756. priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  3757. (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  3758. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  3759. iwl_write_targ_mem(priv, priv->scd_base_addr +
  3760. SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  3761. (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  3762. & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  3763. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  3764. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  3765. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  3766. iwl_release_nic_access(priv);
  3767. spin_unlock_irqrestore(&priv->lock, flags);
  3768. return 0;
  3769. }
  3770. #endif /* CONFIG_IWL4965_HT */
  3771. /**
  3772. * iwl4965_add_station - Initialize a station's hardware rate table
  3773. *
  3774. * The uCode's station table contains a table of fallback rates
  3775. * for automatic fallback during transmission.
  3776. *
  3777. * NOTE: This sets up a default set of values. These will be replaced later
  3778. * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
  3779. * rc80211_simple.
  3780. *
  3781. * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
  3782. * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
  3783. * which requires station table entry to exist).
  3784. */
  3785. void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  3786. {
  3787. int i, r;
  3788. struct iwl4965_link_quality_cmd link_cmd = {
  3789. .reserved1 = 0,
  3790. };
  3791. u16 rate_flags;
  3792. /* Set up the rate scaling to start at selected rate, fall back
  3793. * all the way down to 1M in IEEE order, and then spin on 1M */
  3794. if (is_ap)
  3795. r = IWL_RATE_54M_INDEX;
  3796. else if (priv->band == IEEE80211_BAND_5GHZ)
  3797. r = IWL_RATE_6M_INDEX;
  3798. else
  3799. r = IWL_RATE_1M_INDEX;
  3800. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  3801. rate_flags = 0;
  3802. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  3803. rate_flags |= RATE_MCS_CCK_MSK;
  3804. /* Use Tx antenna B only */
  3805. rate_flags |= RATE_MCS_ANT_B_MSK;
  3806. rate_flags &= ~RATE_MCS_ANT_A_MSK;
  3807. link_cmd.rs_table[i].rate_n_flags =
  3808. iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
  3809. r = iwl4965_get_prev_ieee_rate(r);
  3810. }
  3811. link_cmd.general_params.single_stream_ant_msk = 2;
  3812. link_cmd.general_params.dual_stream_ant_msk = 3;
  3813. link_cmd.agg_params.agg_dis_start_th = 3;
  3814. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  3815. /* Update the rate scaling for control frame Tx to AP */
  3816. link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
  3817. iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
  3818. sizeof(link_cmd), &link_cmd, NULL);
  3819. }
  3820. #ifdef CONFIG_IWL4965_HT
  3821. static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
  3822. enum ieee80211_band band,
  3823. u16 channel, u8 extension_chan_offset)
  3824. {
  3825. const struct iwl_channel_info *ch_info;
  3826. ch_info = iwl_get_channel_info(priv, band, channel);
  3827. if (!is_channel_valid(ch_info))
  3828. return 0;
  3829. if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
  3830. return 0;
  3831. if ((ch_info->fat_extension_channel == extension_chan_offset) ||
  3832. (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
  3833. return 1;
  3834. return 0;
  3835. }
  3836. static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
  3837. struct ieee80211_ht_info *sta_ht_inf)
  3838. {
  3839. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  3840. if ((!iwl_ht_conf->is_ht) ||
  3841. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
  3842. (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
  3843. return 0;
  3844. if (sta_ht_inf) {
  3845. if ((!sta_ht_inf->ht_supported) ||
  3846. (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
  3847. return 0;
  3848. }
  3849. return (iwl4965_is_channel_extension(priv, priv->band,
  3850. iwl_ht_conf->control_channel,
  3851. iwl_ht_conf->extension_chan_offset));
  3852. }
  3853. void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
  3854. {
  3855. struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
  3856. u32 val;
  3857. if (!ht_info->is_ht)
  3858. return;
  3859. /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
  3860. if (iwl4965_is_fat_tx_allowed(priv, NULL))
  3861. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3862. else
  3863. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  3864. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  3865. if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
  3866. IWL_DEBUG_ASSOC("control diff than current %d %d\n",
  3867. le16_to_cpu(rxon->channel),
  3868. ht_info->control_channel);
  3869. rxon->channel = cpu_to_le16(ht_info->control_channel);
  3870. return;
  3871. }
  3872. /* Note: control channel is opposite of extension channel */
  3873. switch (ht_info->extension_chan_offset) {
  3874. case IWL_EXT_CHANNEL_OFFSET_ABOVE:
  3875. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3876. break;
  3877. case IWL_EXT_CHANNEL_OFFSET_BELOW:
  3878. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3879. break;
  3880. case IWL_EXT_CHANNEL_OFFSET_NONE:
  3881. default:
  3882. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3883. break;
  3884. }
  3885. val = ht_info->ht_protection;
  3886. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  3887. iwl4965_set_rxon_chain(priv);
  3888. IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
  3889. "rxon flags 0x%X operation mode :0x%X "
  3890. "extension channel offset 0x%x "
  3891. "control chan %d\n",
  3892. ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
  3893. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  3894. ht_info->extension_chan_offset,
  3895. ht_info->control_channel);
  3896. return;
  3897. }
  3898. void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
  3899. struct ieee80211_ht_info *sta_ht_inf)
  3900. {
  3901. __le32 sta_flags;
  3902. u8 mimo_ps_mode;
  3903. if (!sta_ht_inf || !sta_ht_inf->ht_supported)
  3904. goto done;
  3905. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
  3906. sta_flags = priv->stations[index].sta.station_flags;
  3907. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  3908. switch (mimo_ps_mode) {
  3909. case WLAN_HT_CAP_MIMO_PS_STATIC:
  3910. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  3911. break;
  3912. case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
  3913. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  3914. break;
  3915. case WLAN_HT_CAP_MIMO_PS_DISABLED:
  3916. break;
  3917. default:
  3918. IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
  3919. break;
  3920. }
  3921. sta_flags |= cpu_to_le32(
  3922. (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  3923. sta_flags |= cpu_to_le32(
  3924. (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  3925. if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
  3926. sta_flags |= STA_FLG_FAT_EN_MSK;
  3927. else
  3928. sta_flags &= ~STA_FLG_FAT_EN_MSK;
  3929. priv->stations[index].sta.station_flags = sta_flags;
  3930. done:
  3931. return;
  3932. }
  3933. static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
  3934. int sta_id, int tid, u16 ssn)
  3935. {
  3936. unsigned long flags;
  3937. spin_lock_irqsave(&priv->sta_lock, flags);
  3938. priv->stations[sta_id].sta.station_flags_msk = 0;
  3939. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  3940. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  3941. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  3942. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3943. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3944. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3945. }
  3946. static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
  3947. int sta_id, int tid)
  3948. {
  3949. unsigned long flags;
  3950. spin_lock_irqsave(&priv->sta_lock, flags);
  3951. priv->stations[sta_id].sta.station_flags_msk = 0;
  3952. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  3953. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  3954. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3955. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3956. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3957. }
  3958. /*
  3959. * Find first available (lowest unused) Tx Queue, mark it "active".
  3960. * Called only when finding queue for aggregation.
  3961. * Should never return anything < 7, because they should already
  3962. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  3963. */
  3964. static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
  3965. {
  3966. int txq_id;
  3967. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  3968. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  3969. return txq_id;
  3970. return -1;
  3971. }
  3972. static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
  3973. u16 tid, u16 *start_seq_num)
  3974. {
  3975. struct iwl_priv *priv = hw->priv;
  3976. int sta_id;
  3977. int tx_fifo;
  3978. int txq_id;
  3979. int ssn = -1;
  3980. int ret = 0;
  3981. unsigned long flags;
  3982. struct iwl4965_tid_data *tid_data;
  3983. DECLARE_MAC_BUF(mac);
  3984. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3985. tx_fifo = default_tid_to_tx_fifo[tid];
  3986. else
  3987. return -EINVAL;
  3988. IWL_WARNING("%s on da = %s tid = %d\n",
  3989. __func__, print_mac(mac, da), tid);
  3990. sta_id = iwl4965_hw_find_station(priv, da);
  3991. if (sta_id == IWL_INVALID_STATION)
  3992. return -ENXIO;
  3993. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  3994. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  3995. return -ENXIO;
  3996. }
  3997. txq_id = iwl4965_txq_ctx_activate_free(priv);
  3998. if (txq_id == -1)
  3999. return -ENXIO;
  4000. spin_lock_irqsave(&priv->sta_lock, flags);
  4001. tid_data = &priv->stations[sta_id].tid[tid];
  4002. ssn = SEQ_TO_SN(tid_data->seq_number);
  4003. tid_data->agg.txq_id = txq_id;
  4004. spin_unlock_irqrestore(&priv->sta_lock, flags);
  4005. *start_seq_num = ssn;
  4006. ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  4007. sta_id, tid, ssn);
  4008. if (ret)
  4009. return ret;
  4010. ret = 0;
  4011. if (tid_data->tfds_in_queue == 0) {
  4012. printk(KERN_ERR "HW queue is empty\n");
  4013. tid_data->agg.state = IWL_AGG_ON;
  4014. ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
  4015. } else {
  4016. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  4017. tid_data->tfds_in_queue);
  4018. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  4019. }
  4020. return ret;
  4021. }
  4022. static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
  4023. u16 tid)
  4024. {
  4025. struct iwl_priv *priv = hw->priv;
  4026. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  4027. struct iwl4965_tid_data *tid_data;
  4028. int ret, write_ptr, read_ptr;
  4029. unsigned long flags;
  4030. DECLARE_MAC_BUF(mac);
  4031. if (!da) {
  4032. IWL_ERROR("da = NULL\n");
  4033. return -EINVAL;
  4034. }
  4035. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  4036. tx_fifo_id = default_tid_to_tx_fifo[tid];
  4037. else
  4038. return -EINVAL;
  4039. sta_id = iwl4965_hw_find_station(priv, da);
  4040. if (sta_id == IWL_INVALID_STATION)
  4041. return -ENXIO;
  4042. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  4043. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  4044. tid_data = &priv->stations[sta_id].tid[tid];
  4045. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  4046. txq_id = tid_data->agg.txq_id;
  4047. write_ptr = priv->txq[txq_id].q.write_ptr;
  4048. read_ptr = priv->txq[txq_id].q.read_ptr;
  4049. /* The queue is not empty */
  4050. if (write_ptr != read_ptr) {
  4051. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  4052. priv->stations[sta_id].tid[tid].agg.state =
  4053. IWL_EMPTYING_HW_QUEUE_DELBA;
  4054. return 0;
  4055. }
  4056. IWL_DEBUG_HT("HW queue empty\n");;
  4057. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  4058. spin_lock_irqsave(&priv->lock, flags);
  4059. ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  4060. spin_unlock_irqrestore(&priv->lock, flags);
  4061. if (ret)
  4062. return ret;
  4063. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
  4064. IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
  4065. print_mac(mac, da), tid);
  4066. return 0;
  4067. }
  4068. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  4069. enum ieee80211_ampdu_mlme_action action,
  4070. const u8 *addr, u16 tid, u16 *ssn)
  4071. {
  4072. struct iwl_priv *priv = hw->priv;
  4073. int sta_id;
  4074. DECLARE_MAC_BUF(mac);
  4075. IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
  4076. print_mac(mac, addr), tid);
  4077. sta_id = iwl4965_hw_find_station(priv, addr);
  4078. switch (action) {
  4079. case IEEE80211_AMPDU_RX_START:
  4080. IWL_DEBUG_HT("start Rx\n");
  4081. iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
  4082. break;
  4083. case IEEE80211_AMPDU_RX_STOP:
  4084. IWL_DEBUG_HT("stop Rx\n");
  4085. iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
  4086. break;
  4087. case IEEE80211_AMPDU_TX_START:
  4088. IWL_DEBUG_HT("start Tx\n");
  4089. return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
  4090. case IEEE80211_AMPDU_TX_STOP:
  4091. IWL_DEBUG_HT("stop Tx\n");
  4092. return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
  4093. default:
  4094. IWL_DEBUG_HT("unknown\n");
  4095. return -EINVAL;
  4096. break;
  4097. }
  4098. return 0;
  4099. }
  4100. #endif /* CONFIG_IWL4965_HT */
  4101. /* Set up 4965-specific Rx frame reply handlers */
  4102. void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
  4103. {
  4104. /* Legacy Rx frames */
  4105. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  4106. /* High-throughput (HT) Rx frames */
  4107. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  4108. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  4109. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  4110. iwl4965_rx_missed_beacon_notif;
  4111. #ifdef CONFIG_IWL4965_HT
  4112. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  4113. #endif /* CONFIG_IWL4965_HT */
  4114. }
  4115. void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
  4116. {
  4117. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  4118. INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
  4119. #ifdef CONFIG_IWL4965_SENSITIVITY
  4120. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  4121. #endif
  4122. init_timer(&priv->statistics_periodic);
  4123. priv->statistics_periodic.data = (unsigned long)priv;
  4124. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  4125. }
  4126. void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
  4127. {
  4128. del_timer_sync(&priv->statistics_periodic);
  4129. cancel_delayed_work(&priv->init_alive_start);
  4130. }
  4131. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  4132. .enqueue_hcmd = iwl4965_enqueue_hcmd,
  4133. };
  4134. static struct iwl_lib_ops iwl4965_lib = {
  4135. .init_drv = iwl4965_init_drv,
  4136. .hw_nic_init = iwl4965_hw_nic_init,
  4137. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  4138. .alive_notify = iwl4965_alive_notify,
  4139. .load_ucode = iwl4965_load_bsm,
  4140. .eeprom_ops = {
  4141. .verify_signature = iwlcore_eeprom_verify_signature,
  4142. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  4143. .release_semaphore = iwlcore_eeprom_release_semaphore,
  4144. },
  4145. .radio_kill_sw = iwl4965_radio_kill_sw,
  4146. };
  4147. static struct iwl_ops iwl4965_ops = {
  4148. .lib = &iwl4965_lib,
  4149. .utils = &iwl4965_hcmd_utils,
  4150. };
  4151. static struct iwl_cfg iwl4965_agn_cfg = {
  4152. .name = "4965AGN",
  4153. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  4154. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  4155. .ops = &iwl4965_ops,
  4156. .mod_params = &iwl4965_mod_params,
  4157. };
  4158. struct pci_device_id iwl4965_hw_card_ids[] = {
  4159. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  4160. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  4161. {0}
  4162. };
  4163. MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
  4164. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  4165. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  4166. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  4167. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  4168. module_param_named(hwcrypto, iwl4965_mod_params.hw_crypto, int, 0444);
  4169. MODULE_PARM_DESC(hwcrypto,
  4170. "using hardware crypto engine (default 0 [software])\n");
  4171. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  4172. MODULE_PARM_DESC(debug, "debug output mask");
  4173. module_param_named(
  4174. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  4175. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  4176. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  4177. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  4178. /* QoS */
  4179. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  4180. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  4181. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  4182. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");