pm.c 8.5 KB

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  1. /* linux/arch/arm/plat-s3c/pm.c
  2. *
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2004,2006,2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * S3C common power management (suspend to ram) support.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/suspend.h>
  16. #include <linux/errno.h>
  17. #include <linux/delay.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/io.h>
  20. #include <asm/cacheflush.h>
  21. #include <mach/hardware.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-clock.h>
  24. #include <mach/regs-gpio.h>
  25. #include <mach/regs-mem.h>
  26. #include <mach/regs-irq.h>
  27. #include <asm/irq.h>
  28. #include <plat/pm.h>
  29. #include <plat/pm-core.h>
  30. /* for external use */
  31. unsigned long s3c_pm_flags;
  32. /* Debug code:
  33. *
  34. * This code supports debug output to the low level UARTs for use on
  35. * resume before the console layer is available.
  36. */
  37. #ifdef CONFIG_S3C2410_PM_DEBUG
  38. extern void printascii(const char *);
  39. void s3c_pm_dbg(const char *fmt, ...)
  40. {
  41. va_list va;
  42. char buff[256];
  43. va_start(va, fmt);
  44. vsprintf(buff, fmt, va);
  45. va_end(va);
  46. printascii(buff);
  47. }
  48. static inline void s3c_pm_debug_init(void)
  49. {
  50. /* restart uart clocks so we can use them to output */
  51. s3c_pm_debug_init_uart();
  52. }
  53. #else
  54. #define s3c_pm_debug_init() do { } while(0)
  55. #endif /* CONFIG_S3C2410_PM_DEBUG */
  56. /* Save the UART configurations if we are configured for debug. */
  57. #ifdef CONFIG_S3C2410_PM_DEBUG
  58. struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
  59. static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
  60. {
  61. void __iomem *regs = S3C_VA_UARTx(uart);
  62. save->ulcon = __raw_readl(regs + S3C2410_ULCON);
  63. save->ucon = __raw_readl(regs + S3C2410_UCON);
  64. save->ufcon = __raw_readl(regs + S3C2410_UFCON);
  65. save->umcon = __raw_readl(regs + S3C2410_UMCON);
  66. save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
  67. S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
  68. uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
  69. }
  70. static void s3c_pm_save_uarts(void)
  71. {
  72. struct pm_uart_save *save = uart_save;
  73. unsigned int uart;
  74. for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
  75. s3c_pm_save_uart(uart, save);
  76. }
  77. static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
  78. {
  79. void __iomem *regs = S3C_VA_UARTx(uart);
  80. s3c_pm_arch_update_uart(regs, save);
  81. __raw_writel(save->ulcon, regs + S3C2410_ULCON);
  82. __raw_writel(save->ucon, regs + S3C2410_UCON);
  83. __raw_writel(save->ufcon, regs + S3C2410_UFCON);
  84. __raw_writel(save->umcon, regs + S3C2410_UMCON);
  85. __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
  86. }
  87. static void s3c_pm_restore_uarts(void)
  88. {
  89. struct pm_uart_save *save = uart_save;
  90. unsigned int uart;
  91. for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
  92. s3c_pm_restore_uart(uart, save);
  93. }
  94. #else
  95. static void s3c_pm_save_uarts(void) { }
  96. static void s3c_pm_restore_uarts(void) { }
  97. #endif
  98. /* The IRQ ext-int code goes here, it is too small to currently bother
  99. * with its own file. */
  100. unsigned long s3c_irqwake_intmask = 0xffffffffL;
  101. unsigned long s3c_irqwake_eintmask = 0xffffffffL;
  102. int s3c_irqext_wake(unsigned int irqno, unsigned int state)
  103. {
  104. unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
  105. if (!(s3c_irqwake_eintallow & bit))
  106. return -ENOENT;
  107. printk(KERN_INFO "wake %s for irq %d\n",
  108. state ? "enabled" : "disabled", irqno);
  109. if (!state)
  110. s3c_irqwake_eintmask |= bit;
  111. else
  112. s3c_irqwake_eintmask &= ~bit;
  113. return 0;
  114. }
  115. /* helper functions to save and restore register state */
  116. /**
  117. * s3c_pm_do_save() - save a set of registers for restoration on resume.
  118. * @ptr: Pointer to an array of registers.
  119. * @count: Size of the ptr array.
  120. *
  121. * Run through the list of registers given, saving their contents in the
  122. * array for later restoration when we wakeup.
  123. */
  124. void s3c_pm_do_save(struct sleep_save *ptr, int count)
  125. {
  126. for (; count > 0; count--, ptr++) {
  127. ptr->val = __raw_readl(ptr->reg);
  128. S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
  129. }
  130. }
  131. /**
  132. * s3c_pm_do_restore() - restore register values from the save list.
  133. * @ptr: Pointer to an array of registers.
  134. * @count: Size of the ptr array.
  135. *
  136. * Restore the register values saved from s3c_pm_do_save().
  137. *
  138. * Note, we do not use S3C_PMDBG() in here, as the system may not have
  139. * restore the UARTs state yet
  140. */
  141. void s3c_pm_do_restore(struct sleep_save *ptr, int count)
  142. {
  143. for (; count > 0; count--, ptr++) {
  144. printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
  145. ptr->reg, ptr->val, __raw_readl(ptr->reg));
  146. __raw_writel(ptr->val, ptr->reg);
  147. }
  148. }
  149. /**
  150. * s3c_pm_do_restore_core() - early restore register values from save list.
  151. *
  152. * This is similar to s3c_pm_do_restore() except we try and minimise the
  153. * side effects of the function in case registers that hardware might need
  154. * to work has been restored.
  155. *
  156. * WARNING: Do not put any debug in here that may effect memory or use
  157. * peripherals, as things may be changing!
  158. */
  159. void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
  160. {
  161. for (; count > 0; count--, ptr++)
  162. __raw_writel(ptr->val, ptr->reg);
  163. }
  164. /* s3c2410_pm_show_resume_irqs
  165. *
  166. * print any IRQs asserted at resume time (ie, we woke from)
  167. */
  168. static void s3c_pm_show_resume_irqs(int start, unsigned long which,
  169. unsigned long mask)
  170. {
  171. int i;
  172. which &= ~mask;
  173. for (i = 0; i <= 31; i++) {
  174. if (which & (1L<<i)) {
  175. S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
  176. }
  177. }
  178. }
  179. void (*pm_cpu_prep)(void);
  180. void (*pm_cpu_sleep)(void);
  181. #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
  182. /* s3c_pm_enter
  183. *
  184. * central control for sleep/resume process
  185. */
  186. static int s3c_pm_enter(suspend_state_t state)
  187. {
  188. static unsigned long regs_save[16];
  189. /* ensure the debug is initialised (if enabled) */
  190. s3c_pm_debug_init();
  191. S3C_PMDBG("%s(%d)\n", __func__, state);
  192. if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
  193. printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
  194. return -EINVAL;
  195. }
  196. /* check if we have anything to wake-up with... bad things seem
  197. * to happen if you suspend with no wakeup (system will often
  198. * require a full power-cycle)
  199. */
  200. if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
  201. !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
  202. printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
  203. printk(KERN_ERR "%s: Aborting sleep\n", __func__);
  204. return -EINVAL;
  205. }
  206. /* store the physical address of the register recovery block */
  207. s3c_sleep_save_phys = virt_to_phys(regs_save);
  208. S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
  209. /* save all necessary core registers not covered by the drivers */
  210. s3c_pm_save_gpios();
  211. s3c_pm_save_uarts();
  212. s3c_pm_save_core();
  213. /* set the irq configuration for wake */
  214. s3c_pm_configure_extint();
  215. S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
  216. s3c_irqwake_intmask, s3c_irqwake_eintmask);
  217. s3c_pm_arch_prepare_irqs();
  218. /* call cpu specific preparation */
  219. pm_cpu_prep();
  220. /* flush cache back to ram */
  221. flush_cache_all();
  222. s3c_pm_check_store();
  223. /* send the cpu to sleep... */
  224. s3c_pm_arch_stop_clocks();
  225. /* s3c_cpu_save will also act as our return point from when
  226. * we resume as it saves its own register state and restores it
  227. * during the resume. */
  228. s3c_cpu_save(regs_save);
  229. /* restore the cpu state using the kernel's cpu init code. */
  230. cpu_init();
  231. /* restore the system state */
  232. s3c_pm_restore_core();
  233. s3c_pm_restore_uarts();
  234. s3c_pm_restore_gpios();
  235. s3c_pm_debug_init();
  236. /* check what irq (if any) restored the system */
  237. s3c_pm_arch_show_resume_irqs();
  238. S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
  239. s3c_pm_check_restore();
  240. /* ok, let's return from sleep */
  241. S3C_PMDBG("S3C PM Resume (post-restore)\n");
  242. return 0;
  243. }
  244. /* callback from assembly code */
  245. void s3c_pm_cb_flushcache(void)
  246. {
  247. flush_cache_all();
  248. }
  249. static int s3c_pm_prepare(void)
  250. {
  251. /* prepare check area if configured */
  252. s3c_pm_check_prepare();
  253. return 0;
  254. }
  255. static void s3c_pm_finish(void)
  256. {
  257. s3c_pm_check_cleanup();
  258. }
  259. static struct platform_suspend_ops s3c_pm_ops = {
  260. .enter = s3c_pm_enter,
  261. .prepare = s3c_pm_prepare,
  262. .finish = s3c_pm_finish,
  263. .valid = suspend_valid_only_mem,
  264. };
  265. /* s3c_pm_init
  266. *
  267. * Attach the power management functions. This should be called
  268. * from the board specific initialisation if the board supports
  269. * it.
  270. */
  271. int __init s3c_pm_init(void)
  272. {
  273. printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
  274. suspend_set_ops(&s3c_pm_ops);
  275. return 0;
  276. }