alim15x3.c 14 KB

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  1. /*
  2. * Copyright (C) 1998-2000 Michel Aubry, Maintainer
  3. * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
  4. * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
  5. *
  6. * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
  7. * May be copied or modified under the terms of the GNU General Public License
  8. * Copyright (C) 2002 Alan Cox
  9. * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
  10. * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
  11. * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
  12. *
  13. * (U)DMA capable version of ali 1533/1543(C), 1535(D)
  14. *
  15. **********************************************************************
  16. * 9/7/99 --Parts from the above author are included and need to be
  17. * converted into standard interface, once I finish the thought.
  18. *
  19. * Recent changes
  20. * Don't use LBA48 mode on ALi <= 0xC4
  21. * Don't poke 0x79 with a non ALi northbridge
  22. * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
  23. * Allow UDMA6 on revisions > 0xC4
  24. *
  25. * Documentation
  26. * Chipset documentation available under NDA only
  27. *
  28. */
  29. #include <linux/module.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/pci.h>
  33. #include <linux/ide.h>
  34. #include <linux/init.h>
  35. #include <linux/dmi.h>
  36. #include <asm/io.h>
  37. #define DRV_NAME "alim15x3"
  38. /*
  39. * ALi devices are not plug in. Otherwise these static values would
  40. * need to go. They ought to go away anyway
  41. */
  42. static u8 m5229_revision;
  43. static u8 chip_is_1543c_e;
  44. static struct pci_dev *isa_dev;
  45. static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
  46. {
  47. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  48. int pio_fifo = 0x54 + hwif->channel;
  49. u8 fifo;
  50. int shift = 4 * (drive->dn & 1);
  51. pci_read_config_byte(pdev, pio_fifo, &fifo);
  52. fifo &= ~(0x0F << shift);
  53. fifo |= (on << shift);
  54. pci_write_config_byte(pdev, pio_fifo, fifo);
  55. }
  56. /**
  57. * ali_set_pio_mode - set host controller for PIO mode
  58. * @hwif: port
  59. * @drive: drive
  60. *
  61. * Program the controller for the given PIO mode.
  62. */
  63. static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  64. {
  65. struct pci_dev *dev = to_pci_dev(hwif->dev);
  66. ide_drive_t *pair = ide_get_pair_dev(drive);
  67. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  68. unsigned long T = 1000000 / bus_speed; /* PCI clock based */
  69. int port = hwif->channel ? 0x5c : 0x58;
  70. u8 unit = drive->dn & 1;
  71. struct ide_timing t;
  72. ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
  73. if (pair) {
  74. struct ide_timing p;
  75. ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
  76. ide_timing_merge(&p, &t, &t,
  77. IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  78. if (pair->dma_mode) {
  79. ide_timing_compute(pair, pair->dma_mode, &p, T, 1);
  80. ide_timing_merge(&p, &t, &t,
  81. IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  82. }
  83. }
  84. t.setup = clamp_val(t.setup, 1, 8) & 7;
  85. t.act8b = clamp_val(t.act8b, 1, 8) & 7;
  86. t.rec8b = clamp_val(t.rec8b, 1, 16) & 15;
  87. t.active = clamp_val(t.active, 1, 8) & 7;
  88. t.recover = clamp_val(t.recover, 1, 16) & 15;
  89. /*
  90. * PIO mode => ATA FIFO on, ATAPI FIFO off
  91. */
  92. ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00);
  93. pci_write_config_byte(dev, port, t.setup);
  94. pci_write_config_byte(dev, port + 1, (t.act8b << 4) | t.rec8b);
  95. pci_write_config_byte(dev, port + unit + 2,
  96. (t.active << 4) | t.recover);
  97. }
  98. /**
  99. * ali_udma_filter - compute UDMA mask
  100. * @drive: IDE device
  101. *
  102. * Return available UDMA modes.
  103. *
  104. * The actual rules for the ALi are:
  105. * No UDMA on revisions <= 0x20
  106. * Disk only for revisions < 0xC2
  107. * Not WDC drives on M1543C-E (?)
  108. */
  109. static u8 ali_udma_filter(ide_drive_t *drive)
  110. {
  111. if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
  112. if (drive->media != ide_disk)
  113. return 0;
  114. if (chip_is_1543c_e &&
  115. strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
  116. return 0;
  117. }
  118. return drive->hwif->ultra_mask;
  119. }
  120. /**
  121. * ali_set_dma_mode - set host controller for DMA mode
  122. * @hwif: port
  123. * @drive: drive
  124. *
  125. * Configure the hardware for the desired IDE transfer mode.
  126. */
  127. static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  128. {
  129. struct pci_dev *dev = to_pci_dev(hwif->dev);
  130. const u8 speed = drive->dma_mode;
  131. u8 speed1 = speed;
  132. u8 unit = drive->dn & 1;
  133. u8 tmpbyte = 0x00;
  134. int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
  135. if (speed == XFER_UDMA_6)
  136. speed1 = 0x47;
  137. if (speed < XFER_UDMA_0) {
  138. u8 ultra_enable = (unit) ? 0x7f : 0xf7;
  139. /*
  140. * clear "ultra enable" bit
  141. */
  142. pci_read_config_byte(dev, m5229_udma, &tmpbyte);
  143. tmpbyte &= ultra_enable;
  144. pci_write_config_byte(dev, m5229_udma, tmpbyte);
  145. /*
  146. * FIXME: Oh, my... DMA timings are never set.
  147. */
  148. } else {
  149. pci_read_config_byte(dev, m5229_udma, &tmpbyte);
  150. tmpbyte &= (0x0f << ((1-unit) << 2));
  151. /*
  152. * enable ultra dma and set timing
  153. */
  154. tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
  155. pci_write_config_byte(dev, m5229_udma, tmpbyte);
  156. if (speed >= XFER_UDMA_3) {
  157. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  158. tmpbyte |= 1;
  159. pci_write_config_byte(dev, 0x4b, tmpbyte);
  160. }
  161. }
  162. }
  163. /**
  164. * ali_dma_check - DMA check
  165. * @drive: target device
  166. * @cmd: command
  167. *
  168. * Returns 1 if the DMA cannot be performed, zero on success.
  169. */
  170. static int ali_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
  171. {
  172. if (m5229_revision < 0xC2 && drive->media != ide_disk) {
  173. if (cmd->tf_flags & IDE_TFLAG_WRITE)
  174. return 1; /* try PIO instead of DMA */
  175. }
  176. return 0;
  177. }
  178. /**
  179. * init_chipset_ali15x3 - Initialise an ALi IDE controller
  180. * @dev: PCI device
  181. *
  182. * This function initializes the ALI IDE controller and where
  183. * appropriate also sets up the 1533 southbridge.
  184. */
  185. static int init_chipset_ali15x3(struct pci_dev *dev)
  186. {
  187. unsigned long flags;
  188. u8 tmpbyte;
  189. struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
  190. m5229_revision = dev->revision;
  191. isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
  192. local_irq_save(flags);
  193. if (m5229_revision < 0xC2) {
  194. /*
  195. * revision 0x20 (1543-E, 1543-F)
  196. * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
  197. * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
  198. */
  199. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  200. /*
  201. * clear bit 7
  202. */
  203. pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
  204. /*
  205. * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
  206. */
  207. if (m5229_revision >= 0x20 && isa_dev) {
  208. pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
  209. chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
  210. }
  211. goto out;
  212. }
  213. /*
  214. * 1543C-B?, 1535, 1535D, 1553
  215. * Note 1: not all "motherboard" support this detection
  216. * Note 2: if no udma 66 device, the detection may "error".
  217. * but in this case, we will not set the device to
  218. * ultra 66, the detection result is not important
  219. */
  220. /*
  221. * enable "Cable Detection", m5229, 0x4b, bit3
  222. */
  223. pci_read_config_byte(dev, 0x4b, &tmpbyte);
  224. pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
  225. /*
  226. * We should only tune the 1533 enable if we are using an ALi
  227. * North bridge. We might have no north found on some zany
  228. * box without a device at 0:0.0. The ALi bridge will be at
  229. * 0:0.0 so if we didn't find one we know what is cooking.
  230. */
  231. if (north && north->vendor != PCI_VENDOR_ID_AL)
  232. goto out;
  233. if (m5229_revision < 0xC5 && isa_dev)
  234. {
  235. /*
  236. * set south-bridge's enable bit, m1533, 0x79
  237. */
  238. pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
  239. if (m5229_revision == 0xC2) {
  240. /*
  241. * 1543C-B0 (m1533, 0x79, bit 2)
  242. */
  243. pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
  244. } else if (m5229_revision >= 0xC3) {
  245. /*
  246. * 1553/1535 (m1533, 0x79, bit 1)
  247. */
  248. pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
  249. }
  250. }
  251. out:
  252. /*
  253. * CD_ROM DMA on (m5229, 0x53, bit0)
  254. * Enable this bit even if we want to use PIO.
  255. * PIO FIFO off (m5229, 0x53, bit1)
  256. * The hardware will use 0x54h and 0x55h to control PIO FIFO.
  257. * (Not on later devices it seems)
  258. *
  259. * 0x53 changes meaning on later revs - we must no touch
  260. * bit 1 on them. Need to check if 0x20 is the right break.
  261. */
  262. if (m5229_revision >= 0x20) {
  263. pci_read_config_byte(dev, 0x53, &tmpbyte);
  264. if (m5229_revision <= 0x20)
  265. tmpbyte = (tmpbyte & (~0x02)) | 0x01;
  266. else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
  267. tmpbyte |= 0x03;
  268. else
  269. tmpbyte |= 0x01;
  270. pci_write_config_byte(dev, 0x53, tmpbyte);
  271. }
  272. pci_dev_put(north);
  273. pci_dev_put(isa_dev);
  274. local_irq_restore(flags);
  275. return 0;
  276. }
  277. /*
  278. * Cable special cases
  279. */
  280. static const struct dmi_system_id cable_dmi_table[] = {
  281. {
  282. .ident = "HP Pavilion N5430",
  283. .matches = {
  284. DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
  285. DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
  286. },
  287. },
  288. {
  289. .ident = "Toshiba Satellite S1800-814",
  290. .matches = {
  291. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  292. DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
  293. },
  294. },
  295. { }
  296. };
  297. static int ali_cable_override(struct pci_dev *pdev)
  298. {
  299. /* Fujitsu P2000 */
  300. if (pdev->subsystem_vendor == 0x10CF &&
  301. pdev->subsystem_device == 0x10AF)
  302. return 1;
  303. /* Mitac 8317 (Winbook-A) and relatives */
  304. if (pdev->subsystem_vendor == 0x1071 &&
  305. pdev->subsystem_device == 0x8317)
  306. return 1;
  307. /* Systems by DMI */
  308. if (dmi_check_system(cable_dmi_table))
  309. return 1;
  310. return 0;
  311. }
  312. /**
  313. * ali_cable_detect - cable detection
  314. * @hwif: IDE interface
  315. *
  316. * This checks if the controller and the cable are capable
  317. * of UDMA66 transfers. It doesn't check the drives.
  318. */
  319. static u8 ali_cable_detect(ide_hwif_t *hwif)
  320. {
  321. struct pci_dev *dev = to_pci_dev(hwif->dev);
  322. u8 cbl = ATA_CBL_PATA40, tmpbyte;
  323. if (m5229_revision >= 0xC2) {
  324. /*
  325. * m5229 80-pin cable detection (from Host View)
  326. *
  327. * 0x4a bit0 is 0 => primary channel has 80-pin
  328. * 0x4a bit1 is 0 => secondary channel has 80-pin
  329. *
  330. * Certain laptops use short but suitable cables
  331. * and don't implement the detect logic.
  332. */
  333. if (ali_cable_override(dev))
  334. cbl = ATA_CBL_PATA40_SHORT;
  335. else {
  336. pci_read_config_byte(dev, 0x4a, &tmpbyte);
  337. if ((tmpbyte & (1 << hwif->channel)) == 0)
  338. cbl = ATA_CBL_PATA80;
  339. }
  340. }
  341. return cbl;
  342. }
  343. #ifndef CONFIG_SPARC64
  344. /**
  345. * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
  346. * @hwif: interface to configure
  347. *
  348. * Obtain the IRQ tables for an ALi based IDE solution on the PC
  349. * class platforms. This part of the code isn't applicable to the
  350. * Sparc systems.
  351. */
  352. static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
  353. {
  354. u8 ideic, inmir;
  355. s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
  356. 1, 11, 0, 12, 0, 14, 0, 15 };
  357. int irq = -1;
  358. if (isa_dev) {
  359. /*
  360. * read IDE interface control
  361. */
  362. pci_read_config_byte(isa_dev, 0x58, &ideic);
  363. /* bit0, bit1 */
  364. ideic = ideic & 0x03;
  365. /* get IRQ for IDE Controller */
  366. if ((hwif->channel && ideic == 0x03) ||
  367. (!hwif->channel && !ideic)) {
  368. /*
  369. * get SIRQ1 routing table
  370. */
  371. pci_read_config_byte(isa_dev, 0x44, &inmir);
  372. inmir = inmir & 0x0f;
  373. irq = irq_routing_table[inmir];
  374. } else if (hwif->channel && !(ideic & 0x01)) {
  375. /*
  376. * get SIRQ2 routing table
  377. */
  378. pci_read_config_byte(isa_dev, 0x75, &inmir);
  379. inmir = inmir & 0x0f;
  380. irq = irq_routing_table[inmir];
  381. }
  382. if(irq >= 0)
  383. hwif->irq = irq;
  384. }
  385. }
  386. #else
  387. #define init_hwif_ali15x3 NULL
  388. #endif /* CONFIG_SPARC64 */
  389. /**
  390. * init_dma_ali15x3 - set up DMA on ALi15x3
  391. * @hwif: IDE interface
  392. * @d: IDE port info
  393. *
  394. * Set up the DMA functionality on the ALi 15x3.
  395. */
  396. static int __devinit init_dma_ali15x3(ide_hwif_t *hwif,
  397. const struct ide_port_info *d)
  398. {
  399. struct pci_dev *dev = to_pci_dev(hwif->dev);
  400. unsigned long base = ide_pci_dma_base(hwif, d);
  401. if (base == 0)
  402. return -1;
  403. hwif->dma_base = base;
  404. if (ide_pci_check_simplex(hwif, d) < 0)
  405. return -1;
  406. if (ide_pci_set_master(dev, d->name) < 0)
  407. return -1;
  408. if (!hwif->channel)
  409. outb(inb(base + 2) & 0x60, base + 2);
  410. printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
  411. hwif->name, base, base + 7);
  412. if (ide_allocate_dma_engine(hwif))
  413. return -1;
  414. return 0;
  415. }
  416. static const struct ide_port_ops ali_port_ops = {
  417. .set_pio_mode = ali_set_pio_mode,
  418. .set_dma_mode = ali_set_dma_mode,
  419. .udma_filter = ali_udma_filter,
  420. .cable_detect = ali_cable_detect,
  421. };
  422. static const struct ide_dma_ops ali_dma_ops = {
  423. .dma_host_set = ide_dma_host_set,
  424. .dma_setup = ide_dma_setup,
  425. .dma_start = ide_dma_start,
  426. .dma_end = ide_dma_end,
  427. .dma_test_irq = ide_dma_test_irq,
  428. .dma_lost_irq = ide_dma_lost_irq,
  429. .dma_check = ali_dma_check,
  430. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  431. .dma_sff_read_status = ide_dma_sff_read_status,
  432. };
  433. static const struct ide_port_info ali15x3_chipset __devinitdata = {
  434. .name = DRV_NAME,
  435. .init_chipset = init_chipset_ali15x3,
  436. .init_hwif = init_hwif_ali15x3,
  437. .init_dma = init_dma_ali15x3,
  438. .port_ops = &ali_port_ops,
  439. .dma_ops = &sff_dma_ops,
  440. .pio_mask = ATA_PIO5,
  441. .swdma_mask = ATA_SWDMA2,
  442. .mwdma_mask = ATA_MWDMA2,
  443. };
  444. /**
  445. * alim15x3_init_one - set up an ALi15x3 IDE controller
  446. * @dev: PCI device to set up
  447. *
  448. * Perform the actual set up for an ALi15x3 that has been found by the
  449. * hot plug layer.
  450. */
  451. static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  452. {
  453. struct ide_port_info d = ali15x3_chipset;
  454. u8 rev = dev->revision, idx = id->driver_data;
  455. /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
  456. if (rev <= 0xC4)
  457. d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
  458. if (rev >= 0x20) {
  459. if (rev == 0x20)
  460. d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  461. if (rev < 0xC2)
  462. d.udma_mask = ATA_UDMA2;
  463. else if (rev == 0xC2 || rev == 0xC3)
  464. d.udma_mask = ATA_UDMA4;
  465. else if (rev == 0xC4)
  466. d.udma_mask = ATA_UDMA5;
  467. else
  468. d.udma_mask = ATA_UDMA6;
  469. d.dma_ops = &ali_dma_ops;
  470. } else {
  471. d.host_flags |= IDE_HFLAG_NO_DMA;
  472. d.mwdma_mask = d.swdma_mask = 0;
  473. }
  474. if (idx == 0)
  475. d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
  476. return ide_pci_init_one(dev, &d, NULL);
  477. }
  478. static const struct pci_device_id alim15x3_pci_tbl[] = {
  479. { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
  480. { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
  481. { 0, },
  482. };
  483. MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
  484. static struct pci_driver alim15x3_pci_driver = {
  485. .name = "ALI15x3_IDE",
  486. .id_table = alim15x3_pci_tbl,
  487. .probe = alim15x3_init_one,
  488. .remove = ide_pci_remove,
  489. .suspend = ide_pci_suspend,
  490. .resume = ide_pci_resume,
  491. };
  492. static int __init ali15x3_ide_init(void)
  493. {
  494. return ide_pci_register_driver(&alim15x3_pci_driver);
  495. }
  496. static void __exit ali15x3_ide_exit(void)
  497. {
  498. pci_unregister_driver(&alim15x3_pci_driver);
  499. }
  500. module_init(ali15x3_ide_init);
  501. module_exit(ali15x3_ide_exit);
  502. MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz");
  503. MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
  504. MODULE_LICENSE("GPL");