mcdi.c 32 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240
  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  23. #define MCDI_PDU(efx) \
  24. (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
  25. #define MCDI_DOORBELL(efx) \
  26. (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
  27. #define MCDI_STATUS(efx) \
  28. (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
  29. /* A reboot/assertion causes the MCDI status word to be set after the
  30. * command word is set or a REBOOT event is sent. If we notice a reboot
  31. * via these mechanisms then wait 10ms for the status word to be set. */
  32. #define MCDI_STATUS_DELAY_US 100
  33. #define MCDI_STATUS_DELAY_COUNT 100
  34. #define MCDI_STATUS_SLEEP_MS \
  35. (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= MC_SMEM_PDU_LEN);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= MC_SMEM_PDU_LEN);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned int time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = get_seconds();
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time >= finish)
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. netif_err(efx, hw, efx->net_dev,
  143. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  144. respseq, mcdi->seqno);
  145. rc = EIO;
  146. } else if (error) {
  147. efx_readd(efx, &reg, pdu + 4);
  148. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  149. #define TRANSLATE_ERROR(name) \
  150. case MC_CMD_ERR_ ## name: \
  151. rc = name; \
  152. break
  153. TRANSLATE_ERROR(ENOENT);
  154. TRANSLATE_ERROR(EINTR);
  155. TRANSLATE_ERROR(EACCES);
  156. TRANSLATE_ERROR(EBUSY);
  157. TRANSLATE_ERROR(EINVAL);
  158. TRANSLATE_ERROR(EDEADLK);
  159. TRANSLATE_ERROR(ENOSYS);
  160. TRANSLATE_ERROR(ETIME);
  161. #undef TRANSLATE_ERROR
  162. default:
  163. rc = EIO;
  164. break;
  165. }
  166. } else
  167. rc = 0;
  168. out:
  169. mcdi->resprc = rc;
  170. if (rc)
  171. mcdi->resplen = 0;
  172. /* Return rc=0 like wait_event_timeout() */
  173. return 0;
  174. }
  175. /* Test and clear MC-rebooted flag for this port/function */
  176. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  177. {
  178. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
  179. efx_dword_t reg;
  180. uint32_t value;
  181. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  182. return false;
  183. efx_readd(efx, &reg, addr);
  184. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  185. if (value == 0)
  186. return 0;
  187. EFX_ZERO_DWORD(reg);
  188. efx_writed(efx, &reg, addr);
  189. if (value == MC_STATUS_DWORD_ASSERT)
  190. return -EINTR;
  191. else
  192. return -EIO;
  193. }
  194. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  195. {
  196. /* Wait until the interface becomes QUIESCENT and we win the race
  197. * to mark it RUNNING. */
  198. wait_event(mcdi->wq,
  199. atomic_cmpxchg(&mcdi->state,
  200. MCDI_STATE_QUIESCENT,
  201. MCDI_STATE_RUNNING)
  202. == MCDI_STATE_QUIESCENT);
  203. }
  204. static int efx_mcdi_await_completion(struct efx_nic *efx)
  205. {
  206. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  207. if (wait_event_timeout(
  208. mcdi->wq,
  209. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  210. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  211. return -ETIMEDOUT;
  212. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  213. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  214. * completed the request first, then we'll just end up completing the
  215. * request again, which is safe.
  216. *
  217. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  218. * wait_event_timeout() implicitly provides.
  219. */
  220. if (mcdi->mode == MCDI_MODE_POLL)
  221. return efx_mcdi_poll(efx);
  222. return 0;
  223. }
  224. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  225. {
  226. /* If the interface is RUNNING, then move to COMPLETED and wake any
  227. * waiters. If the interface isn't in RUNNING then we've received a
  228. * duplicate completion after we've already transitioned back to
  229. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  230. * have failed the seqno check].
  231. */
  232. if (atomic_cmpxchg(&mcdi->state,
  233. MCDI_STATE_RUNNING,
  234. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  235. wake_up(&mcdi->wq);
  236. return true;
  237. }
  238. return false;
  239. }
  240. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  241. {
  242. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  243. wake_up(&mcdi->wq);
  244. }
  245. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  246. unsigned int datalen, unsigned int errno)
  247. {
  248. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  249. bool wake = false;
  250. spin_lock(&mcdi->iface_lock);
  251. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  252. if (mcdi->credits)
  253. /* The request has been cancelled */
  254. --mcdi->credits;
  255. else
  256. netif_err(efx, hw, efx->net_dev,
  257. "MC response mismatch tx seq 0x%x rx "
  258. "seq 0x%x\n", seqno, mcdi->seqno);
  259. } else {
  260. mcdi->resprc = errno;
  261. mcdi->resplen = datalen;
  262. wake = true;
  263. }
  264. spin_unlock(&mcdi->iface_lock);
  265. if (wake)
  266. efx_mcdi_complete(mcdi);
  267. }
  268. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  269. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  270. size_t *outlen_actual)
  271. {
  272. efx_mcdi_rpc_start(efx, cmd, inbuf, inlen);
  273. return efx_mcdi_rpc_finish(efx, cmd, inlen,
  274. outbuf, outlen, outlen_actual);
  275. }
  276. void efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd, const u8 *inbuf,
  277. size_t inlen)
  278. {
  279. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  280. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  281. efx_mcdi_acquire(mcdi);
  282. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  283. spin_lock_bh(&mcdi->iface_lock);
  284. ++mcdi->seqno;
  285. spin_unlock_bh(&mcdi->iface_lock);
  286. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  287. }
  288. int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  289. u8 *outbuf, size_t outlen, size_t *outlen_actual)
  290. {
  291. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  292. int rc;
  293. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  294. if (mcdi->mode == MCDI_MODE_POLL)
  295. rc = efx_mcdi_poll(efx);
  296. else
  297. rc = efx_mcdi_await_completion(efx);
  298. if (rc != 0) {
  299. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  300. * and completing a request we've just cancelled, by ensuring
  301. * that the seqno check therein fails.
  302. */
  303. spin_lock_bh(&mcdi->iface_lock);
  304. ++mcdi->seqno;
  305. ++mcdi->credits;
  306. spin_unlock_bh(&mcdi->iface_lock);
  307. netif_err(efx, hw, efx->net_dev,
  308. "MC command 0x%x inlen %d mode %d timed out\n",
  309. cmd, (int)inlen, mcdi->mode);
  310. } else {
  311. size_t resplen;
  312. /* At the very least we need a memory barrier here to ensure
  313. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  314. * a spurious efx_mcdi_ev_cpl() running concurrently by
  315. * acquiring the iface_lock. */
  316. spin_lock_bh(&mcdi->iface_lock);
  317. rc = -mcdi->resprc;
  318. resplen = mcdi->resplen;
  319. spin_unlock_bh(&mcdi->iface_lock);
  320. if (rc == 0) {
  321. efx_mcdi_copyout(efx, outbuf,
  322. min(outlen, mcdi->resplen + 3) & ~0x3);
  323. if (outlen_actual != NULL)
  324. *outlen_actual = resplen;
  325. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  326. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  327. else if (rc == -EIO || rc == -EINTR) {
  328. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  329. -rc);
  330. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  331. } else
  332. netif_dbg(efx, hw, efx->net_dev,
  333. "MC command 0x%x inlen %d failed rc=%d\n",
  334. cmd, (int)inlen, -rc);
  335. if (rc == -EIO || rc == -EINTR) {
  336. msleep(MCDI_STATUS_SLEEP_MS);
  337. efx_mcdi_poll_reboot(efx);
  338. }
  339. }
  340. efx_mcdi_release(mcdi);
  341. return rc;
  342. }
  343. void efx_mcdi_mode_poll(struct efx_nic *efx)
  344. {
  345. struct efx_mcdi_iface *mcdi;
  346. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  347. return;
  348. mcdi = efx_mcdi(efx);
  349. if (mcdi->mode == MCDI_MODE_POLL)
  350. return;
  351. /* We can switch from event completion to polled completion, because
  352. * mcdi requests are always completed in shared memory. We do this by
  353. * switching the mode to POLL'd then completing the request.
  354. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  355. *
  356. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  357. * which efx_mcdi_complete() provides for us.
  358. */
  359. mcdi->mode = MCDI_MODE_POLL;
  360. efx_mcdi_complete(mcdi);
  361. }
  362. void efx_mcdi_mode_event(struct efx_nic *efx)
  363. {
  364. struct efx_mcdi_iface *mcdi;
  365. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  366. return;
  367. mcdi = efx_mcdi(efx);
  368. if (mcdi->mode == MCDI_MODE_EVENTS)
  369. return;
  370. /* We can't switch from polled to event completion in the middle of a
  371. * request, because the completion method is specified in the request.
  372. * So acquire the interface to serialise the requestors. We don't need
  373. * to acquire the iface_lock to change the mode here, but we do need a
  374. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  375. * efx_mcdi_acquire() provides.
  376. */
  377. efx_mcdi_acquire(mcdi);
  378. mcdi->mode = MCDI_MODE_EVENTS;
  379. efx_mcdi_release(mcdi);
  380. }
  381. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  382. {
  383. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  384. /* If there is an outstanding MCDI request, it has been terminated
  385. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  386. * in polled mode, then do nothing because the MC reboot handler will
  387. * set the header correctly. However, if the mcdi interface is waiting
  388. * for a CMDDONE event it won't receive it [and since all MCDI events
  389. * are sent to the same queue, we can't be racing with
  390. * efx_mcdi_ev_cpl()]
  391. *
  392. * There's a race here with efx_mcdi_rpc(), because we might receive
  393. * a REBOOT event *before* the request has been copied out. In polled
  394. * mode (during startup) this is irrelevant, because efx_mcdi_complete()
  395. * is ignored. In event mode, this condition is just an edge-case of
  396. * receiving a REBOOT event after posting the MCDI request. Did the mc
  397. * reboot before or after the copyout? The best we can do always is
  398. * just return failure.
  399. */
  400. spin_lock(&mcdi->iface_lock);
  401. if (efx_mcdi_complete(mcdi)) {
  402. if (mcdi->mode == MCDI_MODE_EVENTS) {
  403. mcdi->resprc = rc;
  404. mcdi->resplen = 0;
  405. ++mcdi->credits;
  406. }
  407. } else {
  408. int count;
  409. /* Nobody was waiting for an MCDI request, so trigger a reset */
  410. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  411. /* Consume the status word since efx_mcdi_rpc_finish() won't */
  412. for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
  413. if (efx_mcdi_poll_reboot(efx))
  414. break;
  415. udelay(MCDI_STATUS_DELAY_US);
  416. }
  417. }
  418. spin_unlock(&mcdi->iface_lock);
  419. }
  420. static unsigned int efx_mcdi_event_link_speed[] = {
  421. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  422. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  423. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  424. };
  425. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  426. {
  427. u32 flags, fcntl, speed, lpa;
  428. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  429. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  430. speed = efx_mcdi_event_link_speed[speed];
  431. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  432. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  433. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  434. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  435. * which is only run after flushing the event queues. Therefore, it
  436. * is safe to modify the link state outside of the mac_lock here.
  437. */
  438. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  439. efx_mcdi_phy_check_fcntl(efx, lpa);
  440. efx_link_status_changed(efx);
  441. }
  442. /* Called from falcon_process_eventq for MCDI events */
  443. void efx_mcdi_process_event(struct efx_channel *channel,
  444. efx_qword_t *event)
  445. {
  446. struct efx_nic *efx = channel->efx;
  447. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  448. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  449. switch (code) {
  450. case MCDI_EVENT_CODE_BADSSERT:
  451. netif_err(efx, hw, efx->net_dev,
  452. "MC watchdog or assertion failure at 0x%x\n", data);
  453. efx_mcdi_ev_death(efx, EINTR);
  454. break;
  455. case MCDI_EVENT_CODE_PMNOTICE:
  456. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  457. break;
  458. case MCDI_EVENT_CODE_CMDDONE:
  459. efx_mcdi_ev_cpl(efx,
  460. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  461. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  462. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  463. break;
  464. case MCDI_EVENT_CODE_LINKCHANGE:
  465. efx_mcdi_process_link_change(efx, event);
  466. break;
  467. case MCDI_EVENT_CODE_SENSOREVT:
  468. efx_mcdi_sensor_event(efx, event);
  469. break;
  470. case MCDI_EVENT_CODE_SCHEDERR:
  471. netif_info(efx, hw, efx->net_dev,
  472. "MC Scheduler error address=0x%x\n", data);
  473. break;
  474. case MCDI_EVENT_CODE_REBOOT:
  475. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  476. efx_mcdi_ev_death(efx, EIO);
  477. break;
  478. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  479. /* MAC stats are gather lazily. We can ignore this. */
  480. break;
  481. case MCDI_EVENT_CODE_FLR:
  482. efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF));
  483. break;
  484. case MCDI_EVENT_CODE_PTP_RX:
  485. case MCDI_EVENT_CODE_PTP_FAULT:
  486. case MCDI_EVENT_CODE_PTP_PPS:
  487. efx_ptp_event(efx, event);
  488. break;
  489. default:
  490. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  491. code);
  492. }
  493. }
  494. /**************************************************************************
  495. *
  496. * Specific request functions
  497. *
  498. **************************************************************************
  499. */
  500. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  501. {
  502. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_OUT_LEN, 4)];
  503. size_t outlength;
  504. const __le16 *ver_words;
  505. int rc;
  506. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  507. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  508. outbuf, sizeof(outbuf), &outlength);
  509. if (rc)
  510. goto fail;
  511. if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
  512. rc = -EIO;
  513. goto fail;
  514. }
  515. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  516. snprintf(buf, len, "%u.%u.%u.%u",
  517. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  518. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  519. return;
  520. fail:
  521. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  522. buf[0] = 0;
  523. }
  524. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  525. bool *was_attached)
  526. {
  527. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  528. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  529. size_t outlen;
  530. int rc;
  531. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  532. driver_operating ? 1 : 0);
  533. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  534. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  535. outbuf, sizeof(outbuf), &outlen);
  536. if (rc)
  537. goto fail;
  538. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  539. rc = -EIO;
  540. goto fail;
  541. }
  542. if (was_attached != NULL)
  543. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  544. return 0;
  545. fail:
  546. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  547. return rc;
  548. }
  549. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  550. u16 *fw_subtype_list, u32 *capabilities)
  551. {
  552. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LENMIN];
  553. size_t outlen, offset, i;
  554. int port_num = efx_port_num(efx);
  555. int rc;
  556. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  557. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  558. outbuf, sizeof(outbuf), &outlen);
  559. if (rc)
  560. goto fail;
  561. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
  562. rc = -EIO;
  563. goto fail;
  564. }
  565. offset = (port_num)
  566. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  567. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  568. if (mac_address)
  569. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  570. if (fw_subtype_list) {
  571. /* Byte-swap and truncate or zero-pad as necessary */
  572. offset = MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST;
  573. for (i = 0;
  574. i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM;
  575. i++) {
  576. fw_subtype_list[i] =
  577. (offset + 2 <= outlen) ?
  578. le16_to_cpup((__le16 *)(outbuf + offset)) : 0;
  579. offset += 2;
  580. }
  581. }
  582. if (capabilities) {
  583. if (port_num)
  584. *capabilities = MCDI_DWORD(outbuf,
  585. GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
  586. else
  587. *capabilities = MCDI_DWORD(outbuf,
  588. GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
  589. }
  590. return 0;
  591. fail:
  592. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  593. __func__, rc, (int)outlen);
  594. return rc;
  595. }
  596. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  597. {
  598. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  599. u32 dest = 0;
  600. int rc;
  601. if (uart)
  602. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  603. if (evq)
  604. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  605. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  606. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  607. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  608. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  609. NULL, 0, NULL);
  610. if (rc)
  611. goto fail;
  612. return 0;
  613. fail:
  614. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  615. return rc;
  616. }
  617. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  618. {
  619. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  620. size_t outlen;
  621. int rc;
  622. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  623. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  624. outbuf, sizeof(outbuf), &outlen);
  625. if (rc)
  626. goto fail;
  627. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  628. rc = -EIO;
  629. goto fail;
  630. }
  631. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  632. return 0;
  633. fail:
  634. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  635. __func__, rc);
  636. return rc;
  637. }
  638. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  639. size_t *size_out, size_t *erase_size_out,
  640. bool *protected_out)
  641. {
  642. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  643. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  644. size_t outlen;
  645. int rc;
  646. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  647. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  648. outbuf, sizeof(outbuf), &outlen);
  649. if (rc)
  650. goto fail;
  651. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  652. rc = -EIO;
  653. goto fail;
  654. }
  655. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  656. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  657. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  658. (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
  659. return 0;
  660. fail:
  661. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  662. return rc;
  663. }
  664. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  665. {
  666. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  667. int rc;
  668. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  669. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  670. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  671. NULL, 0, NULL);
  672. if (rc)
  673. goto fail;
  674. return 0;
  675. fail:
  676. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  677. return rc;
  678. }
  679. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  680. loff_t offset, u8 *buffer, size_t length)
  681. {
  682. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  683. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  684. size_t outlen;
  685. int rc;
  686. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  687. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  688. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  689. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  690. outbuf, sizeof(outbuf), &outlen);
  691. if (rc)
  692. goto fail;
  693. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  694. return 0;
  695. fail:
  696. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  697. return rc;
  698. }
  699. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  700. loff_t offset, const u8 *buffer, size_t length)
  701. {
  702. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  703. int rc;
  704. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  705. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  706. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  707. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  708. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  709. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  710. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  711. NULL, 0, NULL);
  712. if (rc)
  713. goto fail;
  714. return 0;
  715. fail:
  716. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  717. return rc;
  718. }
  719. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  720. loff_t offset, size_t length)
  721. {
  722. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  723. int rc;
  724. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  725. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  726. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  727. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  728. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  729. NULL, 0, NULL);
  730. if (rc)
  731. goto fail;
  732. return 0;
  733. fail:
  734. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  735. return rc;
  736. }
  737. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  738. {
  739. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  740. int rc;
  741. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  742. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  743. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  744. NULL, 0, NULL);
  745. if (rc)
  746. goto fail;
  747. return 0;
  748. fail:
  749. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  750. return rc;
  751. }
  752. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  753. {
  754. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  755. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  756. int rc;
  757. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  758. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  759. outbuf, sizeof(outbuf), NULL);
  760. if (rc)
  761. return rc;
  762. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  763. case MC_CMD_NVRAM_TEST_PASS:
  764. case MC_CMD_NVRAM_TEST_NOTSUPP:
  765. return 0;
  766. default:
  767. return -EIO;
  768. }
  769. }
  770. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  771. {
  772. u32 nvram_types;
  773. unsigned int type;
  774. int rc;
  775. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  776. if (rc)
  777. goto fail1;
  778. type = 0;
  779. while (nvram_types != 0) {
  780. if (nvram_types & 1) {
  781. rc = efx_mcdi_nvram_test(efx, type);
  782. if (rc)
  783. goto fail2;
  784. }
  785. type++;
  786. nvram_types >>= 1;
  787. }
  788. return 0;
  789. fail2:
  790. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  791. __func__, type);
  792. fail1:
  793. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  794. return rc;
  795. }
  796. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  797. {
  798. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  799. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  800. unsigned int flags, index, ofst;
  801. const char *reason;
  802. size_t outlen;
  803. int retry;
  804. int rc;
  805. /* Attempt to read any stored assertion state before we reboot
  806. * the mcfw out of the assertion handler. Retry twice, once
  807. * because a boot-time assertion might cause this command to fail
  808. * with EINTR. And once again because GET_ASSERTS can race with
  809. * MC_CMD_REBOOT running on the other port. */
  810. retry = 2;
  811. do {
  812. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  813. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  814. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  815. outbuf, sizeof(outbuf), &outlen);
  816. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  817. if (rc)
  818. return rc;
  819. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  820. return -EIO;
  821. /* Print out any recorded assertion state */
  822. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  823. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  824. return 0;
  825. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  826. ? "system-level assertion"
  827. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  828. ? "thread-level assertion"
  829. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  830. ? "watchdog reset"
  831. : "unknown assertion";
  832. netif_err(efx, hw, efx->net_dev,
  833. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  834. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  835. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  836. /* Print out the registers */
  837. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  838. for (index = 1; index < 32; index++) {
  839. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  840. MCDI_DWORD2(outbuf, ofst));
  841. ofst += sizeof(efx_dword_t);
  842. }
  843. return 0;
  844. }
  845. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  846. {
  847. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  848. /* If the MC is running debug firmware, it might now be
  849. * waiting for a debugger to attach, but we just want it to
  850. * reboot. We set a flag that makes the command a no-op if it
  851. * has already done so. We don't know what return code to
  852. * expect (0 or -EIO), so ignore it.
  853. */
  854. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  855. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  856. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  857. (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  858. NULL, 0, NULL);
  859. }
  860. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  861. {
  862. int rc;
  863. rc = efx_mcdi_read_assertion(efx);
  864. if (rc)
  865. return rc;
  866. efx_mcdi_exit_assertion(efx);
  867. return 0;
  868. }
  869. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  870. {
  871. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  872. int rc;
  873. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  874. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  875. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  876. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  877. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  878. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  879. NULL, 0, NULL);
  880. if (rc)
  881. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  882. __func__, rc);
  883. }
  884. int efx_mcdi_reset_port(struct efx_nic *efx)
  885. {
  886. int rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL);
  887. if (rc)
  888. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  889. __func__, rc);
  890. return rc;
  891. }
  892. int efx_mcdi_reset_mc(struct efx_nic *efx)
  893. {
  894. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  895. int rc;
  896. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  897. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  898. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  899. NULL, 0, NULL);
  900. /* White is black, and up is down */
  901. if (rc == -EIO)
  902. return 0;
  903. if (rc == 0)
  904. rc = -EIO;
  905. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  906. return rc;
  907. }
  908. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  909. const u8 *mac, int *id_out)
  910. {
  911. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  912. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  913. size_t outlen;
  914. int rc;
  915. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  916. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  917. MC_CMD_FILTER_MODE_SIMPLE);
  918. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  919. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  920. outbuf, sizeof(outbuf), &outlen);
  921. if (rc)
  922. goto fail;
  923. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  924. rc = -EIO;
  925. goto fail;
  926. }
  927. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  928. return 0;
  929. fail:
  930. *id_out = -1;
  931. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  932. return rc;
  933. }
  934. int
  935. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  936. {
  937. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  938. }
  939. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  940. {
  941. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  942. size_t outlen;
  943. int rc;
  944. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  945. outbuf, sizeof(outbuf), &outlen);
  946. if (rc)
  947. goto fail;
  948. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  949. rc = -EIO;
  950. goto fail;
  951. }
  952. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  953. return 0;
  954. fail:
  955. *id_out = -1;
  956. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  957. return rc;
  958. }
  959. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  960. {
  961. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  962. int rc;
  963. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  964. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  965. NULL, 0, NULL);
  966. if (rc)
  967. goto fail;
  968. return 0;
  969. fail:
  970. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  971. return rc;
  972. }
  973. int efx_mcdi_flush_rxqs(struct efx_nic *efx)
  974. {
  975. struct efx_channel *channel;
  976. struct efx_rx_queue *rx_queue;
  977. __le32 *qid;
  978. int rc, count;
  979. BUILD_BUG_ON(EFX_MAX_CHANNELS >
  980. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  981. qid = kmalloc(EFX_MAX_CHANNELS * sizeof(*qid), GFP_KERNEL);
  982. if (qid == NULL)
  983. return -ENOMEM;
  984. count = 0;
  985. efx_for_each_channel(channel, efx) {
  986. efx_for_each_channel_rx_queue(rx_queue, channel) {
  987. if (rx_queue->flush_pending) {
  988. rx_queue->flush_pending = false;
  989. atomic_dec(&efx->rxq_flush_pending);
  990. qid[count++] = cpu_to_le32(
  991. efx_rx_queue_index(rx_queue));
  992. }
  993. }
  994. }
  995. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, (u8 *)qid,
  996. count * sizeof(*qid), NULL, 0, NULL);
  997. WARN_ON(rc > 0);
  998. kfree(qid);
  999. return rc;
  1000. }
  1001. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  1002. {
  1003. int rc;
  1004. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  1005. if (rc)
  1006. goto fail;
  1007. return 0;
  1008. fail:
  1009. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1010. return rc;
  1011. }