tpm_nsc.c 9.8 KB

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  1. /*
  2. * Copyright (C) 2004 IBM Corporation
  3. *
  4. * Authors:
  5. * Leendert van Doorn <leendert@watson.ibm.com>
  6. * Dave Safford <safford@watson.ibm.com>
  7. * Reiner Sailer <sailer@watson.ibm.com>
  8. * Kylene Hall <kjhall@us.ibm.com>
  9. *
  10. * Maintained by: <tpmdd_devel@lists.sourceforge.net>
  11. *
  12. * Device driver for TCG/TCPA TPM (trusted platform module).
  13. * Specifications at www.trustedcomputinggroup.org
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation, version 2 of the
  18. * License.
  19. *
  20. */
  21. #include "tpm.h"
  22. /* National definitions */
  23. enum tpm_nsc_addr{
  24. TPM_NSC_IRQ = 0x07,
  25. TPM_NSC_BASE0_HI = 0x60,
  26. TPM_NSC_BASE0_LO = 0x61,
  27. TPM_NSC_BASE1_HI = 0x62,
  28. TPM_NSC_BASE1_LO = 0x63
  29. };
  30. enum tpm_nsc_index {
  31. NSC_LDN_INDEX = 0x07,
  32. NSC_SID_INDEX = 0x20,
  33. NSC_LDC_INDEX = 0x30,
  34. NSC_DIO_INDEX = 0x60,
  35. NSC_CIO_INDEX = 0x62,
  36. NSC_IRQ_INDEX = 0x70,
  37. NSC_ITS_INDEX = 0x71
  38. };
  39. enum tpm_nsc_status_loc {
  40. NSC_STATUS = 0x01,
  41. NSC_COMMAND = 0x01,
  42. NSC_DATA = 0x00
  43. };
  44. /* status bits */
  45. enum tpm_nsc_status {
  46. NSC_STATUS_OBF = 0x01, /* output buffer full */
  47. NSC_STATUS_IBF = 0x02, /* input buffer full */
  48. NSC_STATUS_F0 = 0x04, /* F0 */
  49. NSC_STATUS_A2 = 0x08, /* A2 */
  50. NSC_STATUS_RDY = 0x10, /* ready to receive command */
  51. NSC_STATUS_IBR = 0x20 /* ready to receive data */
  52. };
  53. /* command bits */
  54. enum tpm_nsc_cmd_mode {
  55. NSC_COMMAND_NORMAL = 0x01, /* normal mode */
  56. NSC_COMMAND_EOC = 0x03,
  57. NSC_COMMAND_CANCEL = 0x22
  58. };
  59. /*
  60. * Wait for a certain status to appear
  61. */
  62. static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
  63. {
  64. unsigned long stop;
  65. /* status immediately available check */
  66. *data = inb(chip->vendor->base + NSC_STATUS);
  67. if ((*data & mask) == val)
  68. return 0;
  69. /* wait for status */
  70. stop = jiffies + 10 * HZ;
  71. do {
  72. msleep(TPM_TIMEOUT);
  73. *data = inb(chip->vendor->base + 1);
  74. if ((*data & mask) == val)
  75. return 0;
  76. }
  77. while (time_before(jiffies, stop));
  78. return -EBUSY;
  79. }
  80. static int nsc_wait_for_ready(struct tpm_chip *chip)
  81. {
  82. int status;
  83. unsigned long stop;
  84. /* status immediately available check */
  85. status = inb(chip->vendor->base + NSC_STATUS);
  86. if (status & NSC_STATUS_OBF)
  87. status = inb(chip->vendor->base + NSC_DATA);
  88. if (status & NSC_STATUS_RDY)
  89. return 0;
  90. /* wait for status */
  91. stop = jiffies + 100;
  92. do {
  93. msleep(TPM_TIMEOUT);
  94. status = inb(chip->vendor->base + NSC_STATUS);
  95. if (status & NSC_STATUS_OBF)
  96. status = inb(chip->vendor->base + NSC_DATA);
  97. if (status & NSC_STATUS_RDY)
  98. return 0;
  99. }
  100. while (time_before(jiffies, stop));
  101. dev_info(chip->dev, "wait for ready failed\n");
  102. return -EBUSY;
  103. }
  104. static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
  105. {
  106. u8 *buffer = buf;
  107. u8 data, *p;
  108. u32 size;
  109. __be32 *native_size;
  110. if (count < 6)
  111. return -EIO;
  112. if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
  113. dev_err(chip->dev, "F0 timeout\n");
  114. return -EIO;
  115. }
  116. if ((data =
  117. inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
  118. dev_err(chip->dev, "not in normal mode (0x%x)\n",
  119. data);
  120. return -EIO;
  121. }
  122. /* read the whole packet */
  123. for (p = buffer; p < &buffer[count]; p++) {
  124. if (wait_for_stat
  125. (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
  126. dev_err(chip->dev,
  127. "OBF timeout (while reading data)\n");
  128. return -EIO;
  129. }
  130. if (data & NSC_STATUS_F0)
  131. break;
  132. *p = inb(chip->vendor->base + NSC_DATA);
  133. }
  134. if ((data & NSC_STATUS_F0) == 0 &&
  135. (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
  136. dev_err(chip->dev, "F0 not set\n");
  137. return -EIO;
  138. }
  139. if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) {
  140. dev_err(chip->dev,
  141. "expected end of command(0x%x)\n", data);
  142. return -EIO;
  143. }
  144. native_size = (__force __be32 *) (buf + 2);
  145. size = be32_to_cpu(*native_size);
  146. if (count < size)
  147. return -EIO;
  148. return size;
  149. }
  150. static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
  151. {
  152. u8 data;
  153. int i;
  154. /*
  155. * If we hit the chip with back to back commands it locks up
  156. * and never set IBF. Hitting it with this "hammer" seems to
  157. * fix it. Not sure why this is needed, we followed the flow
  158. * chart in the manual to the letter.
  159. */
  160. outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
  161. if (nsc_wait_for_ready(chip) != 0)
  162. return -EIO;
  163. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  164. dev_err(chip->dev, "IBF timeout\n");
  165. return -EIO;
  166. }
  167. outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND);
  168. if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
  169. dev_err(chip->dev, "IBR timeout\n");
  170. return -EIO;
  171. }
  172. for (i = 0; i < count; i++) {
  173. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  174. dev_err(chip->dev,
  175. "IBF timeout (while writing data)\n");
  176. return -EIO;
  177. }
  178. outb(buf[i], chip->vendor->base + NSC_DATA);
  179. }
  180. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  181. dev_err(chip->dev, "IBF timeout\n");
  182. return -EIO;
  183. }
  184. outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND);
  185. return count;
  186. }
  187. static void tpm_nsc_cancel(struct tpm_chip *chip)
  188. {
  189. outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
  190. }
  191. static u8 tpm_nsc_status(struct tpm_chip *chip)
  192. {
  193. return inb(chip->vendor->base + NSC_STATUS);
  194. }
  195. static struct file_operations nsc_ops = {
  196. .owner = THIS_MODULE,
  197. .llseek = no_llseek,
  198. .open = tpm_open,
  199. .read = tpm_read,
  200. .write = tpm_write,
  201. .release = tpm_release,
  202. };
  203. static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
  204. static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
  205. static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
  206. static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
  207. static struct attribute * nsc_attrs[] = {
  208. &dev_attr_pubek.attr,
  209. &dev_attr_pcrs.attr,
  210. &dev_attr_caps.attr,
  211. &dev_attr_cancel.attr,
  212. 0,
  213. };
  214. static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
  215. static struct tpm_vendor_specific tpm_nsc = {
  216. .recv = tpm_nsc_recv,
  217. .send = tpm_nsc_send,
  218. .cancel = tpm_nsc_cancel,
  219. .status = tpm_nsc_status,
  220. .req_complete_mask = NSC_STATUS_OBF,
  221. .req_complete_val = NSC_STATUS_OBF,
  222. .req_canceled = NSC_STATUS_RDY,
  223. .attr_group = &nsc_attr_grp,
  224. .miscdev = { .fops = &nsc_ops, },
  225. };
  226. static struct platform_device *pdev = NULL;
  227. static void __devexit tpm_nsc_remove(struct device *dev)
  228. {
  229. struct tpm_chip *chip = dev_get_drvdata(dev);
  230. if ( chip ) {
  231. release_region(chip->vendor->base, 2);
  232. tpm_remove_hardware(chip->dev);
  233. }
  234. }
  235. static struct device_driver nsc_drv = {
  236. .name = "tpm_nsc",
  237. .bus = &platform_bus_type,
  238. .owner = THIS_MODULE,
  239. .suspend = tpm_pm_suspend,
  240. .resume = tpm_pm_resume,
  241. };
  242. static int __init init_nsc(void)
  243. {
  244. int rc = 0;
  245. int lo, hi;
  246. int nscAddrBase = TPM_ADDR;
  247. driver_register(&nsc_drv);
  248. /* select PM channel 1 */
  249. tpm_write_index(nscAddrBase,NSC_LDN_INDEX, 0x12);
  250. /* verify that it is a National part (SID) */
  251. if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
  252. nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
  253. (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
  254. if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
  255. return -ENODEV;
  256. }
  257. hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
  258. lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
  259. tpm_nsc.base = (hi<<8) | lo;
  260. /* enable the DPM module */
  261. tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
  262. pdev = kmalloc(sizeof(struct platform_device), GFP_KERNEL);
  263. if ( !pdev )
  264. return -ENOMEM;
  265. memset(pdev, 0, sizeof(struct platform_device));
  266. pdev->name = "tpm_nscl0";
  267. pdev->id = -1;
  268. pdev->num_resources = 0;
  269. pdev->dev.release = tpm_nsc_remove;
  270. pdev->dev.driver = &nsc_drv;
  271. if ((rc=platform_device_register(pdev)) < 0) {
  272. kfree(pdev);
  273. pdev = NULL;
  274. return rc;
  275. }
  276. if (request_region(tpm_nsc.base, 2, "tpm_nsc0") == NULL ) {
  277. platform_device_unregister(pdev);
  278. kfree(pdev);
  279. pdev = NULL;
  280. return -EBUSY;
  281. }
  282. if ((rc = tpm_register_hardware(&pdev->dev, &tpm_nsc)) < 0) {
  283. release_region(tpm_nsc.base, 2);
  284. platform_device_unregister(pdev);
  285. kfree(pdev);
  286. pdev = NULL;
  287. return rc;
  288. }
  289. dev_dbg(&pdev->dev, "NSC TPM detected\n");
  290. dev_dbg(&pdev->dev,
  291. "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
  292. tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
  293. tpm_read_index(nscAddrBase,0x27));
  294. dev_dbg(&pdev->dev,
  295. "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
  296. tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
  297. tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
  298. dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
  299. (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
  300. dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
  301. (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
  302. dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
  303. tpm_read_index(nscAddrBase,0x70));
  304. dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
  305. tpm_read_index(nscAddrBase,0x71));
  306. dev_dbg(&pdev->dev,
  307. "NSC DMA channel select0 0x%x, select1 0x%x\n",
  308. tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
  309. dev_dbg(&pdev->dev,
  310. "NSC Config "
  311. "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
  312. tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
  313. tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
  314. tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
  315. tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
  316. tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
  317. dev_info(&pdev->dev,
  318. "NSC TPM revision %d\n",
  319. tpm_read_index(nscAddrBase, 0x27) & 0x1F);
  320. return 0;
  321. }
  322. static void __exit cleanup_nsc(void)
  323. {
  324. if (pdev) {
  325. tpm_nsc_remove(&pdev->dev);
  326. platform_device_unregister(pdev);
  327. kfree(pdev);
  328. pdev = NULL;
  329. }
  330. driver_unregister(&nsc_drv);
  331. }
  332. module_init(init_nsc);
  333. module_exit(cleanup_nsc);
  334. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  335. MODULE_DESCRIPTION("TPM Driver");
  336. MODULE_VERSION("2.0");
  337. MODULE_LICENSE("GPL");