bfin_5xx.c 31 KB

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  1. /*
  2. * Blackfin On-Chip Serial Driver
  3. *
  4. * Copyright 2006-2007 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  11. #define SUPPORT_SYSRQ
  12. #endif
  13. #include <linux/module.h>
  14. #include <linux/ioport.h>
  15. #include <linux/init.h>
  16. #include <linux/console.h>
  17. #include <linux/sysrq.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/tty.h>
  20. #include <linux/tty_flip.h>
  21. #include <linux/serial_core.h>
  22. #ifdef CONFIG_KGDB_UART
  23. #include <linux/kgdb.h>
  24. #include <asm/irq_regs.h>
  25. #endif
  26. #include <asm/gpio.h>
  27. #include <asm/mach/bfin_serial_5xx.h>
  28. #ifdef CONFIG_SERIAL_BFIN_DMA
  29. #include <linux/dma-mapping.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <asm/cacheflush.h>
  33. #endif
  34. /* UART name and device definitions */
  35. #define BFIN_SERIAL_NAME "ttyBF"
  36. #define BFIN_SERIAL_MAJOR 204
  37. #define BFIN_SERIAL_MINOR 64
  38. /*
  39. * Setup for console. Argument comes from the menuconfig
  40. */
  41. #define DMA_RX_XCOUNT 512
  42. #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
  43. #define DMA_RX_FLUSH_JIFFIES 5
  44. #ifdef CONFIG_SERIAL_BFIN_DMA
  45. static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
  46. #else
  47. static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
  48. #endif
  49. static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
  50. /*
  51. * interrupts are disabled on entry
  52. */
  53. static void bfin_serial_stop_tx(struct uart_port *port)
  54. {
  55. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  56. struct circ_buf *xmit = &uart->port.info->xmit;
  57. #if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA)
  58. unsigned short ier;
  59. #endif
  60. while (!(UART_GET_LSR(uart) & TEMT))
  61. cpu_relax();
  62. #ifdef CONFIG_SERIAL_BFIN_DMA
  63. disable_dma(uart->tx_dma_channel);
  64. xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
  65. uart->port.icount.tx += uart->tx_count;
  66. uart->tx_count = 0;
  67. uart->tx_done = 1;
  68. #else
  69. #ifdef CONFIG_BF54x
  70. /* Clear TFI bit */
  71. UART_PUT_LSR(uart, TFI);
  72. UART_CLEAR_IER(uart, ETBEI);
  73. #else
  74. ier = UART_GET_IER(uart);
  75. ier &= ~ETBEI;
  76. UART_PUT_IER(uart, ier);
  77. #endif
  78. #endif
  79. }
  80. /*
  81. * port is locked and interrupts are disabled
  82. */
  83. static void bfin_serial_start_tx(struct uart_port *port)
  84. {
  85. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  86. #ifdef CONFIG_SERIAL_BFIN_DMA
  87. if (uart->tx_done)
  88. bfin_serial_dma_tx_chars(uart);
  89. #else
  90. #ifdef CONFIG_BF54x
  91. UART_SET_IER(uart, ETBEI);
  92. #else
  93. unsigned short ier;
  94. ier = UART_GET_IER(uart);
  95. ier |= ETBEI;
  96. UART_PUT_IER(uart, ier);
  97. #endif
  98. bfin_serial_tx_chars(uart);
  99. #endif
  100. }
  101. /*
  102. * Interrupts are enabled
  103. */
  104. static void bfin_serial_stop_rx(struct uart_port *port)
  105. {
  106. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  107. #ifdef CONFIG_KGDB_UART
  108. if (uart->port.line != CONFIG_KGDB_UART_PORT) {
  109. #endif
  110. #ifdef CONFIG_BF54x
  111. UART_CLEAR_IER(uart, ERBFI);
  112. #else
  113. unsigned short ier;
  114. ier = UART_GET_IER(uart);
  115. ier &= ~ERBFI;
  116. UART_PUT_IER(uart, ier);
  117. #endif
  118. #ifdef CONFIG_KGDB_UART
  119. }
  120. #endif
  121. }
  122. /*
  123. * Set the modem control timer to fire immediately.
  124. */
  125. static void bfin_serial_enable_ms(struct uart_port *port)
  126. {
  127. }
  128. #ifdef CONFIG_KGDB_UART
  129. static int kgdb_entry_state;
  130. void kgdb_put_debug_char(int chr)
  131. {
  132. struct bfin_serial_port *uart;
  133. if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
  134. uart = &bfin_serial_ports[0];
  135. else
  136. uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
  137. while (!(UART_GET_LSR(uart) & THRE)) {
  138. SSYNC();
  139. }
  140. #ifndef CONFIG_BF54x
  141. UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
  142. SSYNC();
  143. #endif
  144. UART_PUT_CHAR(uart, (unsigned char)chr);
  145. SSYNC();
  146. }
  147. int kgdb_get_debug_char(void)
  148. {
  149. struct bfin_serial_port *uart;
  150. unsigned char chr;
  151. if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
  152. uart = &bfin_serial_ports[0];
  153. else
  154. uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
  155. while(!(UART_GET_LSR(uart) & DR)) {
  156. SSYNC();
  157. }
  158. #ifndef CONFIG_BF54x
  159. UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
  160. SSYNC();
  161. #endif
  162. chr = UART_GET_CHAR(uart);
  163. SSYNC();
  164. return chr;
  165. }
  166. #endif
  167. #if ANOMALY_05000230 && defined(CONFIG_SERIAL_BFIN_PIO)
  168. # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
  169. # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
  170. #else
  171. # define UART_GET_ANOMALY_THRESHOLD(uart) 0
  172. # define UART_SET_ANOMALY_THRESHOLD(uart, v)
  173. #endif
  174. #ifdef CONFIG_SERIAL_BFIN_PIO
  175. static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
  176. {
  177. struct tty_struct *tty = uart->port.info->tty;
  178. unsigned int status, ch, flg;
  179. static struct timeval anomaly_start = { .tv_sec = 0 };
  180. #ifdef CONFIG_KGDB_UART
  181. struct pt_regs *regs = get_irq_regs();
  182. #endif
  183. status = UART_GET_LSR(uart);
  184. UART_CLEAR_LSR(uart);
  185. ch = UART_GET_CHAR(uart);
  186. uart->port.icount.rx++;
  187. #ifdef CONFIG_KGDB_UART
  188. if (uart->port.line == CONFIG_KGDB_UART_PORT) {
  189. if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
  190. kgdb_breakkey_pressed(regs);
  191. return;
  192. } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
  193. kgdb_entry_state = 1;
  194. } else if (kgdb_entry_state == 1 && ch == 'q') {
  195. kgdb_entry_state = 0;
  196. kgdb_breakkey_pressed(regs);
  197. return;
  198. } else if (ch == 0x3) {/* Ctrl + C */
  199. kgdb_entry_state = 0;
  200. kgdb_breakkey_pressed(regs);
  201. return;
  202. } else {
  203. kgdb_entry_state = 0;
  204. }
  205. }
  206. #endif
  207. if (ANOMALY_05000230) {
  208. /* The BF533 (and BF561) family of processors have a nice anomaly
  209. * where they continuously generate characters for a "single" break.
  210. * We have to basically ignore this flood until the "next" valid
  211. * character comes across. Due to the nature of the flood, it is
  212. * not possible to reliably catch bytes that are sent too quickly
  213. * after this break. So application code talking to the Blackfin
  214. * which sends a break signal must allow at least 1.5 character
  215. * times after the end of the break for things to stabilize. This
  216. * timeout was picked as it must absolutely be larger than 1
  217. * character time +/- some percent. So 1.5 sounds good. All other
  218. * Blackfin families operate properly. Woo.
  219. * Note: While Anomaly 05000230 does not directly address this,
  220. * the changes that went in for it also fixed this issue.
  221. * That anomaly was fixed in 0.5+ silicon. I like bunnies.
  222. */
  223. if (anomaly_start.tv_sec) {
  224. struct timeval curr;
  225. suseconds_t usecs;
  226. if ((~ch & (~ch + 1)) & 0xff)
  227. goto known_good_char;
  228. do_gettimeofday(&curr);
  229. if (curr.tv_sec - anomaly_start.tv_sec > 1)
  230. goto known_good_char;
  231. usecs = 0;
  232. if (curr.tv_sec != anomaly_start.tv_sec)
  233. usecs += USEC_PER_SEC;
  234. usecs += curr.tv_usec - anomaly_start.tv_usec;
  235. if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
  236. goto known_good_char;
  237. if (ch)
  238. anomaly_start.tv_sec = 0;
  239. else
  240. anomaly_start = curr;
  241. return;
  242. known_good_char:
  243. anomaly_start.tv_sec = 0;
  244. }
  245. }
  246. if (status & BI) {
  247. if (ANOMALY_05000230)
  248. if (bfin_revid() < 5)
  249. do_gettimeofday(&anomaly_start);
  250. uart->port.icount.brk++;
  251. if (uart_handle_break(&uart->port))
  252. goto ignore_char;
  253. status &= ~(PE | FE);
  254. }
  255. if (status & PE)
  256. uart->port.icount.parity++;
  257. if (status & OE)
  258. uart->port.icount.overrun++;
  259. if (status & FE)
  260. uart->port.icount.frame++;
  261. status &= uart->port.read_status_mask;
  262. if (status & BI)
  263. flg = TTY_BREAK;
  264. else if (status & PE)
  265. flg = TTY_PARITY;
  266. else if (status & FE)
  267. flg = TTY_FRAME;
  268. else
  269. flg = TTY_NORMAL;
  270. if (uart_handle_sysrq_char(&uart->port, ch))
  271. goto ignore_char;
  272. uart_insert_char(&uart->port, status, OE, ch, flg);
  273. ignore_char:
  274. tty_flip_buffer_push(tty);
  275. }
  276. static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
  277. {
  278. struct circ_buf *xmit = &uart->port.info->xmit;
  279. if (uart->port.x_char) {
  280. UART_PUT_CHAR(uart, uart->port.x_char);
  281. uart->port.icount.tx++;
  282. uart->port.x_char = 0;
  283. }
  284. /*
  285. * Check the modem control lines before
  286. * transmitting anything.
  287. */
  288. bfin_serial_mctrl_check(uart);
  289. if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
  290. bfin_serial_stop_tx(&uart->port);
  291. return;
  292. }
  293. while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
  294. UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
  295. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  296. uart->port.icount.tx++;
  297. SSYNC();
  298. }
  299. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  300. uart_write_wakeup(&uart->port);
  301. if (uart_circ_empty(xmit))
  302. bfin_serial_stop_tx(&uart->port);
  303. }
  304. static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
  305. {
  306. struct bfin_serial_port *uart = dev_id;
  307. spin_lock(&uart->port.lock);
  308. while (UART_GET_LSR(uart) & DR)
  309. bfin_serial_rx_chars(uart);
  310. spin_unlock(&uart->port.lock);
  311. return IRQ_HANDLED;
  312. }
  313. static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
  314. {
  315. struct bfin_serial_port *uart = dev_id;
  316. spin_lock(&uart->port.lock);
  317. if (UART_GET_LSR(uart) & THRE)
  318. bfin_serial_tx_chars(uart);
  319. spin_unlock(&uart->port.lock);
  320. return IRQ_HANDLED;
  321. }
  322. #endif
  323. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  324. static void bfin_serial_do_work(struct work_struct *work)
  325. {
  326. struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
  327. bfin_serial_mctrl_check(uart);
  328. }
  329. #endif
  330. #ifdef CONFIG_SERIAL_BFIN_DMA
  331. static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
  332. {
  333. struct circ_buf *xmit = &uart->port.info->xmit;
  334. unsigned short ier;
  335. int flags = 0;
  336. uart->tx_done = 0;
  337. if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
  338. uart->tx_count = 0;
  339. uart->tx_done = 1;
  340. return;
  341. }
  342. if (uart->port.x_char) {
  343. UART_PUT_CHAR(uart, uart->port.x_char);
  344. uart->port.icount.tx++;
  345. uart->port.x_char = 0;
  346. }
  347. /*
  348. * Check the modem control lines before
  349. * transmitting anything.
  350. */
  351. bfin_serial_mctrl_check(uart);
  352. uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
  353. if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
  354. uart->tx_count = UART_XMIT_SIZE - xmit->tail;
  355. blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
  356. (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
  357. set_dma_config(uart->tx_dma_channel,
  358. set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
  359. INTR_ON_BUF,
  360. DIMENSION_LINEAR,
  361. DATA_SIZE_8,
  362. DMA_SYNC_RESTART));
  363. set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
  364. set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
  365. set_dma_x_modify(uart->tx_dma_channel, 1);
  366. enable_dma(uart->tx_dma_channel);
  367. #ifdef CONFIG_BF54x
  368. UART_SET_IER(uart, ETBEI);
  369. #else
  370. ier = UART_GET_IER(uart);
  371. ier |= ETBEI;
  372. UART_PUT_IER(uart, ier);
  373. #endif
  374. }
  375. static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
  376. {
  377. struct tty_struct *tty = uart->port.info->tty;
  378. int i, flg, status;
  379. status = UART_GET_LSR(uart);
  380. UART_CLEAR_LSR(uart);
  381. uart->port.icount.rx +=
  382. CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
  383. UART_XMIT_SIZE);
  384. if (status & BI) {
  385. uart->port.icount.brk++;
  386. if (uart_handle_break(&uart->port))
  387. goto dma_ignore_char;
  388. status &= ~(PE | FE);
  389. }
  390. if (status & PE)
  391. uart->port.icount.parity++;
  392. if (status & OE)
  393. uart->port.icount.overrun++;
  394. if (status & FE)
  395. uart->port.icount.frame++;
  396. status &= uart->port.read_status_mask;
  397. if (status & BI)
  398. flg = TTY_BREAK;
  399. else if (status & PE)
  400. flg = TTY_PARITY;
  401. else if (status & FE)
  402. flg = TTY_FRAME;
  403. else
  404. flg = TTY_NORMAL;
  405. for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
  406. if (i >= UART_XMIT_SIZE)
  407. i = 0;
  408. if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
  409. uart_insert_char(&uart->port, status, OE,
  410. uart->rx_dma_buf.buf[i], flg);
  411. }
  412. dma_ignore_char:
  413. tty_flip_buffer_push(tty);
  414. }
  415. void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
  416. {
  417. int x_pos, pos;
  418. int flags = 0;
  419. spin_lock_irqsave(&uart->port.lock, flags);
  420. uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
  421. x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
  422. uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
  423. if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
  424. uart->rx_dma_nrows = 0;
  425. x_pos = DMA_RX_XCOUNT - x_pos;
  426. if (x_pos == DMA_RX_XCOUNT)
  427. x_pos = 0;
  428. pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
  429. if (pos != uart->rx_dma_buf.tail) {
  430. uart->rx_dma_buf.head = pos;
  431. bfin_serial_dma_rx_chars(uart);
  432. uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
  433. }
  434. spin_unlock_irqrestore(&uart->port.lock, flags);
  435. uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
  436. add_timer(&(uart->rx_dma_timer));
  437. }
  438. static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
  439. {
  440. struct bfin_serial_port *uart = dev_id;
  441. struct circ_buf *xmit = &uart->port.info->xmit;
  442. unsigned short ier;
  443. spin_lock(&uart->port.lock);
  444. if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
  445. disable_dma(uart->tx_dma_channel);
  446. clear_dma_irqstat(uart->tx_dma_channel);
  447. #ifdef CONFIG_BF54x
  448. UART_CLEAR_IER(uart, ETBEI);
  449. #else
  450. ier = UART_GET_IER(uart);
  451. ier &= ~ETBEI;
  452. UART_PUT_IER(uart, ier);
  453. #endif
  454. xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
  455. uart->port.icount.tx += uart->tx_count;
  456. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  457. uart_write_wakeup(&uart->port);
  458. bfin_serial_dma_tx_chars(uart);
  459. }
  460. spin_unlock(&uart->port.lock);
  461. return IRQ_HANDLED;
  462. }
  463. static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
  464. {
  465. struct bfin_serial_port *uart = dev_id;
  466. unsigned short irqstat;
  467. int pos;
  468. uart->rx_dma_nrows = DMA_RX_YCOUNT -
  469. get_dma_curr_ycount(uart->rx_dma_channel);
  470. pos = DMA_RX_XCOUNT * uart->rx_dma_nrows;
  471. if (pos != uart->rx_dma_buf.tail) {
  472. uart->rx_dma_buf.head = pos;
  473. bfin_serial_dma_rx_chars(uart);
  474. uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
  475. }
  476. spin_lock(&uart->port.lock);
  477. irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
  478. clear_dma_irqstat(uart->rx_dma_channel);
  479. spin_unlock(&uart->port.lock);
  480. return IRQ_HANDLED;
  481. }
  482. #endif
  483. /*
  484. * Return TIOCSER_TEMT when transmitter is not busy.
  485. */
  486. static unsigned int bfin_serial_tx_empty(struct uart_port *port)
  487. {
  488. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  489. unsigned short lsr;
  490. lsr = UART_GET_LSR(uart);
  491. if (lsr & TEMT)
  492. return TIOCSER_TEMT;
  493. else
  494. return 0;
  495. }
  496. static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
  497. {
  498. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  499. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  500. if (uart->cts_pin < 0)
  501. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  502. # ifdef BF54x
  503. if (UART_GET_MSR(uart) & CTS)
  504. # else
  505. if (gpio_get_value(uart->cts_pin))
  506. # endif
  507. return TIOCM_DSR | TIOCM_CAR;
  508. else
  509. #endif
  510. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  511. }
  512. static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  513. {
  514. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  515. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  516. if (uart->rts_pin < 0)
  517. return;
  518. if (mctrl & TIOCM_RTS)
  519. # ifdef BF54x
  520. UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS);
  521. # else
  522. gpio_set_value(uart->rts_pin, 0);
  523. # endif
  524. else
  525. # ifdef BF54x
  526. UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS);
  527. # else
  528. gpio_set_value(uart->rts_pin, 1);
  529. # endif
  530. #endif
  531. }
  532. /*
  533. * Handle any change of modem status signal since we were last called.
  534. */
  535. static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
  536. {
  537. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  538. unsigned int status;
  539. struct uart_info *info = uart->port.info;
  540. struct tty_struct *tty = info->tty;
  541. status = bfin_serial_get_mctrl(&uart->port);
  542. uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
  543. if (!(status & TIOCM_CTS)) {
  544. tty->hw_stopped = 1;
  545. schedule_work(&uart->cts_workqueue);
  546. } else {
  547. tty->hw_stopped = 0;
  548. }
  549. #endif
  550. }
  551. /*
  552. * Interrupts are always disabled.
  553. */
  554. static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
  555. {
  556. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  557. u16 lcr = UART_GET_LCR(uart);
  558. if (break_state)
  559. lcr |= SB;
  560. else
  561. lcr &= ~SB;
  562. UART_PUT_LCR(uart, lcr);
  563. SSYNC();
  564. }
  565. static int bfin_serial_startup(struct uart_port *port)
  566. {
  567. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  568. #ifdef CONFIG_SERIAL_BFIN_DMA
  569. dma_addr_t dma_handle;
  570. if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
  571. printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
  572. return -EBUSY;
  573. }
  574. if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
  575. printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
  576. free_dma(uart->rx_dma_channel);
  577. return -EBUSY;
  578. }
  579. set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
  580. set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
  581. uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
  582. uart->rx_dma_buf.head = 0;
  583. uart->rx_dma_buf.tail = 0;
  584. uart->rx_dma_nrows = 0;
  585. set_dma_config(uart->rx_dma_channel,
  586. set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
  587. INTR_ON_ROW, DIMENSION_2D,
  588. DATA_SIZE_8,
  589. DMA_SYNC_RESTART));
  590. set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
  591. set_dma_x_modify(uart->rx_dma_channel, 1);
  592. set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
  593. set_dma_y_modify(uart->rx_dma_channel, 1);
  594. set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
  595. enable_dma(uart->rx_dma_channel);
  596. uart->rx_dma_timer.data = (unsigned long)(uart);
  597. uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
  598. uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
  599. add_timer(&(uart->rx_dma_timer));
  600. #else
  601. if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
  602. "BFIN_UART_RX", uart)) {
  603. # ifdef CONFIG_KGDB_UART
  604. if (uart->port.line != CONFIG_KGDB_UART_PORT) {
  605. # endif
  606. printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
  607. return -EBUSY;
  608. # ifdef CONFIG_KGDB_UART
  609. }
  610. # endif
  611. }
  612. if (request_irq
  613. (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
  614. "BFIN_UART_TX", uart)) {
  615. printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
  616. free_irq(uart->port.irq, uart);
  617. return -EBUSY;
  618. }
  619. #endif
  620. #ifdef CONFIG_BF54x
  621. UART_SET_IER(uart, ERBFI);
  622. #else
  623. UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
  624. #endif
  625. return 0;
  626. }
  627. static void bfin_serial_shutdown(struct uart_port *port)
  628. {
  629. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  630. #ifdef CONFIG_SERIAL_BFIN_DMA
  631. disable_dma(uart->tx_dma_channel);
  632. free_dma(uart->tx_dma_channel);
  633. disable_dma(uart->rx_dma_channel);
  634. free_dma(uart->rx_dma_channel);
  635. del_timer(&(uart->rx_dma_timer));
  636. dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
  637. #else
  638. #ifdef CONFIG_KGDB_UART
  639. if (uart->port.line != CONFIG_KGDB_UART_PORT)
  640. #endif
  641. free_irq(uart->port.irq, uart);
  642. free_irq(uart->port.irq+1, uart);
  643. #endif
  644. }
  645. static void
  646. bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
  647. struct ktermios *old)
  648. {
  649. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  650. unsigned long flags;
  651. unsigned int baud, quot;
  652. unsigned short val, ier, lsr, lcr = 0;
  653. switch (termios->c_cflag & CSIZE) {
  654. case CS8:
  655. lcr = WLS(8);
  656. break;
  657. case CS7:
  658. lcr = WLS(7);
  659. break;
  660. case CS6:
  661. lcr = WLS(6);
  662. break;
  663. case CS5:
  664. lcr = WLS(5);
  665. break;
  666. default:
  667. printk(KERN_ERR "%s: word lengh not supported\n",
  668. __FUNCTION__);
  669. }
  670. if (termios->c_cflag & CSTOPB)
  671. lcr |= STB;
  672. if (termios->c_cflag & PARENB)
  673. lcr |= PEN;
  674. if (!(termios->c_cflag & PARODD))
  675. lcr |= EPS;
  676. if (termios->c_cflag & CMSPAR)
  677. lcr |= STP;
  678. port->read_status_mask = OE;
  679. if (termios->c_iflag & INPCK)
  680. port->read_status_mask |= (FE | PE);
  681. if (termios->c_iflag & (BRKINT | PARMRK))
  682. port->read_status_mask |= BI;
  683. /*
  684. * Characters to ignore
  685. */
  686. port->ignore_status_mask = 0;
  687. if (termios->c_iflag & IGNPAR)
  688. port->ignore_status_mask |= FE | PE;
  689. if (termios->c_iflag & IGNBRK) {
  690. port->ignore_status_mask |= BI;
  691. /*
  692. * If we're ignoring parity and break indicators,
  693. * ignore overruns too (for real raw support).
  694. */
  695. if (termios->c_iflag & IGNPAR)
  696. port->ignore_status_mask |= OE;
  697. }
  698. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  699. quot = uart_get_divisor(port, baud);
  700. spin_lock_irqsave(&uart->port.lock, flags);
  701. UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
  702. do {
  703. lsr = UART_GET_LSR(uart);
  704. } while (!(lsr & TEMT));
  705. /* Disable UART */
  706. ier = UART_GET_IER(uart);
  707. #ifdef CONFIG_BF54x
  708. UART_CLEAR_IER(uart, 0xF);
  709. #else
  710. UART_PUT_IER(uart, 0);
  711. #endif
  712. #ifndef CONFIG_BF54x
  713. /* Set DLAB in LCR to Access DLL and DLH */
  714. val = UART_GET_LCR(uart);
  715. val |= DLAB;
  716. UART_PUT_LCR(uart, val);
  717. SSYNC();
  718. #endif
  719. UART_PUT_DLL(uart, quot & 0xFF);
  720. SSYNC();
  721. UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
  722. SSYNC();
  723. #ifndef CONFIG_BF54x
  724. /* Clear DLAB in LCR to Access THR RBR IER */
  725. val = UART_GET_LCR(uart);
  726. val &= ~DLAB;
  727. UART_PUT_LCR(uart, val);
  728. SSYNC();
  729. #endif
  730. UART_PUT_LCR(uart, lcr);
  731. /* Enable UART */
  732. #ifdef CONFIG_BF54x
  733. UART_SET_IER(uart, ier);
  734. #else
  735. UART_PUT_IER(uart, ier);
  736. #endif
  737. val = UART_GET_GCTL(uart);
  738. val |= UCEN;
  739. UART_PUT_GCTL(uart, val);
  740. spin_unlock_irqrestore(&uart->port.lock, flags);
  741. }
  742. static const char *bfin_serial_type(struct uart_port *port)
  743. {
  744. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  745. return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
  746. }
  747. /*
  748. * Release the memory region(s) being used by 'port'.
  749. */
  750. static void bfin_serial_release_port(struct uart_port *port)
  751. {
  752. }
  753. /*
  754. * Request the memory region(s) being used by 'port'.
  755. */
  756. static int bfin_serial_request_port(struct uart_port *port)
  757. {
  758. return 0;
  759. }
  760. /*
  761. * Configure/autoconfigure the port.
  762. */
  763. static void bfin_serial_config_port(struct uart_port *port, int flags)
  764. {
  765. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  766. if (flags & UART_CONFIG_TYPE &&
  767. bfin_serial_request_port(&uart->port) == 0)
  768. uart->port.type = PORT_BFIN;
  769. }
  770. /*
  771. * Verify the new serial_struct (for TIOCSSERIAL).
  772. * The only change we allow are to the flags and type, and
  773. * even then only between PORT_BFIN and PORT_UNKNOWN
  774. */
  775. static int
  776. bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
  777. {
  778. return 0;
  779. }
  780. static struct uart_ops bfin_serial_pops = {
  781. .tx_empty = bfin_serial_tx_empty,
  782. .set_mctrl = bfin_serial_set_mctrl,
  783. .get_mctrl = bfin_serial_get_mctrl,
  784. .stop_tx = bfin_serial_stop_tx,
  785. .start_tx = bfin_serial_start_tx,
  786. .stop_rx = bfin_serial_stop_rx,
  787. .enable_ms = bfin_serial_enable_ms,
  788. .break_ctl = bfin_serial_break_ctl,
  789. .startup = bfin_serial_startup,
  790. .shutdown = bfin_serial_shutdown,
  791. .set_termios = bfin_serial_set_termios,
  792. .type = bfin_serial_type,
  793. .release_port = bfin_serial_release_port,
  794. .request_port = bfin_serial_request_port,
  795. .config_port = bfin_serial_config_port,
  796. .verify_port = bfin_serial_verify_port,
  797. };
  798. static void __init bfin_serial_init_ports(void)
  799. {
  800. static int first = 1;
  801. int i;
  802. if (!first)
  803. return;
  804. first = 0;
  805. for (i = 0; i < nr_ports; i++) {
  806. bfin_serial_ports[i].port.uartclk = get_sclk();
  807. bfin_serial_ports[i].port.ops = &bfin_serial_pops;
  808. bfin_serial_ports[i].port.line = i;
  809. bfin_serial_ports[i].port.iotype = UPIO_MEM;
  810. bfin_serial_ports[i].port.membase =
  811. (void __iomem *)bfin_serial_resource[i].uart_base_addr;
  812. bfin_serial_ports[i].port.mapbase =
  813. bfin_serial_resource[i].uart_base_addr;
  814. bfin_serial_ports[i].port.irq =
  815. bfin_serial_resource[i].uart_irq;
  816. bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
  817. #ifdef CONFIG_SERIAL_BFIN_DMA
  818. bfin_serial_ports[i].tx_done = 1;
  819. bfin_serial_ports[i].tx_count = 0;
  820. bfin_serial_ports[i].tx_dma_channel =
  821. bfin_serial_resource[i].uart_tx_dma_channel;
  822. bfin_serial_ports[i].rx_dma_channel =
  823. bfin_serial_resource[i].uart_rx_dma_channel;
  824. init_timer(&(bfin_serial_ports[i].rx_dma_timer));
  825. #endif
  826. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  827. INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
  828. bfin_serial_ports[i].cts_pin =
  829. bfin_serial_resource[i].uart_cts_pin;
  830. bfin_serial_ports[i].rts_pin =
  831. bfin_serial_resource[i].uart_rts_pin;
  832. #endif
  833. bfin_serial_hw_init(&bfin_serial_ports[i]);
  834. }
  835. }
  836. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  837. /*
  838. * If the port was already initialised (eg, by a boot loader),
  839. * try to determine the current setup.
  840. */
  841. static void __init
  842. bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
  843. int *parity, int *bits)
  844. {
  845. unsigned short status;
  846. status = UART_GET_IER(uart) & (ERBFI | ETBEI);
  847. if (status == (ERBFI | ETBEI)) {
  848. /* ok, the port was enabled */
  849. unsigned short lcr, val;
  850. unsigned short dlh, dll;
  851. lcr = UART_GET_LCR(uart);
  852. *parity = 'n';
  853. if (lcr & PEN) {
  854. if (lcr & EPS)
  855. *parity = 'e';
  856. else
  857. *parity = 'o';
  858. }
  859. switch (lcr & 0x03) {
  860. case 0: *bits = 5; break;
  861. case 1: *bits = 6; break;
  862. case 2: *bits = 7; break;
  863. case 3: *bits = 8; break;
  864. }
  865. #ifndef CONFIG_BF54x
  866. /* Set DLAB in LCR to Access DLL and DLH */
  867. val = UART_GET_LCR(uart);
  868. val |= DLAB;
  869. UART_PUT_LCR(uart, val);
  870. #endif
  871. dll = UART_GET_DLL(uart);
  872. dlh = UART_GET_DLH(uart);
  873. #ifndef CONFIG_BF54x
  874. /* Clear DLAB in LCR to Access THR RBR IER */
  875. val = UART_GET_LCR(uart);
  876. val &= ~DLAB;
  877. UART_PUT_LCR(uart, val);
  878. #endif
  879. *baud = get_sclk() / (16*(dll | dlh << 8));
  880. }
  881. pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits);
  882. }
  883. #endif
  884. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  885. static struct uart_driver bfin_serial_reg;
  886. static int __init
  887. bfin_serial_console_setup(struct console *co, char *options)
  888. {
  889. struct bfin_serial_port *uart;
  890. # ifdef CONFIG_SERIAL_BFIN_CONSOLE
  891. int baud = 57600;
  892. int bits = 8;
  893. int parity = 'n';
  894. # ifdef CONFIG_SERIAL_BFIN_CTSRTS
  895. int flow = 'r';
  896. # else
  897. int flow = 'n';
  898. # endif
  899. # endif
  900. /*
  901. * Check whether an invalid uart number has been specified, and
  902. * if so, search for the first available port that does have
  903. * console support.
  904. */
  905. if (co->index == -1 || co->index >= nr_ports)
  906. co->index = 0;
  907. uart = &bfin_serial_ports[co->index];
  908. # ifdef CONFIG_SERIAL_BFIN_CONSOLE
  909. if (options)
  910. uart_parse_options(options, &baud, &parity, &bits, &flow);
  911. else
  912. bfin_serial_console_get_options(uart, &baud, &parity, &bits);
  913. return uart_set_options(&uart->port, co, baud, parity, bits, flow);
  914. # else
  915. return 0;
  916. # endif
  917. }
  918. #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
  919. defined (CONFIG_EARLY_PRINTK) */
  920. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  921. static void bfin_serial_console_putchar(struct uart_port *port, int ch)
  922. {
  923. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  924. while (!(UART_GET_LSR(uart) & THRE))
  925. barrier();
  926. UART_PUT_CHAR(uart, ch);
  927. SSYNC();
  928. }
  929. /*
  930. * Interrupts are disabled on entering
  931. */
  932. static void
  933. bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
  934. {
  935. struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
  936. int flags = 0;
  937. spin_lock_irqsave(&uart->port.lock, flags);
  938. uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
  939. spin_unlock_irqrestore(&uart->port.lock, flags);
  940. }
  941. static struct console bfin_serial_console = {
  942. .name = BFIN_SERIAL_NAME,
  943. .write = bfin_serial_console_write,
  944. .device = uart_console_device,
  945. .setup = bfin_serial_console_setup,
  946. .flags = CON_PRINTBUFFER,
  947. .index = -1,
  948. .data = &bfin_serial_reg,
  949. };
  950. static int __init bfin_serial_rs_console_init(void)
  951. {
  952. bfin_serial_init_ports();
  953. register_console(&bfin_serial_console);
  954. #ifdef CONFIG_KGDB_UART
  955. kgdb_entry_state = 0;
  956. init_kgdb_uart();
  957. #endif
  958. return 0;
  959. }
  960. console_initcall(bfin_serial_rs_console_init);
  961. #define BFIN_SERIAL_CONSOLE &bfin_serial_console
  962. #else
  963. #define BFIN_SERIAL_CONSOLE NULL
  964. #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
  965. #ifdef CONFIG_EARLY_PRINTK
  966. static __init void early_serial_putc(struct uart_port *port, int ch)
  967. {
  968. unsigned timeout = 0xffff;
  969. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  970. while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
  971. cpu_relax();
  972. UART_PUT_CHAR(uart, ch);
  973. }
  974. static __init void early_serial_write(struct console *con, const char *s,
  975. unsigned int n)
  976. {
  977. struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
  978. unsigned int i;
  979. for (i = 0; i < n; i++, s++) {
  980. if (*s == '\n')
  981. early_serial_putc(&uart->port, '\r');
  982. early_serial_putc(&uart->port, *s);
  983. }
  984. }
  985. static struct __init console bfin_early_serial_console = {
  986. .name = "early_BFuart",
  987. .write = early_serial_write,
  988. .device = uart_console_device,
  989. .flags = CON_PRINTBUFFER,
  990. .setup = bfin_serial_console_setup,
  991. .index = -1,
  992. .data = &bfin_serial_reg,
  993. };
  994. struct console __init *bfin_earlyserial_init(unsigned int port,
  995. unsigned int cflag)
  996. {
  997. struct bfin_serial_port *uart;
  998. struct ktermios t;
  999. if (port == -1 || port >= nr_ports)
  1000. port = 0;
  1001. bfin_serial_init_ports();
  1002. bfin_early_serial_console.index = port;
  1003. uart = &bfin_serial_ports[port];
  1004. t.c_cflag = cflag;
  1005. t.c_iflag = 0;
  1006. t.c_oflag = 0;
  1007. t.c_lflag = ICANON;
  1008. t.c_line = port;
  1009. bfin_serial_set_termios(&uart->port, &t, &t);
  1010. return &bfin_early_serial_console;
  1011. }
  1012. #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
  1013. static struct uart_driver bfin_serial_reg = {
  1014. .owner = THIS_MODULE,
  1015. .driver_name = "bfin-uart",
  1016. .dev_name = BFIN_SERIAL_NAME,
  1017. .major = BFIN_SERIAL_MAJOR,
  1018. .minor = BFIN_SERIAL_MINOR,
  1019. .nr = NR_PORTS,
  1020. .cons = BFIN_SERIAL_CONSOLE,
  1021. };
  1022. static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
  1023. {
  1024. struct bfin_serial_port *uart = platform_get_drvdata(dev);
  1025. if (uart)
  1026. uart_suspend_port(&bfin_serial_reg, &uart->port);
  1027. return 0;
  1028. }
  1029. static int bfin_serial_resume(struct platform_device *dev)
  1030. {
  1031. struct bfin_serial_port *uart = platform_get_drvdata(dev);
  1032. if (uart)
  1033. uart_resume_port(&bfin_serial_reg, &uart->port);
  1034. return 0;
  1035. }
  1036. static int bfin_serial_probe(struct platform_device *dev)
  1037. {
  1038. struct resource *res = dev->resource;
  1039. int i;
  1040. for (i = 0; i < dev->num_resources; i++, res++)
  1041. if (res->flags & IORESOURCE_MEM)
  1042. break;
  1043. if (i < dev->num_resources) {
  1044. for (i = 0; i < nr_ports; i++, res++) {
  1045. if (bfin_serial_ports[i].port.mapbase != res->start)
  1046. continue;
  1047. bfin_serial_ports[i].port.dev = &dev->dev;
  1048. uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
  1049. platform_set_drvdata(dev, &bfin_serial_ports[i]);
  1050. }
  1051. }
  1052. return 0;
  1053. }
  1054. static int bfin_serial_remove(struct platform_device *pdev)
  1055. {
  1056. struct bfin_serial_port *uart = platform_get_drvdata(pdev);
  1057. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  1058. gpio_free(uart->cts_pin);
  1059. gpio_free(uart->rts_pin);
  1060. #endif
  1061. platform_set_drvdata(pdev, NULL);
  1062. if (uart)
  1063. uart_remove_one_port(&bfin_serial_reg, &uart->port);
  1064. return 0;
  1065. }
  1066. static struct platform_driver bfin_serial_driver = {
  1067. .probe = bfin_serial_probe,
  1068. .remove = bfin_serial_remove,
  1069. .suspend = bfin_serial_suspend,
  1070. .resume = bfin_serial_resume,
  1071. .driver = {
  1072. .name = "bfin-uart",
  1073. },
  1074. };
  1075. static int __init bfin_serial_init(void)
  1076. {
  1077. int ret;
  1078. #ifdef CONFIG_KGDB_UART
  1079. struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
  1080. struct ktermios t;
  1081. #endif
  1082. pr_info("Serial: Blackfin serial driver\n");
  1083. bfin_serial_init_ports();
  1084. ret = uart_register_driver(&bfin_serial_reg);
  1085. if (ret == 0) {
  1086. ret = platform_driver_register(&bfin_serial_driver);
  1087. if (ret) {
  1088. pr_debug("uart register failed\n");
  1089. uart_unregister_driver(&bfin_serial_reg);
  1090. }
  1091. }
  1092. #ifdef CONFIG_KGDB_UART
  1093. if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
  1094. request_irq(uart->port.irq, bfin_serial_rx_int,
  1095. IRQF_DISABLED, "BFIN_UART_RX", uart);
  1096. pr_info("Request irq for kgdb uart port\n");
  1097. #ifdef CONFIG_BF54x
  1098. UART_SET_IER(uart, ERBFI);
  1099. #else
  1100. UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
  1101. #endif
  1102. SSYNC();
  1103. t.c_cflag = CS8|B57600;
  1104. t.c_iflag = 0;
  1105. t.c_oflag = 0;
  1106. t.c_lflag = ICANON;
  1107. t.c_line = CONFIG_KGDB_UART_PORT;
  1108. bfin_serial_set_termios(&uart->port, &t, &t);
  1109. }
  1110. #endif
  1111. return ret;
  1112. }
  1113. static void __exit bfin_serial_exit(void)
  1114. {
  1115. platform_driver_unregister(&bfin_serial_driver);
  1116. uart_unregister_driver(&bfin_serial_reg);
  1117. }
  1118. module_init(bfin_serial_init);
  1119. module_exit(bfin_serial_exit);
  1120. MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
  1121. MODULE_DESCRIPTION("Blackfin generic serial port driver");
  1122. MODULE_LICENSE("GPL");
  1123. MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);