sh_clk.h 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160
  1. #ifndef __SH_CLOCK_H
  2. #define __SH_CLOCK_H
  3. #include <linux/list.h>
  4. #include <linux/seq_file.h>
  5. #include <linux/cpufreq.h>
  6. #include <linux/types.h>
  7. #include <linux/kref.h>
  8. #include <linux/clk.h>
  9. #include <linux/err.h>
  10. struct clk;
  11. struct clk_mapping {
  12. phys_addr_t phys;
  13. void __iomem *base;
  14. unsigned long len;
  15. struct kref ref;
  16. };
  17. struct clk_ops {
  18. #ifdef CONFIG_SH_CLK_CPG_LEGACY
  19. void (*init)(struct clk *clk);
  20. #endif
  21. int (*enable)(struct clk *clk);
  22. void (*disable)(struct clk *clk);
  23. unsigned long (*recalc)(struct clk *clk);
  24. int (*set_rate)(struct clk *clk, unsigned long rate);
  25. int (*set_parent)(struct clk *clk, struct clk *parent);
  26. long (*round_rate)(struct clk *clk, unsigned long rate);
  27. };
  28. struct clk {
  29. struct list_head node;
  30. struct clk *parent;
  31. struct clk **parent_table; /* list of parents to */
  32. unsigned short parent_num; /* choose between */
  33. unsigned char src_shift; /* source clock field in the */
  34. unsigned char src_width; /* configuration register */
  35. struct clk_ops *ops;
  36. struct list_head children;
  37. struct list_head sibling; /* node for children */
  38. int usecount;
  39. unsigned long rate;
  40. unsigned long flags;
  41. void __iomem *enable_reg;
  42. unsigned int enable_bit;
  43. void __iomem *mapped_reg;
  44. unsigned long arch_flags;
  45. void *priv;
  46. struct clk_mapping *mapping;
  47. struct cpufreq_frequency_table *freq_table;
  48. unsigned int nr_freqs;
  49. };
  50. #define CLK_ENABLE_ON_INIT (1 << 0)
  51. /* drivers/sh/clk.c */
  52. unsigned long followparent_recalc(struct clk *);
  53. void recalculate_root_clocks(void);
  54. void propagate_rate(struct clk *);
  55. int clk_reparent(struct clk *child, struct clk *parent);
  56. int clk_register(struct clk *);
  57. void clk_unregister(struct clk *);
  58. void clk_enable_init_clocks(void);
  59. struct clk_div_mult_table {
  60. unsigned int *divisors;
  61. unsigned int nr_divisors;
  62. unsigned int *multipliers;
  63. unsigned int nr_multipliers;
  64. };
  65. struct cpufreq_frequency_table;
  66. void clk_rate_table_build(struct clk *clk,
  67. struct cpufreq_frequency_table *freq_table,
  68. int nr_freqs,
  69. struct clk_div_mult_table *src_table,
  70. unsigned long *bitmap);
  71. long clk_rate_table_round(struct clk *clk,
  72. struct cpufreq_frequency_table *freq_table,
  73. unsigned long rate);
  74. int clk_rate_table_find(struct clk *clk,
  75. struct cpufreq_frequency_table *freq_table,
  76. unsigned long rate);
  77. long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
  78. unsigned int div_max, unsigned long rate);
  79. long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
  80. unsigned int mult_max, unsigned long rate);
  81. long clk_round_parent(struct clk *clk, unsigned long target,
  82. unsigned long *best_freq, unsigned long *parent_freq,
  83. unsigned int div_min, unsigned int div_max);
  84. #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
  85. { \
  86. .parent = _parent, \
  87. .enable_reg = (void __iomem *)_enable_reg, \
  88. .enable_bit = _enable_bit, \
  89. .flags = _flags, \
  90. }
  91. int sh_clk_mstp32_register(struct clk *clks, int nr);
  92. #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
  93. { \
  94. .parent = _parent, \
  95. .enable_reg = (void __iomem *)_reg, \
  96. .enable_bit = _shift, \
  97. .arch_flags = _div_bitmap, \
  98. .flags = _flags, \
  99. }
  100. struct clk_div4_table {
  101. struct clk_div_mult_table *div_mult_table;
  102. void (*kick)(struct clk *clk);
  103. };
  104. int sh_clk_div4_register(struct clk *clks, int nr,
  105. struct clk_div4_table *table);
  106. int sh_clk_div4_enable_register(struct clk *clks, int nr,
  107. struct clk_div4_table *table);
  108. int sh_clk_div4_reparent_register(struct clk *clks, int nr,
  109. struct clk_div4_table *table);
  110. #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
  111. _num_parents, _src_shift, _src_width) \
  112. { \
  113. .enable_reg = (void __iomem *)_reg, \
  114. .flags = _flags, \
  115. .parent_table = _parents, \
  116. .parent_num = _num_parents, \
  117. .src_shift = _src_shift, \
  118. .src_width = _src_width, \
  119. }
  120. #define SH_CLK_DIV6(_parent, _reg, _flags) \
  121. { \
  122. .parent = _parent, \
  123. .enable_reg = (void __iomem *)_reg, \
  124. .flags = _flags, \
  125. }
  126. int sh_clk_div6_register(struct clk *clks, int nr);
  127. int sh_clk_div6_reparent_register(struct clk *clks, int nr);
  128. #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
  129. #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
  130. #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
  131. #endif /* __SH_CLOCK_H */