exynos_thermal.c 28 KB

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  1. /*
  2. * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3. *
  4. * Copyright (C) 2011 Samsung Electronics
  5. * Donggeun Kim <dg77.kim@samsung.com>
  6. * Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/err.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/clk.h>
  30. #include <linux/workqueue.h>
  31. #include <linux/sysfs.h>
  32. #include <linux/kobject.h>
  33. #include <linux/io.h>
  34. #include <linux/mutex.h>
  35. #include <linux/platform_data/exynos_thermal.h>
  36. #include <linux/thermal.h>
  37. #include <linux/cpufreq.h>
  38. #include <linux/cpu_cooling.h>
  39. #include <linux/of.h>
  40. /* Exynos generic registers */
  41. #define EXYNOS_TMU_REG_TRIMINFO 0x0
  42. #define EXYNOS_TMU_REG_CONTROL 0x20
  43. #define EXYNOS_TMU_REG_STATUS 0x28
  44. #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
  45. #define EXYNOS_TMU_REG_INTEN 0x70
  46. #define EXYNOS_TMU_REG_INTSTAT 0x74
  47. #define EXYNOS_TMU_REG_INTCLEAR 0x78
  48. #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
  49. #define EXYNOS_TMU_GAIN_SHIFT 8
  50. #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
  51. #define EXYNOS_TMU_CORE_ON 3
  52. #define EXYNOS_TMU_CORE_OFF 2
  53. #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
  54. /* Exynos4210 specific registers */
  55. #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
  56. #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
  57. #define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
  58. #define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
  59. #define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
  60. #define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
  61. #define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
  62. #define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
  63. #define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
  64. #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
  65. #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
  66. #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
  67. #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
  68. #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
  69. /* Exynos5250 and Exynos4412 specific registers */
  70. #define EXYNOS_TMU_TRIMINFO_CON 0x14
  71. #define EXYNOS_THD_TEMP_RISE 0x50
  72. #define EXYNOS_THD_TEMP_FALL 0x54
  73. #define EXYNOS_EMUL_CON 0x80
  74. #define EXYNOS_TRIMINFO_RELOAD 0x1
  75. #define EXYNOS_TMU_CLEAR_RISE_INT 0x111
  76. #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
  77. #define EXYNOS_MUX_ADDR_VALUE 6
  78. #define EXYNOS_MUX_ADDR_SHIFT 20
  79. #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
  80. #define EFUSE_MIN_VALUE 40
  81. #define EFUSE_MAX_VALUE 100
  82. /* In-kernel thermal framework related macros & definations */
  83. #define SENSOR_NAME_LEN 16
  84. #define MAX_TRIP_COUNT 8
  85. #define MAX_COOLING_DEVICE 4
  86. #define MAX_THRESHOLD_LEVS 4
  87. #define ACTIVE_INTERVAL 500
  88. #define IDLE_INTERVAL 10000
  89. #define MCELSIUS 1000
  90. #ifdef CONFIG_EXYNOS_THERMAL_EMUL
  91. #define EXYNOS_EMUL_TIME 0x57F0
  92. #define EXYNOS_EMUL_TIME_SHIFT 16
  93. #define EXYNOS_EMUL_DATA_SHIFT 8
  94. #define EXYNOS_EMUL_DATA_MASK 0xFF
  95. #define EXYNOS_EMUL_ENABLE 0x1
  96. #endif /* CONFIG_EXYNOS_THERMAL_EMUL */
  97. /* CPU Zone information */
  98. #define PANIC_ZONE 4
  99. #define WARN_ZONE 3
  100. #define MONITOR_ZONE 2
  101. #define SAFE_ZONE 1
  102. #define GET_ZONE(trip) (trip + 2)
  103. #define GET_TRIP(zone) (zone - 2)
  104. #define EXYNOS_ZONE_COUNT 3
  105. struct exynos_tmu_data {
  106. struct exynos_tmu_platform_data *pdata;
  107. struct resource *mem;
  108. void __iomem *base;
  109. int irq;
  110. enum soc_type soc;
  111. struct work_struct irq_work;
  112. struct mutex lock;
  113. struct clk *clk;
  114. u8 temp_error1, temp_error2;
  115. };
  116. struct thermal_trip_point_conf {
  117. int trip_val[MAX_TRIP_COUNT];
  118. int trip_count;
  119. u8 trigger_falling;
  120. };
  121. struct thermal_cooling_conf {
  122. struct freq_clip_table freq_data[MAX_TRIP_COUNT];
  123. int freq_clip_count;
  124. };
  125. struct thermal_sensor_conf {
  126. char name[SENSOR_NAME_LEN];
  127. int (*read_temperature)(void *data);
  128. struct thermal_trip_point_conf trip_data;
  129. struct thermal_cooling_conf cooling_data;
  130. void *private_data;
  131. };
  132. struct exynos_thermal_zone {
  133. enum thermal_device_mode mode;
  134. struct thermal_zone_device *therm_dev;
  135. struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
  136. unsigned int cool_dev_size;
  137. struct platform_device *exynos4_dev;
  138. struct thermal_sensor_conf *sensor_conf;
  139. bool bind;
  140. };
  141. static struct exynos_thermal_zone *th_zone;
  142. static void exynos_unregister_thermal(void);
  143. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
  144. /* Get mode callback functions for thermal zone */
  145. static int exynos_get_mode(struct thermal_zone_device *thermal,
  146. enum thermal_device_mode *mode)
  147. {
  148. if (th_zone)
  149. *mode = th_zone->mode;
  150. return 0;
  151. }
  152. /* Set mode callback functions for thermal zone */
  153. static int exynos_set_mode(struct thermal_zone_device *thermal,
  154. enum thermal_device_mode mode)
  155. {
  156. if (!th_zone->therm_dev) {
  157. pr_notice("thermal zone not registered\n");
  158. return 0;
  159. }
  160. mutex_lock(&th_zone->therm_dev->lock);
  161. if (mode == THERMAL_DEVICE_ENABLED &&
  162. !th_zone->sensor_conf->trip_data.trigger_falling)
  163. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  164. else
  165. th_zone->therm_dev->polling_delay = 0;
  166. mutex_unlock(&th_zone->therm_dev->lock);
  167. th_zone->mode = mode;
  168. thermal_zone_device_update(th_zone->therm_dev);
  169. pr_info("thermal polling set for duration=%d msec\n",
  170. th_zone->therm_dev->polling_delay);
  171. return 0;
  172. }
  173. /* Get trip type callback functions for thermal zone */
  174. static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
  175. enum thermal_trip_type *type)
  176. {
  177. switch (GET_ZONE(trip)) {
  178. case MONITOR_ZONE:
  179. case WARN_ZONE:
  180. *type = THERMAL_TRIP_ACTIVE;
  181. break;
  182. case PANIC_ZONE:
  183. *type = THERMAL_TRIP_CRITICAL;
  184. break;
  185. default:
  186. return -EINVAL;
  187. }
  188. return 0;
  189. }
  190. /* Get trip temperature callback functions for thermal zone */
  191. static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
  192. unsigned long *temp)
  193. {
  194. if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
  195. return -EINVAL;
  196. *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
  197. /* convert the temperature into millicelsius */
  198. *temp = *temp * MCELSIUS;
  199. return 0;
  200. }
  201. /* Get critical temperature callback functions for thermal zone */
  202. static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
  203. unsigned long *temp)
  204. {
  205. int ret;
  206. /* Panic zone */
  207. ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
  208. return ret;
  209. }
  210. static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
  211. {
  212. int i = 0, ret = -EINVAL;
  213. struct cpufreq_frequency_table *table = NULL;
  214. #ifdef CONFIG_CPU_FREQ
  215. table = cpufreq_frequency_get_table(cpu);
  216. #endif
  217. if (!table)
  218. return ret;
  219. while (table[i].frequency != CPUFREQ_TABLE_END) {
  220. if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
  221. continue;
  222. if (table[i].frequency == freq)
  223. return i;
  224. i++;
  225. }
  226. return ret;
  227. }
  228. /* Bind callback functions for thermal zone */
  229. static int exynos_bind(struct thermal_zone_device *thermal,
  230. struct thermal_cooling_device *cdev)
  231. {
  232. int ret = 0, i, tab_size, level;
  233. struct freq_clip_table *tab_ptr, *clip_data;
  234. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  235. tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
  236. tab_size = data->cooling_data.freq_clip_count;
  237. if (tab_ptr == NULL || tab_size == 0)
  238. return -EINVAL;
  239. /* find the cooling device registered*/
  240. for (i = 0; i < th_zone->cool_dev_size; i++)
  241. if (cdev == th_zone->cool_dev[i])
  242. break;
  243. /* No matching cooling device */
  244. if (i == th_zone->cool_dev_size)
  245. return 0;
  246. /* Bind the thermal zone to the cpufreq cooling device */
  247. for (i = 0; i < tab_size; i++) {
  248. clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
  249. level = exynos_get_frequency_level(0, clip_data->freq_clip_max);
  250. if (level < 0)
  251. return 0;
  252. switch (GET_ZONE(i)) {
  253. case MONITOR_ZONE:
  254. case WARN_ZONE:
  255. if (thermal_zone_bind_cooling_device(thermal, i, cdev,
  256. level, 0)) {
  257. pr_err("error binding cdev inst %d\n", i);
  258. ret = -EINVAL;
  259. }
  260. th_zone->bind = true;
  261. break;
  262. default:
  263. ret = -EINVAL;
  264. }
  265. }
  266. return ret;
  267. }
  268. /* Unbind callback functions for thermal zone */
  269. static int exynos_unbind(struct thermal_zone_device *thermal,
  270. struct thermal_cooling_device *cdev)
  271. {
  272. int ret = 0, i, tab_size;
  273. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  274. if (th_zone->bind == false)
  275. return 0;
  276. tab_size = data->cooling_data.freq_clip_count;
  277. if (tab_size == 0)
  278. return -EINVAL;
  279. /* find the cooling device registered*/
  280. for (i = 0; i < th_zone->cool_dev_size; i++)
  281. if (cdev == th_zone->cool_dev[i])
  282. break;
  283. /* No matching cooling device */
  284. if (i == th_zone->cool_dev_size)
  285. return 0;
  286. /* Bind the thermal zone to the cpufreq cooling device */
  287. for (i = 0; i < tab_size; i++) {
  288. switch (GET_ZONE(i)) {
  289. case MONITOR_ZONE:
  290. case WARN_ZONE:
  291. if (thermal_zone_unbind_cooling_device(thermal, i,
  292. cdev)) {
  293. pr_err("error unbinding cdev inst=%d\n", i);
  294. ret = -EINVAL;
  295. }
  296. th_zone->bind = false;
  297. break;
  298. default:
  299. ret = -EINVAL;
  300. }
  301. }
  302. return ret;
  303. }
  304. /* Get temperature callback functions for thermal zone */
  305. static int exynos_get_temp(struct thermal_zone_device *thermal,
  306. unsigned long *temp)
  307. {
  308. void *data;
  309. if (!th_zone->sensor_conf) {
  310. pr_info("Temperature sensor not initialised\n");
  311. return -EINVAL;
  312. }
  313. data = th_zone->sensor_conf->private_data;
  314. *temp = th_zone->sensor_conf->read_temperature(data);
  315. /* convert the temperature into millicelsius */
  316. *temp = *temp * MCELSIUS;
  317. return 0;
  318. }
  319. /* Get the temperature trend */
  320. static int exynos_get_trend(struct thermal_zone_device *thermal,
  321. int trip, enum thermal_trend *trend)
  322. {
  323. int ret;
  324. unsigned long trip_temp;
  325. ret = exynos_get_trip_temp(thermal, trip, &trip_temp);
  326. if (ret < 0)
  327. return ret;
  328. if (thermal->temperature >= trip_temp)
  329. *trend = THERMAL_TREND_RAISE_FULL;
  330. else
  331. *trend = THERMAL_TREND_DROP_FULL;
  332. return 0;
  333. }
  334. /* Operation callback functions for thermal zone */
  335. static struct thermal_zone_device_ops const exynos_dev_ops = {
  336. .bind = exynos_bind,
  337. .unbind = exynos_unbind,
  338. .get_temp = exynos_get_temp,
  339. .get_trend = exynos_get_trend,
  340. .get_mode = exynos_get_mode,
  341. .set_mode = exynos_set_mode,
  342. .get_trip_type = exynos_get_trip_type,
  343. .get_trip_temp = exynos_get_trip_temp,
  344. .get_crit_temp = exynos_get_crit_temp,
  345. };
  346. /*
  347. * This function may be called from interrupt based temperature sensor
  348. * when threshold is changed.
  349. */
  350. static void exynos_report_trigger(void)
  351. {
  352. unsigned int i;
  353. char data[10];
  354. char *envp[] = { data, NULL };
  355. if (!th_zone || !th_zone->therm_dev)
  356. return;
  357. if (th_zone->bind == false) {
  358. for (i = 0; i < th_zone->cool_dev_size; i++) {
  359. if (!th_zone->cool_dev[i])
  360. continue;
  361. exynos_bind(th_zone->therm_dev,
  362. th_zone->cool_dev[i]);
  363. }
  364. }
  365. thermal_zone_device_update(th_zone->therm_dev);
  366. mutex_lock(&th_zone->therm_dev->lock);
  367. /* Find the level for which trip happened */
  368. for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
  369. if (th_zone->therm_dev->last_temperature <
  370. th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
  371. break;
  372. }
  373. if (th_zone->mode == THERMAL_DEVICE_ENABLED &&
  374. !th_zone->sensor_conf->trip_data.trigger_falling) {
  375. if (i > 0)
  376. th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
  377. else
  378. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  379. }
  380. snprintf(data, sizeof(data), "%u", i);
  381. kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
  382. mutex_unlock(&th_zone->therm_dev->lock);
  383. }
  384. /* Register with the in-kernel thermal management */
  385. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
  386. {
  387. int ret;
  388. struct cpumask mask_val;
  389. if (!sensor_conf || !sensor_conf->read_temperature) {
  390. pr_err("Temperature sensor not initialised\n");
  391. return -EINVAL;
  392. }
  393. th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
  394. if (!th_zone)
  395. return -ENOMEM;
  396. th_zone->sensor_conf = sensor_conf;
  397. cpumask_set_cpu(0, &mask_val);
  398. th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
  399. if (IS_ERR(th_zone->cool_dev[0])) {
  400. pr_err("Failed to register cpufreq cooling device\n");
  401. ret = -EINVAL;
  402. goto err_unregister;
  403. }
  404. th_zone->cool_dev_size++;
  405. th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
  406. EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
  407. sensor_conf->trip_data.trigger_falling ?
  408. 0 : IDLE_INTERVAL);
  409. if (IS_ERR(th_zone->therm_dev)) {
  410. pr_err("Failed to register thermal zone device\n");
  411. ret = PTR_ERR(th_zone->therm_dev);
  412. goto err_unregister;
  413. }
  414. th_zone->mode = THERMAL_DEVICE_ENABLED;
  415. pr_info("Exynos: Kernel Thermal management registered\n");
  416. return 0;
  417. err_unregister:
  418. exynos_unregister_thermal();
  419. return ret;
  420. }
  421. /* Un-Register with the in-kernel thermal management */
  422. static void exynos_unregister_thermal(void)
  423. {
  424. int i;
  425. if (!th_zone)
  426. return;
  427. if (th_zone->therm_dev)
  428. thermal_zone_device_unregister(th_zone->therm_dev);
  429. for (i = 0; i < th_zone->cool_dev_size; i++) {
  430. if (th_zone->cool_dev[i])
  431. cpufreq_cooling_unregister(th_zone->cool_dev[i]);
  432. }
  433. kfree(th_zone);
  434. pr_info("Exynos: Kernel Thermal management unregistered\n");
  435. }
  436. /*
  437. * TMU treats temperature as a mapped temperature code.
  438. * The temperature is converted differently depending on the calibration type.
  439. */
  440. static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
  441. {
  442. struct exynos_tmu_platform_data *pdata = data->pdata;
  443. int temp_code;
  444. if (data->soc == SOC_ARCH_EXYNOS4210)
  445. /* temp should range between 25 and 125 */
  446. if (temp < 25 || temp > 125) {
  447. temp_code = -EINVAL;
  448. goto out;
  449. }
  450. switch (pdata->cal_type) {
  451. case TYPE_TWO_POINT_TRIMMING:
  452. temp_code = (temp - 25) *
  453. (data->temp_error2 - data->temp_error1) /
  454. (85 - 25) + data->temp_error1;
  455. break;
  456. case TYPE_ONE_POINT_TRIMMING:
  457. temp_code = temp + data->temp_error1 - 25;
  458. break;
  459. default:
  460. temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  461. break;
  462. }
  463. out:
  464. return temp_code;
  465. }
  466. /*
  467. * Calculate a temperature value from a temperature code.
  468. * The unit of the temperature is degree Celsius.
  469. */
  470. static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
  471. {
  472. struct exynos_tmu_platform_data *pdata = data->pdata;
  473. int temp;
  474. if (data->soc == SOC_ARCH_EXYNOS4210)
  475. /* temp_code should range between 75 and 175 */
  476. if (temp_code < 75 || temp_code > 175) {
  477. temp = -ENODATA;
  478. goto out;
  479. }
  480. switch (pdata->cal_type) {
  481. case TYPE_TWO_POINT_TRIMMING:
  482. temp = (temp_code - data->temp_error1) * (85 - 25) /
  483. (data->temp_error2 - data->temp_error1) + 25;
  484. break;
  485. case TYPE_ONE_POINT_TRIMMING:
  486. temp = temp_code - data->temp_error1 + 25;
  487. break;
  488. default:
  489. temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  490. break;
  491. }
  492. out:
  493. return temp;
  494. }
  495. static int exynos_tmu_initialize(struct platform_device *pdev)
  496. {
  497. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  498. struct exynos_tmu_platform_data *pdata = data->pdata;
  499. unsigned int status, trim_info;
  500. unsigned int rising_threshold = 0, falling_threshold = 0;
  501. int ret = 0, threshold_code, i, trigger_levs = 0;
  502. mutex_lock(&data->lock);
  503. clk_enable(data->clk);
  504. status = readb(data->base + EXYNOS_TMU_REG_STATUS);
  505. if (!status) {
  506. ret = -EBUSY;
  507. goto out;
  508. }
  509. if (data->soc == SOC_ARCH_EXYNOS) {
  510. __raw_writel(EXYNOS_TRIMINFO_RELOAD,
  511. data->base + EXYNOS_TMU_TRIMINFO_CON);
  512. }
  513. /* Save trimming info in order to perform calibration */
  514. trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
  515. data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
  516. data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
  517. if ((EFUSE_MIN_VALUE > data->temp_error1) ||
  518. (data->temp_error1 > EFUSE_MAX_VALUE) ||
  519. (data->temp_error2 != 0))
  520. data->temp_error1 = pdata->efuse_value;
  521. /* Count trigger levels to be enabled */
  522. for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
  523. if (pdata->trigger_levels[i])
  524. trigger_levs++;
  525. if (data->soc == SOC_ARCH_EXYNOS4210) {
  526. /* Write temperature code for threshold */
  527. threshold_code = temp_to_code(data, pdata->threshold);
  528. if (threshold_code < 0) {
  529. ret = threshold_code;
  530. goto out;
  531. }
  532. writeb(threshold_code,
  533. data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
  534. for (i = 0; i < trigger_levs; i++)
  535. writeb(pdata->trigger_levels[i],
  536. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
  537. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  538. data->base + EXYNOS_TMU_REG_INTCLEAR);
  539. } else if (data->soc == SOC_ARCH_EXYNOS) {
  540. /* Write temperature code for rising and falling threshold */
  541. for (i = 0; i < trigger_levs; i++) {
  542. threshold_code = temp_to_code(data,
  543. pdata->trigger_levels[i]);
  544. if (threshold_code < 0) {
  545. ret = threshold_code;
  546. goto out;
  547. }
  548. rising_threshold |= threshold_code << 8 * i;
  549. if (pdata->threshold_falling) {
  550. threshold_code = temp_to_code(data,
  551. pdata->trigger_levels[i] -
  552. pdata->threshold_falling);
  553. if (threshold_code > 0)
  554. falling_threshold |=
  555. threshold_code << 8 * i;
  556. }
  557. }
  558. writel(rising_threshold,
  559. data->base + EXYNOS_THD_TEMP_RISE);
  560. writel(falling_threshold,
  561. data->base + EXYNOS_THD_TEMP_FALL);
  562. writel(EXYNOS_TMU_CLEAR_RISE_INT | EXYNOS_TMU_CLEAR_FALL_INT,
  563. data->base + EXYNOS_TMU_REG_INTCLEAR);
  564. }
  565. out:
  566. clk_disable(data->clk);
  567. mutex_unlock(&data->lock);
  568. return ret;
  569. }
  570. static void exynos_tmu_control(struct platform_device *pdev, bool on)
  571. {
  572. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  573. struct exynos_tmu_platform_data *pdata = data->pdata;
  574. unsigned int con, interrupt_en;
  575. mutex_lock(&data->lock);
  576. clk_enable(data->clk);
  577. con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
  578. pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
  579. if (data->soc == SOC_ARCH_EXYNOS) {
  580. con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
  581. con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
  582. }
  583. if (on) {
  584. con |= EXYNOS_TMU_CORE_ON;
  585. interrupt_en = pdata->trigger_level3_en << 12 |
  586. pdata->trigger_level2_en << 8 |
  587. pdata->trigger_level1_en << 4 |
  588. pdata->trigger_level0_en;
  589. if (pdata->threshold_falling)
  590. interrupt_en |= interrupt_en << 16;
  591. } else {
  592. con |= EXYNOS_TMU_CORE_OFF;
  593. interrupt_en = 0; /* Disable all interrupts */
  594. }
  595. writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
  596. writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
  597. clk_disable(data->clk);
  598. mutex_unlock(&data->lock);
  599. }
  600. static int exynos_tmu_read(struct exynos_tmu_data *data)
  601. {
  602. u8 temp_code;
  603. int temp;
  604. mutex_lock(&data->lock);
  605. clk_enable(data->clk);
  606. temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
  607. temp = code_to_temp(data, temp_code);
  608. clk_disable(data->clk);
  609. mutex_unlock(&data->lock);
  610. return temp;
  611. }
  612. static void exynos_tmu_work(struct work_struct *work)
  613. {
  614. struct exynos_tmu_data *data = container_of(work,
  615. struct exynos_tmu_data, irq_work);
  616. exynos_report_trigger();
  617. mutex_lock(&data->lock);
  618. clk_enable(data->clk);
  619. if (data->soc == SOC_ARCH_EXYNOS)
  620. writel(EXYNOS_TMU_CLEAR_RISE_INT |
  621. EXYNOS_TMU_CLEAR_FALL_INT,
  622. data->base + EXYNOS_TMU_REG_INTCLEAR);
  623. else
  624. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  625. data->base + EXYNOS_TMU_REG_INTCLEAR);
  626. clk_disable(data->clk);
  627. mutex_unlock(&data->lock);
  628. enable_irq(data->irq);
  629. }
  630. static irqreturn_t exynos_tmu_irq(int irq, void *id)
  631. {
  632. struct exynos_tmu_data *data = id;
  633. disable_irq_nosync(irq);
  634. schedule_work(&data->irq_work);
  635. return IRQ_HANDLED;
  636. }
  637. static struct thermal_sensor_conf exynos_sensor_conf = {
  638. .name = "exynos-therm",
  639. .read_temperature = (int (*)(void *))exynos_tmu_read,
  640. };
  641. #if defined(CONFIG_CPU_EXYNOS4210)
  642. static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
  643. .threshold = 80,
  644. .trigger_levels[0] = 5,
  645. .trigger_levels[1] = 20,
  646. .trigger_levels[2] = 30,
  647. .trigger_level0_en = 1,
  648. .trigger_level1_en = 1,
  649. .trigger_level2_en = 1,
  650. .trigger_level3_en = 0,
  651. .gain = 15,
  652. .reference_voltage = 7,
  653. .cal_type = TYPE_ONE_POINT_TRIMMING,
  654. .freq_tab[0] = {
  655. .freq_clip_max = 800 * 1000,
  656. .temp_level = 85,
  657. },
  658. .freq_tab[1] = {
  659. .freq_clip_max = 200 * 1000,
  660. .temp_level = 100,
  661. },
  662. .freq_tab_count = 2,
  663. .type = SOC_ARCH_EXYNOS4210,
  664. };
  665. #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
  666. #else
  667. #define EXYNOS4210_TMU_DRV_DATA (NULL)
  668. #endif
  669. #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
  670. static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
  671. .threshold_falling = 10,
  672. .trigger_levels[0] = 85,
  673. .trigger_levels[1] = 103,
  674. .trigger_levels[2] = 110,
  675. .trigger_level0_en = 1,
  676. .trigger_level1_en = 1,
  677. .trigger_level2_en = 1,
  678. .trigger_level3_en = 0,
  679. .gain = 8,
  680. .reference_voltage = 16,
  681. .noise_cancel_mode = 4,
  682. .cal_type = TYPE_ONE_POINT_TRIMMING,
  683. .efuse_value = 55,
  684. .freq_tab[0] = {
  685. .freq_clip_max = 800 * 1000,
  686. .temp_level = 85,
  687. },
  688. .freq_tab[1] = {
  689. .freq_clip_max = 200 * 1000,
  690. .temp_level = 103,
  691. },
  692. .freq_tab_count = 2,
  693. .type = SOC_ARCH_EXYNOS,
  694. };
  695. #define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
  696. #else
  697. #define EXYNOS_TMU_DRV_DATA (NULL)
  698. #endif
  699. #ifdef CONFIG_OF
  700. static const struct of_device_id exynos_tmu_match[] = {
  701. {
  702. .compatible = "samsung,exynos4210-tmu",
  703. .data = (void *)EXYNOS4210_TMU_DRV_DATA,
  704. },
  705. {
  706. .compatible = "samsung,exynos5250-tmu",
  707. .data = (void *)EXYNOS_TMU_DRV_DATA,
  708. },
  709. {},
  710. };
  711. MODULE_DEVICE_TABLE(of, exynos_tmu_match);
  712. #endif
  713. static struct platform_device_id exynos_tmu_driver_ids[] = {
  714. {
  715. .name = "exynos4210-tmu",
  716. .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
  717. },
  718. {
  719. .name = "exynos5250-tmu",
  720. .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
  721. },
  722. { },
  723. };
  724. MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
  725. static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
  726. struct platform_device *pdev)
  727. {
  728. #ifdef CONFIG_OF
  729. if (pdev->dev.of_node) {
  730. const struct of_device_id *match;
  731. match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
  732. if (!match)
  733. return NULL;
  734. return (struct exynos_tmu_platform_data *) match->data;
  735. }
  736. #endif
  737. return (struct exynos_tmu_platform_data *)
  738. platform_get_device_id(pdev)->driver_data;
  739. }
  740. #ifdef CONFIG_EXYNOS_THERMAL_EMUL
  741. static ssize_t exynos_tmu_emulation_show(struct device *dev,
  742. struct device_attribute *attr,
  743. char *buf)
  744. {
  745. struct platform_device *pdev = container_of(dev,
  746. struct platform_device, dev);
  747. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  748. unsigned int reg;
  749. u8 temp_code;
  750. int temp = 0;
  751. if (data->soc == SOC_ARCH_EXYNOS4210)
  752. goto out;
  753. mutex_lock(&data->lock);
  754. clk_enable(data->clk);
  755. reg = readl(data->base + EXYNOS_EMUL_CON);
  756. clk_disable(data->clk);
  757. mutex_unlock(&data->lock);
  758. if (reg & EXYNOS_EMUL_ENABLE) {
  759. reg >>= EXYNOS_EMUL_DATA_SHIFT;
  760. temp_code = reg & EXYNOS_EMUL_DATA_MASK;
  761. temp = code_to_temp(data, temp_code);
  762. }
  763. out:
  764. return sprintf(buf, "%d\n", temp * MCELSIUS);
  765. }
  766. static ssize_t exynos_tmu_emulation_store(struct device *dev,
  767. struct device_attribute *attr,
  768. const char *buf, size_t count)
  769. {
  770. struct platform_device *pdev = container_of(dev,
  771. struct platform_device, dev);
  772. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  773. unsigned int reg;
  774. int temp;
  775. if (data->soc == SOC_ARCH_EXYNOS4210)
  776. goto out;
  777. if (!sscanf(buf, "%d\n", &temp) || temp < 0)
  778. return -EINVAL;
  779. mutex_lock(&data->lock);
  780. clk_enable(data->clk);
  781. reg = readl(data->base + EXYNOS_EMUL_CON);
  782. if (temp) {
  783. /* Both CELSIUS and MCELSIUS type are available for input */
  784. if (temp > MCELSIUS)
  785. temp /= MCELSIUS;
  786. reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
  787. (temp_to_code(data, (temp / MCELSIUS))
  788. << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
  789. } else {
  790. reg &= ~EXYNOS_EMUL_ENABLE;
  791. }
  792. writel(reg, data->base + EXYNOS_EMUL_CON);
  793. clk_disable(data->clk);
  794. mutex_unlock(&data->lock);
  795. out:
  796. return count;
  797. }
  798. static DEVICE_ATTR(emulation, 0644, exynos_tmu_emulation_show,
  799. exynos_tmu_emulation_store);
  800. static int create_emulation_sysfs(struct device *dev)
  801. {
  802. return device_create_file(dev, &dev_attr_emulation);
  803. }
  804. static void remove_emulation_sysfs(struct device *dev)
  805. {
  806. device_remove_file(dev, &dev_attr_emulation);
  807. }
  808. #else
  809. static inline int create_emulation_sysfs(struct device *dev) { return 0; }
  810. static inline void remove_emulation_sysfs(struct device *dev) {}
  811. #endif
  812. static int exynos_tmu_probe(struct platform_device *pdev)
  813. {
  814. struct exynos_tmu_data *data;
  815. struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
  816. int ret, i;
  817. if (!pdata)
  818. pdata = exynos_get_driver_data(pdev);
  819. if (!pdata) {
  820. dev_err(&pdev->dev, "No platform init data supplied.\n");
  821. return -ENODEV;
  822. }
  823. data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
  824. GFP_KERNEL);
  825. if (!data) {
  826. dev_err(&pdev->dev, "Failed to allocate driver structure\n");
  827. return -ENOMEM;
  828. }
  829. data->irq = platform_get_irq(pdev, 0);
  830. if (data->irq < 0) {
  831. dev_err(&pdev->dev, "Failed to get platform irq\n");
  832. return data->irq;
  833. }
  834. INIT_WORK(&data->irq_work, exynos_tmu_work);
  835. data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  836. if (!data->mem) {
  837. dev_err(&pdev->dev, "Failed to get platform resource\n");
  838. return -ENOENT;
  839. }
  840. data->base = devm_ioremap_resource(&pdev->dev, data->mem);
  841. if (IS_ERR(data->base))
  842. return PTR_ERR(data->base);
  843. ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
  844. IRQF_TRIGGER_RISING, "exynos-tmu", data);
  845. if (ret) {
  846. dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
  847. return ret;
  848. }
  849. data->clk = clk_get(NULL, "tmu_apbif");
  850. if (IS_ERR(data->clk)) {
  851. dev_err(&pdev->dev, "Failed to get clock\n");
  852. return PTR_ERR(data->clk);
  853. }
  854. if (pdata->type == SOC_ARCH_EXYNOS ||
  855. pdata->type == SOC_ARCH_EXYNOS4210)
  856. data->soc = pdata->type;
  857. else {
  858. ret = -EINVAL;
  859. dev_err(&pdev->dev, "Platform not supported\n");
  860. goto err_clk;
  861. }
  862. data->pdata = pdata;
  863. platform_set_drvdata(pdev, data);
  864. mutex_init(&data->lock);
  865. ret = exynos_tmu_initialize(pdev);
  866. if (ret) {
  867. dev_err(&pdev->dev, "Failed to initialize TMU\n");
  868. goto err_clk;
  869. }
  870. exynos_tmu_control(pdev, true);
  871. /* Register the sensor with thermal management interface */
  872. (&exynos_sensor_conf)->private_data = data;
  873. exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
  874. pdata->trigger_level1_en + pdata->trigger_level2_en +
  875. pdata->trigger_level3_en;
  876. for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
  877. exynos_sensor_conf.trip_data.trip_val[i] =
  878. pdata->threshold + pdata->trigger_levels[i];
  879. exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
  880. exynos_sensor_conf.cooling_data.freq_clip_count =
  881. pdata->freq_tab_count;
  882. for (i = 0; i < pdata->freq_tab_count; i++) {
  883. exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
  884. pdata->freq_tab[i].freq_clip_max;
  885. exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
  886. pdata->freq_tab[i].temp_level;
  887. }
  888. ret = exynos_register_thermal(&exynos_sensor_conf);
  889. if (ret) {
  890. dev_err(&pdev->dev, "Failed to register thermal interface\n");
  891. goto err_clk;
  892. }
  893. ret = create_emulation_sysfs(&pdev->dev);
  894. if (ret)
  895. dev_err(&pdev->dev, "Failed to create emulation mode sysfs node\n");
  896. return 0;
  897. err_clk:
  898. platform_set_drvdata(pdev, NULL);
  899. clk_put(data->clk);
  900. return ret;
  901. }
  902. static int exynos_tmu_remove(struct platform_device *pdev)
  903. {
  904. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  905. remove_emulation_sysfs(&pdev->dev);
  906. exynos_tmu_control(pdev, false);
  907. exynos_unregister_thermal();
  908. clk_put(data->clk);
  909. platform_set_drvdata(pdev, NULL);
  910. return 0;
  911. }
  912. #ifdef CONFIG_PM_SLEEP
  913. static int exynos_tmu_suspend(struct device *dev)
  914. {
  915. exynos_tmu_control(to_platform_device(dev), false);
  916. return 0;
  917. }
  918. static int exynos_tmu_resume(struct device *dev)
  919. {
  920. struct platform_device *pdev = to_platform_device(dev);
  921. exynos_tmu_initialize(pdev);
  922. exynos_tmu_control(pdev, true);
  923. return 0;
  924. }
  925. static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
  926. exynos_tmu_suspend, exynos_tmu_resume);
  927. #define EXYNOS_TMU_PM (&exynos_tmu_pm)
  928. #else
  929. #define EXYNOS_TMU_PM NULL
  930. #endif
  931. static struct platform_driver exynos_tmu_driver = {
  932. .driver = {
  933. .name = "exynos-tmu",
  934. .owner = THIS_MODULE,
  935. .pm = EXYNOS_TMU_PM,
  936. .of_match_table = of_match_ptr(exynos_tmu_match),
  937. },
  938. .probe = exynos_tmu_probe,
  939. .remove = exynos_tmu_remove,
  940. .id_table = exynos_tmu_driver_ids,
  941. };
  942. module_platform_driver(exynos_tmu_driver);
  943. MODULE_DESCRIPTION("EXYNOS TMU Driver");
  944. MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
  945. MODULE_LICENSE("GPL");
  946. MODULE_ALIAS("platform:exynos-tmu");