ps3vram.c 22 KB

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  1. /*
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright 2009 Sony Corporation
  5. *
  6. * Based on the MTD ps3vram driver, which is
  7. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  8. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  9. */
  10. #include <linux/blkdev.h>
  11. #include <linux/delay.h>
  12. #include <linux/proc_fs.h>
  13. #include <linux/seq_file.h>
  14. #include <asm/firmware.h>
  15. #include <asm/iommu.h>
  16. #include <asm/lv1call.h>
  17. #include <asm/ps3.h>
  18. #define DEVICE_NAME "ps3vram"
  19. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  20. #define XDR_IOIF 0x0c000000
  21. #define FIFO_BASE XDR_IOIF
  22. #define FIFO_SIZE (64 * 1024)
  23. #define DMA_PAGE_SIZE (4 * 1024)
  24. #define CACHE_PAGE_SIZE (256 * 1024)
  25. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  26. #define CACHE_OFFSET CACHE_PAGE_SIZE
  27. #define FIFO_OFFSET 0
  28. #define CTRL_PUT 0x10
  29. #define CTRL_GET 0x11
  30. #define CTRL_TOP 0x15
  31. #define UPLOAD_SUBCH 1
  32. #define DOWNLOAD_SUBCH 2
  33. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  34. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  35. #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  36. #define CACHE_PAGE_PRESENT 1
  37. #define CACHE_PAGE_DIRTY 2
  38. struct ps3vram_tag {
  39. unsigned int address;
  40. unsigned int flags;
  41. };
  42. struct ps3vram_cache {
  43. unsigned int page_count;
  44. unsigned int page_size;
  45. struct ps3vram_tag *tags;
  46. unsigned int hit;
  47. unsigned int miss;
  48. };
  49. struct ps3vram_priv {
  50. struct request_queue *queue;
  51. struct gendisk *gendisk;
  52. u64 size;
  53. u64 memory_handle;
  54. u64 context_handle;
  55. u32 *ctrl;
  56. u32 *reports;
  57. u8 __iomem *ddr_base;
  58. u8 *xdr_buf;
  59. u32 *fifo_base;
  60. u32 *fifo_ptr;
  61. struct ps3vram_cache cache;
  62. /* Used to serialize cache/DMA operations */
  63. struct mutex lock;
  64. };
  65. static int ps3vram_major;
  66. static struct block_device_operations ps3vram_fops = {
  67. .owner = THIS_MODULE,
  68. };
  69. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  70. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  71. #define DMA_NOTIFIER_SIZE 0x40
  72. #define NOTIFIER 7 /* notifier used for completion report */
  73. static char *size = "256M";
  74. module_param(size, charp, 0);
  75. MODULE_PARM_DESC(size, "memory size");
  76. static u32 *ps3vram_get_notifier(u32 *reports, int notifier)
  77. {
  78. return (void *)reports + DMA_NOTIFIER_OFFSET_BASE +
  79. DMA_NOTIFIER_SIZE * notifier;
  80. }
  81. static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
  82. {
  83. struct ps3vram_priv *priv = dev->core.driver_data;
  84. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  85. int i;
  86. for (i = 0; i < 4; i++)
  87. notify[i] = 0xffffffff;
  88. }
  89. static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
  90. unsigned int timeout_ms)
  91. {
  92. struct ps3vram_priv *priv = dev->core.driver_data;
  93. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  94. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  95. do {
  96. if (!notify[3])
  97. return 0;
  98. msleep(1);
  99. } while (time_before(jiffies, timeout));
  100. return -ETIMEDOUT;
  101. }
  102. static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
  103. {
  104. struct ps3vram_priv *priv = dev->core.driver_data;
  105. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  106. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  107. }
  108. static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
  109. unsigned int timeout_ms)
  110. {
  111. struct ps3vram_priv *priv = dev->core.driver_data;
  112. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  113. do {
  114. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  115. return 0;
  116. msleep(1);
  117. } while (time_before(jiffies, timeout));
  118. dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
  119. priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
  120. priv->ctrl[CTRL_TOP]);
  121. return -ETIMEDOUT;
  122. }
  123. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  124. {
  125. *(priv->fifo_ptr)++ = data;
  126. }
  127. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
  128. u32 size)
  129. {
  130. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  131. }
  132. static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
  133. {
  134. struct ps3vram_priv *priv = dev->core.driver_data;
  135. int status;
  136. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  137. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  138. /* asking the HV for a blit will kick the FIFO */
  139. status = lv1_gpu_context_attribute(priv->context_handle,
  140. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 0,
  141. 0, 0, 0);
  142. if (status)
  143. dev_err(&dev->core,
  144. "%s: lv1_gpu_context_attribute failed %d\n", __func__,
  145. status);
  146. priv->fifo_ptr = priv->fifo_base;
  147. }
  148. static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
  149. {
  150. struct ps3vram_priv *priv = dev->core.driver_data;
  151. int status;
  152. mutex_lock(&ps3_gpu_mutex);
  153. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  154. (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
  155. /* asking the HV for a blit will kick the FIFO */
  156. status = lv1_gpu_context_attribute(priv->context_handle,
  157. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 0,
  158. 0, 0, 0);
  159. if (status)
  160. dev_err(&dev->core,
  161. "%s: lv1_gpu_context_attribute failed %d\n", __func__,
  162. status);
  163. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  164. FIFO_SIZE - 1024) {
  165. dev_dbg(&dev->core, "FIFO full, rewinding\n");
  166. ps3vram_wait_ring(dev, 200);
  167. ps3vram_rewind_ring(dev);
  168. }
  169. mutex_unlock(&ps3_gpu_mutex);
  170. }
  171. static void ps3vram_bind(struct ps3_system_bus_device *dev)
  172. {
  173. struct ps3vram_priv *priv = dev->core.driver_data;
  174. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  175. ps3vram_out_ring(priv, 0x31337303);
  176. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  177. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  178. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  179. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  180. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  181. ps3vram_out_ring(priv, 0x3137c0de);
  182. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  183. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  184. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  185. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  186. ps3vram_fire_ring(dev);
  187. }
  188. static int ps3vram_upload(struct ps3_system_bus_device *dev,
  189. unsigned int src_offset, unsigned int dst_offset,
  190. int len, int count)
  191. {
  192. struct ps3vram_priv *priv = dev->core.driver_data;
  193. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  194. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  195. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  196. ps3vram_out_ring(priv, dst_offset);
  197. ps3vram_out_ring(priv, len);
  198. ps3vram_out_ring(priv, len);
  199. ps3vram_out_ring(priv, len);
  200. ps3vram_out_ring(priv, count);
  201. ps3vram_out_ring(priv, (1 << 8) | 1);
  202. ps3vram_out_ring(priv, 0);
  203. ps3vram_notifier_reset(dev);
  204. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  205. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  206. ps3vram_out_ring(priv, 0);
  207. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  208. ps3vram_out_ring(priv, 0);
  209. ps3vram_fire_ring(dev);
  210. if (ps3vram_notifier_wait(dev, 200) < 0) {
  211. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  212. return -1;
  213. }
  214. return 0;
  215. }
  216. static int ps3vram_download(struct ps3_system_bus_device *dev,
  217. unsigned int src_offset, unsigned int dst_offset,
  218. int len, int count)
  219. {
  220. struct ps3vram_priv *priv = dev->core.driver_data;
  221. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  222. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  223. ps3vram_out_ring(priv, src_offset);
  224. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  225. ps3vram_out_ring(priv, len);
  226. ps3vram_out_ring(priv, len);
  227. ps3vram_out_ring(priv, len);
  228. ps3vram_out_ring(priv, count);
  229. ps3vram_out_ring(priv, (1 << 8) | 1);
  230. ps3vram_out_ring(priv, 0);
  231. ps3vram_notifier_reset(dev);
  232. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  233. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  234. ps3vram_out_ring(priv, 0);
  235. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  236. ps3vram_out_ring(priv, 0);
  237. ps3vram_fire_ring(dev);
  238. if (ps3vram_notifier_wait(dev, 200) < 0) {
  239. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  240. return -1;
  241. }
  242. return 0;
  243. }
  244. static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
  245. {
  246. struct ps3vram_priv *priv = dev->core.driver_data;
  247. struct ps3vram_cache *cache = &priv->cache;
  248. if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
  249. return;
  250. dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
  251. cache->tags[entry].address);
  252. if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
  253. cache->tags[entry].address, DMA_PAGE_SIZE,
  254. cache->page_size / DMA_PAGE_SIZE) < 0) {
  255. dev_err(&dev->core,
  256. "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
  257. entry * cache->page_size, cache->tags[entry].address,
  258. cache->page_size);
  259. }
  260. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  261. }
  262. static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
  263. unsigned int address)
  264. {
  265. struct ps3vram_priv *priv = dev->core.driver_data;
  266. struct ps3vram_cache *cache = &priv->cache;
  267. dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
  268. if (ps3vram_download(dev, address,
  269. CACHE_OFFSET + entry * cache->page_size,
  270. DMA_PAGE_SIZE,
  271. cache->page_size / DMA_PAGE_SIZE) < 0) {
  272. dev_err(&dev->core,
  273. "Failed to download from 0x%x to 0x%x size 0x%x\n",
  274. address, entry * cache->page_size, cache->page_size);
  275. }
  276. cache->tags[entry].address = address;
  277. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  278. }
  279. static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
  280. {
  281. struct ps3vram_priv *priv = dev->core.driver_data;
  282. struct ps3vram_cache *cache = &priv->cache;
  283. int i;
  284. dev_dbg(&dev->core, "FLUSH\n");
  285. for (i = 0; i < cache->page_count; i++) {
  286. ps3vram_cache_evict(dev, i);
  287. cache->tags[i].flags = 0;
  288. }
  289. }
  290. static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
  291. loff_t address)
  292. {
  293. struct ps3vram_priv *priv = dev->core.driver_data;
  294. struct ps3vram_cache *cache = &priv->cache;
  295. unsigned int base;
  296. unsigned int offset;
  297. int i;
  298. static int counter;
  299. offset = (unsigned int) (address & (cache->page_size - 1));
  300. base = (unsigned int) (address - offset);
  301. /* fully associative check */
  302. for (i = 0; i < cache->page_count; i++) {
  303. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  304. cache->tags[i].address == base) {
  305. cache->hit++;
  306. dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
  307. cache->tags[i].address);
  308. return i;
  309. }
  310. }
  311. /* choose a random entry */
  312. i = (jiffies + (counter++)) % cache->page_count;
  313. dev_dbg(&dev->core, "Using entry %d\n", i);
  314. ps3vram_cache_evict(dev, i);
  315. ps3vram_cache_load(dev, i, base);
  316. cache->miss++;
  317. return i;
  318. }
  319. static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
  320. {
  321. struct ps3vram_priv *priv = dev->core.driver_data;
  322. priv->cache.page_count = CACHE_PAGE_COUNT;
  323. priv->cache.page_size = CACHE_PAGE_SIZE;
  324. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  325. CACHE_PAGE_COUNT, GFP_KERNEL);
  326. if (priv->cache.tags == NULL) {
  327. dev_err(&dev->core, "Could not allocate cache tags\n");
  328. return -ENOMEM;
  329. }
  330. dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
  331. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  332. return 0;
  333. }
  334. static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
  335. {
  336. struct ps3vram_priv *priv = dev->core.driver_data;
  337. ps3vram_cache_flush(dev);
  338. kfree(priv->cache.tags);
  339. }
  340. static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
  341. size_t len, size_t *retlen, u_char *buf)
  342. {
  343. struct ps3vram_priv *priv = dev->core.driver_data;
  344. unsigned int cached, count;
  345. dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
  346. (unsigned int)from, len);
  347. if (from >= priv->size)
  348. return -EIO;
  349. if (len > priv->size - from)
  350. len = priv->size - from;
  351. /* Copy from vram to buf */
  352. count = len;
  353. while (count) {
  354. unsigned int offset, avail;
  355. unsigned int entry;
  356. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  357. avail = priv->cache.page_size - offset;
  358. mutex_lock(&priv->lock);
  359. entry = ps3vram_cache_match(dev, from);
  360. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  361. dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
  362. "avail=%08x count=%08x\n", __func__,
  363. (unsigned int)from, cached, offset, avail, count);
  364. if (avail > count)
  365. avail = count;
  366. memcpy(buf, priv->xdr_buf + cached, avail);
  367. mutex_unlock(&priv->lock);
  368. buf += avail;
  369. count -= avail;
  370. from += avail;
  371. }
  372. *retlen = len;
  373. return 0;
  374. }
  375. static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
  376. size_t len, size_t *retlen, const u_char *buf)
  377. {
  378. struct ps3vram_priv *priv = dev->core.driver_data;
  379. unsigned int cached, count;
  380. if (to >= priv->size)
  381. return -EIO;
  382. if (len > priv->size - to)
  383. len = priv->size - to;
  384. /* Copy from buf to vram */
  385. count = len;
  386. while (count) {
  387. unsigned int offset, avail;
  388. unsigned int entry;
  389. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  390. avail = priv->cache.page_size - offset;
  391. mutex_lock(&priv->lock);
  392. entry = ps3vram_cache_match(dev, to);
  393. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  394. dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
  395. "avail=%08x count=%08x\n", __func__, (unsigned int)to,
  396. cached, offset, avail, count);
  397. if (avail > count)
  398. avail = count;
  399. memcpy(priv->xdr_buf + cached, buf, avail);
  400. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  401. mutex_unlock(&priv->lock);
  402. buf += avail;
  403. count -= avail;
  404. to += avail;
  405. }
  406. *retlen = len;
  407. return 0;
  408. }
  409. static int ps3vram_proc_show(struct seq_file *m, void *v)
  410. {
  411. struct ps3vram_priv *priv = m->private;
  412. seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
  413. return 0;
  414. }
  415. static int ps3vram_proc_open(struct inode *inode, struct file *file)
  416. {
  417. return single_open(file, ps3vram_proc_show, PDE(inode)->data);
  418. }
  419. static const struct file_operations ps3vram_proc_fops = {
  420. .owner = THIS_MODULE,
  421. .open = ps3vram_proc_open,
  422. .read = seq_read,
  423. .llseek = seq_lseek,
  424. .release = single_release,
  425. };
  426. static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev)
  427. {
  428. struct ps3vram_priv *priv = dev->core.driver_data;
  429. struct proc_dir_entry *pde;
  430. pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops,
  431. priv);
  432. if (!pde)
  433. dev_warn(&dev->core, "failed to create /proc entry\n");
  434. }
  435. static int ps3vram_make_request(struct request_queue *q, struct bio *bio)
  436. {
  437. struct ps3_system_bus_device *dev = q->queuedata;
  438. int write = bio_data_dir(bio) == WRITE;
  439. const char *op = write ? "write" : "read";
  440. loff_t offset = bio->bi_sector << 9;
  441. int error = 0;
  442. struct bio_vec *bvec;
  443. unsigned int i;
  444. dev_dbg(&dev->core, "%s\n", __func__);
  445. bio_for_each_segment(bvec, bio, i) {
  446. /* PS3 is ppc64, so we don't handle highmem */
  447. char *ptr = page_address(bvec->bv_page) + bvec->bv_offset;
  448. size_t len = bvec->bv_len, retlen;
  449. dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
  450. len, offset);
  451. if (write)
  452. error = ps3vram_write(dev, offset, len, &retlen, ptr);
  453. else
  454. error = ps3vram_read(dev, offset, len, &retlen, ptr);
  455. if (error) {
  456. dev_err(&dev->core, "%s failed\n", op);
  457. goto out;
  458. }
  459. if (retlen != len) {
  460. dev_err(&dev->core, "Short %s\n", op);
  461. error = -EIO;
  462. goto out;
  463. }
  464. offset += len;
  465. }
  466. dev_dbg(&dev->core, "%s completed\n", op);
  467. out:
  468. bio_endio(bio, error);
  469. return 0;
  470. }
  471. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  472. {
  473. struct ps3vram_priv *priv;
  474. int error, status;
  475. struct request_queue *queue;
  476. struct gendisk *gendisk;
  477. u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
  478. reports_size, xdr_lpar;
  479. char *rest;
  480. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  481. if (!priv) {
  482. error = -ENOMEM;
  483. goto fail;
  484. }
  485. mutex_init(&priv->lock);
  486. dev->core.driver_data = priv;
  487. priv = dev->core.driver_data;
  488. /* Allocate XDR buffer (1MiB aligned) */
  489. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  490. get_order(XDR_BUF_SIZE));
  491. if (priv->xdr_buf == NULL) {
  492. dev_err(&dev->core, "Could not allocate XDR buffer\n");
  493. error = -ENOMEM;
  494. goto fail_free_priv;
  495. }
  496. /* Put FIFO at begginning of XDR buffer */
  497. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  498. priv->fifo_ptr = priv->fifo_base;
  499. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  500. if (ps3_open_hv_device(dev)) {
  501. dev_err(&dev->core, "ps3_open_hv_device failed\n");
  502. error = -EAGAIN;
  503. goto out_free_xdr_buf;
  504. }
  505. /* Request memory */
  506. status = -1;
  507. ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
  508. if (!ddr_size) {
  509. dev_err(&dev->core, "Specified size is too small\n");
  510. error = -EINVAL;
  511. goto out_close_gpu;
  512. }
  513. while (ddr_size > 0) {
  514. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  515. &priv->memory_handle,
  516. &ddr_lpar);
  517. if (!status)
  518. break;
  519. ddr_size -= 1024*1024;
  520. }
  521. if (status) {
  522. dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
  523. status);
  524. error = -ENOMEM;
  525. goto out_close_gpu;
  526. }
  527. /* Request context */
  528. status = lv1_gpu_context_allocate(priv->memory_handle, 0,
  529. &priv->context_handle, &ctrl_lpar,
  530. &info_lpar, &reports_lpar,
  531. &reports_size);
  532. if (status) {
  533. dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
  534. status);
  535. error = -ENOMEM;
  536. goto out_free_memory;
  537. }
  538. /* Map XDR buffer to RSX */
  539. xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
  540. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  541. xdr_lpar, XDR_BUF_SIZE,
  542. CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
  543. CBE_IOPTE_M);
  544. if (status) {
  545. dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
  546. status);
  547. error = -ENOMEM;
  548. goto out_free_context;
  549. }
  550. priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE);
  551. if (!priv->ddr_base) {
  552. dev_err(&dev->core, "ioremap DDR failed\n");
  553. error = -ENOMEM;
  554. goto out_unmap_context;
  555. }
  556. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  557. if (!priv->ctrl) {
  558. dev_err(&dev->core, "ioremap CTRL failed\n");
  559. error = -ENOMEM;
  560. goto out_unmap_vram;
  561. }
  562. priv->reports = ioremap(reports_lpar, reports_size);
  563. if (!priv->reports) {
  564. dev_err(&dev->core, "ioremap REPORTS failed\n");
  565. error = -ENOMEM;
  566. goto out_unmap_ctrl;
  567. }
  568. mutex_lock(&ps3_gpu_mutex);
  569. ps3vram_init_ring(dev);
  570. mutex_unlock(&ps3_gpu_mutex);
  571. priv->size = ddr_size;
  572. ps3vram_bind(dev);
  573. mutex_lock(&ps3_gpu_mutex);
  574. error = ps3vram_wait_ring(dev, 100);
  575. mutex_unlock(&ps3_gpu_mutex);
  576. if (error < 0) {
  577. dev_err(&dev->core, "Failed to initialize channels\n");
  578. error = -ETIMEDOUT;
  579. goto out_unmap_reports;
  580. }
  581. ps3vram_cache_init(dev);
  582. ps3vram_proc_init(dev);
  583. queue = blk_alloc_queue(GFP_KERNEL);
  584. if (!queue) {
  585. dev_err(&dev->core, "blk_alloc_queue failed\n");
  586. error = -ENOMEM;
  587. goto out_cache_cleanup;
  588. }
  589. priv->queue = queue;
  590. queue->queuedata = dev;
  591. blk_queue_make_request(queue, ps3vram_make_request);
  592. blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS);
  593. blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS);
  594. blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE);
  595. blk_queue_max_sectors(queue, SAFE_MAX_SECTORS);
  596. gendisk = alloc_disk(1);
  597. if (!gendisk) {
  598. dev_err(&dev->core, "alloc_disk failed\n");
  599. error = -ENOMEM;
  600. goto fail_cleanup_queue;
  601. }
  602. priv->gendisk = gendisk;
  603. gendisk->major = ps3vram_major;
  604. gendisk->first_minor = 0;
  605. gendisk->fops = &ps3vram_fops;
  606. gendisk->queue = queue;
  607. gendisk->private_data = dev;
  608. gendisk->driverfs_dev = &dev->core;
  609. strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
  610. set_capacity(gendisk, priv->size >> 9);
  611. dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
  612. gendisk->disk_name, get_capacity(gendisk) >> 11);
  613. add_disk(gendisk);
  614. return 0;
  615. fail_cleanup_queue:
  616. blk_cleanup_queue(queue);
  617. out_cache_cleanup:
  618. remove_proc_entry(DEVICE_NAME, NULL);
  619. ps3vram_cache_cleanup(dev);
  620. out_unmap_reports:
  621. iounmap(priv->reports);
  622. out_unmap_ctrl:
  623. iounmap(priv->ctrl);
  624. out_unmap_vram:
  625. iounmap(priv->ddr_base);
  626. out_unmap_context:
  627. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
  628. XDR_BUF_SIZE, CBE_IOPTE_M);
  629. out_free_context:
  630. lv1_gpu_context_free(priv->context_handle);
  631. out_free_memory:
  632. lv1_gpu_memory_free(priv->memory_handle);
  633. out_close_gpu:
  634. ps3_close_hv_device(dev);
  635. out_free_xdr_buf:
  636. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  637. fail_free_priv:
  638. kfree(priv);
  639. dev->core.driver_data = NULL;
  640. fail:
  641. return error;
  642. }
  643. static int ps3vram_remove(struct ps3_system_bus_device *dev)
  644. {
  645. struct ps3vram_priv *priv = dev->core.driver_data;
  646. del_gendisk(priv->gendisk);
  647. put_disk(priv->gendisk);
  648. blk_cleanup_queue(priv->queue);
  649. remove_proc_entry(DEVICE_NAME, NULL);
  650. ps3vram_cache_cleanup(dev);
  651. iounmap(priv->reports);
  652. iounmap(priv->ctrl);
  653. iounmap(priv->ddr_base);
  654. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  655. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  656. XDR_BUF_SIZE, CBE_IOPTE_M);
  657. lv1_gpu_context_free(priv->context_handle);
  658. lv1_gpu_memory_free(priv->memory_handle);
  659. ps3_close_hv_device(dev);
  660. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  661. kfree(priv);
  662. dev->core.driver_data = NULL;
  663. return 0;
  664. }
  665. static struct ps3_system_bus_driver ps3vram = {
  666. .match_id = PS3_MATCH_ID_GPU,
  667. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  668. .core.name = DEVICE_NAME,
  669. .core.owner = THIS_MODULE,
  670. .probe = ps3vram_probe,
  671. .remove = ps3vram_remove,
  672. .shutdown = ps3vram_remove,
  673. };
  674. static int __init ps3vram_init(void)
  675. {
  676. int error;
  677. if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
  678. return -ENODEV;
  679. error = register_blkdev(0, DEVICE_NAME);
  680. if (error <= 0) {
  681. pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
  682. return error;
  683. }
  684. ps3vram_major = error;
  685. pr_info("%s: registered block device major %d\n", DEVICE_NAME,
  686. ps3vram_major);
  687. error = ps3_system_bus_driver_register(&ps3vram);
  688. if (error)
  689. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  690. return error;
  691. }
  692. static void __exit ps3vram_exit(void)
  693. {
  694. ps3_system_bus_driver_unregister(&ps3vram);
  695. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  696. }
  697. module_init(ps3vram_init);
  698. module_exit(ps3vram_exit);
  699. MODULE_LICENSE("GPL");
  700. MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
  701. MODULE_AUTHOR("Sony Corporation");
  702. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);