netxen_nic_init.c 29 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  163. rds_ring = &recv_ctx->rds_rings[ring];
  164. if (rds_ring->rx_buf_arr) {
  165. vfree(rds_ring->rx_buf_arr);
  166. rds_ring->rx_buf_arr = NULL;
  167. }
  168. }
  169. tx_ring = &adapter->tx_ring;
  170. if (tx_ring->cmd_buf_arr)
  171. vfree(tx_ring->cmd_buf_arr);
  172. return;
  173. }
  174. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  175. {
  176. struct netxen_recv_context *recv_ctx;
  177. struct nx_host_rds_ring *rds_ring;
  178. struct nx_host_sds_ring *sds_ring;
  179. struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
  180. struct netxen_rx_buffer *rx_buf;
  181. int ring, i, num_rx_bufs;
  182. struct netxen_cmd_buffer *cmd_buf_arr;
  183. struct net_device *netdev = adapter->netdev;
  184. struct pci_dev *pdev = adapter->pdev;
  185. tx_ring->num_desc = adapter->num_txd;
  186. cmd_buf_arr =
  187. (struct netxen_cmd_buffer *)vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  188. if (cmd_buf_arr == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  194. tx_ring->cmd_buf_arr = cmd_buf_arr;
  195. recv_ctx = &adapter->recv_ctx;
  196. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  197. rds_ring = &recv_ctx->rds_rings[ring];
  198. switch (ring) {
  199. case RCV_RING_NORMAL:
  200. rds_ring->num_desc = adapter->num_rxd;
  201. if (adapter->ahw.cut_through) {
  202. rds_ring->dma_size =
  203. NX_CT_DEFAULT_RX_BUF_LEN;
  204. rds_ring->skb_size =
  205. NX_CT_DEFAULT_RX_BUF_LEN;
  206. } else {
  207. rds_ring->dma_size = RX_DMA_MAP_LEN;
  208. rds_ring->skb_size =
  209. MAX_RX_BUFFER_LENGTH;
  210. }
  211. break;
  212. case RCV_RING_JUMBO:
  213. rds_ring->num_desc = adapter->num_jumbo_rxd;
  214. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  215. rds_ring->dma_size =
  216. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  217. else
  218. rds_ring->dma_size =
  219. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  220. rds_ring->skb_size =
  221. rds_ring->dma_size + NET_IP_ALIGN;
  222. break;
  223. case RCV_RING_LRO:
  224. rds_ring->num_desc = adapter->num_lro_rxd;
  225. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  226. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  227. break;
  228. }
  229. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  230. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  231. if (rds_ring->rx_buf_arr == NULL) {
  232. printk(KERN_ERR "%s: Failed to allocate "
  233. "rx buffer ring %d\n",
  234. netdev->name, ring);
  235. /* free whatever was already allocated */
  236. goto err_out;
  237. }
  238. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  239. INIT_LIST_HEAD(&rds_ring->free_list);
  240. /*
  241. * Now go through all of them, set reference handles
  242. * and put them in the queues.
  243. */
  244. num_rx_bufs = rds_ring->num_desc;
  245. rx_buf = rds_ring->rx_buf_arr;
  246. for (i = 0; i < num_rx_bufs; i++) {
  247. list_add_tail(&rx_buf->list,
  248. &rds_ring->free_list);
  249. rx_buf->ref_handle = i;
  250. rx_buf->state = NETXEN_BUFFER_FREE;
  251. rx_buf++;
  252. }
  253. spin_lock_init(&rds_ring->lock);
  254. }
  255. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  256. sds_ring = &recv_ctx->sds_rings[ring];
  257. sds_ring->irq = adapter->msix_entries[ring].vector;
  258. sds_ring->adapter = adapter;
  259. sds_ring->num_desc = adapter->num_rxd;
  260. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  261. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  262. }
  263. return 0;
  264. err_out:
  265. netxen_free_sw_resources(adapter);
  266. return -ENOMEM;
  267. }
  268. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  269. {
  270. switch (adapter->ahw.port_type) {
  271. case NETXEN_NIC_GBE:
  272. adapter->enable_phy_interrupts =
  273. netxen_niu_gbe_enable_phy_interrupts;
  274. adapter->disable_phy_interrupts =
  275. netxen_niu_gbe_disable_phy_interrupts;
  276. adapter->macaddr_set = netxen_niu_macaddr_set;
  277. adapter->set_mtu = netxen_nic_set_mtu_gb;
  278. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  279. adapter->phy_read = netxen_niu_gbe_phy_read;
  280. adapter->phy_write = netxen_niu_gbe_phy_write;
  281. adapter->init_port = netxen_niu_gbe_init_port;
  282. adapter->stop_port = netxen_niu_disable_gbe_port;
  283. break;
  284. case NETXEN_NIC_XGBE:
  285. adapter->enable_phy_interrupts =
  286. netxen_niu_xgbe_enable_phy_interrupts;
  287. adapter->disable_phy_interrupts =
  288. netxen_niu_xgbe_disable_phy_interrupts;
  289. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  290. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  291. adapter->init_port = netxen_niu_xg_init_port;
  292. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  293. adapter->stop_port = netxen_niu_disable_xg_port;
  294. break;
  295. default:
  296. break;
  297. }
  298. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  299. adapter->set_mtu = nx_fw_cmd_set_mtu;
  300. adapter->set_promisc = netxen_p3_nic_set_promisc;
  301. }
  302. }
  303. /*
  304. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  305. * address to external PCI CRB address.
  306. */
  307. static u32 netxen_decode_crb_addr(u32 addr)
  308. {
  309. int i;
  310. u32 base_addr, offset, pci_base;
  311. crb_addr_transform_setup();
  312. pci_base = NETXEN_ADDR_ERROR;
  313. base_addr = addr & 0xfff00000;
  314. offset = addr & 0x000fffff;
  315. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  316. if (crb_addr_xform[i] == base_addr) {
  317. pci_base = i << 20;
  318. break;
  319. }
  320. }
  321. if (pci_base == NETXEN_ADDR_ERROR)
  322. return pci_base;
  323. else
  324. return (pci_base + offset);
  325. }
  326. static long rom_max_timeout = 100;
  327. static long rom_lock_timeout = 10000;
  328. static int rom_lock(struct netxen_adapter *adapter)
  329. {
  330. int iter;
  331. u32 done = 0;
  332. int timeout = 0;
  333. while (!done) {
  334. /* acquire semaphore2 from PCI HW block */
  335. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  336. &done);
  337. if (done == 1)
  338. break;
  339. if (timeout >= rom_lock_timeout)
  340. return -EIO;
  341. timeout++;
  342. /*
  343. * Yield CPU
  344. */
  345. if (!in_atomic())
  346. schedule();
  347. else {
  348. for (iter = 0; iter < 20; iter++)
  349. cpu_relax(); /*This a nop instr on i386 */
  350. }
  351. }
  352. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  353. return 0;
  354. }
  355. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  356. {
  357. long timeout = 0;
  358. long done = 0;
  359. cond_resched();
  360. while (done == 0) {
  361. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  362. done &= 2;
  363. timeout++;
  364. if (timeout >= rom_max_timeout) {
  365. printk("Timeout reached waiting for rom done");
  366. return -EIO;
  367. }
  368. }
  369. return 0;
  370. }
  371. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  372. {
  373. u32 val;
  374. /* release semaphore2 */
  375. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  376. }
  377. static int do_rom_fast_read(struct netxen_adapter *adapter,
  378. int addr, int *valp)
  379. {
  380. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  381. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  382. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  383. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  384. if (netxen_wait_rom_done(adapter)) {
  385. printk("Error waiting for rom done\n");
  386. return -EIO;
  387. }
  388. /* reset abyte_cnt and dummy_byte_cnt */
  389. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  390. udelay(10);
  391. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  392. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  393. return 0;
  394. }
  395. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  396. u8 *bytes, size_t size)
  397. {
  398. int addridx;
  399. int ret = 0;
  400. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  401. int v;
  402. ret = do_rom_fast_read(adapter, addridx, &v);
  403. if (ret != 0)
  404. break;
  405. *(__le32 *)bytes = cpu_to_le32(v);
  406. bytes += 4;
  407. }
  408. return ret;
  409. }
  410. int
  411. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  412. u8 *bytes, size_t size)
  413. {
  414. int ret;
  415. ret = rom_lock(adapter);
  416. if (ret < 0)
  417. return ret;
  418. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  419. netxen_rom_unlock(adapter);
  420. return ret;
  421. }
  422. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  423. {
  424. int ret;
  425. if (rom_lock(adapter) != 0)
  426. return -EIO;
  427. ret = do_rom_fast_read(adapter, addr, valp);
  428. netxen_rom_unlock(adapter);
  429. return ret;
  430. }
  431. #define NETXEN_BOARDTYPE 0x4008
  432. #define NETXEN_BOARDNUM 0x400c
  433. #define NETXEN_CHIPNUM 0x4010
  434. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  435. {
  436. int addr, val;
  437. int i, n, init_delay = 0;
  438. struct crb_addr_pair *buf;
  439. unsigned offset;
  440. u32 off;
  441. /* resetall */
  442. rom_lock(adapter);
  443. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  444. 0xffffffff);
  445. netxen_rom_unlock(adapter);
  446. if (verbose) {
  447. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  448. printk("P2 ROM board type: 0x%08x\n", val);
  449. else
  450. printk("Could not read board type\n");
  451. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  452. printk("P2 ROM board num: 0x%08x\n", val);
  453. else
  454. printk("Could not read board number\n");
  455. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  456. printk("P2 ROM chip num: 0x%08x\n", val);
  457. else
  458. printk("Could not read chip number\n");
  459. }
  460. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  461. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  462. (n != 0xcafecafe) ||
  463. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  464. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  465. "n: %08x\n", netxen_nic_driver_name, n);
  466. return -EIO;
  467. }
  468. offset = n & 0xffffU;
  469. n = (n >> 16) & 0xffffU;
  470. } else {
  471. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  472. !(n & 0x80000000)) {
  473. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  474. "n: %08x\n", netxen_nic_driver_name, n);
  475. return -EIO;
  476. }
  477. offset = 1;
  478. n &= ~0x80000000;
  479. }
  480. if (n < 1024) {
  481. if (verbose)
  482. printk(KERN_DEBUG "%s: %d CRB init values found"
  483. " in ROM.\n", netxen_nic_driver_name, n);
  484. } else {
  485. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  486. " initialized.\n", __func__, n);
  487. return -EIO;
  488. }
  489. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  490. if (buf == NULL) {
  491. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  492. netxen_nic_driver_name);
  493. return -ENOMEM;
  494. }
  495. for (i = 0; i < n; i++) {
  496. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  497. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  498. kfree(buf);
  499. return -EIO;
  500. }
  501. buf[i].addr = addr;
  502. buf[i].data = val;
  503. if (verbose)
  504. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  505. netxen_nic_driver_name,
  506. (u32)netxen_decode_crb_addr(addr), val);
  507. }
  508. for (i = 0; i < n; i++) {
  509. off = netxen_decode_crb_addr(buf[i].addr);
  510. if (off == NETXEN_ADDR_ERROR) {
  511. printk(KERN_ERR"CRB init value out of range %x\n",
  512. buf[i].addr);
  513. continue;
  514. }
  515. off += NETXEN_PCI_CRBSPACE;
  516. /* skipping cold reboot MAGIC */
  517. if (off == NETXEN_CAM_RAM(0x1fc))
  518. continue;
  519. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  520. /* do not reset PCI */
  521. if (off == (ROMUSB_GLB + 0xbc))
  522. continue;
  523. if (off == (ROMUSB_GLB + 0xa8))
  524. continue;
  525. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  526. continue;
  527. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  528. continue;
  529. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  530. continue;
  531. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  532. buf[i].data = 0x1020;
  533. /* skip the function enable register */
  534. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  535. continue;
  536. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  537. continue;
  538. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  539. continue;
  540. }
  541. if (off == NETXEN_ADDR_ERROR) {
  542. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  543. netxen_nic_driver_name, buf[i].addr);
  544. continue;
  545. }
  546. init_delay = 1;
  547. /* After writing this register, HW needs time for CRB */
  548. /* to quiet down (else crb_window returns 0xffffffff) */
  549. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  550. init_delay = 1000;
  551. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  552. /* hold xdma in reset also */
  553. buf[i].data = NETXEN_NIC_XDMA_RESET;
  554. buf[i].data = 0x8000ff;
  555. }
  556. }
  557. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  558. msleep(init_delay);
  559. }
  560. kfree(buf);
  561. /* disable_peg_cache_all */
  562. /* unreset_net_cache */
  563. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  564. adapter->hw_read_wx(adapter,
  565. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  566. netxen_crb_writelit_adapter(adapter,
  567. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  568. }
  569. /* p2dn replyCount */
  570. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  571. /* disable_peg_cache 0 */
  572. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  573. /* disable_peg_cache 1 */
  574. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  575. /* peg_clr_all */
  576. /* peg_clr 0 */
  577. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  578. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  579. /* peg_clr 1 */
  580. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  581. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  582. /* peg_clr 2 */
  583. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  584. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  585. /* peg_clr 3 */
  586. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  587. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  588. return 0;
  589. }
  590. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  591. {
  592. uint64_t addr;
  593. uint32_t hi;
  594. uint32_t lo;
  595. adapter->dummy_dma.addr =
  596. pci_alloc_consistent(adapter->pdev,
  597. NETXEN_HOST_DUMMY_DMA_SIZE,
  598. &adapter->dummy_dma.phys_addr);
  599. if (adapter->dummy_dma.addr == NULL) {
  600. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  601. __func__);
  602. return -ENOMEM;
  603. }
  604. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  605. hi = (addr >> 32) & 0xffffffff;
  606. lo = addr & 0xffffffff;
  607. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  608. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  609. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  610. uint32_t temp = 0;
  611. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  612. }
  613. return 0;
  614. }
  615. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  616. {
  617. int i = 100;
  618. if (!adapter->dummy_dma.addr)
  619. return;
  620. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  621. do {
  622. if (dma_watchdog_shutdown_request(adapter) == 1)
  623. break;
  624. msleep(50);
  625. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  626. break;
  627. } while (--i);
  628. }
  629. if (i) {
  630. pci_free_consistent(adapter->pdev,
  631. NETXEN_HOST_DUMMY_DMA_SIZE,
  632. adapter->dummy_dma.addr,
  633. adapter->dummy_dma.phys_addr);
  634. adapter->dummy_dma.addr = NULL;
  635. } else {
  636. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  637. adapter->netdev->name);
  638. }
  639. }
  640. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  641. {
  642. u32 val = 0;
  643. int retries = 60;
  644. if (!pegtune_val) {
  645. do {
  646. val = adapter->pci_read_normalize(adapter,
  647. CRB_CMDPEG_STATE);
  648. if (val == PHAN_INITIALIZE_COMPLETE ||
  649. val == PHAN_INITIALIZE_ACK)
  650. return 0;
  651. msleep(500);
  652. } while (--retries);
  653. if (!retries) {
  654. pegtune_val = adapter->pci_read_normalize(adapter,
  655. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  656. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  657. "pegtune_val=%x\n", pegtune_val);
  658. return -1;
  659. }
  660. }
  661. return 0;
  662. }
  663. static int
  664. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  665. {
  666. u32 val = 0;
  667. int retries = 2000;
  668. do {
  669. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  670. if (val == PHAN_PEG_RCV_INITIALIZED)
  671. return 0;
  672. msleep(10);
  673. } while (--retries);
  674. if (!retries) {
  675. printk(KERN_ERR "Receive Peg initialization not "
  676. "complete, state: 0x%x.\n", val);
  677. return -EIO;
  678. }
  679. return 0;
  680. }
  681. int netxen_init_firmware(struct netxen_adapter *adapter)
  682. {
  683. int err;
  684. err = netxen_receive_peg_ready(adapter);
  685. if (err)
  686. return err;
  687. adapter->pci_write_normalize(adapter,
  688. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  689. adapter->pci_write_normalize(adapter,
  690. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  691. adapter->pci_write_normalize(adapter,
  692. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  693. adapter->pci_write_normalize(adapter,
  694. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  695. return err;
  696. }
  697. static int
  698. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  699. struct nx_host_rds_ring *rds_ring,
  700. struct netxen_rx_buffer *buffer)
  701. {
  702. struct sk_buff *skb;
  703. dma_addr_t dma;
  704. struct pci_dev *pdev = adapter->pdev;
  705. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  706. if (!buffer->skb)
  707. return 1;
  708. skb = buffer->skb;
  709. if (!adapter->ahw.cut_through)
  710. skb_reserve(skb, 2);
  711. dma = pci_map_single(pdev, skb->data,
  712. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  713. if (pci_dma_mapping_error(pdev, dma)) {
  714. dev_kfree_skb_any(skb);
  715. buffer->skb = NULL;
  716. return 1;
  717. }
  718. buffer->skb = skb;
  719. buffer->dma = dma;
  720. buffer->state = NETXEN_BUFFER_BUSY;
  721. return 0;
  722. }
  723. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  724. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  725. {
  726. struct netxen_rx_buffer *buffer;
  727. struct sk_buff *skb;
  728. buffer = &rds_ring->rx_buf_arr[index];
  729. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  730. PCI_DMA_FROMDEVICE);
  731. skb = buffer->skb;
  732. if (!skb)
  733. goto no_skb;
  734. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  735. adapter->stats.csummed++;
  736. skb->ip_summed = CHECKSUM_UNNECESSARY;
  737. } else
  738. skb->ip_summed = CHECKSUM_NONE;
  739. skb->dev = adapter->netdev;
  740. buffer->skb = NULL;
  741. no_skb:
  742. buffer->state = NETXEN_BUFFER_FREE;
  743. return skb;
  744. }
  745. static struct netxen_rx_buffer *
  746. netxen_process_rcv(struct netxen_adapter *adapter,
  747. int ring, int index, int length, int cksum, int pkt_offset)
  748. {
  749. struct net_device *netdev = adapter->netdev;
  750. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  751. struct netxen_rx_buffer *buffer;
  752. struct sk_buff *skb;
  753. struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
  754. if (unlikely(index > rds_ring->num_desc))
  755. return NULL;
  756. buffer = &rds_ring->rx_buf_arr[index];
  757. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  758. if (!skb)
  759. return buffer;
  760. if (length > rds_ring->skb_size)
  761. skb_put(skb, rds_ring->skb_size);
  762. else
  763. skb_put(skb, length);
  764. if (pkt_offset)
  765. skb_pull(skb, pkt_offset);
  766. skb->protocol = eth_type_trans(skb, netdev);
  767. netif_receive_skb(skb);
  768. adapter->stats.no_rcv++;
  769. adapter->stats.rxbytes += length;
  770. return buffer;
  771. }
  772. #define netxen_merge_rx_buffers(list, head) \
  773. do { list_splice_tail_init(list, head); } while (0);
  774. int
  775. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  776. {
  777. struct netxen_adapter *adapter = sds_ring->adapter;
  778. struct list_head *cur;
  779. struct status_desc *desc;
  780. struct netxen_rx_buffer *rxbuf;
  781. u32 consumer = sds_ring->consumer;
  782. int count = 0;
  783. u64 sts_data;
  784. int opcode, ring, index, length, cksum, pkt_offset;
  785. while (count < max) {
  786. desc = &sds_ring->desc_head[consumer];
  787. sts_data = le64_to_cpu(desc->status_desc_data);
  788. if (!(sts_data & STATUS_OWNER_HOST))
  789. break;
  790. ring = netxen_get_sts_type(sts_data);
  791. if (ring > RCV_RING_JUMBO)
  792. continue;
  793. opcode = netxen_get_sts_opcode(sts_data);
  794. index = netxen_get_sts_refhandle(sts_data);
  795. length = netxen_get_sts_totallength(sts_data);
  796. cksum = netxen_get_sts_status(sts_data);
  797. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  798. rxbuf = netxen_process_rcv(adapter, ring, index,
  799. length, cksum, pkt_offset);
  800. if (rxbuf)
  801. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  802. desc->status_desc_data = cpu_to_le64(STATUS_OWNER_PHANTOM);
  803. consumer = get_next_index(consumer, sds_ring->num_desc);
  804. count++;
  805. }
  806. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  807. struct nx_host_rds_ring *rds_ring =
  808. &adapter->recv_ctx.rds_rings[ring];
  809. if (!list_empty(&sds_ring->free_list[ring])) {
  810. list_for_each(cur, &sds_ring->free_list[ring]) {
  811. rxbuf = list_entry(cur,
  812. struct netxen_rx_buffer, list);
  813. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  814. }
  815. spin_lock(&rds_ring->lock);
  816. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  817. &rds_ring->free_list);
  818. spin_unlock(&rds_ring->lock);
  819. }
  820. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  821. }
  822. if (count) {
  823. sds_ring->consumer = consumer;
  824. adapter->pci_write_normalize(adapter,
  825. sds_ring->crb_sts_consumer, consumer);
  826. }
  827. return count;
  828. }
  829. /* Process Command status ring */
  830. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  831. {
  832. u32 sw_consumer, hw_consumer;
  833. int count = 0, i;
  834. struct netxen_cmd_buffer *buffer;
  835. struct pci_dev *pdev = adapter->pdev;
  836. struct net_device *netdev = adapter->netdev;
  837. struct netxen_skb_frag *frag;
  838. int done = 0;
  839. struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
  840. if (!spin_trylock(&adapter->tx_clean_lock))
  841. return 1;
  842. sw_consumer = tx_ring->sw_consumer;
  843. barrier(); /* hw_consumer can change underneath */
  844. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  845. while (sw_consumer != hw_consumer) {
  846. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  847. if (buffer->skb) {
  848. frag = &buffer->frag_array[0];
  849. pci_unmap_single(pdev, frag->dma, frag->length,
  850. PCI_DMA_TODEVICE);
  851. frag->dma = 0ULL;
  852. for (i = 1; i < buffer->frag_count; i++) {
  853. frag++; /* Get the next frag */
  854. pci_unmap_page(pdev, frag->dma, frag->length,
  855. PCI_DMA_TODEVICE);
  856. frag->dma = 0ULL;
  857. }
  858. adapter->stats.xmitfinished++;
  859. dev_kfree_skb_any(buffer->skb);
  860. buffer->skb = NULL;
  861. }
  862. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  863. if (++count >= MAX_STATUS_HANDLE)
  864. break;
  865. }
  866. if (count) {
  867. tx_ring->sw_consumer = sw_consumer;
  868. smp_mb();
  869. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  870. netif_tx_lock(netdev);
  871. netif_wake_queue(netdev);
  872. smp_mb();
  873. netif_tx_unlock(netdev);
  874. }
  875. }
  876. /*
  877. * If everything is freed up to consumer then check if the ring is full
  878. * If the ring is full then check if more needs to be freed and
  879. * schedule the call back again.
  880. *
  881. * This happens when there are 2 CPUs. One could be freeing and the
  882. * other filling it. If the ring is full when we get out of here and
  883. * the card has already interrupted the host then the host can miss the
  884. * interrupt.
  885. *
  886. * There is still a possible race condition and the host could miss an
  887. * interrupt. The card has to take care of this.
  888. */
  889. barrier(); /* hw_consumer can change underneath */
  890. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  891. done = (sw_consumer == hw_consumer);
  892. spin_unlock(&adapter->tx_clean_lock);
  893. return (done);
  894. }
  895. void
  896. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  897. struct nx_host_rds_ring *rds_ring)
  898. {
  899. struct rcv_desc *pdesc;
  900. struct netxen_rx_buffer *buffer;
  901. int producer, count = 0;
  902. netxen_ctx_msg msg = 0;
  903. struct list_head *head;
  904. producer = rds_ring->producer;
  905. spin_lock(&rds_ring->lock);
  906. head = &rds_ring->free_list;
  907. while (!list_empty(head)) {
  908. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  909. if (!buffer->skb) {
  910. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  911. break;
  912. }
  913. count++;
  914. list_del(&buffer->list);
  915. /* make a rcv descriptor */
  916. pdesc = &rds_ring->desc_head[producer];
  917. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  918. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  919. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  920. producer = get_next_index(producer, rds_ring->num_desc);
  921. }
  922. spin_unlock(&rds_ring->lock);
  923. if (count) {
  924. rds_ring->producer = producer;
  925. adapter->pci_write_normalize(adapter,
  926. rds_ring->crb_rcv_producer,
  927. (producer-1) & (rds_ring->num_desc-1));
  928. if (adapter->fw_major < 4) {
  929. /*
  930. * Write a doorbell msg to tell phanmon of change in
  931. * receive ring producer
  932. * Only for firmware version < 4.0.0
  933. */
  934. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  935. netxen_set_msg_privid(msg);
  936. netxen_set_msg_count(msg,
  937. ((producer - 1) &
  938. (rds_ring->num_desc - 1)));
  939. netxen_set_msg_ctxid(msg, adapter->portnum);
  940. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  941. writel(msg,
  942. DB_NORMALIZE(adapter,
  943. NETXEN_RCV_PRODUCER_OFFSET));
  944. }
  945. }
  946. }
  947. static void
  948. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  949. struct nx_host_rds_ring *rds_ring)
  950. {
  951. struct rcv_desc *pdesc;
  952. struct netxen_rx_buffer *buffer;
  953. int producer, count = 0;
  954. struct list_head *head;
  955. producer = rds_ring->producer;
  956. if (!spin_trylock(&rds_ring->lock))
  957. return;
  958. head = &rds_ring->free_list;
  959. while (!list_empty(head)) {
  960. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  961. if (!buffer->skb) {
  962. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  963. break;
  964. }
  965. count++;
  966. list_del(&buffer->list);
  967. /* make a rcv descriptor */
  968. pdesc = &rds_ring->desc_head[producer];
  969. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  970. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  971. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  972. producer = get_next_index(producer, rds_ring->num_desc);
  973. }
  974. if (count) {
  975. rds_ring->producer = producer;
  976. adapter->pci_write_normalize(adapter,
  977. rds_ring->crb_rcv_producer,
  978. (producer - 1) & (rds_ring->num_desc - 1));
  979. wmb();
  980. }
  981. spin_unlock(&rds_ring->lock);
  982. }
  983. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  984. {
  985. memset(&adapter->stats, 0, sizeof(adapter->stats));
  986. return;
  987. }