netxen_nic.h 45 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #ifndef _NETXEN_NIC_H_
  31. #define _NETXEN_NIC_H_
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/types.h>
  35. #include <linux/ioport.h>
  36. #include <linux/pci.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/etherdevice.h>
  39. #include <linux/ip.h>
  40. #include <linux/in.h>
  41. #include <linux/tcp.h>
  42. #include <linux/skbuff.h>
  43. #include <linux/ethtool.h>
  44. #include <linux/mii.h>
  45. #include <linux/timer.h>
  46. #include <linux/vmalloc.h>
  47. #include <asm/io.h>
  48. #include <asm/byteorder.h>
  49. #include "netxen_nic_hw.h"
  50. #define _NETXEN_NIC_LINUX_MAJOR 4
  51. #define _NETXEN_NIC_LINUX_MINOR 0
  52. #define _NETXEN_NIC_LINUX_SUBVERSION 30
  53. #define NETXEN_NIC_LINUX_VERSIONID "4.0.30"
  54. #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
  55. #define NETXEN_NUM_FLASH_SECTORS (64)
  56. #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  57. #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
  58. * NETXEN_FLASH_SECTOR_SIZE)
  59. #define PHAN_VENDOR_ID 0x4040
  60. #define RCV_DESC_RINGSIZE(rds_ring) \
  61. (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  62. #define RCV_BUFF_RINGSIZE(rds_ring) \
  63. (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  64. #define STATUS_DESC_RINGSIZE(sds_ring) \
  65. (sizeof(struct status_desc) * (sds_ring)->num_desc)
  66. #define TX_BUFF_RINGSIZE(tx_ring) \
  67. (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  68. #define TX_DESC_RINGSIZE(tx_ring) \
  69. (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  70. #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  71. #define NETXEN_RCV_PRODUCER_OFFSET 0
  72. #define NETXEN_RCV_PEG_DB_ID 2
  73. #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  74. #define FLASH_SUCCESS 0
  75. #define ADDR_IN_WINDOW1(off) \
  76. ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
  77. /*
  78. * normalize a 64MB crb address to 32MB PCI window
  79. * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  80. */
  81. #define NETXEN_CRB_NORMAL(reg) \
  82. ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
  83. #define NETXEN_CRB_NORMALIZE(adapter, reg) \
  84. pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
  85. #define DB_NORMALIZE(adapter, off) \
  86. (adapter->ahw.db_base + (off))
  87. #define NX_P2_C0 0x24
  88. #define NX_P2_C1 0x25
  89. #define NX_P3_A0 0x30
  90. #define NX_P3_A2 0x30
  91. #define NX_P3_B0 0x40
  92. #define NX_P3_B1 0x41
  93. #define NX_P3_B2 0x42
  94. #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
  95. #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
  96. #define FIRST_PAGE_GROUP_START 0
  97. #define FIRST_PAGE_GROUP_END 0x100000
  98. #define SECOND_PAGE_GROUP_START 0x6000000
  99. #define SECOND_PAGE_GROUP_END 0x68BC000
  100. #define THIRD_PAGE_GROUP_START 0x70E4000
  101. #define THIRD_PAGE_GROUP_END 0x8000000
  102. #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
  103. #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
  104. #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
  105. #define P2_MAX_MTU (8000)
  106. #define P3_MAX_MTU (9600)
  107. #define NX_ETHERMTU 1500
  108. #define NX_MAX_ETHERHDR 32 /* This contains some padding */
  109. #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
  110. #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
  111. #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
  112. #define NX_CT_DEFAULT_RX_BUF_LEN 2048
  113. #define MAX_RX_BUFFER_LENGTH 1760
  114. #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
  115. #define MAX_RX_LRO_BUFFER_LENGTH (8062)
  116. #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
  117. #define RX_JUMBO_DMA_MAP_LEN \
  118. (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
  119. #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
  120. /*
  121. * Maximum number of ring contexts
  122. */
  123. #define MAX_RING_CTX 1
  124. /* Opcodes to be used with the commands */
  125. #define TX_ETHER_PKT 0x01
  126. #define TX_TCP_PKT 0x02
  127. #define TX_UDP_PKT 0x03
  128. #define TX_IP_PKT 0x04
  129. #define TX_TCP_LSO 0x05
  130. #define TX_TCP_LSO6 0x06
  131. #define TX_IPSEC 0x07
  132. #define TX_IPSEC_CMD 0x0a
  133. #define TX_TCPV6_PKT 0x0b
  134. #define TX_UDPV6_PKT 0x0c
  135. /* The following opcodes are for internal consumption. */
  136. #define NETXEN_CONTROL_OP 0x10
  137. #define PEGNET_REQUEST 0x11
  138. #define MAX_NUM_CARDS 4
  139. #define MAX_BUFFERS_PER_CMD 32
  140. /*
  141. * Following are the states of the Phantom. Phantom will set them and
  142. * Host will read to check if the fields are correct.
  143. */
  144. #define PHAN_INITIALIZE_START 0xff00
  145. #define PHAN_INITIALIZE_FAILED 0xffff
  146. #define PHAN_INITIALIZE_COMPLETE 0xff01
  147. /* Host writes the following to notify that it has done the init-handshake */
  148. #define PHAN_INITIALIZE_ACK 0xf00f
  149. #define NUM_RCV_DESC_RINGS 3
  150. #define NUM_STS_DESC_RINGS 4
  151. #define RCV_RING_NORMAL 0
  152. #define RCV_RING_JUMBO 1
  153. #define RCV_RING_LRO 2
  154. #define MAX_CMD_DESCRIPTORS 4096
  155. #define MAX_RCV_DESCRIPTORS 16384
  156. #define MAX_CMD_DESCRIPTORS_HOST 1024
  157. #define MAX_RCV_DESCRIPTORS_1G 2048
  158. #define MAX_RCV_DESCRIPTORS_10G 4096
  159. #define MAX_JUMBO_RCV_DESCRIPTORS 1024
  160. #define MAX_LRO_RCV_DESCRIPTORS 8
  161. #define NETXEN_CTX_SIGNATURE 0xdee0
  162. #define NETXEN_RCV_PRODUCER(ringid) (ringid)
  163. #define PHAN_PEG_RCV_INITIALIZED 0xff01
  164. #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
  165. #define get_next_index(index, length) \
  166. (((index) + 1) & ((length) - 1))
  167. #define get_index_range(index,length,count) \
  168. (((index) + (count)) & ((length) - 1))
  169. #define MPORT_SINGLE_FUNCTION_MODE 0x1111
  170. #define MPORT_MULTI_FUNCTION_MODE 0x2222
  171. #include "netxen_nic_phan_reg.h"
  172. /*
  173. * NetXen host-peg signal message structure
  174. *
  175. * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
  176. * Bit 2 : priv_id => must be 1
  177. * Bit 3-17 : count => for doorbell
  178. * Bit 18-27 : ctx_id => Context id
  179. * Bit 28-31 : opcode
  180. */
  181. typedef u32 netxen_ctx_msg;
  182. #define netxen_set_msg_peg_id(config_word, val) \
  183. ((config_word) &= ~3, (config_word) |= val & 3)
  184. #define netxen_set_msg_privid(config_word) \
  185. ((config_word) |= 1 << 2)
  186. #define netxen_set_msg_count(config_word, val) \
  187. ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
  188. #define netxen_set_msg_ctxid(config_word, val) \
  189. ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
  190. #define netxen_set_msg_opcode(config_word, val) \
  191. ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
  192. struct netxen_rcv_context {
  193. __le64 rcv_ring_addr;
  194. __le32 rcv_ring_size;
  195. __le32 rsrvd;
  196. };
  197. struct netxen_ring_ctx {
  198. /* one command ring */
  199. __le64 cmd_consumer_offset;
  200. __le64 cmd_ring_addr;
  201. __le32 cmd_ring_size;
  202. __le32 rsrvd;
  203. /* three receive rings */
  204. struct netxen_rcv_context rcv_ctx[3];
  205. /* one status ring */
  206. __le64 sts_ring_addr;
  207. __le32 sts_ring_size;
  208. __le32 ctx_id;
  209. } __attribute__ ((aligned(64)));
  210. /*
  211. * Following data structures describe the descriptors that will be used.
  212. * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
  213. * we are doing LSO (above the 1500 size packet) only.
  214. */
  215. /*
  216. * The size of reference handle been changed to 16 bits to pass the MSS fields
  217. * for the LSO packet
  218. */
  219. #define FLAGS_CHECKSUM_ENABLED 0x01
  220. #define FLAGS_LSO_ENABLED 0x02
  221. #define FLAGS_IPSEC_SA_ADD 0x04
  222. #define FLAGS_IPSEC_SA_DELETE 0x08
  223. #define FLAGS_VLAN_TAGGED 0x10
  224. #define netxen_set_cmd_desc_port(cmd_desc, var) \
  225. ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
  226. #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
  227. ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
  228. #define netxen_set_tx_port(_desc, _port) \
  229. (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
  230. #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
  231. (_desc)->flags_opcode = \
  232. cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
  233. #define netxen_set_tx_frags_len(_desc, _frags, _len) \
  234. (_desc)->num_of_buffers_total_length = \
  235. cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
  236. struct cmd_desc_type0 {
  237. u8 tcp_hdr_offset; /* For LSO only */
  238. u8 ip_hdr_offset; /* For LSO only */
  239. /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
  240. __le16 flags_opcode;
  241. /* Bit pattern: 0-7 total number of segments,
  242. 8-31 Total size of the packet */
  243. __le32 num_of_buffers_total_length;
  244. union {
  245. struct {
  246. __le32 addr_low_part2;
  247. __le32 addr_high_part2;
  248. };
  249. __le64 addr_buffer2;
  250. };
  251. __le16 reference_handle; /* changed to u16 to add mss */
  252. __le16 mss; /* passed by NDIS_PACKET for LSO */
  253. /* Bit pattern 0-3 port, 0-3 ctx id */
  254. u8 port_ctxid;
  255. u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
  256. __le16 conn_id; /* IPSec offoad only */
  257. union {
  258. struct {
  259. __le32 addr_low_part3;
  260. __le32 addr_high_part3;
  261. };
  262. __le64 addr_buffer3;
  263. };
  264. union {
  265. struct {
  266. __le32 addr_low_part1;
  267. __le32 addr_high_part1;
  268. };
  269. __le64 addr_buffer1;
  270. };
  271. __le16 buffer_length[4];
  272. union {
  273. struct {
  274. __le32 addr_low_part4;
  275. __le32 addr_high_part4;
  276. };
  277. __le64 addr_buffer4;
  278. };
  279. __le64 unused;
  280. } __attribute__ ((aligned(64)));
  281. /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
  282. struct rcv_desc {
  283. __le16 reference_handle;
  284. __le16 reserved;
  285. __le32 buffer_length; /* allocated buffer length (usually 2K) */
  286. __le64 addr_buffer;
  287. };
  288. /* opcode field in status_desc */
  289. #define NETXEN_NIC_RXPKT_DESC 0x04
  290. #define NETXEN_OLD_RXPKT_DESC 0x3f
  291. /* for status field in status_desc */
  292. #define STATUS_NEED_CKSUM (1)
  293. #define STATUS_CKSUM_OK (2)
  294. /* owner bits of status_desc */
  295. #define STATUS_OWNER_HOST (0x1ULL << 56)
  296. #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
  297. /* Note: sizeof(status_desc) should always be a mutliple of 2 */
  298. #define netxen_get_sts_port(sts_data) \
  299. ((sts_data) & 0x0F)
  300. #define netxen_get_sts_status(sts_data) \
  301. (((sts_data) >> 4) & 0x0F)
  302. #define netxen_get_sts_type(sts_data) \
  303. (((sts_data) >> 8) & 0x0F)
  304. #define netxen_get_sts_totallength(sts_data) \
  305. (((sts_data) >> 12) & 0xFFFF)
  306. #define netxen_get_sts_refhandle(sts_data) \
  307. (((sts_data) >> 28) & 0xFFFF)
  308. #define netxen_get_sts_prot(sts_data) \
  309. (((sts_data) >> 44) & 0x0F)
  310. #define netxen_get_sts_pkt_offset(sts_data) \
  311. (((sts_data) >> 48) & 0x1F)
  312. #define netxen_get_sts_opcode(sts_data) \
  313. (((sts_data) >> 58) & 0x03F)
  314. struct status_desc {
  315. /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
  316. 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
  317. 53-55 desc_cnt, 56-57 owner, 58-63 opcode
  318. */
  319. __le64 status_desc_data;
  320. union {
  321. struct {
  322. __le32 hash_value;
  323. u8 hash_type;
  324. u8 msg_type;
  325. u8 unused;
  326. union {
  327. /* Bit pattern: 0-6 lro_count indicates frag
  328. * sequence, 7 last_frag indicates last frag
  329. */
  330. u8 lro;
  331. /* chained buffers */
  332. u8 nr_frags;
  333. };
  334. };
  335. struct {
  336. __le16 frag_handles[4];
  337. };
  338. };
  339. } __attribute__ ((aligned(16)));
  340. /* The version of the main data structure */
  341. #define NETXEN_BDINFO_VERSION 1
  342. /* Magic number to let user know flash is programmed */
  343. #define NETXEN_BDINFO_MAGIC 0x12345678
  344. /* Max number of Gig ports on a Phantom board */
  345. #define NETXEN_MAX_PORTS 4
  346. #define NETXEN_BRDTYPE_P1_BD 0x0000
  347. #define NETXEN_BRDTYPE_P1_SB 0x0001
  348. #define NETXEN_BRDTYPE_P1_SMAX 0x0002
  349. #define NETXEN_BRDTYPE_P1_SOCK 0x0003
  350. #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
  351. #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
  352. #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
  353. #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
  354. #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
  355. #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
  356. #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
  357. #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
  358. #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
  359. #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
  360. #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
  361. #define NETXEN_BRDTYPE_P3_4_GB 0x0024
  362. #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
  363. #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
  364. #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
  365. #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
  366. #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
  367. #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
  368. #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
  369. #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
  370. #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
  371. #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
  372. struct netxen_board_info {
  373. u32 header_version;
  374. u32 board_mfg;
  375. u32 board_type;
  376. u32 board_num;
  377. u32 chip_id;
  378. u32 chip_minor;
  379. u32 chip_major;
  380. u32 chip_pkg;
  381. u32 chip_lot;
  382. u32 port_mask; /* available niu ports */
  383. u32 peg_mask; /* available pegs */
  384. u32 icache_ok; /* can we run with icache? */
  385. u32 dcache_ok; /* can we run with dcache? */
  386. u32 casper_ok;
  387. u32 mac_addr_lo_0;
  388. u32 mac_addr_lo_1;
  389. u32 mac_addr_lo_2;
  390. u32 mac_addr_lo_3;
  391. /* MN-related config */
  392. u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
  393. u32 mn_sync_shift_cclk;
  394. u32 mn_sync_shift_mclk;
  395. u32 mn_wb_en;
  396. u32 mn_crystal_freq; /* in MHz */
  397. u32 mn_speed; /* in MHz */
  398. u32 mn_org;
  399. u32 mn_depth;
  400. u32 mn_ranks_0; /* ranks per slot */
  401. u32 mn_ranks_1; /* ranks per slot */
  402. u32 mn_rd_latency_0;
  403. u32 mn_rd_latency_1;
  404. u32 mn_rd_latency_2;
  405. u32 mn_rd_latency_3;
  406. u32 mn_rd_latency_4;
  407. u32 mn_rd_latency_5;
  408. u32 mn_rd_latency_6;
  409. u32 mn_rd_latency_7;
  410. u32 mn_rd_latency_8;
  411. u32 mn_dll_val[18];
  412. u32 mn_mode_reg; /* MIU DDR Mode Register */
  413. u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
  414. u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
  415. u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
  416. u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
  417. /* SN-related config */
  418. u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
  419. u32 sn_pt_mode; /* pass through mode */
  420. u32 sn_ecc_en;
  421. u32 sn_wb_en;
  422. u32 sn_crystal_freq;
  423. u32 sn_speed;
  424. u32 sn_org;
  425. u32 sn_depth;
  426. u32 sn_dll_tap;
  427. u32 sn_rd_latency;
  428. u32 mac_addr_hi_0;
  429. u32 mac_addr_hi_1;
  430. u32 mac_addr_hi_2;
  431. u32 mac_addr_hi_3;
  432. u32 magic; /* indicates flash has been initialized */
  433. u32 mn_rdimm;
  434. u32 mn_dll_override;
  435. };
  436. #define FLASH_NUM_PORTS (4)
  437. struct netxen_flash_mac_addr {
  438. u32 flash_addr[32];
  439. };
  440. struct netxen_user_old_info {
  441. u8 flash_md5[16];
  442. u8 crbinit_md5[16];
  443. u8 brdcfg_md5[16];
  444. /* bootloader */
  445. u32 bootld_version;
  446. u32 bootld_size;
  447. u8 bootld_md5[16];
  448. /* image */
  449. u32 image_version;
  450. u32 image_size;
  451. u8 image_md5[16];
  452. /* primary image status */
  453. u32 primary_status;
  454. u32 secondary_present;
  455. /* MAC address , 4 ports */
  456. struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
  457. };
  458. #define FLASH_NUM_MAC_PER_PORT 32
  459. struct netxen_user_info {
  460. u8 flash_md5[16 * 64];
  461. /* bootloader */
  462. u32 bootld_version;
  463. u32 bootld_size;
  464. /* image */
  465. u32 image_version;
  466. u32 image_size;
  467. /* primary image status */
  468. u32 primary_status;
  469. u32 secondary_present;
  470. /* MAC address , 4 ports, 32 address per port */
  471. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  472. u32 sub_sys_id;
  473. u8 serial_num[32];
  474. /* Any user defined data */
  475. };
  476. /*
  477. * Flash Layout - new format.
  478. */
  479. struct netxen_new_user_info {
  480. u8 flash_md5[16 * 64];
  481. /* bootloader */
  482. u32 bootld_version;
  483. u32 bootld_size;
  484. /* image */
  485. u32 image_version;
  486. u32 image_size;
  487. /* primary image status */
  488. u32 primary_status;
  489. u32 secondary_present;
  490. /* MAC address , 4 ports, 32 address per port */
  491. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  492. u32 sub_sys_id;
  493. u8 serial_num[32];
  494. /* Any user defined data */
  495. };
  496. #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
  497. #define SECONDARY_IMAGE_ABSENT 0xffffffff
  498. #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
  499. #define PRIMARY_IMAGE_BAD 0xffffffff
  500. /* Flash memory map */
  501. #define NETXEN_CRBINIT_START 0 /* crbinit section */
  502. #define NETXEN_BRDCFG_START 0x4000 /* board config */
  503. #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
  504. #define NETXEN_BOOTLD_START 0x10000 /* bootld */
  505. #define NETXEN_IMAGE_START 0x43000 /* compressed image */
  506. #define NETXEN_SECONDARY_START 0x200000 /* backup images */
  507. #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
  508. #define NETXEN_USER_START 0x3E8000 /* Firmare info */
  509. #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
  510. #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
  511. #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
  512. #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
  513. #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
  514. #define NX_FW_MIN_SIZE (0x3fffff)
  515. #define NX_P2_MN_ROMIMAGE 0
  516. #define NX_P3_CT_ROMIMAGE 1
  517. #define NX_P3_MN_ROMIMAGE 2
  518. #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
  519. #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
  520. #define NETXEN_INIT_SECTOR (0)
  521. #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
  522. #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
  523. #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
  524. #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
  525. #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
  526. #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
  527. #define NETXEN_NUM_CONFIG_SECTORS (1)
  528. extern char netxen_nic_driver_name[];
  529. /* Number of status descriptors to handle per interrupt */
  530. #define MAX_STATUS_HANDLE (64)
  531. /*
  532. * netxen_skb_frag{} is to contain mapping info for each SG list. This
  533. * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
  534. */
  535. struct netxen_skb_frag {
  536. u64 dma;
  537. u64 length;
  538. };
  539. #define _netxen_set_bits(config_word, start, bits, val) {\
  540. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
  541. unsigned long long __tvalue = (val); \
  542. (config_word) &= ~__tmask; \
  543. (config_word) |= (((__tvalue) << (start)) & __tmask); \
  544. }
  545. #define _netxen_clear_bits(config_word, start, bits) {\
  546. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
  547. (config_word) &= ~__tmask; \
  548. }
  549. /* Following defines are for the state of the buffers */
  550. #define NETXEN_BUFFER_FREE 0
  551. #define NETXEN_BUFFER_BUSY 1
  552. /*
  553. * There will be one netxen_buffer per skb packet. These will be
  554. * used to save the dma info for pci_unmap_page()
  555. */
  556. struct netxen_cmd_buffer {
  557. struct sk_buff *skb;
  558. struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
  559. u32 frag_count;
  560. };
  561. /* In rx_buffer, we do not need multiple fragments as is a single buffer */
  562. struct netxen_rx_buffer {
  563. struct list_head list;
  564. struct sk_buff *skb;
  565. u64 dma;
  566. u16 ref_handle;
  567. u16 state;
  568. };
  569. /* Board types */
  570. #define NETXEN_NIC_GBE 0x01
  571. #define NETXEN_NIC_XGBE 0x02
  572. /*
  573. * One hardware_context{} per adapter
  574. * contains interrupt info as well shared hardware info.
  575. */
  576. struct netxen_hardware_context {
  577. void __iomem *pci_base0;
  578. void __iomem *pci_base1;
  579. void __iomem *pci_base2;
  580. void __iomem *db_base;
  581. unsigned long db_len;
  582. unsigned long pci_len0;
  583. int qdr_sn_window;
  584. int ddr_mn_window;
  585. unsigned long mn_win_crb;
  586. unsigned long ms_win_crb;
  587. u8 cut_through;
  588. u8 revision_id;
  589. u8 pci_func;
  590. u8 linkup;
  591. u16 port_type;
  592. u16 board_type;
  593. };
  594. #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
  595. #define ETHERNET_FCS_SIZE 4
  596. struct netxen_adapter_stats {
  597. u64 xmitcalled;
  598. u64 xmitfinished;
  599. u64 rxdropped;
  600. u64 txdropped;
  601. u64 csummed;
  602. u64 no_rcv;
  603. u64 rxbytes;
  604. u64 txbytes;
  605. };
  606. /*
  607. * Rcv Descriptor Context. One such per Rcv Descriptor. There may
  608. * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
  609. */
  610. struct nx_host_rds_ring {
  611. u32 producer;
  612. u32 crb_rcv_producer;
  613. u32 num_desc;
  614. u32 dma_size;
  615. u32 skb_size;
  616. u32 flags;
  617. struct rcv_desc *desc_head;
  618. struct netxen_rx_buffer *rx_buf_arr;
  619. struct list_head free_list;
  620. spinlock_t lock;
  621. dma_addr_t phys_addr;
  622. };
  623. struct nx_host_sds_ring {
  624. u32 consumer;
  625. u32 crb_sts_consumer;
  626. u32 crb_intr_mask;
  627. u32 num_desc;
  628. struct status_desc *desc_head;
  629. struct netxen_adapter *adapter;
  630. struct napi_struct napi;
  631. struct list_head free_list[NUM_RCV_DESC_RINGS];
  632. int irq;
  633. dma_addr_t phys_addr;
  634. char name[IFNAMSIZ+4];
  635. };
  636. struct nx_host_tx_ring {
  637. u32 producer;
  638. __le32 *hw_consumer;
  639. u32 sw_consumer;
  640. u32 crb_cmd_producer;
  641. u32 crb_cmd_consumer;
  642. u32 num_desc;
  643. struct netxen_cmd_buffer *cmd_buf_arr;
  644. struct cmd_desc_type0 *desc_head;
  645. dma_addr_t phys_addr;
  646. };
  647. /*
  648. * Receive context. There is one such structure per instance of the
  649. * receive processing. Any state information that is relevant to
  650. * the receive, and is must be in this structure. The global data may be
  651. * present elsewhere.
  652. */
  653. struct netxen_recv_context {
  654. u32 state;
  655. u16 context_id;
  656. u16 virt_port;
  657. struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
  658. struct nx_host_sds_ring sds_rings[NUM_STS_DESC_RINGS];
  659. };
  660. /* New HW context creation */
  661. #define NX_OS_CRB_RETRY_COUNT 4000
  662. #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
  663. (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
  664. #define NX_CDRP_CLEAR 0x00000000
  665. #define NX_CDRP_CMD_BIT 0x80000000
  666. /*
  667. * All responses must have the NX_CDRP_CMD_BIT cleared
  668. * in the crb NX_CDRP_CRB_OFFSET.
  669. */
  670. #define NX_CDRP_FORM_RSP(rsp) (rsp)
  671. #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
  672. #define NX_CDRP_RSP_OK 0x00000001
  673. #define NX_CDRP_RSP_FAIL 0x00000002
  674. #define NX_CDRP_RSP_TIMEOUT 0x00000003
  675. /*
  676. * All commands must have the NX_CDRP_CMD_BIT set in
  677. * the crb NX_CDRP_CRB_OFFSET.
  678. */
  679. #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
  680. #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
  681. #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
  682. #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
  683. #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
  684. #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
  685. #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
  686. #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
  687. #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
  688. #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
  689. #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
  690. #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
  691. #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
  692. #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
  693. #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
  694. #define NX_CDRP_CMD_SET_MTU 0x00000012
  695. #define NX_CDRP_CMD_MAX 0x00000013
  696. #define NX_RCODE_SUCCESS 0
  697. #define NX_RCODE_NO_HOST_MEM 1
  698. #define NX_RCODE_NO_HOST_RESOURCE 2
  699. #define NX_RCODE_NO_CARD_CRB 3
  700. #define NX_RCODE_NO_CARD_MEM 4
  701. #define NX_RCODE_NO_CARD_RESOURCE 5
  702. #define NX_RCODE_INVALID_ARGS 6
  703. #define NX_RCODE_INVALID_ACTION 7
  704. #define NX_RCODE_INVALID_STATE 8
  705. #define NX_RCODE_NOT_SUPPORTED 9
  706. #define NX_RCODE_NOT_PERMITTED 10
  707. #define NX_RCODE_NOT_READY 11
  708. #define NX_RCODE_DOES_NOT_EXIST 12
  709. #define NX_RCODE_ALREADY_EXISTS 13
  710. #define NX_RCODE_BAD_SIGNATURE 14
  711. #define NX_RCODE_CMD_NOT_IMPL 15
  712. #define NX_RCODE_CMD_INVALID 16
  713. #define NX_RCODE_TIMEOUT 17
  714. #define NX_RCODE_CMD_FAILED 18
  715. #define NX_RCODE_MAX_EXCEEDED 19
  716. #define NX_RCODE_MAX 20
  717. #define NX_DESTROY_CTX_RESET 0
  718. #define NX_DESTROY_CTX_D3_RESET 1
  719. #define NX_DESTROY_CTX_MAX 2
  720. /*
  721. * Capabilities
  722. */
  723. #define NX_CAP_BIT(class, bit) (1 << bit)
  724. #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
  725. #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
  726. #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
  727. #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
  728. #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
  729. #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
  730. #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
  731. #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
  732. #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
  733. /*
  734. * Context state
  735. */
  736. #define NX_HOST_CTX_STATE_FREED 0
  737. #define NX_HOST_CTX_STATE_ALLOCATED 1
  738. #define NX_HOST_CTX_STATE_ACTIVE 2
  739. #define NX_HOST_CTX_STATE_DISABLED 3
  740. #define NX_HOST_CTX_STATE_QUIESCED 4
  741. #define NX_HOST_CTX_STATE_MAX 5
  742. /*
  743. * Rx context
  744. */
  745. typedef struct {
  746. __le64 host_phys_addr; /* Ring base addr */
  747. __le32 ring_size; /* Ring entries */
  748. __le16 msi_index;
  749. __le16 rsvd; /* Padding */
  750. } nx_hostrq_sds_ring_t;
  751. typedef struct {
  752. __le64 host_phys_addr; /* Ring base addr */
  753. __le64 buff_size; /* Packet buffer size */
  754. __le32 ring_size; /* Ring entries */
  755. __le32 ring_kind; /* Class of ring */
  756. } nx_hostrq_rds_ring_t;
  757. typedef struct {
  758. __le64 host_rsp_dma_addr; /* Response dma'd here */
  759. __le32 capabilities[4]; /* Flag bit vector */
  760. __le32 host_int_crb_mode; /* Interrupt crb usage */
  761. __le32 host_rds_crb_mode; /* RDS crb usage */
  762. /* These ring offsets are relative to data[0] below */
  763. __le32 rds_ring_offset; /* Offset to RDS config */
  764. __le32 sds_ring_offset; /* Offset to SDS config */
  765. __le16 num_rds_rings; /* Count of RDS rings */
  766. __le16 num_sds_rings; /* Count of SDS rings */
  767. __le16 rsvd1; /* Padding */
  768. __le16 rsvd2; /* Padding */
  769. u8 reserved[128]; /* reserve space for future expansion*/
  770. /* MUST BE 64-bit aligned.
  771. The following is packed:
  772. - N hostrq_rds_rings
  773. - N hostrq_sds_rings */
  774. char data[0];
  775. } nx_hostrq_rx_ctx_t;
  776. typedef struct {
  777. __le32 host_producer_crb; /* Crb to use */
  778. __le32 rsvd1; /* Padding */
  779. } nx_cardrsp_rds_ring_t;
  780. typedef struct {
  781. __le32 host_consumer_crb; /* Crb to use */
  782. __le32 interrupt_crb; /* Crb to use */
  783. } nx_cardrsp_sds_ring_t;
  784. typedef struct {
  785. /* These ring offsets are relative to data[0] below */
  786. __le32 rds_ring_offset; /* Offset to RDS config */
  787. __le32 sds_ring_offset; /* Offset to SDS config */
  788. __le32 host_ctx_state; /* Starting State */
  789. __le32 num_fn_per_port; /* How many PCI fn share the port */
  790. __le16 num_rds_rings; /* Count of RDS rings */
  791. __le16 num_sds_rings; /* Count of SDS rings */
  792. __le16 context_id; /* Handle for context */
  793. u8 phys_port; /* Physical id of port */
  794. u8 virt_port; /* Virtual/Logical id of port */
  795. u8 reserved[128]; /* save space for future expansion */
  796. /* MUST BE 64-bit aligned.
  797. The following is packed:
  798. - N cardrsp_rds_rings
  799. - N cardrs_sds_rings */
  800. char data[0];
  801. } nx_cardrsp_rx_ctx_t;
  802. #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
  803. (sizeof(HOSTRQ_RX) + \
  804. (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
  805. (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
  806. #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
  807. (sizeof(CARDRSP_RX) + \
  808. (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
  809. (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
  810. /*
  811. * Tx context
  812. */
  813. typedef struct {
  814. __le64 host_phys_addr; /* Ring base addr */
  815. __le32 ring_size; /* Ring entries */
  816. __le32 rsvd; /* Padding */
  817. } nx_hostrq_cds_ring_t;
  818. typedef struct {
  819. __le64 host_rsp_dma_addr; /* Response dma'd here */
  820. __le64 cmd_cons_dma_addr; /* */
  821. __le64 dummy_dma_addr; /* */
  822. __le32 capabilities[4]; /* Flag bit vector */
  823. __le32 host_int_crb_mode; /* Interrupt crb usage */
  824. __le32 rsvd1; /* Padding */
  825. __le16 rsvd2; /* Padding */
  826. __le16 interrupt_ctl;
  827. __le16 msi_index;
  828. __le16 rsvd3; /* Padding */
  829. nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
  830. u8 reserved[128]; /* future expansion */
  831. } nx_hostrq_tx_ctx_t;
  832. typedef struct {
  833. __le32 host_producer_crb; /* Crb to use */
  834. __le32 interrupt_crb; /* Crb to use */
  835. } nx_cardrsp_cds_ring_t;
  836. typedef struct {
  837. __le32 host_ctx_state; /* Starting state */
  838. __le16 context_id; /* Handle for context */
  839. u8 phys_port; /* Physical id of port */
  840. u8 virt_port; /* Virtual/Logical id of port */
  841. nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
  842. u8 reserved[128]; /* future expansion */
  843. } nx_cardrsp_tx_ctx_t;
  844. #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
  845. #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
  846. /* CRB */
  847. #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
  848. #define NX_HOST_RDS_CRB_MODE_SHARED 1
  849. #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
  850. #define NX_HOST_RDS_CRB_MODE_MAX 3
  851. #define NX_HOST_INT_CRB_MODE_UNIQUE 0
  852. #define NX_HOST_INT_CRB_MODE_SHARED 1
  853. #define NX_HOST_INT_CRB_MODE_NORX 2
  854. #define NX_HOST_INT_CRB_MODE_NOTX 3
  855. #define NX_HOST_INT_CRB_MODE_NORXTX 4
  856. /* MAC */
  857. #define MC_COUNT_P2 16
  858. #define MC_COUNT_P3 38
  859. #define NETXEN_MAC_NOOP 0
  860. #define NETXEN_MAC_ADD 1
  861. #define NETXEN_MAC_DEL 2
  862. typedef struct nx_mac_list_s {
  863. struct nx_mac_list_s *next;
  864. uint8_t mac_addr[MAX_ADDR_LEN];
  865. } nx_mac_list_t;
  866. /*
  867. * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
  868. * adjusted based on configured MTU.
  869. */
  870. #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
  871. #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
  872. #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
  873. #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
  874. #define NETXEN_NIC_INTR_DEFAULT 0x04
  875. typedef union {
  876. struct {
  877. uint16_t rx_packets;
  878. uint16_t rx_time_us;
  879. uint16_t tx_packets;
  880. uint16_t tx_time_us;
  881. } data;
  882. uint64_t word;
  883. } nx_nic_intr_coalesce_data_t;
  884. typedef struct {
  885. uint16_t stats_time_us;
  886. uint16_t rate_sample_time;
  887. uint16_t flags;
  888. uint16_t rsvd_1;
  889. uint32_t low_threshold;
  890. uint32_t high_threshold;
  891. nx_nic_intr_coalesce_data_t normal;
  892. nx_nic_intr_coalesce_data_t low;
  893. nx_nic_intr_coalesce_data_t high;
  894. nx_nic_intr_coalesce_data_t irq;
  895. } nx_nic_intr_coalesce_t;
  896. #define NX_HOST_REQUEST 0x13
  897. #define NX_NIC_REQUEST 0x14
  898. #define NX_MAC_EVENT 0x1
  899. /*
  900. * Driver --> Firmware
  901. */
  902. #define NX_NIC_H2C_OPCODE_START 0
  903. #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
  904. #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
  905. #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
  906. #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
  907. #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
  908. #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
  909. #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
  910. #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
  911. #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
  912. #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
  913. #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
  914. #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
  915. #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
  916. #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
  917. #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
  918. #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
  919. #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
  920. #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
  921. #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
  922. #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
  923. #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
  924. #define NX_NIC_C2C_OPCODE 22
  925. #define NX_NIC_H2C_OPCODE_LAST 23
  926. /*
  927. * Firmware --> Driver
  928. */
  929. #define NX_NIC_C2H_OPCODE_START 128
  930. #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
  931. #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
  932. #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
  933. #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
  934. #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
  935. #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
  936. #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
  937. #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
  938. #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
  939. #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
  940. #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
  941. #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
  942. #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
  943. #define NX_NIC_C2H_OPCODE_LAST 142
  944. #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
  945. #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
  946. #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
  947. typedef struct {
  948. __le64 qhdr;
  949. __le64 req_hdr;
  950. __le64 words[6];
  951. } nx_nic_req_t;
  952. typedef struct {
  953. u8 op;
  954. u8 tag;
  955. u8 mac_addr[6];
  956. } nx_mac_req_t;
  957. #define MAX_PENDING_DESC_BLOCK_SIZE 64
  958. #define NETXEN_NIC_MSI_ENABLED 0x02
  959. #define NETXEN_NIC_MSIX_ENABLED 0x04
  960. #define NETXEN_IS_MSI_FAMILY(adapter) \
  961. ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
  962. #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
  963. #define NETXEN_MSIX_TBL_SPACE 8192
  964. #define NETXEN_PCI_REG_MSIX_TBL 0x44
  965. #define NETXEN_DB_MAPSIZE_BYTES 0x1000
  966. #define NETXEN_NETDEV_WEIGHT 128
  967. #define NETXEN_ADAPTER_UP_MAGIC 777
  968. #define NETXEN_NIC_PEG_TUNE 0
  969. struct netxen_dummy_dma {
  970. void *addr;
  971. dma_addr_t phys_addr;
  972. };
  973. struct netxen_adapter {
  974. struct netxen_hardware_context ahw;
  975. struct net_device *netdev;
  976. struct pci_dev *pdev;
  977. nx_mac_list_t *mac_list;
  978. u32 curr_window;
  979. u32 crb_win;
  980. rwlock_t adapter_lock;
  981. spinlock_t tx_clean_lock;
  982. u32 num_txd;
  983. u32 num_rxd;
  984. u32 num_jumbo_rxd;
  985. u32 num_lro_rxd;
  986. u8 max_rds_rings;
  987. u8 max_sds_rings;
  988. u8 driver_mismatch;
  989. u8 msix_supported;
  990. u8 rx_csum;
  991. u8 pci_using_dac;
  992. u8 portnum;
  993. u8 physical_port;
  994. u8 mc_enabled;
  995. u8 max_mc_count;
  996. u16 tx_context_id;
  997. u16 mtu;
  998. u16 is_up;
  999. u16 link_speed;
  1000. u16 link_duplex;
  1001. u16 link_autoneg;
  1002. u16 resv1;
  1003. u32 resv2;
  1004. u32 flags;
  1005. u32 irq;
  1006. u32 temp;
  1007. u32 fw_major;
  1008. u32 fw_version;
  1009. struct netxen_adapter_stats stats;
  1010. struct netxen_recv_context recv_ctx;
  1011. struct nx_host_tx_ring tx_ring;
  1012. /* Context interface shared between card and host */
  1013. struct netxen_ring_ctx *ctx_desc;
  1014. dma_addr_t ctx_desc_phys_addr;
  1015. int (*enable_phy_interrupts) (struct netxen_adapter *);
  1016. int (*disable_phy_interrupts) (struct netxen_adapter *);
  1017. int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
  1018. int (*set_mtu) (struct netxen_adapter *, int);
  1019. int (*set_promisc) (struct netxen_adapter *, u32);
  1020. int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
  1021. int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
  1022. int (*init_port) (struct netxen_adapter *, int);
  1023. int (*stop_port) (struct netxen_adapter *);
  1024. int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
  1025. int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
  1026. int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
  1027. int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
  1028. int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
  1029. u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
  1030. void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
  1031. u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
  1032. unsigned long (*pci_set_window)(struct netxen_adapter *,
  1033. unsigned long long);
  1034. struct netxen_legacy_intr_set legacy_intr;
  1035. struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
  1036. struct netxen_dummy_dma dummy_dma;
  1037. struct work_struct watchdog_task;
  1038. struct timer_list watchdog_timer;
  1039. struct work_struct tx_timeout_task;
  1040. struct net_device_stats net_stats;
  1041. nx_nic_intr_coalesce_t coal;
  1042. };
  1043. /*
  1044. * NetXen dma watchdog control structure
  1045. *
  1046. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1047. * Bit 1 : disable_request => 1 req disable dma watchdog
  1048. * Bit 2 : enable_request => 1 req enable dma watchdog
  1049. * Bit 3-31 : unused
  1050. */
  1051. #define netxen_set_dma_watchdog_disable_req(config_word) \
  1052. _netxen_set_bits(config_word, 1, 1, 1)
  1053. #define netxen_set_dma_watchdog_enable_req(config_word) \
  1054. _netxen_set_bits(config_word, 2, 1, 1)
  1055. #define netxen_get_dma_watchdog_enabled(config_word) \
  1056. ((config_word) & 0x1)
  1057. #define netxen_get_dma_watchdog_disabled(config_word) \
  1058. (((config_word) >> 1) & 0x1)
  1059. /* Max number of xmit producer threads that can run simultaneously */
  1060. #define MAX_XMIT_PRODUCERS 16
  1061. #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
  1062. ((adapter)->ahw.pci_base0 + (off))
  1063. #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
  1064. ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
  1065. #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
  1066. ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
  1067. static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
  1068. unsigned long off)
  1069. {
  1070. if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
  1071. return (adapter->ahw.pci_base0 + off);
  1072. } else if ((off < SECOND_PAGE_GROUP_END) &&
  1073. (off >= SECOND_PAGE_GROUP_START)) {
  1074. return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
  1075. } else if ((off < THIRD_PAGE_GROUP_END) &&
  1076. (off >= THIRD_PAGE_GROUP_START)) {
  1077. return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
  1078. }
  1079. return NULL;
  1080. }
  1081. static inline void __iomem *pci_base(struct netxen_adapter *adapter,
  1082. unsigned long off)
  1083. {
  1084. if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
  1085. return adapter->ahw.pci_base0;
  1086. } else if ((off < SECOND_PAGE_GROUP_END) &&
  1087. (off >= SECOND_PAGE_GROUP_START)) {
  1088. return adapter->ahw.pci_base1;
  1089. } else if ((off < THIRD_PAGE_GROUP_END) &&
  1090. (off >= THIRD_PAGE_GROUP_START)) {
  1091. return adapter->ahw.pci_base2;
  1092. }
  1093. return NULL;
  1094. }
  1095. int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  1096. int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  1097. int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  1098. int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  1099. int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
  1100. __u32 * readval);
  1101. int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
  1102. long reg, __u32 val);
  1103. /* Functions available from netxen_nic_hw.c */
  1104. int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
  1105. int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
  1106. void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
  1107. int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
  1108. void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
  1109. void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
  1110. void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
  1111. void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
  1112. int netxen_nic_get_board_info(struct netxen_adapter *adapter);
  1113. void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
  1114. int netxen_nic_wol_supported(struct netxen_adapter *adapter);
  1115. int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
  1116. ulong off, void *data, int len);
  1117. int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
  1118. ulong off, void *data, int len);
  1119. int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
  1120. u64 off, void *data, int size);
  1121. int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
  1122. u64 off, void *data, int size);
  1123. int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
  1124. u64 off, u32 data);
  1125. u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
  1126. void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
  1127. u64 off, u32 data);
  1128. u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
  1129. unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
  1130. unsigned long long addr);
  1131. void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
  1132. u32 wndw);
  1133. int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
  1134. ulong off, void *data, int len);
  1135. int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
  1136. ulong off, void *data, int len);
  1137. int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
  1138. u64 off, void *data, int size);
  1139. int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
  1140. u64 off, void *data, int size);
  1141. void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
  1142. unsigned long off, int data);
  1143. int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
  1144. u64 off, u32 data);
  1145. u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
  1146. void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
  1147. u64 off, u32 data);
  1148. u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
  1149. unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
  1150. unsigned long long addr);
  1151. /* Functions from netxen_nic_init.c */
  1152. void netxen_free_adapter_offload(struct netxen_adapter *adapter);
  1153. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
  1154. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
  1155. int netxen_load_firmware(struct netxen_adapter *adapter);
  1156. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
  1157. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
  1158. int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  1159. u8 *bytes, size_t size);
  1160. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  1161. u8 *bytes, size_t size);
  1162. int netxen_flash_unlock(struct netxen_adapter *adapter);
  1163. int netxen_backup_crbinit(struct netxen_adapter *adapter);
  1164. int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
  1165. int netxen_flash_erase_primary(struct netxen_adapter *adapter);
  1166. void netxen_halt_pegs(struct netxen_adapter *adapter);
  1167. int netxen_rom_se(struct netxen_adapter *adapter, int addr);
  1168. int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
  1169. void netxen_free_sw_resources(struct netxen_adapter *adapter);
  1170. int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
  1171. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  1172. void netxen_release_rx_buffers(struct netxen_adapter *adapter);
  1173. void netxen_release_tx_buffers(struct netxen_adapter *adapter);
  1174. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
  1175. int netxen_init_firmware(struct netxen_adapter *adapter);
  1176. void netxen_nic_clear_stats(struct netxen_adapter *adapter);
  1177. void netxen_watchdog_task(struct work_struct *work);
  1178. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1179. struct nx_host_rds_ring *rds_ring);
  1180. int netxen_process_cmd_ring(struct netxen_adapter *adapter);
  1181. int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
  1182. void netxen_p2_nic_set_multi(struct net_device *netdev);
  1183. void netxen_p3_nic_set_multi(struct net_device *netdev);
  1184. void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
  1185. int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
  1186. int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
  1187. int netxen_config_rss(struct netxen_adapter *adapter, int enable);
  1188. int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
  1189. int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
  1190. int netxen_nic_set_mac(struct net_device *netdev, void *p);
  1191. struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
  1192. void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
  1193. struct nx_host_tx_ring *tx_ring, uint32_t crb_producer);
  1194. /*
  1195. * NetXen Board information
  1196. */
  1197. #define NETXEN_MAX_SHORT_NAME 32
  1198. struct netxen_brdinfo {
  1199. int brdtype; /* type of board */
  1200. long ports; /* max no of physical ports */
  1201. char short_name[NETXEN_MAX_SHORT_NAME];
  1202. };
  1203. static const struct netxen_brdinfo netxen_boards[] = {
  1204. {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
  1205. {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
  1206. {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
  1207. {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
  1208. {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
  1209. {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
  1210. {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
  1211. {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
  1212. {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
  1213. {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
  1214. {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
  1215. {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
  1216. {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
  1217. {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
  1218. {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
  1219. {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
  1220. {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
  1221. {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
  1222. {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
  1223. };
  1224. #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
  1225. static inline void get_brd_name_by_type(u32 type, char *name)
  1226. {
  1227. int i, found = 0;
  1228. for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
  1229. if (netxen_boards[i].brdtype == type) {
  1230. strcpy(name, netxen_boards[i].short_name);
  1231. found = 1;
  1232. break;
  1233. }
  1234. }
  1235. if (!found)
  1236. name = "Unknown";
  1237. }
  1238. static inline int
  1239. dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
  1240. {
  1241. u32 ctrl;
  1242. /* check if already inactive */
  1243. if (adapter->hw_read_wx(adapter,
  1244. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  1245. printk(KERN_ERR "failed to read dma watchdog status\n");
  1246. if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
  1247. return 1;
  1248. /* Send the disable request */
  1249. netxen_set_dma_watchdog_disable_req(ctrl);
  1250. netxen_crb_writelit_adapter(adapter,
  1251. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  1252. return 0;
  1253. }
  1254. static inline int
  1255. dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
  1256. {
  1257. u32 ctrl;
  1258. if (adapter->hw_read_wx(adapter,
  1259. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  1260. printk(KERN_ERR "failed to read dma watchdog status\n");
  1261. return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
  1262. }
  1263. static inline int
  1264. dma_watchdog_wakeup(struct netxen_adapter *adapter)
  1265. {
  1266. u32 ctrl;
  1267. if (adapter->hw_read_wx(adapter,
  1268. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
  1269. printk(KERN_ERR "failed to read dma watchdog status\n");
  1270. if (netxen_get_dma_watchdog_enabled(ctrl))
  1271. return 1;
  1272. /* send the wakeup request */
  1273. netxen_set_dma_watchdog_enable_req(ctrl);
  1274. netxen_crb_writelit_adapter(adapter,
  1275. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  1276. return 0;
  1277. }
  1278. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
  1279. int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
  1280. extern void netxen_change_ringparam(struct netxen_adapter *adapter);
  1281. extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
  1282. int *valp);
  1283. extern struct ethtool_ops netxen_nic_ethtool_ops;
  1284. #endif /* __NETXEN_NIC_H_ */