dpi.c 8.1 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dpi.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "DPI"
  23. #include <linux/kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <linux/errno.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/regulator/consumer.h>
  29. #include <video/omapdss.h>
  30. #include <plat/cpu.h>
  31. #include "dss.h"
  32. static struct {
  33. struct regulator *vdds_dsi_reg;
  34. struct platform_device *dsidev;
  35. } dpi;
  36. static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
  37. {
  38. int dsi_module;
  39. dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
  40. return dsi_get_dsidev_from_id(dsi_module);
  41. }
  42. static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
  43. {
  44. if (dssdev->clocks.dispc.dispc_fclk_src ==
  45. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  46. dssdev->clocks.dispc.dispc_fclk_src ==
  47. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
  48. dssdev->clocks.dispc.channel.lcd_clk_src ==
  49. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  50. dssdev->clocks.dispc.channel.lcd_clk_src ==
  51. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
  52. return true;
  53. else
  54. return false;
  55. }
  56. static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
  57. unsigned long pck_req, unsigned long *fck, int *lck_div,
  58. int *pck_div)
  59. {
  60. struct dsi_clock_info dsi_cinfo;
  61. struct dispc_clock_info dispc_cinfo;
  62. int r;
  63. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
  64. &dsi_cinfo, &dispc_cinfo);
  65. if (r)
  66. return r;
  67. r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
  68. if (r)
  69. return r;
  70. dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
  71. r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  72. if (r) {
  73. dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
  74. return r;
  75. }
  76. *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  77. *lck_div = dispc_cinfo.lck_div;
  78. *pck_div = dispc_cinfo.pck_div;
  79. return 0;
  80. }
  81. static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
  82. unsigned long pck_req, unsigned long *fck, int *lck_div,
  83. int *pck_div)
  84. {
  85. struct dss_clock_info dss_cinfo;
  86. struct dispc_clock_info dispc_cinfo;
  87. int r;
  88. r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
  89. if (r)
  90. return r;
  91. r = dss_set_clock_div(&dss_cinfo);
  92. if (r)
  93. return r;
  94. r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  95. if (r)
  96. return r;
  97. *fck = dss_cinfo.fck;
  98. *lck_div = dispc_cinfo.lck_div;
  99. *pck_div = dispc_cinfo.pck_div;
  100. return 0;
  101. }
  102. static int dpi_set_mode(struct omap_dss_device *dssdev)
  103. {
  104. struct omap_video_timings *t = &dssdev->panel.timings;
  105. int lck_div = 0, pck_div = 0;
  106. unsigned long fck = 0;
  107. unsigned long pck;
  108. bool is_tft;
  109. int r = 0;
  110. dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
  111. dssdev->panel.acbi, dssdev->panel.acb);
  112. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  113. if (dpi_use_dsi_pll(dssdev))
  114. r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
  115. &fck, &lck_div, &pck_div);
  116. else
  117. r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
  118. &fck, &lck_div, &pck_div);
  119. if (r)
  120. return r;
  121. pck = fck / lck_div / pck_div / 1000;
  122. if (pck != t->pixel_clock) {
  123. DSSWARN("Could not find exact pixel clock. "
  124. "Requested %d kHz, got %lu kHz\n",
  125. t->pixel_clock, pck);
  126. t->pixel_clock = pck;
  127. }
  128. dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
  129. return 0;
  130. }
  131. static void dpi_basic_init(struct omap_dss_device *dssdev)
  132. {
  133. bool is_tft;
  134. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  135. dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
  136. dispc_mgr_enable_stallmode(dssdev->manager->id, false);
  137. dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
  138. OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
  139. dispc_mgr_set_tft_data_lines(dssdev->manager->id,
  140. dssdev->phy.dpi.data_lines);
  141. }
  142. int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
  143. {
  144. int r;
  145. if (dssdev->manager == NULL) {
  146. DSSERR("failed to enable display: no manager\n");
  147. return -ENODEV;
  148. }
  149. r = omap_dss_start_device(dssdev);
  150. if (r) {
  151. DSSERR("failed to start device\n");
  152. goto err_start_dev;
  153. }
  154. if (cpu_is_omap34xx()) {
  155. r = regulator_enable(dpi.vdds_dsi_reg);
  156. if (r)
  157. goto err_reg_enable;
  158. }
  159. r = dss_runtime_get();
  160. if (r)
  161. goto err_get_dss;
  162. r = dispc_runtime_get();
  163. if (r)
  164. goto err_get_dispc;
  165. dpi_basic_init(dssdev);
  166. if (dpi_use_dsi_pll(dssdev)) {
  167. r = dsi_runtime_get(dpi.dsidev);
  168. if (r)
  169. goto err_get_dsi;
  170. r = dsi_pll_init(dpi.dsidev, 0, 1);
  171. if (r)
  172. goto err_dsi_pll_init;
  173. }
  174. r = dpi_set_mode(dssdev);
  175. if (r)
  176. goto err_set_mode;
  177. mdelay(2);
  178. dssdev->manager->enable(dssdev->manager);
  179. return 0;
  180. err_set_mode:
  181. if (dpi_use_dsi_pll(dssdev))
  182. dsi_pll_uninit(dpi.dsidev, true);
  183. err_dsi_pll_init:
  184. if (dpi_use_dsi_pll(dssdev))
  185. dsi_runtime_put(dpi.dsidev);
  186. err_get_dsi:
  187. dispc_runtime_put();
  188. err_get_dispc:
  189. dss_runtime_put();
  190. err_get_dss:
  191. if (cpu_is_omap34xx())
  192. regulator_disable(dpi.vdds_dsi_reg);
  193. err_reg_enable:
  194. omap_dss_stop_device(dssdev);
  195. err_start_dev:
  196. return r;
  197. }
  198. EXPORT_SYMBOL(omapdss_dpi_display_enable);
  199. void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
  200. {
  201. dssdev->manager->disable(dssdev->manager);
  202. if (dpi_use_dsi_pll(dssdev)) {
  203. dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
  204. dsi_pll_uninit(dpi.dsidev, true);
  205. dsi_runtime_put(dpi.dsidev);
  206. }
  207. dispc_runtime_put();
  208. dss_runtime_put();
  209. if (cpu_is_omap34xx())
  210. regulator_disable(dpi.vdds_dsi_reg);
  211. omap_dss_stop_device(dssdev);
  212. }
  213. EXPORT_SYMBOL(omapdss_dpi_display_disable);
  214. void dpi_set_timings(struct omap_dss_device *dssdev,
  215. struct omap_video_timings *timings)
  216. {
  217. int r;
  218. DSSDBG("dpi_set_timings\n");
  219. dssdev->panel.timings = *timings;
  220. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  221. r = dss_runtime_get();
  222. if (r)
  223. return;
  224. r = dispc_runtime_get();
  225. if (r) {
  226. dss_runtime_put();
  227. return;
  228. }
  229. dpi_set_mode(dssdev);
  230. dispc_mgr_go(dssdev->manager->id);
  231. dispc_runtime_put();
  232. dss_runtime_put();
  233. }
  234. }
  235. EXPORT_SYMBOL(dpi_set_timings);
  236. int dpi_check_timings(struct omap_dss_device *dssdev,
  237. struct omap_video_timings *timings)
  238. {
  239. bool is_tft;
  240. int r;
  241. int lck_div, pck_div;
  242. unsigned long fck;
  243. unsigned long pck;
  244. struct dispc_clock_info dispc_cinfo;
  245. if (!dispc_lcd_timings_ok(timings))
  246. return -EINVAL;
  247. if (timings->pixel_clock == 0)
  248. return -EINVAL;
  249. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  250. if (dpi_use_dsi_pll(dssdev)) {
  251. struct dsi_clock_info dsi_cinfo;
  252. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
  253. timings->pixel_clock * 1000,
  254. &dsi_cinfo, &dispc_cinfo);
  255. if (r)
  256. return r;
  257. fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  258. } else {
  259. struct dss_clock_info dss_cinfo;
  260. r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
  261. &dss_cinfo, &dispc_cinfo);
  262. if (r)
  263. return r;
  264. fck = dss_cinfo.fck;
  265. }
  266. lck_div = dispc_cinfo.lck_div;
  267. pck_div = dispc_cinfo.pck_div;
  268. pck = fck / lck_div / pck_div / 1000;
  269. timings->pixel_clock = pck;
  270. return 0;
  271. }
  272. EXPORT_SYMBOL(dpi_check_timings);
  273. int dpi_init_display(struct omap_dss_device *dssdev)
  274. {
  275. DSSDBG("init_display\n");
  276. if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
  277. struct regulator *vdds_dsi;
  278. vdds_dsi = dss_get_vdds_dsi();
  279. if (IS_ERR(vdds_dsi)) {
  280. DSSERR("can't get VDDS_DSI regulator\n");
  281. return PTR_ERR(vdds_dsi);
  282. }
  283. dpi.vdds_dsi_reg = vdds_dsi;
  284. }
  285. if (dpi_use_dsi_pll(dssdev)) {
  286. enum omap_dss_clk_source dispc_fclk_src =
  287. dssdev->clocks.dispc.dispc_fclk_src;
  288. dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
  289. }
  290. return 0;
  291. }
  292. int dpi_init(void)
  293. {
  294. return 0;
  295. }
  296. void dpi_exit(void)
  297. {
  298. }