armada-370-xp.dtsi 2.9 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. * Ben Dooks <ben.dooks@codethink.co.uk>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * This file contains the definitions that are common to the Armada
  16. * 370 and Armada XP SoC.
  17. */
  18. /include/ "skeleton.dtsi"
  19. / {
  20. model = "Marvell Armada 370 and XP SoC";
  21. compatible = "marvell,armada-370-xp";
  22. cpus {
  23. cpu@0 {
  24. compatible = "marvell,sheeva-v7";
  25. };
  26. };
  27. mpic: interrupt-controller@d0020000 {
  28. compatible = "marvell,mpic";
  29. #interrupt-cells = <1>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. interrupt-controller;
  33. };
  34. coherency-fabric@d0020200 {
  35. compatible = "marvell,coherency-fabric";
  36. reg = <0xd0020200 0xb0>,
  37. <0xd0021810 0x1c>;
  38. };
  39. soc {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. compatible = "simple-bus";
  43. interrupt-parent = <&mpic>;
  44. ranges;
  45. serial@d0012000 {
  46. compatible = "ns16550";
  47. reg = <0xd0012000 0x100>;
  48. reg-shift = <2>;
  49. interrupts = <41>;
  50. status = "disabled";
  51. };
  52. serial@d0012100 {
  53. compatible = "ns16550";
  54. reg = <0xd0012100 0x100>;
  55. reg-shift = <2>;
  56. interrupts = <42>;
  57. status = "disabled";
  58. };
  59. timer@d0020300 {
  60. compatible = "marvell,armada-370-xp-timer";
  61. reg = <0xd0020300 0x30>;
  62. interrupts = <37>, <38>, <39>, <40>;
  63. clocks = <&coreclk 2>;
  64. };
  65. addr-decoding@d0020000 {
  66. compatible = "marvell,armada-addr-decoding-controller";
  67. reg = <0xd0020000 0x258>;
  68. };
  69. sata@d00a0000 {
  70. compatible = "marvell,orion-sata";
  71. reg = <0xd00a0000 0x2400>;
  72. interrupts = <55>;
  73. clocks = <&gateclk 15>, <&gateclk 30>;
  74. clock-names = "0", "1";
  75. status = "disabled";
  76. };
  77. mdio {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. compatible = "marvell,orion-mdio";
  81. reg = <0xd0072004 0x4>;
  82. };
  83. ethernet@d0070000 {
  84. compatible = "marvell,armada-370-neta";
  85. reg = <0xd0070000 0x2500>;
  86. interrupts = <8>;
  87. clocks = <&gateclk 4>;
  88. status = "disabled";
  89. };
  90. ethernet@d0074000 {
  91. compatible = "marvell,armada-370-neta";
  92. reg = <0xd0074000 0x2500>;
  93. interrupts = <10>;
  94. clocks = <&gateclk 3>;
  95. status = "disabled";
  96. };
  97. i2c0: i2c@d0011000 {
  98. compatible = "marvell,mv64xxx-i2c";
  99. reg = <0xd0011000 0x20>;
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. interrupts = <31>;
  103. timeout-ms = <1000>;
  104. clocks = <&coreclk 0>;
  105. status = "disabled";
  106. };
  107. i2c1: i2c@d0011100 {
  108. compatible = "marvell,mv64xxx-i2c";
  109. reg = <0xd0011100 0x20>;
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. interrupts = <32>;
  113. timeout-ms = <1000>;
  114. clocks = <&coreclk 0>;
  115. status = "disabled";
  116. };
  117. };
  118. };