iwl-agn.c 112 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #define DRV_VERSION IWLWIFI_VERSION VD
  67. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  68. MODULE_VERSION(DRV_VERSION);
  69. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  70. MODULE_LICENSE("GPL");
  71. MODULE_ALIAS("iwl4965");
  72. /*************** STATION TABLE MANAGEMENT ****
  73. * mac80211 should be examined to determine if sta_info is duplicating
  74. * the functionality provided here
  75. */
  76. /**************************************************************/
  77. /**
  78. * iwl_commit_rxon - commit staging_rxon to hardware
  79. *
  80. * The RXON command in staging_rxon is committed to the hardware and
  81. * the active_rxon structure is updated with the new data. This
  82. * function correctly transitions out of the RXON_ASSOC_MSK state if
  83. * a HW tune is required based on the RXON structure changes.
  84. */
  85. int iwl_commit_rxon(struct iwl_priv *priv)
  86. {
  87. /* cast away the const for active_rxon in this function */
  88. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  89. int ret;
  90. bool new_assoc =
  91. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  92. if (!iwl_is_alive(priv))
  93. return -EBUSY;
  94. /* always get timestamp with Rx frame */
  95. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  96. ret = iwl_check_rxon_cmd(priv);
  97. if (ret) {
  98. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  99. return -EINVAL;
  100. }
  101. /*
  102. * receive commit_rxon request
  103. * abort any previous channel switch if still in process
  104. */
  105. if (priv->switch_rxon.switch_in_progress &&
  106. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  107. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  108. le16_to_cpu(priv->switch_rxon.channel));
  109. priv->switch_rxon.switch_in_progress = false;
  110. }
  111. /* If we don't need to send a full RXON, we can use
  112. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  113. * and other flags for the current radio configuration. */
  114. if (!iwl_full_rxon_required(priv)) {
  115. ret = iwl_send_rxon_assoc(priv);
  116. if (ret) {
  117. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  118. return ret;
  119. }
  120. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  121. iwl_print_rx_config_cmd(priv);
  122. return 0;
  123. }
  124. /* station table will be cleared */
  125. priv->assoc_station_added = 0;
  126. /* If we are currently associated and the new config requires
  127. * an RXON_ASSOC and the new config wants the associated mask enabled,
  128. * we must clear the associated from the active configuration
  129. * before we apply the new config */
  130. if (iwl_is_associated(priv) && new_assoc) {
  131. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  132. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  133. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  134. sizeof(struct iwl_rxon_cmd),
  135. &priv->active_rxon);
  136. /* If the mask clearing failed then we set
  137. * active_rxon back to what it was previously */
  138. if (ret) {
  139. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  140. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  141. return ret;
  142. }
  143. }
  144. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  145. "* with%s RXON_FILTER_ASSOC_MSK\n"
  146. "* channel = %d\n"
  147. "* bssid = %pM\n",
  148. (new_assoc ? "" : "out"),
  149. le16_to_cpu(priv->staging_rxon.channel),
  150. priv->staging_rxon.bssid_addr);
  151. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  152. /* Apply the new configuration
  153. * RXON unassoc clears the station table in uCode, send it before
  154. * we add the bcast station. If assoc bit is set, we will send RXON
  155. * after having added the bcast and bssid station.
  156. */
  157. if (!new_assoc) {
  158. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  159. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  160. if (ret) {
  161. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  162. return ret;
  163. }
  164. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  165. }
  166. iwl_clear_stations_table(priv);
  167. priv->start_calib = 0;
  168. /* Add the broadcast address so we can send broadcast frames */
  169. priv->cfg->ops->lib->add_bcast_station(priv);
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /*
  188. * allow CTS-to-self if possible for new association.
  189. * this is relevant only for 5000 series and up,
  190. * but will not damage 4965
  191. */
  192. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  193. /* Apply the new configuration
  194. * RXON assoc doesn't clear the station table in uCode,
  195. */
  196. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  197. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  198. if (ret) {
  199. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  200. return ret;
  201. }
  202. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  203. }
  204. iwl_print_rx_config_cmd(priv);
  205. iwl_init_sensitivity(priv);
  206. /* If we issue a new RXON command which required a tune then we must
  207. * send a new TXPOWER command or we won't be able to Tx any frames */
  208. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  209. if (ret) {
  210. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  211. return ret;
  212. }
  213. return 0;
  214. }
  215. void iwl_update_chain_flags(struct iwl_priv *priv)
  216. {
  217. if (priv->cfg->ops->hcmd->set_rxon_chain)
  218. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  219. iwlcore_commit_rxon(priv);
  220. }
  221. static void iwl_clear_free_frames(struct iwl_priv *priv)
  222. {
  223. struct list_head *element;
  224. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  225. priv->frames_count);
  226. while (!list_empty(&priv->free_frames)) {
  227. element = priv->free_frames.next;
  228. list_del(element);
  229. kfree(list_entry(element, struct iwl_frame, list));
  230. priv->frames_count--;
  231. }
  232. if (priv->frames_count) {
  233. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  234. priv->frames_count);
  235. priv->frames_count = 0;
  236. }
  237. }
  238. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  239. {
  240. struct iwl_frame *frame;
  241. struct list_head *element;
  242. if (list_empty(&priv->free_frames)) {
  243. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  244. if (!frame) {
  245. IWL_ERR(priv, "Could not allocate frame!\n");
  246. return NULL;
  247. }
  248. priv->frames_count++;
  249. return frame;
  250. }
  251. element = priv->free_frames.next;
  252. list_del(element);
  253. return list_entry(element, struct iwl_frame, list);
  254. }
  255. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  256. {
  257. memset(frame, 0, sizeof(*frame));
  258. list_add(&frame->list, &priv->free_frames);
  259. }
  260. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  261. struct ieee80211_hdr *hdr,
  262. int left)
  263. {
  264. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  265. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  266. (priv->iw_mode != NL80211_IFTYPE_AP)))
  267. return 0;
  268. if (priv->ibss_beacon->len > left)
  269. return 0;
  270. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  271. return priv->ibss_beacon->len;
  272. }
  273. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  274. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  275. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  276. u8 *beacon, u32 frame_size)
  277. {
  278. u16 tim_idx;
  279. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  280. /*
  281. * The index is relative to frame start but we start looking at the
  282. * variable-length part of the beacon.
  283. */
  284. tim_idx = mgmt->u.beacon.variable - beacon;
  285. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  286. while ((tim_idx < (frame_size - 2)) &&
  287. (beacon[tim_idx] != WLAN_EID_TIM))
  288. tim_idx += beacon[tim_idx+1] + 2;
  289. /* If TIM field was found, set variables */
  290. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  291. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  292. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  293. } else
  294. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  295. }
  296. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  297. struct iwl_frame *frame)
  298. {
  299. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  300. u32 frame_size;
  301. u32 rate_flags;
  302. u32 rate;
  303. /*
  304. * We have to set up the TX command, the TX Beacon command, and the
  305. * beacon contents.
  306. */
  307. /* Initialize memory */
  308. tx_beacon_cmd = &frame->u.beacon;
  309. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  310. /* Set up TX beacon contents */
  311. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  312. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  313. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  314. return 0;
  315. /* Set up TX command fields */
  316. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  317. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  318. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  319. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  320. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  321. /* Set up TX beacon command fields */
  322. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  323. frame_size);
  324. /* Set up packet rate and flags */
  325. rate = iwl_rate_get_lowest_plcp(priv);
  326. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  327. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  328. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  329. rate_flags |= RATE_MCS_CCK_MSK;
  330. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  331. rate_flags);
  332. return sizeof(*tx_beacon_cmd) + frame_size;
  333. }
  334. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  335. {
  336. struct iwl_frame *frame;
  337. unsigned int frame_size;
  338. int rc;
  339. frame = iwl_get_free_frame(priv);
  340. if (!frame) {
  341. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  342. "command.\n");
  343. return -ENOMEM;
  344. }
  345. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  346. if (!frame_size) {
  347. IWL_ERR(priv, "Error configuring the beacon command\n");
  348. iwl_free_frame(priv, frame);
  349. return -EINVAL;
  350. }
  351. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  352. &frame->u.cmd[0]);
  353. iwl_free_frame(priv, frame);
  354. return rc;
  355. }
  356. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  357. {
  358. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  359. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  360. if (sizeof(dma_addr_t) > sizeof(u32))
  361. addr |=
  362. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  363. return addr;
  364. }
  365. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  366. {
  367. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  368. return le16_to_cpu(tb->hi_n_len) >> 4;
  369. }
  370. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  371. dma_addr_t addr, u16 len)
  372. {
  373. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  374. u16 hi_n_len = len << 4;
  375. put_unaligned_le32(addr, &tb->lo);
  376. if (sizeof(dma_addr_t) > sizeof(u32))
  377. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  378. tb->hi_n_len = cpu_to_le16(hi_n_len);
  379. tfd->num_tbs = idx + 1;
  380. }
  381. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  382. {
  383. return tfd->num_tbs & 0x1f;
  384. }
  385. /**
  386. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  387. * @priv - driver private data
  388. * @txq - tx queue
  389. *
  390. * Does NOT advance any TFD circular buffer read/write indexes
  391. * Does NOT free the TFD itself (which is within circular buffer)
  392. */
  393. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  394. {
  395. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  396. struct iwl_tfd *tfd;
  397. struct pci_dev *dev = priv->pci_dev;
  398. int index = txq->q.read_ptr;
  399. int i;
  400. int num_tbs;
  401. tfd = &tfd_tmp[index];
  402. /* Sanity check on number of chunks */
  403. num_tbs = iwl_tfd_get_num_tbs(tfd);
  404. if (num_tbs >= IWL_NUM_OF_TBS) {
  405. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  406. /* @todo issue fatal error, it is quite serious situation */
  407. return;
  408. }
  409. /* Unmap tx_cmd */
  410. if (num_tbs)
  411. pci_unmap_single(dev,
  412. pci_unmap_addr(&txq->meta[index], mapping),
  413. pci_unmap_len(&txq->meta[index], len),
  414. PCI_DMA_BIDIRECTIONAL);
  415. /* Unmap chunks, if any. */
  416. for (i = 1; i < num_tbs; i++) {
  417. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  418. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  419. if (txq->txb) {
  420. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  421. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  422. }
  423. }
  424. }
  425. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  426. struct iwl_tx_queue *txq,
  427. dma_addr_t addr, u16 len,
  428. u8 reset, u8 pad)
  429. {
  430. struct iwl_queue *q;
  431. struct iwl_tfd *tfd, *tfd_tmp;
  432. u32 num_tbs;
  433. q = &txq->q;
  434. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  435. tfd = &tfd_tmp[q->write_ptr];
  436. if (reset)
  437. memset(tfd, 0, sizeof(*tfd));
  438. num_tbs = iwl_tfd_get_num_tbs(tfd);
  439. /* Each TFD can point to a maximum 20 Tx buffers */
  440. if (num_tbs >= IWL_NUM_OF_TBS) {
  441. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  442. IWL_NUM_OF_TBS);
  443. return -EINVAL;
  444. }
  445. BUG_ON(addr & ~DMA_BIT_MASK(36));
  446. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  447. IWL_ERR(priv, "Unaligned address = %llx\n",
  448. (unsigned long long)addr);
  449. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  450. return 0;
  451. }
  452. /*
  453. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  454. * given Tx queue, and enable the DMA channel used for that queue.
  455. *
  456. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  457. * channels supported in hardware.
  458. */
  459. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  460. struct iwl_tx_queue *txq)
  461. {
  462. int txq_id = txq->q.id;
  463. /* Circular buffer (TFD queue in DRAM) physical base address */
  464. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  465. txq->q.dma_addr >> 8);
  466. return 0;
  467. }
  468. /******************************************************************************
  469. *
  470. * Generic RX handler implementations
  471. *
  472. ******************************************************************************/
  473. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  474. struct iwl_rx_mem_buffer *rxb)
  475. {
  476. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  477. struct iwl_alive_resp *palive;
  478. struct delayed_work *pwork;
  479. palive = &pkt->u.alive_frame;
  480. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  481. "0x%01X 0x%01X\n",
  482. palive->is_valid, palive->ver_type,
  483. palive->ver_subtype);
  484. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  485. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  486. memcpy(&priv->card_alive_init,
  487. &pkt->u.alive_frame,
  488. sizeof(struct iwl_init_alive_resp));
  489. pwork = &priv->init_alive_start;
  490. } else {
  491. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  492. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  493. sizeof(struct iwl_alive_resp));
  494. pwork = &priv->alive_start;
  495. }
  496. /* We delay the ALIVE response by 5ms to
  497. * give the HW RF Kill time to activate... */
  498. if (palive->is_valid == UCODE_VALID_OK)
  499. queue_delayed_work(priv->workqueue, pwork,
  500. msecs_to_jiffies(5));
  501. else
  502. IWL_WARN(priv, "uCode did not respond OK.\n");
  503. }
  504. static void iwl_bg_beacon_update(struct work_struct *work)
  505. {
  506. struct iwl_priv *priv =
  507. container_of(work, struct iwl_priv, beacon_update);
  508. struct sk_buff *beacon;
  509. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  510. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  511. if (!beacon) {
  512. IWL_ERR(priv, "update beacon failed\n");
  513. return;
  514. }
  515. mutex_lock(&priv->mutex);
  516. /* new beacon skb is allocated every time; dispose previous.*/
  517. if (priv->ibss_beacon)
  518. dev_kfree_skb(priv->ibss_beacon);
  519. priv->ibss_beacon = beacon;
  520. mutex_unlock(&priv->mutex);
  521. iwl_send_beacon_cmd(priv);
  522. }
  523. /**
  524. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  525. *
  526. * This callback is provided in order to send a statistics request.
  527. *
  528. * This timer function is continually reset to execute within
  529. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  530. * was received. We need to ensure we receive the statistics in order
  531. * to update the temperature used for calibrating the TXPOWER.
  532. */
  533. static void iwl_bg_statistics_periodic(unsigned long data)
  534. {
  535. struct iwl_priv *priv = (struct iwl_priv *)data;
  536. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  537. return;
  538. /* dont send host command if rf-kill is on */
  539. if (!iwl_is_ready_rf(priv))
  540. return;
  541. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  542. }
  543. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  544. u32 start_idx, u32 num_events,
  545. u32 mode)
  546. {
  547. u32 i;
  548. u32 ptr; /* SRAM byte address of log data */
  549. u32 ev, time, data; /* event log data */
  550. unsigned long reg_flags;
  551. if (mode == 0)
  552. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  553. else
  554. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  555. /* Make sure device is powered up for SRAM reads */
  556. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  557. if (iwl_grab_nic_access(priv)) {
  558. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  559. return;
  560. }
  561. /* Set starting address; reads will auto-increment */
  562. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  563. rmb();
  564. /*
  565. * "time" is actually "data" for mode 0 (no timestamp).
  566. * place event id # at far right for easier visual parsing.
  567. */
  568. for (i = 0; i < num_events; i++) {
  569. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  570. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  571. if (mode == 0) {
  572. trace_iwlwifi_dev_ucode_cont_event(priv,
  573. 0, time, ev);
  574. } else {
  575. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  576. trace_iwlwifi_dev_ucode_cont_event(priv,
  577. time, data, ev);
  578. }
  579. }
  580. /* Allow device to power down */
  581. iwl_release_nic_access(priv);
  582. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  583. }
  584. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  585. {
  586. u32 capacity; /* event log capacity in # entries */
  587. u32 base; /* SRAM byte address of event log header */
  588. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  589. u32 num_wraps; /* # times uCode wrapped to top of log */
  590. u32 next_entry; /* index of next entry to be written by uCode */
  591. if (priv->ucode_type == UCODE_INIT)
  592. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  593. else
  594. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  595. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  596. capacity = iwl_read_targ_mem(priv, base);
  597. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  598. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  599. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  600. } else
  601. return;
  602. if (num_wraps == priv->event_log.num_wraps) {
  603. iwl_print_cont_event_trace(priv,
  604. base, priv->event_log.next_entry,
  605. next_entry - priv->event_log.next_entry,
  606. mode);
  607. priv->event_log.non_wraps_count++;
  608. } else {
  609. if ((num_wraps - priv->event_log.num_wraps) > 1)
  610. priv->event_log.wraps_more_count++;
  611. else
  612. priv->event_log.wraps_once_count++;
  613. trace_iwlwifi_dev_ucode_wrap_event(priv,
  614. num_wraps - priv->event_log.num_wraps,
  615. next_entry, priv->event_log.next_entry);
  616. if (next_entry < priv->event_log.next_entry) {
  617. iwl_print_cont_event_trace(priv, base,
  618. priv->event_log.next_entry,
  619. capacity - priv->event_log.next_entry,
  620. mode);
  621. iwl_print_cont_event_trace(priv, base, 0,
  622. next_entry, mode);
  623. } else {
  624. iwl_print_cont_event_trace(priv, base,
  625. next_entry, capacity - next_entry,
  626. mode);
  627. iwl_print_cont_event_trace(priv, base, 0,
  628. next_entry, mode);
  629. }
  630. }
  631. priv->event_log.num_wraps = num_wraps;
  632. priv->event_log.next_entry = next_entry;
  633. }
  634. /**
  635. * iwl_bg_ucode_trace - Timer callback to log ucode event
  636. *
  637. * The timer is continually set to execute every
  638. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  639. * this function is to perform continuous uCode event logging operation
  640. * if enabled
  641. */
  642. static void iwl_bg_ucode_trace(unsigned long data)
  643. {
  644. struct iwl_priv *priv = (struct iwl_priv *)data;
  645. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  646. return;
  647. if (priv->event_log.ucode_trace) {
  648. iwl_continuous_event_trace(priv);
  649. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  650. mod_timer(&priv->ucode_trace,
  651. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  652. }
  653. }
  654. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  655. struct iwl_rx_mem_buffer *rxb)
  656. {
  657. #ifdef CONFIG_IWLWIFI_DEBUG
  658. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  659. struct iwl4965_beacon_notif *beacon =
  660. (struct iwl4965_beacon_notif *)pkt->u.raw;
  661. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  662. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  663. "tsf %d %d rate %d\n",
  664. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  665. beacon->beacon_notify_hdr.failure_frame,
  666. le32_to_cpu(beacon->ibss_mgr_status),
  667. le32_to_cpu(beacon->high_tsf),
  668. le32_to_cpu(beacon->low_tsf), rate);
  669. #endif
  670. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  671. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  672. queue_work(priv->workqueue, &priv->beacon_update);
  673. }
  674. /* Handle notification from uCode that card's power state is changing
  675. * due to software, hardware, or critical temperature RFKILL */
  676. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  677. struct iwl_rx_mem_buffer *rxb)
  678. {
  679. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  680. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  681. unsigned long status = priv->status;
  682. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  683. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  684. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  685. (flags & CT_CARD_DISABLED) ?
  686. "Reached" : "Not reached");
  687. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  688. CT_CARD_DISABLED)) {
  689. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  690. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  691. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  692. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  693. if (!(flags & RXON_CARD_DISABLED)) {
  694. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  695. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  696. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  697. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  698. }
  699. if (flags & CT_CARD_DISABLED)
  700. iwl_tt_enter_ct_kill(priv);
  701. }
  702. if (!(flags & CT_CARD_DISABLED))
  703. iwl_tt_exit_ct_kill(priv);
  704. if (flags & HW_CARD_DISABLED)
  705. set_bit(STATUS_RF_KILL_HW, &priv->status);
  706. else
  707. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  708. if (!(flags & RXON_CARD_DISABLED))
  709. iwl_scan_cancel(priv);
  710. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  711. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  712. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  713. test_bit(STATUS_RF_KILL_HW, &priv->status));
  714. else
  715. wake_up_interruptible(&priv->wait_command_queue);
  716. }
  717. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  718. {
  719. if (src == IWL_PWR_SRC_VAUX) {
  720. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  721. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  722. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  723. ~APMG_PS_CTRL_MSK_PWR_SRC);
  724. } else {
  725. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  726. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  727. ~APMG_PS_CTRL_MSK_PWR_SRC);
  728. }
  729. return 0;
  730. }
  731. /**
  732. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  733. *
  734. * Setup the RX handlers for each of the reply types sent from the uCode
  735. * to the host.
  736. *
  737. * This function chains into the hardware specific files for them to setup
  738. * any hardware specific handlers as well.
  739. */
  740. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  741. {
  742. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  743. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  744. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  745. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  746. iwl_rx_spectrum_measure_notif;
  747. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  748. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  749. iwl_rx_pm_debug_statistics_notif;
  750. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  751. /*
  752. * The same handler is used for both the REPLY to a discrete
  753. * statistics request from the host as well as for the periodic
  754. * statistics notifications (after received beacons) from the uCode.
  755. */
  756. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  757. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  758. iwl_setup_rx_scan_handlers(priv);
  759. /* status change handler */
  760. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  761. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  762. iwl_rx_missed_beacon_notif;
  763. /* Rx handlers */
  764. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  765. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  766. /* block ack */
  767. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  768. /* Set up hardware specific Rx handlers */
  769. priv->cfg->ops->lib->rx_handler_setup(priv);
  770. }
  771. /**
  772. * iwl_rx_handle - Main entry function for receiving responses from uCode
  773. *
  774. * Uses the priv->rx_handlers callback function array to invoke
  775. * the appropriate handlers, including command responses,
  776. * frame-received notifications, and other notifications.
  777. */
  778. void iwl_rx_handle(struct iwl_priv *priv)
  779. {
  780. struct iwl_rx_mem_buffer *rxb;
  781. struct iwl_rx_packet *pkt;
  782. struct iwl_rx_queue *rxq = &priv->rxq;
  783. u32 r, i;
  784. int reclaim;
  785. unsigned long flags;
  786. u8 fill_rx = 0;
  787. u32 count = 8;
  788. int total_empty;
  789. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  790. * buffer that the driver may process (last buffer filled by ucode). */
  791. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  792. i = rxq->read;
  793. /* Rx interrupt, but nothing sent from uCode */
  794. if (i == r)
  795. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  796. /* calculate total frames need to be restock after handling RX */
  797. total_empty = r - rxq->write_actual;
  798. if (total_empty < 0)
  799. total_empty += RX_QUEUE_SIZE;
  800. if (total_empty > (RX_QUEUE_SIZE / 2))
  801. fill_rx = 1;
  802. while (i != r) {
  803. rxb = rxq->queue[i];
  804. /* If an RXB doesn't have a Rx queue slot associated with it,
  805. * then a bug has been introduced in the queue refilling
  806. * routines -- catch it here */
  807. BUG_ON(rxb == NULL);
  808. rxq->queue[i] = NULL;
  809. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  810. PAGE_SIZE << priv->hw_params.rx_page_order,
  811. PCI_DMA_FROMDEVICE);
  812. pkt = rxb_addr(rxb);
  813. trace_iwlwifi_dev_rx(priv, pkt,
  814. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  815. /* Reclaim a command buffer only if this packet is a response
  816. * to a (driver-originated) command.
  817. * If the packet (e.g. Rx frame) originated from uCode,
  818. * there is no command buffer to reclaim.
  819. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  820. * but apparently a few don't get set; catch them here. */
  821. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  822. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  823. (pkt->hdr.cmd != REPLY_RX) &&
  824. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  825. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  826. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  827. (pkt->hdr.cmd != REPLY_TX);
  828. /* Based on type of command response or notification,
  829. * handle those that need handling via function in
  830. * rx_handlers table. See iwl_setup_rx_handlers() */
  831. if (priv->rx_handlers[pkt->hdr.cmd]) {
  832. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  833. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  834. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  835. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  836. } else {
  837. /* No handling needed */
  838. IWL_DEBUG_RX(priv,
  839. "r %d i %d No handler needed for %s, 0x%02x\n",
  840. r, i, get_cmd_string(pkt->hdr.cmd),
  841. pkt->hdr.cmd);
  842. }
  843. /*
  844. * XXX: After here, we should always check rxb->page
  845. * against NULL before touching it or its virtual
  846. * memory (pkt). Because some rx_handler might have
  847. * already taken or freed the pages.
  848. */
  849. if (reclaim) {
  850. /* Invoke any callbacks, transfer the buffer to caller,
  851. * and fire off the (possibly) blocking iwl_send_cmd()
  852. * as we reclaim the driver command queue */
  853. if (rxb->page)
  854. iwl_tx_cmd_complete(priv, rxb);
  855. else
  856. IWL_WARN(priv, "Claim null rxb?\n");
  857. }
  858. /* Reuse the page if possible. For notification packets and
  859. * SKBs that fail to Rx correctly, add them back into the
  860. * rx_free list for reuse later. */
  861. spin_lock_irqsave(&rxq->lock, flags);
  862. if (rxb->page != NULL) {
  863. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  864. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  865. PCI_DMA_FROMDEVICE);
  866. list_add_tail(&rxb->list, &rxq->rx_free);
  867. rxq->free_count++;
  868. } else
  869. list_add_tail(&rxb->list, &rxq->rx_used);
  870. spin_unlock_irqrestore(&rxq->lock, flags);
  871. i = (i + 1) & RX_QUEUE_MASK;
  872. /* If there are a lot of unused frames,
  873. * restock the Rx queue so ucode wont assert. */
  874. if (fill_rx) {
  875. count++;
  876. if (count >= 8) {
  877. rxq->read = i;
  878. iwl_rx_replenish_now(priv);
  879. count = 0;
  880. }
  881. }
  882. }
  883. /* Backtrack one entry */
  884. rxq->read = i;
  885. if (fill_rx)
  886. iwl_rx_replenish_now(priv);
  887. else
  888. iwl_rx_queue_restock(priv);
  889. }
  890. /* call this function to flush any scheduled tasklet */
  891. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  892. {
  893. /* wait to make sure we flush pending tasklet*/
  894. synchronize_irq(priv->pci_dev->irq);
  895. tasklet_kill(&priv->irq_tasklet);
  896. }
  897. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  898. {
  899. u32 inta, handled = 0;
  900. u32 inta_fh;
  901. unsigned long flags;
  902. u32 i;
  903. #ifdef CONFIG_IWLWIFI_DEBUG
  904. u32 inta_mask;
  905. #endif
  906. spin_lock_irqsave(&priv->lock, flags);
  907. /* Ack/clear/reset pending uCode interrupts.
  908. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  909. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  910. inta = iwl_read32(priv, CSR_INT);
  911. iwl_write32(priv, CSR_INT, inta);
  912. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  913. * Any new interrupts that happen after this, either while we're
  914. * in this tasklet, or later, will show up in next ISR/tasklet. */
  915. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  916. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  917. #ifdef CONFIG_IWLWIFI_DEBUG
  918. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  919. /* just for debug */
  920. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  921. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  922. inta, inta_mask, inta_fh);
  923. }
  924. #endif
  925. spin_unlock_irqrestore(&priv->lock, flags);
  926. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  927. * atomic, make sure that inta covers all the interrupts that
  928. * we've discovered, even if FH interrupt came in just after
  929. * reading CSR_INT. */
  930. if (inta_fh & CSR49_FH_INT_RX_MASK)
  931. inta |= CSR_INT_BIT_FH_RX;
  932. if (inta_fh & CSR49_FH_INT_TX_MASK)
  933. inta |= CSR_INT_BIT_FH_TX;
  934. /* Now service all interrupt bits discovered above. */
  935. if (inta & CSR_INT_BIT_HW_ERR) {
  936. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  937. /* Tell the device to stop sending interrupts */
  938. iwl_disable_interrupts(priv);
  939. priv->isr_stats.hw++;
  940. iwl_irq_handle_error(priv);
  941. handled |= CSR_INT_BIT_HW_ERR;
  942. return;
  943. }
  944. #ifdef CONFIG_IWLWIFI_DEBUG
  945. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  946. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  947. if (inta & CSR_INT_BIT_SCD) {
  948. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  949. "the frame/frames.\n");
  950. priv->isr_stats.sch++;
  951. }
  952. /* Alive notification via Rx interrupt will do the real work */
  953. if (inta & CSR_INT_BIT_ALIVE) {
  954. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  955. priv->isr_stats.alive++;
  956. }
  957. }
  958. #endif
  959. /* Safely ignore these bits for debug checks below */
  960. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  961. /* HW RF KILL switch toggled */
  962. if (inta & CSR_INT_BIT_RF_KILL) {
  963. int hw_rf_kill = 0;
  964. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  965. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  966. hw_rf_kill = 1;
  967. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  968. hw_rf_kill ? "disable radio" : "enable radio");
  969. priv->isr_stats.rfkill++;
  970. /* driver only loads ucode once setting the interface up.
  971. * the driver allows loading the ucode even if the radio
  972. * is killed. Hence update the killswitch state here. The
  973. * rfkill handler will care about restarting if needed.
  974. */
  975. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  976. if (hw_rf_kill)
  977. set_bit(STATUS_RF_KILL_HW, &priv->status);
  978. else
  979. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  980. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  981. }
  982. handled |= CSR_INT_BIT_RF_KILL;
  983. }
  984. /* Chip got too hot and stopped itself */
  985. if (inta & CSR_INT_BIT_CT_KILL) {
  986. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  987. priv->isr_stats.ctkill++;
  988. handled |= CSR_INT_BIT_CT_KILL;
  989. }
  990. /* Error detected by uCode */
  991. if (inta & CSR_INT_BIT_SW_ERR) {
  992. IWL_ERR(priv, "Microcode SW error detected. "
  993. " Restarting 0x%X.\n", inta);
  994. priv->isr_stats.sw++;
  995. priv->isr_stats.sw_err = inta;
  996. iwl_irq_handle_error(priv);
  997. handled |= CSR_INT_BIT_SW_ERR;
  998. }
  999. /*
  1000. * uCode wakes up after power-down sleep.
  1001. * Tell device about any new tx or host commands enqueued,
  1002. * and about any Rx buffers made available while asleep.
  1003. */
  1004. if (inta & CSR_INT_BIT_WAKEUP) {
  1005. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1006. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1007. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1008. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1009. priv->isr_stats.wakeup++;
  1010. handled |= CSR_INT_BIT_WAKEUP;
  1011. }
  1012. /* All uCode command responses, including Tx command responses,
  1013. * Rx "responses" (frame-received notification), and other
  1014. * notifications from uCode come through here*/
  1015. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1016. iwl_rx_handle(priv);
  1017. priv->isr_stats.rx++;
  1018. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1019. }
  1020. /* This "Tx" DMA channel is used only for loading uCode */
  1021. if (inta & CSR_INT_BIT_FH_TX) {
  1022. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1023. priv->isr_stats.tx++;
  1024. handled |= CSR_INT_BIT_FH_TX;
  1025. /* Wake up uCode load routine, now that load is complete */
  1026. priv->ucode_write_complete = 1;
  1027. wake_up_interruptible(&priv->wait_command_queue);
  1028. }
  1029. if (inta & ~handled) {
  1030. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1031. priv->isr_stats.unhandled++;
  1032. }
  1033. if (inta & ~(priv->inta_mask)) {
  1034. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1035. inta & ~priv->inta_mask);
  1036. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1037. }
  1038. /* Re-enable all interrupts */
  1039. /* only Re-enable if diabled by irq */
  1040. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1041. iwl_enable_interrupts(priv);
  1042. #ifdef CONFIG_IWLWIFI_DEBUG
  1043. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1044. inta = iwl_read32(priv, CSR_INT);
  1045. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1046. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1047. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1048. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1049. }
  1050. #endif
  1051. }
  1052. /* tasklet for iwlagn interrupt */
  1053. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1054. {
  1055. u32 inta = 0;
  1056. u32 handled = 0;
  1057. unsigned long flags;
  1058. u32 i;
  1059. #ifdef CONFIG_IWLWIFI_DEBUG
  1060. u32 inta_mask;
  1061. #endif
  1062. spin_lock_irqsave(&priv->lock, flags);
  1063. /* Ack/clear/reset pending uCode interrupts.
  1064. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1065. */
  1066. /* There is a hardware bug in the interrupt mask function that some
  1067. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1068. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1069. * ICT interrupt handling mechanism has another bug that might cause
  1070. * these unmasked interrupts fail to be detected. We workaround the
  1071. * hardware bugs here by ACKing all the possible interrupts so that
  1072. * interrupt coalescing can still be achieved.
  1073. */
  1074. iwl_write32(priv, CSR_INT, priv->inta | ~priv->inta_mask);
  1075. inta = priv->inta;
  1076. #ifdef CONFIG_IWLWIFI_DEBUG
  1077. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1078. /* just for debug */
  1079. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1080. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1081. inta, inta_mask);
  1082. }
  1083. #endif
  1084. spin_unlock_irqrestore(&priv->lock, flags);
  1085. /* saved interrupt in inta variable now we can reset priv->inta */
  1086. priv->inta = 0;
  1087. /* Now service all interrupt bits discovered above. */
  1088. if (inta & CSR_INT_BIT_HW_ERR) {
  1089. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1090. /* Tell the device to stop sending interrupts */
  1091. iwl_disable_interrupts(priv);
  1092. priv->isr_stats.hw++;
  1093. iwl_irq_handle_error(priv);
  1094. handled |= CSR_INT_BIT_HW_ERR;
  1095. return;
  1096. }
  1097. #ifdef CONFIG_IWLWIFI_DEBUG
  1098. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1099. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1100. if (inta & CSR_INT_BIT_SCD) {
  1101. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1102. "the frame/frames.\n");
  1103. priv->isr_stats.sch++;
  1104. }
  1105. /* Alive notification via Rx interrupt will do the real work */
  1106. if (inta & CSR_INT_BIT_ALIVE) {
  1107. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1108. priv->isr_stats.alive++;
  1109. }
  1110. }
  1111. #endif
  1112. /* Safely ignore these bits for debug checks below */
  1113. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1114. /* HW RF KILL switch toggled */
  1115. if (inta & CSR_INT_BIT_RF_KILL) {
  1116. int hw_rf_kill = 0;
  1117. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1118. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1119. hw_rf_kill = 1;
  1120. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1121. hw_rf_kill ? "disable radio" : "enable radio");
  1122. priv->isr_stats.rfkill++;
  1123. /* driver only loads ucode once setting the interface up.
  1124. * the driver allows loading the ucode even if the radio
  1125. * is killed. Hence update the killswitch state here. The
  1126. * rfkill handler will care about restarting if needed.
  1127. */
  1128. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1129. if (hw_rf_kill)
  1130. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1131. else
  1132. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1133. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1134. }
  1135. handled |= CSR_INT_BIT_RF_KILL;
  1136. }
  1137. /* Chip got too hot and stopped itself */
  1138. if (inta & CSR_INT_BIT_CT_KILL) {
  1139. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1140. priv->isr_stats.ctkill++;
  1141. handled |= CSR_INT_BIT_CT_KILL;
  1142. }
  1143. /* Error detected by uCode */
  1144. if (inta & CSR_INT_BIT_SW_ERR) {
  1145. IWL_ERR(priv, "Microcode SW error detected. "
  1146. " Restarting 0x%X.\n", inta);
  1147. priv->isr_stats.sw++;
  1148. priv->isr_stats.sw_err = inta;
  1149. iwl_irq_handle_error(priv);
  1150. handled |= CSR_INT_BIT_SW_ERR;
  1151. }
  1152. /* uCode wakes up after power-down sleep */
  1153. if (inta & CSR_INT_BIT_WAKEUP) {
  1154. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1155. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1156. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1157. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1158. priv->isr_stats.wakeup++;
  1159. handled |= CSR_INT_BIT_WAKEUP;
  1160. }
  1161. /* All uCode command responses, including Tx command responses,
  1162. * Rx "responses" (frame-received notification), and other
  1163. * notifications from uCode come through here*/
  1164. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1165. CSR_INT_BIT_RX_PERIODIC)) {
  1166. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1167. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1168. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1169. iwl_write32(priv, CSR_FH_INT_STATUS,
  1170. CSR49_FH_INT_RX_MASK);
  1171. }
  1172. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1173. handled |= CSR_INT_BIT_RX_PERIODIC;
  1174. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1175. }
  1176. /* Sending RX interrupt require many steps to be done in the
  1177. * the device:
  1178. * 1- write interrupt to current index in ICT table.
  1179. * 2- dma RX frame.
  1180. * 3- update RX shared data to indicate last write index.
  1181. * 4- send interrupt.
  1182. * This could lead to RX race, driver could receive RX interrupt
  1183. * but the shared data changes does not reflect this;
  1184. * periodic interrupt will detect any dangling Rx activity.
  1185. */
  1186. /* Disable periodic interrupt; we use it as just a one-shot. */
  1187. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1188. CSR_INT_PERIODIC_DIS);
  1189. iwl_rx_handle(priv);
  1190. /*
  1191. * Enable periodic interrupt in 8 msec only if we received
  1192. * real RX interrupt (instead of just periodic int), to catch
  1193. * any dangling Rx interrupt. If it was just the periodic
  1194. * interrupt, there was no dangling Rx activity, and no need
  1195. * to extend the periodic interrupt; one-shot is enough.
  1196. */
  1197. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1198. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1199. CSR_INT_PERIODIC_ENA);
  1200. priv->isr_stats.rx++;
  1201. }
  1202. /* This "Tx" DMA channel is used only for loading uCode */
  1203. if (inta & CSR_INT_BIT_FH_TX) {
  1204. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1205. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1206. priv->isr_stats.tx++;
  1207. handled |= CSR_INT_BIT_FH_TX;
  1208. /* Wake up uCode load routine, now that load is complete */
  1209. priv->ucode_write_complete = 1;
  1210. wake_up_interruptible(&priv->wait_command_queue);
  1211. }
  1212. if (inta & ~handled) {
  1213. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1214. priv->isr_stats.unhandled++;
  1215. }
  1216. if (inta & ~(priv->inta_mask)) {
  1217. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1218. inta & ~priv->inta_mask);
  1219. }
  1220. /* Re-enable all interrupts */
  1221. /* only Re-enable if diabled by irq */
  1222. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1223. iwl_enable_interrupts(priv);
  1224. }
  1225. /******************************************************************************
  1226. *
  1227. * uCode download functions
  1228. *
  1229. ******************************************************************************/
  1230. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1231. {
  1232. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1233. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1234. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1235. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1236. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1237. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1238. }
  1239. static void iwl_nic_start(struct iwl_priv *priv)
  1240. {
  1241. /* Remove all resets to allow NIC to operate */
  1242. iwl_write32(priv, CSR_RESET, 0);
  1243. }
  1244. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1245. static int iwl_mac_setup_register(struct iwl_priv *priv);
  1246. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1247. {
  1248. const char *name_pre = priv->cfg->fw_name_pre;
  1249. if (first)
  1250. priv->fw_index = priv->cfg->ucode_api_max;
  1251. else
  1252. priv->fw_index--;
  1253. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1254. IWL_ERR(priv, "no suitable firmware found!\n");
  1255. return -ENOENT;
  1256. }
  1257. sprintf(priv->firmware_name, "%s%d%s",
  1258. name_pre, priv->fw_index, ".ucode");
  1259. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1260. priv->firmware_name);
  1261. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1262. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1263. iwl_ucode_callback);
  1264. }
  1265. /**
  1266. * iwl_ucode_callback - callback when firmware was loaded
  1267. *
  1268. * If loaded successfully, copies the firmware into buffers
  1269. * for the card to fetch (via DMA).
  1270. */
  1271. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1272. {
  1273. struct iwl_priv *priv = context;
  1274. struct iwl_ucode_header *ucode;
  1275. const unsigned int api_max = priv->cfg->ucode_api_max;
  1276. const unsigned int api_min = priv->cfg->ucode_api_min;
  1277. u8 *src;
  1278. size_t len;
  1279. u32 api_ver, build;
  1280. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1281. int err;
  1282. u16 eeprom_ver;
  1283. if (!ucode_raw) {
  1284. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1285. priv->firmware_name);
  1286. goto try_again;
  1287. }
  1288. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1289. priv->firmware_name, ucode_raw->size);
  1290. /* Make sure that we got at least the v1 header! */
  1291. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1292. IWL_ERR(priv, "File size way too small!\n");
  1293. goto try_again;
  1294. }
  1295. /* Data from ucode file: header followed by uCode images */
  1296. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1297. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1298. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1299. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1300. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1301. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1302. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1303. init_data_size =
  1304. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1305. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1306. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1307. /* api_ver should match the api version forming part of the
  1308. * firmware filename ... but we don't check for that and only rely
  1309. * on the API version read from firmware header from here on forward */
  1310. if (api_ver < api_min || api_ver > api_max) {
  1311. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1312. "Driver supports v%u, firmware is v%u.\n",
  1313. api_max, api_ver);
  1314. goto try_again;
  1315. }
  1316. if (api_ver != api_max)
  1317. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1318. "got v%u. New firmware can be obtained "
  1319. "from http://www.intellinuxwireless.org.\n",
  1320. api_max, api_ver);
  1321. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1322. IWL_UCODE_MAJOR(priv->ucode_ver),
  1323. IWL_UCODE_MINOR(priv->ucode_ver),
  1324. IWL_UCODE_API(priv->ucode_ver),
  1325. IWL_UCODE_SERIAL(priv->ucode_ver));
  1326. snprintf(priv->hw->wiphy->fw_version,
  1327. sizeof(priv->hw->wiphy->fw_version),
  1328. "%u.%u.%u.%u",
  1329. IWL_UCODE_MAJOR(priv->ucode_ver),
  1330. IWL_UCODE_MINOR(priv->ucode_ver),
  1331. IWL_UCODE_API(priv->ucode_ver),
  1332. IWL_UCODE_SERIAL(priv->ucode_ver));
  1333. if (build)
  1334. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1335. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1336. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1337. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1338. ? "OTP" : "EEPROM", eeprom_ver);
  1339. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1340. priv->ucode_ver);
  1341. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1342. inst_size);
  1343. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1344. data_size);
  1345. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1346. init_size);
  1347. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1348. init_data_size);
  1349. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1350. boot_size);
  1351. /*
  1352. * For any of the failures below (before allocating pci memory)
  1353. * we will try to load a version with a smaller API -- maybe the
  1354. * user just got a corrupted version of the latest API.
  1355. */
  1356. /* Verify size of file vs. image size info in file's header */
  1357. if (ucode_raw->size !=
  1358. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1359. inst_size + data_size + init_size +
  1360. init_data_size + boot_size) {
  1361. IWL_DEBUG_INFO(priv,
  1362. "uCode file size %d does not match expected size\n",
  1363. (int)ucode_raw->size);
  1364. goto try_again;
  1365. }
  1366. /* Verify that uCode images will fit in card's SRAM */
  1367. if (inst_size > priv->hw_params.max_inst_size) {
  1368. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1369. inst_size);
  1370. goto try_again;
  1371. }
  1372. if (data_size > priv->hw_params.max_data_size) {
  1373. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1374. data_size);
  1375. goto try_again;
  1376. }
  1377. if (init_size > priv->hw_params.max_inst_size) {
  1378. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1379. init_size);
  1380. goto try_again;
  1381. }
  1382. if (init_data_size > priv->hw_params.max_data_size) {
  1383. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1384. init_data_size);
  1385. goto try_again;
  1386. }
  1387. if (boot_size > priv->hw_params.max_bsm_size) {
  1388. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1389. boot_size);
  1390. goto try_again;
  1391. }
  1392. /* Allocate ucode buffers for card's bus-master loading ... */
  1393. /* Runtime instructions and 2 copies of data:
  1394. * 1) unmodified from disk
  1395. * 2) backup cache for save/restore during power-downs */
  1396. priv->ucode_code.len = inst_size;
  1397. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1398. priv->ucode_data.len = data_size;
  1399. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1400. priv->ucode_data_backup.len = data_size;
  1401. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1402. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1403. !priv->ucode_data_backup.v_addr)
  1404. goto err_pci_alloc;
  1405. /* Initialization instructions and data */
  1406. if (init_size && init_data_size) {
  1407. priv->ucode_init.len = init_size;
  1408. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1409. priv->ucode_init_data.len = init_data_size;
  1410. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1411. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1412. goto err_pci_alloc;
  1413. }
  1414. /* Bootstrap (instructions only, no data) */
  1415. if (boot_size) {
  1416. priv->ucode_boot.len = boot_size;
  1417. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1418. if (!priv->ucode_boot.v_addr)
  1419. goto err_pci_alloc;
  1420. }
  1421. /* Copy images into buffers for card's bus-master reads ... */
  1422. /* Runtime instructions (first block of data in file) */
  1423. len = inst_size;
  1424. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1425. memcpy(priv->ucode_code.v_addr, src, len);
  1426. src += len;
  1427. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1428. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1429. /* Runtime data (2nd block)
  1430. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1431. len = data_size;
  1432. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1433. memcpy(priv->ucode_data.v_addr, src, len);
  1434. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1435. src += len;
  1436. /* Initialization instructions (3rd block) */
  1437. if (init_size) {
  1438. len = init_size;
  1439. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1440. len);
  1441. memcpy(priv->ucode_init.v_addr, src, len);
  1442. src += len;
  1443. }
  1444. /* Initialization data (4th block) */
  1445. if (init_data_size) {
  1446. len = init_data_size;
  1447. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1448. len);
  1449. memcpy(priv->ucode_init_data.v_addr, src, len);
  1450. src += len;
  1451. }
  1452. /* Bootstrap instructions (5th block) */
  1453. len = boot_size;
  1454. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1455. memcpy(priv->ucode_boot.v_addr, src, len);
  1456. /**************************************************
  1457. * This is still part of probe() in a sense...
  1458. *
  1459. * 9. Setup and register with mac80211 and debugfs
  1460. **************************************************/
  1461. err = iwl_mac_setup_register(priv);
  1462. if (err)
  1463. goto out_unbind;
  1464. err = iwl_dbgfs_register(priv, DRV_NAME);
  1465. if (err)
  1466. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1467. /* We have our copies now, allow OS release its copies */
  1468. release_firmware(ucode_raw);
  1469. complete(&priv->firmware_loading_complete);
  1470. return;
  1471. try_again:
  1472. /* try next, if any */
  1473. if (iwl_request_firmware(priv, false))
  1474. goto out_unbind;
  1475. release_firmware(ucode_raw);
  1476. return;
  1477. err_pci_alloc:
  1478. IWL_ERR(priv, "failed to allocate pci memory\n");
  1479. iwl_dealloc_ucode_pci(priv);
  1480. out_unbind:
  1481. complete(&priv->firmware_loading_complete);
  1482. device_release_driver(&priv->pci_dev->dev);
  1483. release_firmware(ucode_raw);
  1484. }
  1485. static const char *desc_lookup_text[] = {
  1486. "OK",
  1487. "FAIL",
  1488. "BAD_PARAM",
  1489. "BAD_CHECKSUM",
  1490. "NMI_INTERRUPT_WDG",
  1491. "SYSASSERT",
  1492. "FATAL_ERROR",
  1493. "BAD_COMMAND",
  1494. "HW_ERROR_TUNE_LOCK",
  1495. "HW_ERROR_TEMPERATURE",
  1496. "ILLEGAL_CHAN_FREQ",
  1497. "VCC_NOT_STABLE",
  1498. "FH_ERROR",
  1499. "NMI_INTERRUPT_HOST",
  1500. "NMI_INTERRUPT_ACTION_PT",
  1501. "NMI_INTERRUPT_UNKNOWN",
  1502. "UCODE_VERSION_MISMATCH",
  1503. "HW_ERROR_ABS_LOCK",
  1504. "HW_ERROR_CAL_LOCK_FAIL",
  1505. "NMI_INTERRUPT_INST_ACTION_PT",
  1506. "NMI_INTERRUPT_DATA_ACTION_PT",
  1507. "NMI_TRM_HW_ER",
  1508. "NMI_INTERRUPT_TRM",
  1509. "NMI_INTERRUPT_BREAK_POINT"
  1510. "DEBUG_0",
  1511. "DEBUG_1",
  1512. "DEBUG_2",
  1513. "DEBUG_3",
  1514. "ADVANCED SYSASSERT"
  1515. };
  1516. static const char *desc_lookup(int i)
  1517. {
  1518. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1519. if (i < 0 || i > max)
  1520. i = max;
  1521. return desc_lookup_text[i];
  1522. }
  1523. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1524. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1525. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1526. {
  1527. u32 data2, line;
  1528. u32 desc, time, count, base, data1;
  1529. u32 blink1, blink2, ilink1, ilink2;
  1530. if (priv->ucode_type == UCODE_INIT)
  1531. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1532. else
  1533. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1534. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1535. IWL_ERR(priv,
  1536. "Not valid error log pointer 0x%08X for %s uCode\n",
  1537. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1538. return;
  1539. }
  1540. count = iwl_read_targ_mem(priv, base);
  1541. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1542. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1543. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1544. priv->status, count);
  1545. }
  1546. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1547. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1548. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1549. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1550. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1551. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1552. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1553. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1554. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1555. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1556. blink1, blink2, ilink1, ilink2);
  1557. IWL_ERR(priv, "Desc Time "
  1558. "data1 data2 line\n");
  1559. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1560. desc_lookup(desc), desc, time, data1, data2, line);
  1561. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1562. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1563. ilink1, ilink2);
  1564. }
  1565. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1566. /**
  1567. * iwl_print_event_log - Dump error event log to syslog
  1568. *
  1569. */
  1570. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1571. u32 num_events, u32 mode,
  1572. int pos, char **buf, size_t bufsz)
  1573. {
  1574. u32 i;
  1575. u32 base; /* SRAM byte address of event log header */
  1576. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1577. u32 ptr; /* SRAM byte address of log data */
  1578. u32 ev, time, data; /* event log data */
  1579. unsigned long reg_flags;
  1580. if (num_events == 0)
  1581. return pos;
  1582. if (priv->ucode_type == UCODE_INIT)
  1583. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1584. else
  1585. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1586. if (mode == 0)
  1587. event_size = 2 * sizeof(u32);
  1588. else
  1589. event_size = 3 * sizeof(u32);
  1590. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1591. /* Make sure device is powered up for SRAM reads */
  1592. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1593. iwl_grab_nic_access(priv);
  1594. /* Set starting address; reads will auto-increment */
  1595. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1596. rmb();
  1597. /* "time" is actually "data" for mode 0 (no timestamp).
  1598. * place event id # at far right for easier visual parsing. */
  1599. for (i = 0; i < num_events; i++) {
  1600. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1601. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1602. if (mode == 0) {
  1603. /* data, ev */
  1604. if (bufsz) {
  1605. pos += scnprintf(*buf + pos, bufsz - pos,
  1606. "EVT_LOG:0x%08x:%04u\n",
  1607. time, ev);
  1608. } else {
  1609. trace_iwlwifi_dev_ucode_event(priv, 0,
  1610. time, ev);
  1611. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1612. time, ev);
  1613. }
  1614. } else {
  1615. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1616. if (bufsz) {
  1617. pos += scnprintf(*buf + pos, bufsz - pos,
  1618. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1619. time, data, ev);
  1620. } else {
  1621. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1622. time, data, ev);
  1623. trace_iwlwifi_dev_ucode_event(priv, time,
  1624. data, ev);
  1625. }
  1626. }
  1627. }
  1628. /* Allow device to power down */
  1629. iwl_release_nic_access(priv);
  1630. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1631. return pos;
  1632. }
  1633. /**
  1634. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1635. */
  1636. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1637. u32 num_wraps, u32 next_entry,
  1638. u32 size, u32 mode,
  1639. int pos, char **buf, size_t bufsz)
  1640. {
  1641. /*
  1642. * display the newest DEFAULT_LOG_ENTRIES entries
  1643. * i.e the entries just before the next ont that uCode would fill.
  1644. */
  1645. if (num_wraps) {
  1646. if (next_entry < size) {
  1647. pos = iwl_print_event_log(priv,
  1648. capacity - (size - next_entry),
  1649. size - next_entry, mode,
  1650. pos, buf, bufsz);
  1651. pos = iwl_print_event_log(priv, 0,
  1652. next_entry, mode,
  1653. pos, buf, bufsz);
  1654. } else
  1655. pos = iwl_print_event_log(priv, next_entry - size,
  1656. size, mode, pos, buf, bufsz);
  1657. } else {
  1658. if (next_entry < size) {
  1659. pos = iwl_print_event_log(priv, 0, next_entry,
  1660. mode, pos, buf, bufsz);
  1661. } else {
  1662. pos = iwl_print_event_log(priv, next_entry - size,
  1663. size, mode, pos, buf, bufsz);
  1664. }
  1665. }
  1666. return pos;
  1667. }
  1668. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1669. #define MAX_EVENT_LOG_SIZE (512)
  1670. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1671. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1672. char **buf, bool display)
  1673. {
  1674. u32 base; /* SRAM byte address of event log header */
  1675. u32 capacity; /* event log capacity in # entries */
  1676. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1677. u32 num_wraps; /* # times uCode wrapped to top of log */
  1678. u32 next_entry; /* index of next entry to be written by uCode */
  1679. u32 size; /* # entries that we'll print */
  1680. int pos = 0;
  1681. size_t bufsz = 0;
  1682. if (priv->ucode_type == UCODE_INIT)
  1683. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1684. else
  1685. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1686. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1687. IWL_ERR(priv,
  1688. "Invalid event log pointer 0x%08X for %s uCode\n",
  1689. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1690. return -EINVAL;
  1691. }
  1692. /* event log header */
  1693. capacity = iwl_read_targ_mem(priv, base);
  1694. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1695. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1696. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1697. if (capacity > MAX_EVENT_LOG_SIZE) {
  1698. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1699. capacity, MAX_EVENT_LOG_SIZE);
  1700. capacity = MAX_EVENT_LOG_SIZE;
  1701. }
  1702. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1703. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1704. next_entry, MAX_EVENT_LOG_SIZE);
  1705. next_entry = MAX_EVENT_LOG_SIZE;
  1706. }
  1707. size = num_wraps ? capacity : next_entry;
  1708. /* bail out if nothing in log */
  1709. if (size == 0) {
  1710. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1711. return pos;
  1712. }
  1713. #ifdef CONFIG_IWLWIFI_DEBUG
  1714. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1715. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1716. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1717. #else
  1718. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1719. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1720. #endif
  1721. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1722. size);
  1723. #ifdef CONFIG_IWLWIFI_DEBUG
  1724. if (display) {
  1725. if (full_log)
  1726. bufsz = capacity * 48;
  1727. else
  1728. bufsz = size * 48;
  1729. *buf = kmalloc(bufsz, GFP_KERNEL);
  1730. if (!*buf)
  1731. return -ENOMEM;
  1732. }
  1733. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1734. /*
  1735. * if uCode has wrapped back to top of log,
  1736. * start at the oldest entry,
  1737. * i.e the next one that uCode would fill.
  1738. */
  1739. if (num_wraps)
  1740. pos = iwl_print_event_log(priv, next_entry,
  1741. capacity - next_entry, mode,
  1742. pos, buf, bufsz);
  1743. /* (then/else) start at top of log */
  1744. pos = iwl_print_event_log(priv, 0,
  1745. next_entry, mode, pos, buf, bufsz);
  1746. } else
  1747. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1748. next_entry, size, mode,
  1749. pos, buf, bufsz);
  1750. #else
  1751. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1752. next_entry, size, mode,
  1753. pos, buf, bufsz);
  1754. #endif
  1755. return pos;
  1756. }
  1757. /**
  1758. * iwl_alive_start - called after REPLY_ALIVE notification received
  1759. * from protocol/runtime uCode (initialization uCode's
  1760. * Alive gets handled by iwl_init_alive_start()).
  1761. */
  1762. static void iwl_alive_start(struct iwl_priv *priv)
  1763. {
  1764. int ret = 0;
  1765. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1766. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1767. /* We had an error bringing up the hardware, so take it
  1768. * all the way back down so we can try again */
  1769. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1770. goto restart;
  1771. }
  1772. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1773. * This is a paranoid check, because we would not have gotten the
  1774. * "runtime" alive if code weren't properly loaded. */
  1775. if (iwl_verify_ucode(priv)) {
  1776. /* Runtime instruction load was bad;
  1777. * take it all the way back down so we can try again */
  1778. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1779. goto restart;
  1780. }
  1781. iwl_clear_stations_table(priv);
  1782. ret = priv->cfg->ops->lib->alive_notify(priv);
  1783. if (ret) {
  1784. IWL_WARN(priv,
  1785. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1786. goto restart;
  1787. }
  1788. /* After the ALIVE response, we can send host commands to the uCode */
  1789. set_bit(STATUS_ALIVE, &priv->status);
  1790. if (iwl_is_rfkill(priv))
  1791. return;
  1792. ieee80211_wake_queues(priv->hw);
  1793. priv->active_rate = priv->rates_mask;
  1794. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1795. /* Configure Tx antenna selection based on H/W config */
  1796. if (priv->cfg->ops->hcmd->set_tx_ant)
  1797. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1798. if (iwl_is_associated(priv)) {
  1799. struct iwl_rxon_cmd *active_rxon =
  1800. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1801. /* apply any changes in staging */
  1802. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1803. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1804. } else {
  1805. /* Initialize our rx_config data */
  1806. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1807. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1808. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1809. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1810. }
  1811. /* Configure Bluetooth device coexistence support */
  1812. iwl_send_bt_config(priv);
  1813. iwl_reset_run_time_calib(priv);
  1814. /* Configure the adapter for unassociated operation */
  1815. iwlcore_commit_rxon(priv);
  1816. /* At this point, the NIC is initialized and operational */
  1817. iwl_rf_kill_ct_config(priv);
  1818. iwl_leds_init(priv);
  1819. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1820. set_bit(STATUS_READY, &priv->status);
  1821. wake_up_interruptible(&priv->wait_command_queue);
  1822. iwl_power_update_mode(priv, true);
  1823. /* reassociate for ADHOC mode */
  1824. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1825. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1826. priv->vif);
  1827. if (beacon)
  1828. iwl_mac_beacon_update(priv->hw, beacon);
  1829. }
  1830. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1831. iwl_set_mode(priv, priv->iw_mode);
  1832. return;
  1833. restart:
  1834. queue_work(priv->workqueue, &priv->restart);
  1835. }
  1836. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1837. static void __iwl_down(struct iwl_priv *priv)
  1838. {
  1839. unsigned long flags;
  1840. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1841. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1842. if (!exit_pending)
  1843. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1844. iwl_clear_stations_table(priv);
  1845. /* Unblock any waiting calls */
  1846. wake_up_interruptible_all(&priv->wait_command_queue);
  1847. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1848. * exiting the module */
  1849. if (!exit_pending)
  1850. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1851. /* stop and reset the on-board processor */
  1852. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1853. /* tell the device to stop sending interrupts */
  1854. spin_lock_irqsave(&priv->lock, flags);
  1855. iwl_disable_interrupts(priv);
  1856. spin_unlock_irqrestore(&priv->lock, flags);
  1857. iwl_synchronize_irq(priv);
  1858. if (priv->mac80211_registered)
  1859. ieee80211_stop_queues(priv->hw);
  1860. /* If we have not previously called iwl_init() then
  1861. * clear all bits but the RF Kill bit and return */
  1862. if (!iwl_is_init(priv)) {
  1863. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1864. STATUS_RF_KILL_HW |
  1865. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1866. STATUS_GEO_CONFIGURED |
  1867. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1868. STATUS_EXIT_PENDING;
  1869. goto exit;
  1870. }
  1871. /* ...otherwise clear out all the status bits but the RF Kill
  1872. * bit and continue taking the NIC down. */
  1873. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1874. STATUS_RF_KILL_HW |
  1875. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1876. STATUS_GEO_CONFIGURED |
  1877. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1878. STATUS_FW_ERROR |
  1879. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1880. STATUS_EXIT_PENDING;
  1881. /* device going down, Stop using ICT table */
  1882. iwl_disable_ict(priv);
  1883. iwl_txq_ctx_stop(priv);
  1884. iwl_rxq_stop(priv);
  1885. /* Power-down device's busmaster DMA clocks */
  1886. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1887. udelay(5);
  1888. /* Make sure (redundant) we've released our request to stay awake */
  1889. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1890. /* Stop the device, and put it in low power state */
  1891. priv->cfg->ops->lib->apm_ops.stop(priv);
  1892. exit:
  1893. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1894. if (priv->ibss_beacon)
  1895. dev_kfree_skb(priv->ibss_beacon);
  1896. priv->ibss_beacon = NULL;
  1897. /* clear out any free frames */
  1898. iwl_clear_free_frames(priv);
  1899. }
  1900. static void iwl_down(struct iwl_priv *priv)
  1901. {
  1902. mutex_lock(&priv->mutex);
  1903. __iwl_down(priv);
  1904. mutex_unlock(&priv->mutex);
  1905. iwl_cancel_deferred_work(priv);
  1906. }
  1907. #define HW_READY_TIMEOUT (50)
  1908. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1909. {
  1910. int ret = 0;
  1911. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1912. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1913. /* See if we got it */
  1914. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1915. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1916. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1917. HW_READY_TIMEOUT);
  1918. if (ret != -ETIMEDOUT)
  1919. priv->hw_ready = true;
  1920. else
  1921. priv->hw_ready = false;
  1922. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1923. (priv->hw_ready == 1) ? "ready" : "not ready");
  1924. return ret;
  1925. }
  1926. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1927. {
  1928. int ret = 0;
  1929. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1930. ret = iwl_set_hw_ready(priv);
  1931. if (priv->hw_ready)
  1932. return ret;
  1933. /* If HW is not ready, prepare the conditions to check again */
  1934. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1935. CSR_HW_IF_CONFIG_REG_PREPARE);
  1936. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1937. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1938. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1939. /* HW should be ready by now, check again. */
  1940. if (ret != -ETIMEDOUT)
  1941. iwl_set_hw_ready(priv);
  1942. return ret;
  1943. }
  1944. #define MAX_HW_RESTARTS 5
  1945. static int __iwl_up(struct iwl_priv *priv)
  1946. {
  1947. int i;
  1948. int ret;
  1949. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1950. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1951. return -EIO;
  1952. }
  1953. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1954. IWL_ERR(priv, "ucode not available for device bringup\n");
  1955. return -EIO;
  1956. }
  1957. iwl_prepare_card_hw(priv);
  1958. if (!priv->hw_ready) {
  1959. IWL_WARN(priv, "Exit HW not ready\n");
  1960. return -EIO;
  1961. }
  1962. /* If platform's RF_KILL switch is NOT set to KILL */
  1963. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1964. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1965. else
  1966. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1967. if (iwl_is_rfkill(priv)) {
  1968. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1969. iwl_enable_interrupts(priv);
  1970. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1971. return 0;
  1972. }
  1973. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1974. ret = iwl_hw_nic_init(priv);
  1975. if (ret) {
  1976. IWL_ERR(priv, "Unable to init nic\n");
  1977. return ret;
  1978. }
  1979. /* make sure rfkill handshake bits are cleared */
  1980. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1981. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1982. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1983. /* clear (again), then enable host interrupts */
  1984. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1985. iwl_enable_interrupts(priv);
  1986. /* really make sure rfkill handshake bits are cleared */
  1987. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1988. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1989. /* Copy original ucode data image from disk into backup cache.
  1990. * This will be used to initialize the on-board processor's
  1991. * data SRAM for a clean start when the runtime program first loads. */
  1992. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1993. priv->ucode_data.len);
  1994. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1995. iwl_clear_stations_table(priv);
  1996. /* load bootstrap state machine,
  1997. * load bootstrap program into processor's memory,
  1998. * prepare to load the "initialize" uCode */
  1999. ret = priv->cfg->ops->lib->load_ucode(priv);
  2000. if (ret) {
  2001. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2002. ret);
  2003. continue;
  2004. }
  2005. /* start card; "initialize" will load runtime ucode */
  2006. iwl_nic_start(priv);
  2007. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2008. return 0;
  2009. }
  2010. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2011. __iwl_down(priv);
  2012. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2013. /* tried to restart and config the device for as long as our
  2014. * patience could withstand */
  2015. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2016. return -EIO;
  2017. }
  2018. /*****************************************************************************
  2019. *
  2020. * Workqueue callbacks
  2021. *
  2022. *****************************************************************************/
  2023. static void iwl_bg_init_alive_start(struct work_struct *data)
  2024. {
  2025. struct iwl_priv *priv =
  2026. container_of(data, struct iwl_priv, init_alive_start.work);
  2027. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2028. return;
  2029. mutex_lock(&priv->mutex);
  2030. priv->cfg->ops->lib->init_alive_start(priv);
  2031. mutex_unlock(&priv->mutex);
  2032. }
  2033. static void iwl_bg_alive_start(struct work_struct *data)
  2034. {
  2035. struct iwl_priv *priv =
  2036. container_of(data, struct iwl_priv, alive_start.work);
  2037. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2038. return;
  2039. /* enable dram interrupt */
  2040. iwl_reset_ict(priv);
  2041. mutex_lock(&priv->mutex);
  2042. iwl_alive_start(priv);
  2043. mutex_unlock(&priv->mutex);
  2044. }
  2045. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2046. {
  2047. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2048. run_time_calib_work);
  2049. mutex_lock(&priv->mutex);
  2050. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2051. test_bit(STATUS_SCANNING, &priv->status)) {
  2052. mutex_unlock(&priv->mutex);
  2053. return;
  2054. }
  2055. if (priv->start_calib) {
  2056. iwl_chain_noise_calibration(priv, &priv->statistics);
  2057. iwl_sensitivity_calibration(priv, &priv->statistics);
  2058. }
  2059. mutex_unlock(&priv->mutex);
  2060. return;
  2061. }
  2062. static void iwl_bg_restart(struct work_struct *data)
  2063. {
  2064. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2065. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2066. return;
  2067. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2068. mutex_lock(&priv->mutex);
  2069. priv->vif = NULL;
  2070. priv->is_open = 0;
  2071. mutex_unlock(&priv->mutex);
  2072. iwl_down(priv);
  2073. ieee80211_restart_hw(priv->hw);
  2074. } else {
  2075. iwl_down(priv);
  2076. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2077. return;
  2078. mutex_lock(&priv->mutex);
  2079. __iwl_up(priv);
  2080. mutex_unlock(&priv->mutex);
  2081. }
  2082. }
  2083. static void iwl_bg_rx_replenish(struct work_struct *data)
  2084. {
  2085. struct iwl_priv *priv =
  2086. container_of(data, struct iwl_priv, rx_replenish);
  2087. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2088. return;
  2089. mutex_lock(&priv->mutex);
  2090. iwl_rx_replenish(priv);
  2091. mutex_unlock(&priv->mutex);
  2092. }
  2093. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2094. void iwl_post_associate(struct iwl_priv *priv)
  2095. {
  2096. struct ieee80211_conf *conf = NULL;
  2097. int ret = 0;
  2098. unsigned long flags;
  2099. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2100. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2101. return;
  2102. }
  2103. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2104. priv->assoc_id, priv->active_rxon.bssid_addr);
  2105. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2106. return;
  2107. if (!priv->vif || !priv->is_open)
  2108. return;
  2109. iwl_scan_cancel_timeout(priv, 200);
  2110. conf = ieee80211_get_hw_conf(priv->hw);
  2111. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2112. iwlcore_commit_rxon(priv);
  2113. iwl_setup_rxon_timing(priv);
  2114. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2115. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2116. if (ret)
  2117. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2118. "Attempting to continue.\n");
  2119. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2120. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2121. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2122. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2123. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2124. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2125. priv->assoc_id, priv->beacon_int);
  2126. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2127. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2128. else
  2129. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2130. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2131. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2132. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2133. else
  2134. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2135. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2136. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2137. }
  2138. iwlcore_commit_rxon(priv);
  2139. switch (priv->iw_mode) {
  2140. case NL80211_IFTYPE_STATION:
  2141. break;
  2142. case NL80211_IFTYPE_ADHOC:
  2143. /* assume default assoc id */
  2144. priv->assoc_id = 1;
  2145. iwl_rxon_add_station(priv, priv->bssid, 0);
  2146. iwl_send_beacon_cmd(priv);
  2147. break;
  2148. default:
  2149. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2150. __func__, priv->iw_mode);
  2151. break;
  2152. }
  2153. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2154. priv->assoc_station_added = 1;
  2155. spin_lock_irqsave(&priv->lock, flags);
  2156. iwl_activate_qos(priv, 0);
  2157. spin_unlock_irqrestore(&priv->lock, flags);
  2158. /* the chain noise calibration will enabled PM upon completion
  2159. * If chain noise has already been run, then we need to enable
  2160. * power management here */
  2161. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2162. iwl_power_update_mode(priv, false);
  2163. /* Enable Rx differential gain and sensitivity calibrations */
  2164. iwl_chain_noise_reset(priv);
  2165. priv->start_calib = 1;
  2166. }
  2167. /*****************************************************************************
  2168. *
  2169. * mac80211 entry point functions
  2170. *
  2171. *****************************************************************************/
  2172. #define UCODE_READY_TIMEOUT (4 * HZ)
  2173. /*
  2174. * Not a mac80211 entry point function, but it fits in with all the
  2175. * other mac80211 functions grouped here.
  2176. */
  2177. static int iwl_mac_setup_register(struct iwl_priv *priv)
  2178. {
  2179. int ret;
  2180. struct ieee80211_hw *hw = priv->hw;
  2181. hw->rate_control_algorithm = "iwl-agn-rs";
  2182. /* Tell mac80211 our characteristics */
  2183. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2184. IEEE80211_HW_NOISE_DBM |
  2185. IEEE80211_HW_AMPDU_AGGREGATION |
  2186. IEEE80211_HW_SPECTRUM_MGMT;
  2187. if (!priv->cfg->broken_powersave)
  2188. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2189. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2190. if (priv->cfg->sku & IWL_SKU_N)
  2191. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2192. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2193. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2194. hw->wiphy->interface_modes =
  2195. BIT(NL80211_IFTYPE_STATION) |
  2196. BIT(NL80211_IFTYPE_ADHOC);
  2197. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2198. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2199. /*
  2200. * For now, disable PS by default because it affects
  2201. * RX performance significantly.
  2202. */
  2203. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2204. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2205. /* we create the 802.11 header and a zero-length SSID element */
  2206. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2207. /* Default value; 4 EDCA QOS priorities */
  2208. hw->queues = 4;
  2209. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2210. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2211. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2212. &priv->bands[IEEE80211_BAND_2GHZ];
  2213. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2214. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2215. &priv->bands[IEEE80211_BAND_5GHZ];
  2216. ret = ieee80211_register_hw(priv->hw);
  2217. if (ret) {
  2218. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2219. return ret;
  2220. }
  2221. priv->mac80211_registered = 1;
  2222. return 0;
  2223. }
  2224. static int iwl_mac_start(struct ieee80211_hw *hw)
  2225. {
  2226. struct iwl_priv *priv = hw->priv;
  2227. int ret;
  2228. IWL_DEBUG_MAC80211(priv, "enter\n");
  2229. /* we should be verifying the device is ready to be opened */
  2230. mutex_lock(&priv->mutex);
  2231. ret = __iwl_up(priv);
  2232. mutex_unlock(&priv->mutex);
  2233. if (ret)
  2234. return ret;
  2235. if (iwl_is_rfkill(priv))
  2236. goto out;
  2237. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2238. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2239. * mac80211 will not be run successfully. */
  2240. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2241. test_bit(STATUS_READY, &priv->status),
  2242. UCODE_READY_TIMEOUT);
  2243. if (!ret) {
  2244. if (!test_bit(STATUS_READY, &priv->status)) {
  2245. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2246. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2247. return -ETIMEDOUT;
  2248. }
  2249. }
  2250. iwl_led_start(priv);
  2251. out:
  2252. priv->is_open = 1;
  2253. IWL_DEBUG_MAC80211(priv, "leave\n");
  2254. return 0;
  2255. }
  2256. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2257. {
  2258. struct iwl_priv *priv = hw->priv;
  2259. IWL_DEBUG_MAC80211(priv, "enter\n");
  2260. if (!priv->is_open)
  2261. return;
  2262. priv->is_open = 0;
  2263. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2264. /* stop mac, cancel any scan request and clear
  2265. * RXON_FILTER_ASSOC_MSK BIT
  2266. */
  2267. mutex_lock(&priv->mutex);
  2268. iwl_scan_cancel_timeout(priv, 100);
  2269. mutex_unlock(&priv->mutex);
  2270. }
  2271. iwl_down(priv);
  2272. flush_workqueue(priv->workqueue);
  2273. /* enable interrupts again in order to receive rfkill changes */
  2274. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2275. iwl_enable_interrupts(priv);
  2276. IWL_DEBUG_MAC80211(priv, "leave\n");
  2277. }
  2278. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2279. {
  2280. struct iwl_priv *priv = hw->priv;
  2281. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2282. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2283. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2284. if (iwl_tx_skb(priv, skb))
  2285. dev_kfree_skb_any(skb);
  2286. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2287. return NETDEV_TX_OK;
  2288. }
  2289. void iwl_config_ap(struct iwl_priv *priv)
  2290. {
  2291. int ret = 0;
  2292. unsigned long flags;
  2293. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2294. return;
  2295. /* The following should be done only at AP bring up */
  2296. if (!iwl_is_associated(priv)) {
  2297. /* RXON - unassoc (to set timing command) */
  2298. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2299. iwlcore_commit_rxon(priv);
  2300. /* RXON Timing */
  2301. iwl_setup_rxon_timing(priv);
  2302. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2303. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2304. if (ret)
  2305. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2306. "Attempting to continue.\n");
  2307. /* AP has all antennas */
  2308. priv->chain_noise_data.active_chains =
  2309. priv->hw_params.valid_rx_ant;
  2310. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2311. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2312. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2313. /* FIXME: what should be the assoc_id for AP? */
  2314. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2315. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2316. priv->staging_rxon.flags |=
  2317. RXON_FLG_SHORT_PREAMBLE_MSK;
  2318. else
  2319. priv->staging_rxon.flags &=
  2320. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2321. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2322. if (priv->assoc_capability &
  2323. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2324. priv->staging_rxon.flags |=
  2325. RXON_FLG_SHORT_SLOT_MSK;
  2326. else
  2327. priv->staging_rxon.flags &=
  2328. ~RXON_FLG_SHORT_SLOT_MSK;
  2329. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2330. priv->staging_rxon.flags &=
  2331. ~RXON_FLG_SHORT_SLOT_MSK;
  2332. }
  2333. /* restore RXON assoc */
  2334. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2335. iwlcore_commit_rxon(priv);
  2336. iwl_reset_qos(priv);
  2337. spin_lock_irqsave(&priv->lock, flags);
  2338. iwl_activate_qos(priv, 1);
  2339. spin_unlock_irqrestore(&priv->lock, flags);
  2340. iwl_add_bcast_station(priv);
  2341. }
  2342. iwl_send_beacon_cmd(priv);
  2343. /* FIXME - we need to add code here to detect a totally new
  2344. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2345. * clear sta table, add BCAST sta... */
  2346. }
  2347. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2348. struct ieee80211_vif *vif,
  2349. struct ieee80211_key_conf *keyconf,
  2350. struct ieee80211_sta *sta,
  2351. u32 iv32, u16 *phase1key)
  2352. {
  2353. struct iwl_priv *priv = hw->priv;
  2354. IWL_DEBUG_MAC80211(priv, "enter\n");
  2355. iwl_update_tkip_key(priv, keyconf,
  2356. sta ? sta->addr : iwl_bcast_addr,
  2357. iv32, phase1key);
  2358. IWL_DEBUG_MAC80211(priv, "leave\n");
  2359. }
  2360. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2361. struct ieee80211_vif *vif,
  2362. struct ieee80211_sta *sta,
  2363. struct ieee80211_key_conf *key)
  2364. {
  2365. struct iwl_priv *priv = hw->priv;
  2366. const u8 *addr;
  2367. int ret;
  2368. u8 sta_id;
  2369. bool is_default_wep_key = false;
  2370. IWL_DEBUG_MAC80211(priv, "enter\n");
  2371. if (priv->cfg->mod_params->sw_crypto) {
  2372. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2373. return -EOPNOTSUPP;
  2374. }
  2375. addr = sta ? sta->addr : iwl_bcast_addr;
  2376. sta_id = iwl_find_station(priv, addr);
  2377. if (sta_id == IWL_INVALID_STATION) {
  2378. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2379. addr);
  2380. return -EINVAL;
  2381. }
  2382. mutex_lock(&priv->mutex);
  2383. iwl_scan_cancel_timeout(priv, 100);
  2384. mutex_unlock(&priv->mutex);
  2385. /* If we are getting WEP group key and we didn't receive any key mapping
  2386. * so far, we are in legacy wep mode (group key only), otherwise we are
  2387. * in 1X mode.
  2388. * In legacy wep mode, we use another host command to the uCode */
  2389. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2390. priv->iw_mode != NL80211_IFTYPE_AP) {
  2391. if (cmd == SET_KEY)
  2392. is_default_wep_key = !priv->key_mapping_key;
  2393. else
  2394. is_default_wep_key =
  2395. (key->hw_key_idx == HW_KEY_DEFAULT);
  2396. }
  2397. switch (cmd) {
  2398. case SET_KEY:
  2399. if (is_default_wep_key)
  2400. ret = iwl_set_default_wep_key(priv, key);
  2401. else
  2402. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2403. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2404. break;
  2405. case DISABLE_KEY:
  2406. if (is_default_wep_key)
  2407. ret = iwl_remove_default_wep_key(priv, key);
  2408. else
  2409. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2410. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2411. break;
  2412. default:
  2413. ret = -EINVAL;
  2414. }
  2415. IWL_DEBUG_MAC80211(priv, "leave\n");
  2416. return ret;
  2417. }
  2418. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2419. struct ieee80211_vif *vif,
  2420. enum ieee80211_ampdu_mlme_action action,
  2421. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2422. {
  2423. struct iwl_priv *priv = hw->priv;
  2424. int ret;
  2425. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2426. sta->addr, tid);
  2427. if (!(priv->cfg->sku & IWL_SKU_N))
  2428. return -EACCES;
  2429. switch (action) {
  2430. case IEEE80211_AMPDU_RX_START:
  2431. IWL_DEBUG_HT(priv, "start Rx\n");
  2432. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2433. case IEEE80211_AMPDU_RX_STOP:
  2434. IWL_DEBUG_HT(priv, "stop Rx\n");
  2435. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2436. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2437. return 0;
  2438. else
  2439. return ret;
  2440. case IEEE80211_AMPDU_TX_START:
  2441. IWL_DEBUG_HT(priv, "start Tx\n");
  2442. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2443. case IEEE80211_AMPDU_TX_STOP:
  2444. IWL_DEBUG_HT(priv, "stop Tx\n");
  2445. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2446. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2447. return 0;
  2448. else
  2449. return ret;
  2450. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2451. /* do nothing */
  2452. return -EOPNOTSUPP;
  2453. default:
  2454. IWL_DEBUG_HT(priv, "unknown\n");
  2455. return -EINVAL;
  2456. break;
  2457. }
  2458. return 0;
  2459. }
  2460. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2461. struct ieee80211_low_level_stats *stats)
  2462. {
  2463. struct iwl_priv *priv = hw->priv;
  2464. priv = hw->priv;
  2465. IWL_DEBUG_MAC80211(priv, "enter\n");
  2466. IWL_DEBUG_MAC80211(priv, "leave\n");
  2467. return 0;
  2468. }
  2469. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2470. struct ieee80211_vif *vif,
  2471. enum sta_notify_cmd cmd,
  2472. struct ieee80211_sta *sta)
  2473. {
  2474. struct iwl_priv *priv = hw->priv;
  2475. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2476. int sta_id;
  2477. /*
  2478. * TODO: We really should use this callback to
  2479. * actually maintain the station table in
  2480. * the device.
  2481. */
  2482. switch (cmd) {
  2483. case STA_NOTIFY_ADD:
  2484. atomic_set(&sta_priv->pending_frames, 0);
  2485. if (vif->type == NL80211_IFTYPE_AP)
  2486. sta_priv->client = true;
  2487. break;
  2488. case STA_NOTIFY_SLEEP:
  2489. WARN_ON(!sta_priv->client);
  2490. sta_priv->asleep = true;
  2491. if (atomic_read(&sta_priv->pending_frames) > 0)
  2492. ieee80211_sta_block_awake(hw, sta, true);
  2493. break;
  2494. case STA_NOTIFY_AWAKE:
  2495. WARN_ON(!sta_priv->client);
  2496. if (!sta_priv->asleep)
  2497. break;
  2498. sta_priv->asleep = false;
  2499. sta_id = iwl_find_station(priv, sta->addr);
  2500. if (sta_id != IWL_INVALID_STATION)
  2501. iwl_sta_modify_ps_wake(priv, sta_id);
  2502. break;
  2503. default:
  2504. break;
  2505. }
  2506. }
  2507. /*****************************************************************************
  2508. *
  2509. * sysfs attributes
  2510. *
  2511. *****************************************************************************/
  2512. #ifdef CONFIG_IWLWIFI_DEBUG
  2513. /*
  2514. * The following adds a new attribute to the sysfs representation
  2515. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2516. * used for controlling the debug level.
  2517. *
  2518. * See the level definitions in iwl for details.
  2519. *
  2520. * The debug_level being managed using sysfs below is a per device debug
  2521. * level that is used instead of the global debug level if it (the per
  2522. * device debug level) is set.
  2523. */
  2524. static ssize_t show_debug_level(struct device *d,
  2525. struct device_attribute *attr, char *buf)
  2526. {
  2527. struct iwl_priv *priv = dev_get_drvdata(d);
  2528. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2529. }
  2530. static ssize_t store_debug_level(struct device *d,
  2531. struct device_attribute *attr,
  2532. const char *buf, size_t count)
  2533. {
  2534. struct iwl_priv *priv = dev_get_drvdata(d);
  2535. unsigned long val;
  2536. int ret;
  2537. ret = strict_strtoul(buf, 0, &val);
  2538. if (ret)
  2539. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2540. else {
  2541. priv->debug_level = val;
  2542. if (iwl_alloc_traffic_mem(priv))
  2543. IWL_ERR(priv,
  2544. "Not enough memory to generate traffic log\n");
  2545. }
  2546. return strnlen(buf, count);
  2547. }
  2548. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2549. show_debug_level, store_debug_level);
  2550. #endif /* CONFIG_IWLWIFI_DEBUG */
  2551. static ssize_t show_temperature(struct device *d,
  2552. struct device_attribute *attr, char *buf)
  2553. {
  2554. struct iwl_priv *priv = dev_get_drvdata(d);
  2555. if (!iwl_is_alive(priv))
  2556. return -EAGAIN;
  2557. return sprintf(buf, "%d\n", priv->temperature);
  2558. }
  2559. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2560. static ssize_t show_tx_power(struct device *d,
  2561. struct device_attribute *attr, char *buf)
  2562. {
  2563. struct iwl_priv *priv = dev_get_drvdata(d);
  2564. if (!iwl_is_ready_rf(priv))
  2565. return sprintf(buf, "off\n");
  2566. else
  2567. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2568. }
  2569. static ssize_t store_tx_power(struct device *d,
  2570. struct device_attribute *attr,
  2571. const char *buf, size_t count)
  2572. {
  2573. struct iwl_priv *priv = dev_get_drvdata(d);
  2574. unsigned long val;
  2575. int ret;
  2576. ret = strict_strtoul(buf, 10, &val);
  2577. if (ret)
  2578. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2579. else {
  2580. ret = iwl_set_tx_power(priv, val, false);
  2581. if (ret)
  2582. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2583. ret);
  2584. else
  2585. ret = count;
  2586. }
  2587. return ret;
  2588. }
  2589. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2590. static ssize_t show_flags(struct device *d,
  2591. struct device_attribute *attr, char *buf)
  2592. {
  2593. struct iwl_priv *priv = dev_get_drvdata(d);
  2594. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2595. }
  2596. static ssize_t store_flags(struct device *d,
  2597. struct device_attribute *attr,
  2598. const char *buf, size_t count)
  2599. {
  2600. struct iwl_priv *priv = dev_get_drvdata(d);
  2601. unsigned long val;
  2602. u32 flags;
  2603. int ret = strict_strtoul(buf, 0, &val);
  2604. if (ret)
  2605. return ret;
  2606. flags = (u32)val;
  2607. mutex_lock(&priv->mutex);
  2608. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2609. /* Cancel any currently running scans... */
  2610. if (iwl_scan_cancel_timeout(priv, 100))
  2611. IWL_WARN(priv, "Could not cancel scan.\n");
  2612. else {
  2613. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2614. priv->staging_rxon.flags = cpu_to_le32(flags);
  2615. iwlcore_commit_rxon(priv);
  2616. }
  2617. }
  2618. mutex_unlock(&priv->mutex);
  2619. return count;
  2620. }
  2621. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2622. static ssize_t show_filter_flags(struct device *d,
  2623. struct device_attribute *attr, char *buf)
  2624. {
  2625. struct iwl_priv *priv = dev_get_drvdata(d);
  2626. return sprintf(buf, "0x%04X\n",
  2627. le32_to_cpu(priv->active_rxon.filter_flags));
  2628. }
  2629. static ssize_t store_filter_flags(struct device *d,
  2630. struct device_attribute *attr,
  2631. const char *buf, size_t count)
  2632. {
  2633. struct iwl_priv *priv = dev_get_drvdata(d);
  2634. unsigned long val;
  2635. u32 filter_flags;
  2636. int ret = strict_strtoul(buf, 0, &val);
  2637. if (ret)
  2638. return ret;
  2639. filter_flags = (u32)val;
  2640. mutex_lock(&priv->mutex);
  2641. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2642. /* Cancel any currently running scans... */
  2643. if (iwl_scan_cancel_timeout(priv, 100))
  2644. IWL_WARN(priv, "Could not cancel scan.\n");
  2645. else {
  2646. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2647. "0x%04X\n", filter_flags);
  2648. priv->staging_rxon.filter_flags =
  2649. cpu_to_le32(filter_flags);
  2650. iwlcore_commit_rxon(priv);
  2651. }
  2652. }
  2653. mutex_unlock(&priv->mutex);
  2654. return count;
  2655. }
  2656. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2657. store_filter_flags);
  2658. static ssize_t show_statistics(struct device *d,
  2659. struct device_attribute *attr, char *buf)
  2660. {
  2661. struct iwl_priv *priv = dev_get_drvdata(d);
  2662. u32 size = sizeof(struct iwl_notif_statistics);
  2663. u32 len = 0, ofs = 0;
  2664. u8 *data = (u8 *)&priv->statistics;
  2665. int rc = 0;
  2666. if (!iwl_is_alive(priv))
  2667. return -EAGAIN;
  2668. mutex_lock(&priv->mutex);
  2669. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2670. mutex_unlock(&priv->mutex);
  2671. if (rc) {
  2672. len = sprintf(buf,
  2673. "Error sending statistics request: 0x%08X\n", rc);
  2674. return len;
  2675. }
  2676. while (size && (PAGE_SIZE - len)) {
  2677. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2678. PAGE_SIZE - len, 1);
  2679. len = strlen(buf);
  2680. if (PAGE_SIZE - len)
  2681. buf[len++] = '\n';
  2682. ofs += 16;
  2683. size -= min(size, 16U);
  2684. }
  2685. return len;
  2686. }
  2687. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2688. static ssize_t show_rts_ht_protection(struct device *d,
  2689. struct device_attribute *attr, char *buf)
  2690. {
  2691. struct iwl_priv *priv = dev_get_drvdata(d);
  2692. return sprintf(buf, "%s\n",
  2693. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2694. }
  2695. static ssize_t store_rts_ht_protection(struct device *d,
  2696. struct device_attribute *attr,
  2697. const char *buf, size_t count)
  2698. {
  2699. struct iwl_priv *priv = dev_get_drvdata(d);
  2700. unsigned long val;
  2701. int ret;
  2702. ret = strict_strtoul(buf, 10, &val);
  2703. if (ret)
  2704. IWL_INFO(priv, "Input is not in decimal form.\n");
  2705. else {
  2706. if (!iwl_is_associated(priv))
  2707. priv->cfg->use_rts_for_ht = val ? true : false;
  2708. else
  2709. IWL_ERR(priv, "Sta associated with AP - "
  2710. "Change protection mechanism is not allowed\n");
  2711. ret = count;
  2712. }
  2713. return ret;
  2714. }
  2715. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2716. show_rts_ht_protection, store_rts_ht_protection);
  2717. /*****************************************************************************
  2718. *
  2719. * driver setup and teardown
  2720. *
  2721. *****************************************************************************/
  2722. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2723. {
  2724. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2725. init_waitqueue_head(&priv->wait_command_queue);
  2726. INIT_WORK(&priv->restart, iwl_bg_restart);
  2727. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2728. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2729. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2730. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2731. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2732. iwl_setup_scan_deferred_work(priv);
  2733. if (priv->cfg->ops->lib->setup_deferred_work)
  2734. priv->cfg->ops->lib->setup_deferred_work(priv);
  2735. init_timer(&priv->statistics_periodic);
  2736. priv->statistics_periodic.data = (unsigned long)priv;
  2737. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2738. init_timer(&priv->ucode_trace);
  2739. priv->ucode_trace.data = (unsigned long)priv;
  2740. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2741. if (!priv->cfg->use_isr_legacy)
  2742. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2743. iwl_irq_tasklet, (unsigned long)priv);
  2744. else
  2745. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2746. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2747. }
  2748. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2749. {
  2750. if (priv->cfg->ops->lib->cancel_deferred_work)
  2751. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2752. cancel_delayed_work_sync(&priv->init_alive_start);
  2753. cancel_delayed_work(&priv->scan_check);
  2754. cancel_work_sync(&priv->start_internal_scan);
  2755. cancel_delayed_work(&priv->alive_start);
  2756. cancel_work_sync(&priv->beacon_update);
  2757. del_timer_sync(&priv->statistics_periodic);
  2758. del_timer_sync(&priv->ucode_trace);
  2759. }
  2760. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2761. struct ieee80211_rate *rates)
  2762. {
  2763. int i;
  2764. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2765. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2766. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2767. rates[i].hw_value_short = i;
  2768. rates[i].flags = 0;
  2769. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2770. /*
  2771. * If CCK != 1M then set short preamble rate flag.
  2772. */
  2773. rates[i].flags |=
  2774. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2775. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2776. }
  2777. }
  2778. }
  2779. static int iwl_init_drv(struct iwl_priv *priv)
  2780. {
  2781. int ret;
  2782. priv->ibss_beacon = NULL;
  2783. spin_lock_init(&priv->sta_lock);
  2784. spin_lock_init(&priv->hcmd_lock);
  2785. INIT_LIST_HEAD(&priv->free_frames);
  2786. mutex_init(&priv->mutex);
  2787. mutex_init(&priv->sync_cmd_mutex);
  2788. /* Clear the driver's (not device's) station table */
  2789. iwl_clear_stations_table(priv);
  2790. priv->ieee_channels = NULL;
  2791. priv->ieee_rates = NULL;
  2792. priv->band = IEEE80211_BAND_2GHZ;
  2793. priv->iw_mode = NL80211_IFTYPE_STATION;
  2794. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2795. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2796. /* initialize force reset */
  2797. priv->force_reset[IWL_RF_RESET].reset_duration =
  2798. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2799. priv->force_reset[IWL_FW_RESET].reset_duration =
  2800. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2801. /* Choose which receivers/antennas to use */
  2802. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2803. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2804. iwl_init_scan_params(priv);
  2805. iwl_reset_qos(priv);
  2806. priv->qos_data.qos_active = 0;
  2807. priv->qos_data.qos_cap.val = 0;
  2808. priv->rates_mask = IWL_RATES_MASK;
  2809. /* Set the tx_power_user_lmt to the lowest power level
  2810. * this value will get overwritten by channel max power avg
  2811. * from eeprom */
  2812. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2813. ret = iwl_init_channel_map(priv);
  2814. if (ret) {
  2815. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2816. goto err;
  2817. }
  2818. ret = iwlcore_init_geos(priv);
  2819. if (ret) {
  2820. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2821. goto err_free_channel_map;
  2822. }
  2823. iwl_init_hw_rates(priv, priv->ieee_rates);
  2824. return 0;
  2825. err_free_channel_map:
  2826. iwl_free_channel_map(priv);
  2827. err:
  2828. return ret;
  2829. }
  2830. static void iwl_uninit_drv(struct iwl_priv *priv)
  2831. {
  2832. iwl_calib_free_results(priv);
  2833. iwlcore_free_geos(priv);
  2834. iwl_free_channel_map(priv);
  2835. kfree(priv->scan);
  2836. }
  2837. static struct attribute *iwl_sysfs_entries[] = {
  2838. &dev_attr_flags.attr,
  2839. &dev_attr_filter_flags.attr,
  2840. &dev_attr_statistics.attr,
  2841. &dev_attr_temperature.attr,
  2842. &dev_attr_tx_power.attr,
  2843. &dev_attr_rts_ht_protection.attr,
  2844. #ifdef CONFIG_IWLWIFI_DEBUG
  2845. &dev_attr_debug_level.attr,
  2846. #endif
  2847. NULL
  2848. };
  2849. static struct attribute_group iwl_attribute_group = {
  2850. .name = NULL, /* put in device directory */
  2851. .attrs = iwl_sysfs_entries,
  2852. };
  2853. static struct ieee80211_ops iwl_hw_ops = {
  2854. .tx = iwl_mac_tx,
  2855. .start = iwl_mac_start,
  2856. .stop = iwl_mac_stop,
  2857. .add_interface = iwl_mac_add_interface,
  2858. .remove_interface = iwl_mac_remove_interface,
  2859. .config = iwl_mac_config,
  2860. .configure_filter = iwl_configure_filter,
  2861. .set_key = iwl_mac_set_key,
  2862. .update_tkip_key = iwl_mac_update_tkip_key,
  2863. .get_stats = iwl_mac_get_stats,
  2864. .conf_tx = iwl_mac_conf_tx,
  2865. .reset_tsf = iwl_mac_reset_tsf,
  2866. .bss_info_changed = iwl_bss_info_changed,
  2867. .ampdu_action = iwl_mac_ampdu_action,
  2868. .hw_scan = iwl_mac_hw_scan,
  2869. .sta_notify = iwl_mac_sta_notify,
  2870. };
  2871. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2872. {
  2873. int err = 0;
  2874. struct iwl_priv *priv;
  2875. struct ieee80211_hw *hw;
  2876. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2877. unsigned long flags;
  2878. u16 pci_cmd;
  2879. /************************
  2880. * 1. Allocating HW data
  2881. ************************/
  2882. /* Disabling hardware scan means that mac80211 will perform scans
  2883. * "the hard way", rather than using device's scan. */
  2884. if (cfg->mod_params->disable_hw_scan) {
  2885. if (iwl_debug_level & IWL_DL_INFO)
  2886. dev_printk(KERN_DEBUG, &(pdev->dev),
  2887. "Disabling hw_scan\n");
  2888. iwl_hw_ops.hw_scan = NULL;
  2889. }
  2890. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2891. if (!hw) {
  2892. err = -ENOMEM;
  2893. goto out;
  2894. }
  2895. priv = hw->priv;
  2896. /* At this point both hw and priv are allocated. */
  2897. SET_IEEE80211_DEV(hw, &pdev->dev);
  2898. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2899. priv->cfg = cfg;
  2900. priv->pci_dev = pdev;
  2901. priv->inta_mask = CSR_INI_SET_MASK;
  2902. #ifdef CONFIG_IWLWIFI_DEBUG
  2903. atomic_set(&priv->restrict_refcnt, 0);
  2904. #endif
  2905. if (iwl_alloc_traffic_mem(priv))
  2906. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2907. /**************************
  2908. * 2. Initializing PCI bus
  2909. **************************/
  2910. if (pci_enable_device(pdev)) {
  2911. err = -ENODEV;
  2912. goto out_ieee80211_free_hw;
  2913. }
  2914. pci_set_master(pdev);
  2915. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2916. if (!err)
  2917. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2918. if (err) {
  2919. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2920. if (!err)
  2921. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2922. /* both attempts failed: */
  2923. if (err) {
  2924. IWL_WARN(priv, "No suitable DMA available.\n");
  2925. goto out_pci_disable_device;
  2926. }
  2927. }
  2928. err = pci_request_regions(pdev, DRV_NAME);
  2929. if (err)
  2930. goto out_pci_disable_device;
  2931. pci_set_drvdata(pdev, priv);
  2932. /***********************
  2933. * 3. Read REV register
  2934. ***********************/
  2935. priv->hw_base = pci_iomap(pdev, 0, 0);
  2936. if (!priv->hw_base) {
  2937. err = -ENODEV;
  2938. goto out_pci_release_regions;
  2939. }
  2940. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2941. (unsigned long long) pci_resource_len(pdev, 0));
  2942. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2943. /* these spin locks will be used in apm_ops.init and EEPROM access
  2944. * we should init now
  2945. */
  2946. spin_lock_init(&priv->reg_lock);
  2947. spin_lock_init(&priv->lock);
  2948. /*
  2949. * stop and reset the on-board processor just in case it is in a
  2950. * strange state ... like being left stranded by a primary kernel
  2951. * and this is now the kdump kernel trying to start up
  2952. */
  2953. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2954. iwl_hw_detect(priv);
  2955. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2956. priv->cfg->name, priv->hw_rev);
  2957. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2958. * PCI Tx retries from interfering with C3 CPU state */
  2959. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2960. iwl_prepare_card_hw(priv);
  2961. if (!priv->hw_ready) {
  2962. IWL_WARN(priv, "Failed, HW not ready\n");
  2963. goto out_iounmap;
  2964. }
  2965. /*****************
  2966. * 4. Read EEPROM
  2967. *****************/
  2968. /* Read the EEPROM */
  2969. err = iwl_eeprom_init(priv);
  2970. if (err) {
  2971. IWL_ERR(priv, "Unable to init EEPROM\n");
  2972. goto out_iounmap;
  2973. }
  2974. err = iwl_eeprom_check_version(priv);
  2975. if (err)
  2976. goto out_free_eeprom;
  2977. /* extract MAC Address */
  2978. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2979. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2980. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2981. /************************
  2982. * 5. Setup HW constants
  2983. ************************/
  2984. if (iwl_set_hw_params(priv)) {
  2985. IWL_ERR(priv, "failed to set hw parameters\n");
  2986. goto out_free_eeprom;
  2987. }
  2988. /*******************
  2989. * 6. Setup priv
  2990. *******************/
  2991. err = iwl_init_drv(priv);
  2992. if (err)
  2993. goto out_free_eeprom;
  2994. /* At this point both hw and priv are initialized. */
  2995. /********************
  2996. * 7. Setup services
  2997. ********************/
  2998. spin_lock_irqsave(&priv->lock, flags);
  2999. iwl_disable_interrupts(priv);
  3000. spin_unlock_irqrestore(&priv->lock, flags);
  3001. pci_enable_msi(priv->pci_dev);
  3002. iwl_alloc_isr_ict(priv);
  3003. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3004. IRQF_SHARED, DRV_NAME, priv);
  3005. if (err) {
  3006. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3007. goto out_disable_msi;
  3008. }
  3009. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  3010. if (err) {
  3011. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3012. goto out_free_irq;
  3013. }
  3014. iwl_setup_deferred_work(priv);
  3015. iwl_setup_rx_handlers(priv);
  3016. /*********************************************
  3017. * 8. Enable interrupts and read RFKILL state
  3018. *********************************************/
  3019. /* enable interrupts if needed: hw bug w/a */
  3020. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3021. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3022. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3023. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3024. }
  3025. iwl_enable_interrupts(priv);
  3026. /* If platform's RF_KILL switch is NOT set to KILL */
  3027. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3028. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3029. else
  3030. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3031. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3032. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3033. iwl_power_initialize(priv);
  3034. iwl_tt_initialize(priv);
  3035. init_completion(&priv->firmware_loading_complete);
  3036. err = iwl_request_firmware(priv, true);
  3037. if (err)
  3038. goto out_remove_sysfs;
  3039. return 0;
  3040. out_remove_sysfs:
  3041. destroy_workqueue(priv->workqueue);
  3042. priv->workqueue = NULL;
  3043. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3044. out_free_irq:
  3045. free_irq(priv->pci_dev->irq, priv);
  3046. iwl_free_isr_ict(priv);
  3047. out_disable_msi:
  3048. pci_disable_msi(priv->pci_dev);
  3049. iwl_uninit_drv(priv);
  3050. out_free_eeprom:
  3051. iwl_eeprom_free(priv);
  3052. out_iounmap:
  3053. pci_iounmap(pdev, priv->hw_base);
  3054. out_pci_release_regions:
  3055. pci_set_drvdata(pdev, NULL);
  3056. pci_release_regions(pdev);
  3057. out_pci_disable_device:
  3058. pci_disable_device(pdev);
  3059. out_ieee80211_free_hw:
  3060. iwl_free_traffic_mem(priv);
  3061. ieee80211_free_hw(priv->hw);
  3062. out:
  3063. return err;
  3064. }
  3065. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3066. {
  3067. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3068. unsigned long flags;
  3069. if (!priv)
  3070. return;
  3071. wait_for_completion(&priv->firmware_loading_complete);
  3072. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3073. iwl_dbgfs_unregister(priv);
  3074. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3075. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3076. * to be called and iwl_down since we are removing the device
  3077. * we need to set STATUS_EXIT_PENDING bit.
  3078. */
  3079. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3080. if (priv->mac80211_registered) {
  3081. ieee80211_unregister_hw(priv->hw);
  3082. priv->mac80211_registered = 0;
  3083. } else {
  3084. iwl_down(priv);
  3085. }
  3086. /*
  3087. * Make sure device is reset to low power before unloading driver.
  3088. * This may be redundant with iwl_down(), but there are paths to
  3089. * run iwl_down() without calling apm_ops.stop(), and there are
  3090. * paths to avoid running iwl_down() at all before leaving driver.
  3091. * This (inexpensive) call *makes sure* device is reset.
  3092. */
  3093. priv->cfg->ops->lib->apm_ops.stop(priv);
  3094. iwl_tt_exit(priv);
  3095. /* make sure we flush any pending irq or
  3096. * tasklet for the driver
  3097. */
  3098. spin_lock_irqsave(&priv->lock, flags);
  3099. iwl_disable_interrupts(priv);
  3100. spin_unlock_irqrestore(&priv->lock, flags);
  3101. iwl_synchronize_irq(priv);
  3102. iwl_dealloc_ucode_pci(priv);
  3103. if (priv->rxq.bd)
  3104. iwl_rx_queue_free(priv, &priv->rxq);
  3105. iwl_hw_txq_ctx_free(priv);
  3106. iwl_clear_stations_table(priv);
  3107. iwl_eeprom_free(priv);
  3108. /*netif_stop_queue(dev); */
  3109. flush_workqueue(priv->workqueue);
  3110. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3111. * priv->workqueue... so we can't take down the workqueue
  3112. * until now... */
  3113. destroy_workqueue(priv->workqueue);
  3114. priv->workqueue = NULL;
  3115. iwl_free_traffic_mem(priv);
  3116. free_irq(priv->pci_dev->irq, priv);
  3117. pci_disable_msi(priv->pci_dev);
  3118. pci_iounmap(pdev, priv->hw_base);
  3119. pci_release_regions(pdev);
  3120. pci_disable_device(pdev);
  3121. pci_set_drvdata(pdev, NULL);
  3122. iwl_uninit_drv(priv);
  3123. iwl_free_isr_ict(priv);
  3124. if (priv->ibss_beacon)
  3125. dev_kfree_skb(priv->ibss_beacon);
  3126. ieee80211_free_hw(priv->hw);
  3127. }
  3128. /*****************************************************************************
  3129. *
  3130. * driver and module entry point
  3131. *
  3132. *****************************************************************************/
  3133. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3134. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3135. #ifdef CONFIG_IWL4965
  3136. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3137. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3138. #endif /* CONFIG_IWL4965 */
  3139. #ifdef CONFIG_IWL5000
  3140. /* 5100 Series WiFi */
  3141. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3142. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3143. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3144. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3145. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3146. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3147. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3148. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3149. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3150. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3151. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3152. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3153. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3154. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3155. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3156. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3157. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3158. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3159. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3160. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3161. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3162. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3163. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3164. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3165. /* 5300 Series WiFi */
  3166. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3167. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3168. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3169. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3170. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3171. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3172. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3173. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3174. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3175. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3176. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3177. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3178. /* 5350 Series WiFi/WiMax */
  3179. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3180. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3181. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3182. /* 5150 Series Wifi/WiMax */
  3183. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3184. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3185. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3186. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3187. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3188. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3189. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3190. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3191. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3192. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3193. /* 6x00 Series */
  3194. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3195. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3196. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3197. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3198. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3199. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3200. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3201. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3202. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3203. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3204. /* 6x50 WiFi/WiMax Series */
  3205. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3206. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3207. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3208. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3209. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3210. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3211. /* 1000 Series WiFi */
  3212. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3213. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3214. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3215. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3216. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3217. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3218. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3219. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3220. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3221. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3222. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3223. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3224. #endif /* CONFIG_IWL5000 */
  3225. {0}
  3226. };
  3227. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3228. static struct pci_driver iwl_driver = {
  3229. .name = DRV_NAME,
  3230. .id_table = iwl_hw_card_ids,
  3231. .probe = iwl_pci_probe,
  3232. .remove = __devexit_p(iwl_pci_remove),
  3233. #ifdef CONFIG_PM
  3234. .suspend = iwl_pci_suspend,
  3235. .resume = iwl_pci_resume,
  3236. #endif
  3237. };
  3238. static int __init iwl_init(void)
  3239. {
  3240. int ret;
  3241. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3242. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3243. ret = iwlagn_rate_control_register();
  3244. if (ret) {
  3245. printk(KERN_ERR DRV_NAME
  3246. "Unable to register rate control algorithm: %d\n", ret);
  3247. return ret;
  3248. }
  3249. ret = pci_register_driver(&iwl_driver);
  3250. if (ret) {
  3251. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3252. goto error_register;
  3253. }
  3254. return ret;
  3255. error_register:
  3256. iwlagn_rate_control_unregister();
  3257. return ret;
  3258. }
  3259. static void __exit iwl_exit(void)
  3260. {
  3261. pci_unregister_driver(&iwl_driver);
  3262. iwlagn_rate_control_unregister();
  3263. }
  3264. module_exit(iwl_exit);
  3265. module_init(iwl_init);
  3266. #ifdef CONFIG_IWLWIFI_DEBUG
  3267. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3268. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3269. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3270. MODULE_PARM_DESC(debug, "debug output mask");
  3271. #endif