ahci.c 46 KB

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  1. /*
  2. * ahci.c - AHCI SATA support
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2004-2005 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * AHCI hardware documentation:
  30. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/pci.h>
  37. #include <linux/init.h>
  38. #include <linux/blkdev.h>
  39. #include <linux/delay.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/device.h>
  43. #include <scsi/scsi_host.h>
  44. #include <scsi/scsi_cmnd.h>
  45. #include <linux/libata.h>
  46. #define DRV_NAME "ahci"
  47. #define DRV_VERSION "2.1"
  48. enum {
  49. AHCI_PCI_BAR = 5,
  50. AHCI_MAX_PORTS = 32,
  51. AHCI_MAX_SG = 168, /* hardware max is 64K */
  52. AHCI_DMA_BOUNDARY = 0xffffffff,
  53. AHCI_USE_CLUSTERING = 0,
  54. AHCI_MAX_CMDS = 32,
  55. AHCI_CMD_SZ = 32,
  56. AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
  57. AHCI_RX_FIS_SZ = 256,
  58. AHCI_CMD_TBL_CDB = 0x40,
  59. AHCI_CMD_TBL_HDR_SZ = 0x80,
  60. AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
  61. AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
  62. AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
  63. AHCI_RX_FIS_SZ,
  64. AHCI_IRQ_ON_SG = (1 << 31),
  65. AHCI_CMD_ATAPI = (1 << 5),
  66. AHCI_CMD_WRITE = (1 << 6),
  67. AHCI_CMD_PREFETCH = (1 << 7),
  68. AHCI_CMD_RESET = (1 << 8),
  69. AHCI_CMD_CLR_BUSY = (1 << 10),
  70. RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
  71. RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
  72. RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
  73. board_ahci = 0,
  74. board_ahci_pi = 1,
  75. board_ahci_vt8251 = 2,
  76. board_ahci_ign_iferr = 3,
  77. /* global controller registers */
  78. HOST_CAP = 0x00, /* host capabilities */
  79. HOST_CTL = 0x04, /* global host control */
  80. HOST_IRQ_STAT = 0x08, /* interrupt status */
  81. HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
  82. HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
  83. /* HOST_CTL bits */
  84. HOST_RESET = (1 << 0), /* reset controller; self-clear */
  85. HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
  86. HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
  87. /* HOST_CAP bits */
  88. HOST_CAP_SSC = (1 << 14), /* Slumber capable */
  89. HOST_CAP_CLO = (1 << 24), /* Command List Override support */
  90. HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
  91. HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
  92. HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
  93. /* registers for each SATA port */
  94. PORT_LST_ADDR = 0x00, /* command list DMA addr */
  95. PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
  96. PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
  97. PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
  98. PORT_IRQ_STAT = 0x10, /* interrupt status */
  99. PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
  100. PORT_CMD = 0x18, /* port command */
  101. PORT_TFDATA = 0x20, /* taskfile data */
  102. PORT_SIG = 0x24, /* device TF signature */
  103. PORT_CMD_ISSUE = 0x38, /* command issue */
  104. PORT_SCR = 0x28, /* SATA phy register block */
  105. PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
  106. PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
  107. PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
  108. PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
  109. /* PORT_IRQ_{STAT,MASK} bits */
  110. PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
  111. PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
  112. PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
  113. PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
  114. PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
  115. PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
  116. PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
  117. PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
  118. PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
  119. PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
  120. PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
  121. PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
  122. PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
  123. PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
  124. PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
  125. PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
  126. PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
  127. PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
  128. PORT_IRQ_IF_ERR |
  129. PORT_IRQ_CONNECT |
  130. PORT_IRQ_PHYRDY |
  131. PORT_IRQ_UNK_FIS,
  132. PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
  133. PORT_IRQ_TF_ERR |
  134. PORT_IRQ_HBUS_DATA_ERR,
  135. DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
  136. PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
  137. PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
  138. /* PORT_CMD bits */
  139. PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
  140. PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
  141. PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
  142. PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
  143. PORT_CMD_CLO = (1 << 3), /* Command list override */
  144. PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
  145. PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
  146. PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
  147. PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
  148. PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
  149. PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
  150. PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
  151. /* ap->flags bits */
  152. AHCI_FLAG_NO_NCQ = (1 << 24),
  153. AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
  154. AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
  155. };
  156. struct ahci_cmd_hdr {
  157. u32 opts;
  158. u32 status;
  159. u32 tbl_addr;
  160. u32 tbl_addr_hi;
  161. u32 reserved[4];
  162. };
  163. struct ahci_sg {
  164. u32 addr;
  165. u32 addr_hi;
  166. u32 reserved;
  167. u32 flags_size;
  168. };
  169. struct ahci_host_priv {
  170. u32 cap; /* cache of HOST_CAP register */
  171. u32 port_map; /* cache of HOST_PORTS_IMPL reg */
  172. };
  173. struct ahci_port_priv {
  174. struct ahci_cmd_hdr *cmd_slot;
  175. dma_addr_t cmd_slot_dma;
  176. void *cmd_tbl;
  177. dma_addr_t cmd_tbl_dma;
  178. void *rx_fis;
  179. dma_addr_t rx_fis_dma;
  180. /* for NCQ spurious interrupt analysis */
  181. unsigned int ncq_saw_d2h:1;
  182. unsigned int ncq_saw_dmas:1;
  183. unsigned int ncq_saw_sdb:1;
  184. };
  185. static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
  186. static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  187. static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  188. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
  189. static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
  190. static void ahci_irq_clear(struct ata_port *ap);
  191. static int ahci_port_start(struct ata_port *ap);
  192. static void ahci_port_stop(struct ata_port *ap);
  193. static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
  194. static void ahci_qc_prep(struct ata_queued_cmd *qc);
  195. static u8 ahci_check_status(struct ata_port *ap);
  196. static void ahci_freeze(struct ata_port *ap);
  197. static void ahci_thaw(struct ata_port *ap);
  198. static void ahci_error_handler(struct ata_port *ap);
  199. static void ahci_vt8251_error_handler(struct ata_port *ap);
  200. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
  201. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
  202. static int ahci_port_resume(struct ata_port *ap);
  203. static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  204. static int ahci_pci_device_resume(struct pci_dev *pdev);
  205. static struct scsi_host_template ahci_sht = {
  206. .module = THIS_MODULE,
  207. .name = DRV_NAME,
  208. .ioctl = ata_scsi_ioctl,
  209. .queuecommand = ata_scsi_queuecmd,
  210. .change_queue_depth = ata_scsi_change_queue_depth,
  211. .can_queue = AHCI_MAX_CMDS - 1,
  212. .this_id = ATA_SHT_THIS_ID,
  213. .sg_tablesize = AHCI_MAX_SG,
  214. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  215. .emulated = ATA_SHT_EMULATED,
  216. .use_clustering = AHCI_USE_CLUSTERING,
  217. .proc_name = DRV_NAME,
  218. .dma_boundary = AHCI_DMA_BOUNDARY,
  219. .slave_configure = ata_scsi_slave_config,
  220. .slave_destroy = ata_scsi_slave_destroy,
  221. .bios_param = ata_std_bios_param,
  222. .suspend = ata_scsi_device_suspend,
  223. .resume = ata_scsi_device_resume,
  224. };
  225. static const struct ata_port_operations ahci_ops = {
  226. .port_disable = ata_port_disable,
  227. .check_status = ahci_check_status,
  228. .check_altstatus = ahci_check_status,
  229. .dev_select = ata_noop_dev_select,
  230. .tf_read = ahci_tf_read,
  231. .qc_prep = ahci_qc_prep,
  232. .qc_issue = ahci_qc_issue,
  233. .irq_handler = ahci_interrupt,
  234. .irq_clear = ahci_irq_clear,
  235. .irq_on = ata_dummy_irq_on,
  236. .irq_ack = ata_dummy_irq_ack,
  237. .scr_read = ahci_scr_read,
  238. .scr_write = ahci_scr_write,
  239. .freeze = ahci_freeze,
  240. .thaw = ahci_thaw,
  241. .error_handler = ahci_error_handler,
  242. .post_internal_cmd = ahci_post_internal_cmd,
  243. .port_suspend = ahci_port_suspend,
  244. .port_resume = ahci_port_resume,
  245. .port_start = ahci_port_start,
  246. .port_stop = ahci_port_stop,
  247. };
  248. static const struct ata_port_operations ahci_vt8251_ops = {
  249. .port_disable = ata_port_disable,
  250. .check_status = ahci_check_status,
  251. .check_altstatus = ahci_check_status,
  252. .dev_select = ata_noop_dev_select,
  253. .tf_read = ahci_tf_read,
  254. .qc_prep = ahci_qc_prep,
  255. .qc_issue = ahci_qc_issue,
  256. .irq_handler = ahci_interrupt,
  257. .irq_clear = ahci_irq_clear,
  258. .irq_on = ata_dummy_irq_on,
  259. .irq_ack = ata_dummy_irq_ack,
  260. .scr_read = ahci_scr_read,
  261. .scr_write = ahci_scr_write,
  262. .freeze = ahci_freeze,
  263. .thaw = ahci_thaw,
  264. .error_handler = ahci_vt8251_error_handler,
  265. .post_internal_cmd = ahci_post_internal_cmd,
  266. .port_suspend = ahci_port_suspend,
  267. .port_resume = ahci_port_resume,
  268. .port_start = ahci_port_start,
  269. .port_stop = ahci_port_stop,
  270. };
  271. static const struct ata_port_info ahci_port_info[] = {
  272. /* board_ahci */
  273. {
  274. .sht = &ahci_sht,
  275. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  276. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  277. ATA_FLAG_SKIP_D2H_BSY,
  278. .pio_mask = 0x1f, /* pio0-4 */
  279. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  280. .port_ops = &ahci_ops,
  281. },
  282. /* board_ahci_pi */
  283. {
  284. .sht = &ahci_sht,
  285. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  286. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  287. ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
  288. .pio_mask = 0x1f, /* pio0-4 */
  289. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  290. .port_ops = &ahci_ops,
  291. },
  292. /* board_ahci_vt8251 */
  293. {
  294. .sht = &ahci_sht,
  295. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  296. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  297. ATA_FLAG_SKIP_D2H_BSY |
  298. ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
  299. .pio_mask = 0x1f, /* pio0-4 */
  300. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  301. .port_ops = &ahci_vt8251_ops,
  302. },
  303. /* board_ahci_ign_iferr */
  304. {
  305. .sht = &ahci_sht,
  306. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  307. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  308. ATA_FLAG_SKIP_D2H_BSY |
  309. AHCI_FLAG_IGN_IRQ_IF_ERR,
  310. .pio_mask = 0x1f, /* pio0-4 */
  311. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  312. .port_ops = &ahci_ops,
  313. },
  314. };
  315. static const struct pci_device_id ahci_pci_tbl[] = {
  316. /* Intel */
  317. { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
  318. { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
  319. { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
  320. { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
  321. { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
  322. { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
  323. { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
  324. { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
  325. { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
  326. { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
  327. { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
  328. { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
  329. { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
  330. { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
  331. { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
  332. { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
  333. { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
  334. { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
  335. { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
  336. { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
  337. { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
  338. { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
  339. { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
  340. { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
  341. { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
  342. { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
  343. /* JMicron 360/1/3/5/6, match class to avoid IDE function */
  344. { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  345. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
  346. /* ATI */
  347. { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
  348. { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
  349. /* VIA */
  350. { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
  351. /* NVIDIA */
  352. { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
  353. { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
  354. { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
  355. { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
  356. { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
  357. { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
  358. { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
  359. { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
  360. { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
  361. { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
  362. { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
  363. { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
  364. { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
  365. { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
  366. { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
  367. { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
  368. { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
  369. { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
  370. { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
  371. { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
  372. /* SiS */
  373. { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
  374. { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
  375. { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
  376. /* Generic, PCI class code for AHCI */
  377. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  378. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
  379. { } /* terminate list */
  380. };
  381. static struct pci_driver ahci_pci_driver = {
  382. .name = DRV_NAME,
  383. .id_table = ahci_pci_tbl,
  384. .probe = ahci_init_one,
  385. .remove = ata_pci_remove_one,
  386. .suspend = ahci_pci_device_suspend,
  387. .resume = ahci_pci_device_resume,
  388. };
  389. static inline int ahci_nr_ports(u32 cap)
  390. {
  391. return (cap & 0x1f) + 1;
  392. }
  393. static inline void __iomem *ahci_port_base(void __iomem *base,
  394. unsigned int port)
  395. {
  396. return base + 0x100 + (port * 0x80);
  397. }
  398. static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
  399. {
  400. unsigned int sc_reg;
  401. switch (sc_reg_in) {
  402. case SCR_STATUS: sc_reg = 0; break;
  403. case SCR_CONTROL: sc_reg = 1; break;
  404. case SCR_ERROR: sc_reg = 2; break;
  405. case SCR_ACTIVE: sc_reg = 3; break;
  406. default:
  407. return 0xffffffffU;
  408. }
  409. return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
  410. }
  411. static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
  412. u32 val)
  413. {
  414. unsigned int sc_reg;
  415. switch (sc_reg_in) {
  416. case SCR_STATUS: sc_reg = 0; break;
  417. case SCR_CONTROL: sc_reg = 1; break;
  418. case SCR_ERROR: sc_reg = 2; break;
  419. case SCR_ACTIVE: sc_reg = 3; break;
  420. default:
  421. return;
  422. }
  423. writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
  424. }
  425. static void ahci_start_engine(void __iomem *port_mmio)
  426. {
  427. u32 tmp;
  428. /* start DMA */
  429. tmp = readl(port_mmio + PORT_CMD);
  430. tmp |= PORT_CMD_START;
  431. writel(tmp, port_mmio + PORT_CMD);
  432. readl(port_mmio + PORT_CMD); /* flush */
  433. }
  434. static int ahci_stop_engine(void __iomem *port_mmio)
  435. {
  436. u32 tmp;
  437. tmp = readl(port_mmio + PORT_CMD);
  438. /* check if the HBA is idle */
  439. if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
  440. return 0;
  441. /* setting HBA to idle */
  442. tmp &= ~PORT_CMD_START;
  443. writel(tmp, port_mmio + PORT_CMD);
  444. /* wait for engine to stop. This could be as long as 500 msec */
  445. tmp = ata_wait_register(port_mmio + PORT_CMD,
  446. PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
  447. if (tmp & PORT_CMD_LIST_ON)
  448. return -EIO;
  449. return 0;
  450. }
  451. static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
  452. dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
  453. {
  454. u32 tmp;
  455. /* set FIS registers */
  456. if (cap & HOST_CAP_64)
  457. writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
  458. writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
  459. if (cap & HOST_CAP_64)
  460. writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
  461. writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
  462. /* enable FIS reception */
  463. tmp = readl(port_mmio + PORT_CMD);
  464. tmp |= PORT_CMD_FIS_RX;
  465. writel(tmp, port_mmio + PORT_CMD);
  466. /* flush */
  467. readl(port_mmio + PORT_CMD);
  468. }
  469. static int ahci_stop_fis_rx(void __iomem *port_mmio)
  470. {
  471. u32 tmp;
  472. /* disable FIS reception */
  473. tmp = readl(port_mmio + PORT_CMD);
  474. tmp &= ~PORT_CMD_FIS_RX;
  475. writel(tmp, port_mmio + PORT_CMD);
  476. /* wait for completion, spec says 500ms, give it 1000 */
  477. tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
  478. PORT_CMD_FIS_ON, 10, 1000);
  479. if (tmp & PORT_CMD_FIS_ON)
  480. return -EBUSY;
  481. return 0;
  482. }
  483. static void ahci_power_up(void __iomem *port_mmio, u32 cap)
  484. {
  485. u32 cmd;
  486. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  487. /* spin up device */
  488. if (cap & HOST_CAP_SSS) {
  489. cmd |= PORT_CMD_SPIN_UP;
  490. writel(cmd, port_mmio + PORT_CMD);
  491. }
  492. /* wake up link */
  493. writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
  494. }
  495. static void ahci_power_down(void __iomem *port_mmio, u32 cap)
  496. {
  497. u32 cmd, scontrol;
  498. if (!(cap & HOST_CAP_SSS))
  499. return;
  500. /* put device into listen mode, first set PxSCTL.DET to 0 */
  501. scontrol = readl(port_mmio + PORT_SCR_CTL);
  502. scontrol &= ~0xf;
  503. writel(scontrol, port_mmio + PORT_SCR_CTL);
  504. /* then set PxCMD.SUD to 0 */
  505. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  506. cmd &= ~PORT_CMD_SPIN_UP;
  507. writel(cmd, port_mmio + PORT_CMD);
  508. }
  509. static void ahci_init_port(void __iomem *port_mmio, u32 cap,
  510. dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
  511. {
  512. /* enable FIS reception */
  513. ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
  514. /* enable DMA */
  515. ahci_start_engine(port_mmio);
  516. }
  517. static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
  518. {
  519. int rc;
  520. /* disable DMA */
  521. rc = ahci_stop_engine(port_mmio);
  522. if (rc) {
  523. *emsg = "failed to stop engine";
  524. return rc;
  525. }
  526. /* disable FIS reception */
  527. rc = ahci_stop_fis_rx(port_mmio);
  528. if (rc) {
  529. *emsg = "failed stop FIS RX";
  530. return rc;
  531. }
  532. return 0;
  533. }
  534. static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
  535. {
  536. u32 cap_save, impl_save, tmp;
  537. cap_save = readl(mmio + HOST_CAP);
  538. impl_save = readl(mmio + HOST_PORTS_IMPL);
  539. /* global controller reset */
  540. tmp = readl(mmio + HOST_CTL);
  541. if ((tmp & HOST_RESET) == 0) {
  542. writel(tmp | HOST_RESET, mmio + HOST_CTL);
  543. readl(mmio + HOST_CTL); /* flush */
  544. }
  545. /* reset must complete within 1 second, or
  546. * the hardware should be considered fried.
  547. */
  548. ssleep(1);
  549. tmp = readl(mmio + HOST_CTL);
  550. if (tmp & HOST_RESET) {
  551. dev_printk(KERN_ERR, &pdev->dev,
  552. "controller reset failed (0x%x)\n", tmp);
  553. return -EIO;
  554. }
  555. /* turn on AHCI mode */
  556. writel(HOST_AHCI_EN, mmio + HOST_CTL);
  557. (void) readl(mmio + HOST_CTL); /* flush */
  558. /* These write-once registers are normally cleared on reset.
  559. * Restore BIOS values... which we HOPE were present before
  560. * reset.
  561. */
  562. if (!impl_save) {
  563. impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
  564. dev_printk(KERN_WARNING, &pdev->dev,
  565. "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
  566. }
  567. writel(cap_save, mmio + HOST_CAP);
  568. writel(impl_save, mmio + HOST_PORTS_IMPL);
  569. (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
  570. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  571. u16 tmp16;
  572. /* configure PCS */
  573. pci_read_config_word(pdev, 0x92, &tmp16);
  574. tmp16 |= 0xf;
  575. pci_write_config_word(pdev, 0x92, tmp16);
  576. }
  577. return 0;
  578. }
  579. static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
  580. int n_ports, unsigned int port_flags,
  581. struct ahci_host_priv *hpriv)
  582. {
  583. int i, rc;
  584. u32 tmp;
  585. for (i = 0; i < n_ports; i++) {
  586. void __iomem *port_mmio = ahci_port_base(mmio, i);
  587. const char *emsg = NULL;
  588. if ((port_flags & AHCI_FLAG_HONOR_PI) &&
  589. !(hpriv->port_map & (1 << i)))
  590. continue;
  591. /* make sure port is not active */
  592. rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
  593. if (rc)
  594. dev_printk(KERN_WARNING, &pdev->dev,
  595. "%s (%d)\n", emsg, rc);
  596. /* clear SError */
  597. tmp = readl(port_mmio + PORT_SCR_ERR);
  598. VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
  599. writel(tmp, port_mmio + PORT_SCR_ERR);
  600. /* clear port IRQ */
  601. tmp = readl(port_mmio + PORT_IRQ_STAT);
  602. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  603. if (tmp)
  604. writel(tmp, port_mmio + PORT_IRQ_STAT);
  605. writel(1 << i, mmio + HOST_IRQ_STAT);
  606. }
  607. tmp = readl(mmio + HOST_CTL);
  608. VPRINTK("HOST_CTL 0x%x\n", tmp);
  609. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  610. tmp = readl(mmio + HOST_CTL);
  611. VPRINTK("HOST_CTL 0x%x\n", tmp);
  612. }
  613. static unsigned int ahci_dev_classify(struct ata_port *ap)
  614. {
  615. void __iomem *port_mmio = ap->ioaddr.cmd_addr;
  616. struct ata_taskfile tf;
  617. u32 tmp;
  618. tmp = readl(port_mmio + PORT_SIG);
  619. tf.lbah = (tmp >> 24) & 0xff;
  620. tf.lbam = (tmp >> 16) & 0xff;
  621. tf.lbal = (tmp >> 8) & 0xff;
  622. tf.nsect = (tmp) & 0xff;
  623. return ata_dev_classify(&tf);
  624. }
  625. static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  626. u32 opts)
  627. {
  628. dma_addr_t cmd_tbl_dma;
  629. cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
  630. pp->cmd_slot[tag].opts = cpu_to_le32(opts);
  631. pp->cmd_slot[tag].status = 0;
  632. pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
  633. pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
  634. }
  635. static int ahci_clo(struct ata_port *ap)
  636. {
  637. void __iomem *port_mmio = ap->ioaddr.cmd_addr;
  638. struct ahci_host_priv *hpriv = ap->host->private_data;
  639. u32 tmp;
  640. if (!(hpriv->cap & HOST_CAP_CLO))
  641. return -EOPNOTSUPP;
  642. tmp = readl(port_mmio + PORT_CMD);
  643. tmp |= PORT_CMD_CLO;
  644. writel(tmp, port_mmio + PORT_CMD);
  645. tmp = ata_wait_register(port_mmio + PORT_CMD,
  646. PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
  647. if (tmp & PORT_CMD_CLO)
  648. return -EIO;
  649. return 0;
  650. }
  651. static int ahci_softreset(struct ata_port *ap, unsigned int *class)
  652. {
  653. struct ahci_port_priv *pp = ap->private_data;
  654. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  655. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  656. const u32 cmd_fis_len = 5; /* five dwords */
  657. const char *reason = NULL;
  658. struct ata_taskfile tf;
  659. u32 tmp;
  660. u8 *fis;
  661. int rc;
  662. DPRINTK("ENTER\n");
  663. if (ata_port_offline(ap)) {
  664. DPRINTK("PHY reports no device\n");
  665. *class = ATA_DEV_NONE;
  666. return 0;
  667. }
  668. /* prepare for SRST (AHCI-1.1 10.4.1) */
  669. rc = ahci_stop_engine(port_mmio);
  670. if (rc) {
  671. reason = "failed to stop engine";
  672. goto fail_restart;
  673. }
  674. /* check BUSY/DRQ, perform Command List Override if necessary */
  675. if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
  676. rc = ahci_clo(ap);
  677. if (rc == -EOPNOTSUPP) {
  678. reason = "port busy but CLO unavailable";
  679. goto fail_restart;
  680. } else if (rc) {
  681. reason = "port busy but CLO failed";
  682. goto fail_restart;
  683. }
  684. }
  685. /* restart engine */
  686. ahci_start_engine(port_mmio);
  687. ata_tf_init(ap->device, &tf);
  688. fis = pp->cmd_tbl;
  689. /* issue the first D2H Register FIS */
  690. ahci_fill_cmd_slot(pp, 0,
  691. cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
  692. tf.ctl |= ATA_SRST;
  693. ata_tf_to_fis(&tf, fis, 0);
  694. fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
  695. writel(1, port_mmio + PORT_CMD_ISSUE);
  696. tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
  697. if (tmp & 0x1) {
  698. rc = -EIO;
  699. reason = "1st FIS failed";
  700. goto fail;
  701. }
  702. /* spec says at least 5us, but be generous and sleep for 1ms */
  703. msleep(1);
  704. /* issue the second D2H Register FIS */
  705. ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
  706. tf.ctl &= ~ATA_SRST;
  707. ata_tf_to_fis(&tf, fis, 0);
  708. fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
  709. writel(1, port_mmio + PORT_CMD_ISSUE);
  710. readl(port_mmio + PORT_CMD_ISSUE); /* flush */
  711. /* spec mandates ">= 2ms" before checking status.
  712. * We wait 150ms, because that was the magic delay used for
  713. * ATAPI devices in Hale Landis's ATADRVR, for the period of time
  714. * between when the ATA command register is written, and then
  715. * status is checked. Because waiting for "a while" before
  716. * checking status is fine, post SRST, we perform this magic
  717. * delay here as well.
  718. */
  719. msleep(150);
  720. *class = ATA_DEV_NONE;
  721. if (ata_port_online(ap)) {
  722. if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
  723. rc = -EIO;
  724. reason = "device not ready";
  725. goto fail;
  726. }
  727. *class = ahci_dev_classify(ap);
  728. }
  729. DPRINTK("EXIT, class=%u\n", *class);
  730. return 0;
  731. fail_restart:
  732. ahci_start_engine(port_mmio);
  733. fail:
  734. ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
  735. return rc;
  736. }
  737. static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
  738. {
  739. struct ahci_port_priv *pp = ap->private_data;
  740. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  741. struct ata_taskfile tf;
  742. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  743. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  744. int rc;
  745. DPRINTK("ENTER\n");
  746. ahci_stop_engine(port_mmio);
  747. /* clear D2H reception area to properly wait for D2H FIS */
  748. ata_tf_init(ap->device, &tf);
  749. tf.command = 0x80;
  750. ata_tf_to_fis(&tf, d2h_fis, 0);
  751. rc = sata_std_hardreset(ap, class);
  752. ahci_start_engine(port_mmio);
  753. if (rc == 0 && ata_port_online(ap))
  754. *class = ahci_dev_classify(ap);
  755. if (*class == ATA_DEV_UNKNOWN)
  756. *class = ATA_DEV_NONE;
  757. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  758. return rc;
  759. }
  760. static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
  761. {
  762. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  763. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  764. int rc;
  765. DPRINTK("ENTER\n");
  766. ahci_stop_engine(port_mmio);
  767. rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
  768. /* vt8251 needs SError cleared for the port to operate */
  769. ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
  770. ahci_start_engine(port_mmio);
  771. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  772. /* vt8251 doesn't clear BSY on signature FIS reception,
  773. * request follow-up softreset.
  774. */
  775. return rc ?: -EAGAIN;
  776. }
  777. static void ahci_postreset(struct ata_port *ap, unsigned int *class)
  778. {
  779. void __iomem *port_mmio = ap->ioaddr.cmd_addr;
  780. u32 new_tmp, tmp;
  781. ata_std_postreset(ap, class);
  782. /* Make sure port's ATAPI bit is set appropriately */
  783. new_tmp = tmp = readl(port_mmio + PORT_CMD);
  784. if (*class == ATA_DEV_ATAPI)
  785. new_tmp |= PORT_CMD_ATAPI;
  786. else
  787. new_tmp &= ~PORT_CMD_ATAPI;
  788. if (new_tmp != tmp) {
  789. writel(new_tmp, port_mmio + PORT_CMD);
  790. readl(port_mmio + PORT_CMD); /* flush */
  791. }
  792. }
  793. static u8 ahci_check_status(struct ata_port *ap)
  794. {
  795. void __iomem *mmio = ap->ioaddr.cmd_addr;
  796. return readl(mmio + PORT_TFDATA) & 0xFF;
  797. }
  798. static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  799. {
  800. struct ahci_port_priv *pp = ap->private_data;
  801. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  802. ata_tf_from_fis(d2h_fis, tf);
  803. }
  804. static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
  805. {
  806. struct scatterlist *sg;
  807. struct ahci_sg *ahci_sg;
  808. unsigned int n_sg = 0;
  809. VPRINTK("ENTER\n");
  810. /*
  811. * Next, the S/G list.
  812. */
  813. ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
  814. ata_for_each_sg(sg, qc) {
  815. dma_addr_t addr = sg_dma_address(sg);
  816. u32 sg_len = sg_dma_len(sg);
  817. ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
  818. ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
  819. ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
  820. ahci_sg++;
  821. n_sg++;
  822. }
  823. return n_sg;
  824. }
  825. static void ahci_qc_prep(struct ata_queued_cmd *qc)
  826. {
  827. struct ata_port *ap = qc->ap;
  828. struct ahci_port_priv *pp = ap->private_data;
  829. int is_atapi = is_atapi_taskfile(&qc->tf);
  830. void *cmd_tbl;
  831. u32 opts;
  832. const u32 cmd_fis_len = 5; /* five dwords */
  833. unsigned int n_elem;
  834. /*
  835. * Fill in command table information. First, the header,
  836. * a SATA Register - Host to Device command FIS.
  837. */
  838. cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
  839. ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
  840. if (is_atapi) {
  841. memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
  842. memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
  843. }
  844. n_elem = 0;
  845. if (qc->flags & ATA_QCFLAG_DMAMAP)
  846. n_elem = ahci_fill_sg(qc, cmd_tbl);
  847. /*
  848. * Fill in command slot information.
  849. */
  850. opts = cmd_fis_len | n_elem << 16;
  851. if (qc->tf.flags & ATA_TFLAG_WRITE)
  852. opts |= AHCI_CMD_WRITE;
  853. if (is_atapi)
  854. opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
  855. ahci_fill_cmd_slot(pp, qc->tag, opts);
  856. }
  857. static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
  858. {
  859. struct ahci_port_priv *pp = ap->private_data;
  860. struct ata_eh_info *ehi = &ap->eh_info;
  861. unsigned int err_mask = 0, action = 0;
  862. struct ata_queued_cmd *qc;
  863. u32 serror;
  864. ata_ehi_clear_desc(ehi);
  865. /* AHCI needs SError cleared; otherwise, it might lock up */
  866. serror = ahci_scr_read(ap, SCR_ERROR);
  867. ahci_scr_write(ap, SCR_ERROR, serror);
  868. /* analyze @irq_stat */
  869. ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
  870. /* some controllers set IRQ_IF_ERR on device errors, ignore it */
  871. if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
  872. irq_stat &= ~PORT_IRQ_IF_ERR;
  873. if (irq_stat & PORT_IRQ_TF_ERR)
  874. err_mask |= AC_ERR_DEV;
  875. if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
  876. err_mask |= AC_ERR_HOST_BUS;
  877. action |= ATA_EH_SOFTRESET;
  878. }
  879. if (irq_stat & PORT_IRQ_IF_ERR) {
  880. err_mask |= AC_ERR_ATA_BUS;
  881. action |= ATA_EH_SOFTRESET;
  882. ata_ehi_push_desc(ehi, ", interface fatal error");
  883. }
  884. if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
  885. ata_ehi_hotplugged(ehi);
  886. ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
  887. "connection status changed" : "PHY RDY changed");
  888. }
  889. if (irq_stat & PORT_IRQ_UNK_FIS) {
  890. u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
  891. err_mask |= AC_ERR_HSM;
  892. action |= ATA_EH_SOFTRESET;
  893. ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
  894. unk[0], unk[1], unk[2], unk[3]);
  895. }
  896. /* okay, let's hand over to EH */
  897. ehi->serror |= serror;
  898. ehi->action |= action;
  899. qc = ata_qc_from_tag(ap, ap->active_tag);
  900. if (qc)
  901. qc->err_mask |= err_mask;
  902. else
  903. ehi->err_mask |= err_mask;
  904. if (irq_stat & PORT_IRQ_FREEZE)
  905. ata_port_freeze(ap);
  906. else
  907. ata_port_abort(ap);
  908. }
  909. static void ahci_host_intr(struct ata_port *ap)
  910. {
  911. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  912. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  913. struct ata_eh_info *ehi = &ap->eh_info;
  914. struct ahci_port_priv *pp = ap->private_data;
  915. u32 status, qc_active;
  916. int rc, known_irq = 0;
  917. status = readl(port_mmio + PORT_IRQ_STAT);
  918. writel(status, port_mmio + PORT_IRQ_STAT);
  919. if (unlikely(status & PORT_IRQ_ERROR)) {
  920. ahci_error_intr(ap, status);
  921. return;
  922. }
  923. if (ap->sactive)
  924. qc_active = readl(port_mmio + PORT_SCR_ACT);
  925. else
  926. qc_active = readl(port_mmio + PORT_CMD_ISSUE);
  927. rc = ata_qc_complete_multiple(ap, qc_active, NULL);
  928. if (rc > 0)
  929. return;
  930. if (rc < 0) {
  931. ehi->err_mask |= AC_ERR_HSM;
  932. ehi->action |= ATA_EH_SOFTRESET;
  933. ata_port_freeze(ap);
  934. return;
  935. }
  936. /* hmmm... a spurious interupt */
  937. /* if !NCQ, ignore. No modern ATA device has broken HSM
  938. * implementation for non-NCQ commands.
  939. */
  940. if (!ap->sactive)
  941. return;
  942. if (status & PORT_IRQ_D2H_REG_FIS) {
  943. if (!pp->ncq_saw_d2h)
  944. ata_port_printk(ap, KERN_INFO,
  945. "D2H reg with I during NCQ, "
  946. "this message won't be printed again\n");
  947. pp->ncq_saw_d2h = 1;
  948. known_irq = 1;
  949. }
  950. if (status & PORT_IRQ_DMAS_FIS) {
  951. if (!pp->ncq_saw_dmas)
  952. ata_port_printk(ap, KERN_INFO,
  953. "DMAS FIS during NCQ, "
  954. "this message won't be printed again\n");
  955. pp->ncq_saw_dmas = 1;
  956. known_irq = 1;
  957. }
  958. if (status & PORT_IRQ_SDB_FIS) {
  959. const __le32 *f = pp->rx_fis + RX_FIS_SDB;
  960. if (le32_to_cpu(f[1])) {
  961. /* SDB FIS containing spurious completions
  962. * might be dangerous, whine and fail commands
  963. * with HSM violation. EH will turn off NCQ
  964. * after several such failures.
  965. */
  966. ata_ehi_push_desc(ehi,
  967. "spurious completions during NCQ "
  968. "issue=0x%x SAct=0x%x FIS=%08x:%08x",
  969. readl(port_mmio + PORT_CMD_ISSUE),
  970. readl(port_mmio + PORT_SCR_ACT),
  971. le32_to_cpu(f[0]), le32_to_cpu(f[1]));
  972. ehi->err_mask |= AC_ERR_HSM;
  973. ehi->action |= ATA_EH_SOFTRESET;
  974. ata_port_freeze(ap);
  975. } else {
  976. if (!pp->ncq_saw_sdb)
  977. ata_port_printk(ap, KERN_INFO,
  978. "spurious SDB FIS %08x:%08x during NCQ, "
  979. "this message won't be printed again\n",
  980. le32_to_cpu(f[0]), le32_to_cpu(f[1]));
  981. pp->ncq_saw_sdb = 1;
  982. }
  983. known_irq = 1;
  984. }
  985. if (!known_irq)
  986. ata_port_printk(ap, KERN_INFO, "spurious interrupt "
  987. "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
  988. status, ap->active_tag, ap->sactive);
  989. }
  990. static void ahci_irq_clear(struct ata_port *ap)
  991. {
  992. /* TODO */
  993. }
  994. static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
  995. {
  996. struct ata_host *host = dev_instance;
  997. struct ahci_host_priv *hpriv;
  998. unsigned int i, handled = 0;
  999. void __iomem *mmio;
  1000. u32 irq_stat, irq_ack = 0;
  1001. VPRINTK("ENTER\n");
  1002. hpriv = host->private_data;
  1003. mmio = host->iomap[AHCI_PCI_BAR];
  1004. /* sigh. 0xffffffff is a valid return from h/w */
  1005. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1006. irq_stat &= hpriv->port_map;
  1007. if (!irq_stat)
  1008. return IRQ_NONE;
  1009. spin_lock(&host->lock);
  1010. for (i = 0; i < host->n_ports; i++) {
  1011. struct ata_port *ap;
  1012. if (!(irq_stat & (1 << i)))
  1013. continue;
  1014. ap = host->ports[i];
  1015. if (ap) {
  1016. ahci_host_intr(ap);
  1017. VPRINTK("port %u\n", i);
  1018. } else {
  1019. VPRINTK("port %u (no irq)\n", i);
  1020. if (ata_ratelimit())
  1021. dev_printk(KERN_WARNING, host->dev,
  1022. "interrupt on disabled port %u\n", i);
  1023. }
  1024. irq_ack |= (1 << i);
  1025. }
  1026. if (irq_ack) {
  1027. writel(irq_ack, mmio + HOST_IRQ_STAT);
  1028. handled = 1;
  1029. }
  1030. spin_unlock(&host->lock);
  1031. VPRINTK("EXIT\n");
  1032. return IRQ_RETVAL(handled);
  1033. }
  1034. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
  1035. {
  1036. struct ata_port *ap = qc->ap;
  1037. void __iomem *port_mmio = ap->ioaddr.cmd_addr;
  1038. if (qc->tf.protocol == ATA_PROT_NCQ)
  1039. writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
  1040. writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
  1041. readl(port_mmio + PORT_CMD_ISSUE); /* flush */
  1042. return 0;
  1043. }
  1044. static void ahci_freeze(struct ata_port *ap)
  1045. {
  1046. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1047. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1048. /* turn IRQ off */
  1049. writel(0, port_mmio + PORT_IRQ_MASK);
  1050. }
  1051. static void ahci_thaw(struct ata_port *ap)
  1052. {
  1053. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1054. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1055. u32 tmp;
  1056. /* clear IRQ */
  1057. tmp = readl(port_mmio + PORT_IRQ_STAT);
  1058. writel(tmp, port_mmio + PORT_IRQ_STAT);
  1059. writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
  1060. /* turn IRQ back on */
  1061. writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
  1062. }
  1063. static void ahci_error_handler(struct ata_port *ap)
  1064. {
  1065. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1066. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1067. if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
  1068. /* restart engine */
  1069. ahci_stop_engine(port_mmio);
  1070. ahci_start_engine(port_mmio);
  1071. }
  1072. /* perform recovery */
  1073. ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
  1074. ahci_postreset);
  1075. }
  1076. static void ahci_vt8251_error_handler(struct ata_port *ap)
  1077. {
  1078. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1079. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1080. if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
  1081. /* restart engine */
  1082. ahci_stop_engine(port_mmio);
  1083. ahci_start_engine(port_mmio);
  1084. }
  1085. /* perform recovery */
  1086. ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
  1087. ahci_postreset);
  1088. }
  1089. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
  1090. {
  1091. struct ata_port *ap = qc->ap;
  1092. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1093. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1094. if (qc->flags & ATA_QCFLAG_FAILED)
  1095. qc->err_mask |= AC_ERR_OTHER;
  1096. if (qc->err_mask) {
  1097. /* make DMA engine forget about the failed command */
  1098. ahci_stop_engine(port_mmio);
  1099. ahci_start_engine(port_mmio);
  1100. }
  1101. }
  1102. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
  1103. {
  1104. struct ahci_host_priv *hpriv = ap->host->private_data;
  1105. struct ahci_port_priv *pp = ap->private_data;
  1106. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1107. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1108. const char *emsg = NULL;
  1109. int rc;
  1110. rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
  1111. if (rc == 0)
  1112. ahci_power_down(port_mmio, hpriv->cap);
  1113. else {
  1114. ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
  1115. ahci_init_port(port_mmio, hpriv->cap,
  1116. pp->cmd_slot_dma, pp->rx_fis_dma);
  1117. }
  1118. return rc;
  1119. }
  1120. static int ahci_port_resume(struct ata_port *ap)
  1121. {
  1122. struct ahci_port_priv *pp = ap->private_data;
  1123. struct ahci_host_priv *hpriv = ap->host->private_data;
  1124. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1125. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1126. ahci_power_up(port_mmio, hpriv->cap);
  1127. ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
  1128. return 0;
  1129. }
  1130. static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
  1131. {
  1132. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  1133. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1134. u32 ctl;
  1135. if (mesg.event == PM_EVENT_SUSPEND) {
  1136. /* AHCI spec rev1.1 section 8.3.3:
  1137. * Software must disable interrupts prior to requesting a
  1138. * transition of the HBA to D3 state.
  1139. */
  1140. ctl = readl(mmio + HOST_CTL);
  1141. ctl &= ~HOST_IRQ_EN;
  1142. writel(ctl, mmio + HOST_CTL);
  1143. readl(mmio + HOST_CTL); /* flush */
  1144. }
  1145. return ata_pci_device_suspend(pdev, mesg);
  1146. }
  1147. static int ahci_pci_device_resume(struct pci_dev *pdev)
  1148. {
  1149. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  1150. struct ahci_host_priv *hpriv = host->private_data;
  1151. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1152. int rc;
  1153. rc = ata_pci_device_do_resume(pdev);
  1154. if (rc)
  1155. return rc;
  1156. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
  1157. rc = ahci_reset_controller(mmio, pdev);
  1158. if (rc)
  1159. return rc;
  1160. ahci_init_controller(mmio, pdev, host->n_ports,
  1161. host->ports[0]->flags, hpriv);
  1162. }
  1163. ata_host_resume(host);
  1164. return 0;
  1165. }
  1166. static int ahci_port_start(struct ata_port *ap)
  1167. {
  1168. struct device *dev = ap->host->dev;
  1169. struct ahci_host_priv *hpriv = ap->host->private_data;
  1170. struct ahci_port_priv *pp;
  1171. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1172. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1173. void *mem;
  1174. dma_addr_t mem_dma;
  1175. int rc;
  1176. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1177. if (!pp)
  1178. return -ENOMEM;
  1179. rc = ata_pad_alloc(ap, dev);
  1180. if (rc)
  1181. return rc;
  1182. mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
  1183. GFP_KERNEL);
  1184. if (!mem)
  1185. return -ENOMEM;
  1186. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  1187. /*
  1188. * First item in chunk of DMA memory: 32-slot command table,
  1189. * 32 bytes each in size
  1190. */
  1191. pp->cmd_slot = mem;
  1192. pp->cmd_slot_dma = mem_dma;
  1193. mem += AHCI_CMD_SLOT_SZ;
  1194. mem_dma += AHCI_CMD_SLOT_SZ;
  1195. /*
  1196. * Second item: Received-FIS area
  1197. */
  1198. pp->rx_fis = mem;
  1199. pp->rx_fis_dma = mem_dma;
  1200. mem += AHCI_RX_FIS_SZ;
  1201. mem_dma += AHCI_RX_FIS_SZ;
  1202. /*
  1203. * Third item: data area for storing a single command
  1204. * and its scatter-gather table
  1205. */
  1206. pp->cmd_tbl = mem;
  1207. pp->cmd_tbl_dma = mem_dma;
  1208. ap->private_data = pp;
  1209. /* power up port */
  1210. ahci_power_up(port_mmio, hpriv->cap);
  1211. /* initialize port */
  1212. ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
  1213. return 0;
  1214. }
  1215. static void ahci_port_stop(struct ata_port *ap)
  1216. {
  1217. struct ahci_host_priv *hpriv = ap->host->private_data;
  1218. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1219. void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
  1220. const char *emsg = NULL;
  1221. int rc;
  1222. /* de-initialize port */
  1223. rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
  1224. if (rc)
  1225. ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
  1226. }
  1227. static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
  1228. unsigned int port_idx)
  1229. {
  1230. VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
  1231. base = ahci_port_base(base, port_idx);
  1232. VPRINTK("base now==0x%lx\n", base);
  1233. port->cmd_addr = base;
  1234. port->scr_addr = base + PORT_SCR;
  1235. VPRINTK("EXIT\n");
  1236. }
  1237. static int ahci_host_init(struct ata_probe_ent *probe_ent)
  1238. {
  1239. struct ahci_host_priv *hpriv = probe_ent->private_data;
  1240. struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
  1241. void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
  1242. unsigned int i, cap_n_ports, using_dac;
  1243. int rc;
  1244. rc = ahci_reset_controller(mmio, pdev);
  1245. if (rc)
  1246. return rc;
  1247. hpriv->cap = readl(mmio + HOST_CAP);
  1248. hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
  1249. cap_n_ports = ahci_nr_ports(hpriv->cap);
  1250. VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
  1251. hpriv->cap, hpriv->port_map, cap_n_ports);
  1252. if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
  1253. unsigned int n_ports = cap_n_ports;
  1254. u32 port_map = hpriv->port_map;
  1255. int max_port = 0;
  1256. for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
  1257. if (port_map & (1 << i)) {
  1258. n_ports--;
  1259. port_map &= ~(1 << i);
  1260. max_port = i;
  1261. } else
  1262. probe_ent->dummy_port_mask |= 1 << i;
  1263. }
  1264. if (n_ports || port_map)
  1265. dev_printk(KERN_WARNING, &pdev->dev,
  1266. "nr_ports (%u) and implemented port map "
  1267. "(0x%x) don't match\n",
  1268. cap_n_ports, hpriv->port_map);
  1269. probe_ent->n_ports = max_port + 1;
  1270. } else
  1271. probe_ent->n_ports = cap_n_ports;
  1272. using_dac = hpriv->cap & HOST_CAP_64;
  1273. if (using_dac &&
  1274. !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  1275. rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  1276. if (rc) {
  1277. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1278. if (rc) {
  1279. dev_printk(KERN_ERR, &pdev->dev,
  1280. "64-bit DMA enable failed\n");
  1281. return rc;
  1282. }
  1283. }
  1284. } else {
  1285. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1286. if (rc) {
  1287. dev_printk(KERN_ERR, &pdev->dev,
  1288. "32-bit DMA enable failed\n");
  1289. return rc;
  1290. }
  1291. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1292. if (rc) {
  1293. dev_printk(KERN_ERR, &pdev->dev,
  1294. "32-bit consistent DMA enable failed\n");
  1295. return rc;
  1296. }
  1297. }
  1298. for (i = 0; i < probe_ent->n_ports; i++)
  1299. ahci_setup_port(&probe_ent->port[i], mmio, i);
  1300. ahci_init_controller(mmio, pdev, probe_ent->n_ports,
  1301. probe_ent->port_flags, hpriv);
  1302. pci_set_master(pdev);
  1303. return 0;
  1304. }
  1305. static void ahci_print_info(struct ata_probe_ent *probe_ent)
  1306. {
  1307. struct ahci_host_priv *hpriv = probe_ent->private_data;
  1308. struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
  1309. void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
  1310. u32 vers, cap, impl, speed;
  1311. const char *speed_s;
  1312. u16 cc;
  1313. const char *scc_s;
  1314. vers = readl(mmio + HOST_VERSION);
  1315. cap = hpriv->cap;
  1316. impl = hpriv->port_map;
  1317. speed = (cap >> 20) & 0xf;
  1318. if (speed == 1)
  1319. speed_s = "1.5";
  1320. else if (speed == 2)
  1321. speed_s = "3";
  1322. else
  1323. speed_s = "?";
  1324. pci_read_config_word(pdev, 0x0a, &cc);
  1325. if (cc == PCI_CLASS_STORAGE_IDE)
  1326. scc_s = "IDE";
  1327. else if (cc == PCI_CLASS_STORAGE_SATA)
  1328. scc_s = "SATA";
  1329. else if (cc == PCI_CLASS_STORAGE_RAID)
  1330. scc_s = "RAID";
  1331. else
  1332. scc_s = "unknown";
  1333. dev_printk(KERN_INFO, &pdev->dev,
  1334. "AHCI %02x%02x.%02x%02x "
  1335. "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
  1336. ,
  1337. (vers >> 24) & 0xff,
  1338. (vers >> 16) & 0xff,
  1339. (vers >> 8) & 0xff,
  1340. vers & 0xff,
  1341. ((cap >> 8) & 0x1f) + 1,
  1342. (cap & 0x1f) + 1,
  1343. speed_s,
  1344. impl,
  1345. scc_s);
  1346. dev_printk(KERN_INFO, &pdev->dev,
  1347. "flags: "
  1348. "%s%s%s%s%s%s"
  1349. "%s%s%s%s%s%s%s\n"
  1350. ,
  1351. cap & (1 << 31) ? "64bit " : "",
  1352. cap & (1 << 30) ? "ncq " : "",
  1353. cap & (1 << 28) ? "ilck " : "",
  1354. cap & (1 << 27) ? "stag " : "",
  1355. cap & (1 << 26) ? "pm " : "",
  1356. cap & (1 << 25) ? "led " : "",
  1357. cap & (1 << 24) ? "clo " : "",
  1358. cap & (1 << 19) ? "nz " : "",
  1359. cap & (1 << 18) ? "only " : "",
  1360. cap & (1 << 17) ? "pmp " : "",
  1361. cap & (1 << 15) ? "pio " : "",
  1362. cap & (1 << 14) ? "slum " : "",
  1363. cap & (1 << 13) ? "part " : ""
  1364. );
  1365. }
  1366. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1367. {
  1368. static int printed_version;
  1369. unsigned int board_idx = (unsigned int) ent->driver_data;
  1370. struct device *dev = &pdev->dev;
  1371. struct ata_probe_ent *probe_ent;
  1372. struct ahci_host_priv *hpriv;
  1373. int rc;
  1374. VPRINTK("ENTER\n");
  1375. WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
  1376. if (!printed_version++)
  1377. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  1378. rc = pcim_enable_device(pdev);
  1379. if (rc)
  1380. return rc;
  1381. rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
  1382. if (rc == -EBUSY)
  1383. pcim_pin_device(pdev);
  1384. if (rc)
  1385. return rc;
  1386. if (pci_enable_msi(pdev))
  1387. pci_intx(pdev, 1);
  1388. probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
  1389. if (probe_ent == NULL)
  1390. return -ENOMEM;
  1391. probe_ent->dev = pci_dev_to_dev(pdev);
  1392. INIT_LIST_HEAD(&probe_ent->node);
  1393. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  1394. if (!hpriv)
  1395. return -ENOMEM;
  1396. probe_ent->sht = ahci_port_info[board_idx].sht;
  1397. probe_ent->port_flags = ahci_port_info[board_idx].flags;
  1398. probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
  1399. probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
  1400. probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
  1401. probe_ent->irq = pdev->irq;
  1402. probe_ent->irq_flags = IRQF_SHARED;
  1403. probe_ent->iomap = pcim_iomap_table(pdev);
  1404. probe_ent->private_data = hpriv;
  1405. /* initialize adapter */
  1406. rc = ahci_host_init(probe_ent);
  1407. if (rc)
  1408. return rc;
  1409. if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
  1410. (hpriv->cap & HOST_CAP_NCQ))
  1411. probe_ent->port_flags |= ATA_FLAG_NCQ;
  1412. ahci_print_info(probe_ent);
  1413. if (!ata_device_add(probe_ent))
  1414. return -ENODEV;
  1415. devm_kfree(dev, probe_ent);
  1416. return 0;
  1417. }
  1418. static int __init ahci_init(void)
  1419. {
  1420. return pci_register_driver(&ahci_pci_driver);
  1421. }
  1422. static void __exit ahci_exit(void)
  1423. {
  1424. pci_unregister_driver(&ahci_pci_driver);
  1425. }
  1426. MODULE_AUTHOR("Jeff Garzik");
  1427. MODULE_DESCRIPTION("AHCI SATA low-level driver");
  1428. MODULE_LICENSE("GPL");
  1429. MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
  1430. MODULE_VERSION(DRV_VERSION);
  1431. module_init(ahci_init);
  1432. module_exit(ahci_exit);