pxa2xx-i2s.c 6.7 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * Revision history
  14. * 12th Aug 2005 Initial version.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/initval.h>
  23. #include <sound/soc.h>
  24. #include <asm/hardware.h>
  25. #include <asm/arch/pxa-regs.h>
  26. #include <asm/arch/audio.h>
  27. #include "pxa2xx-pcm.h"
  28. #include "pxa2xx-i2s.h"
  29. struct pxa_i2s_port {
  30. u32 sadiv;
  31. u32 sacr0;
  32. u32 sacr1;
  33. u32 saimr;
  34. int master;
  35. u32 fmt;
  36. };
  37. static struct pxa_i2s_port pxa_i2s;
  38. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  39. .name = "I2S PCM Stereo out",
  40. .dev_addr = __PREG(SADR),
  41. .drcmr = &DRCMRTXSADR,
  42. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  43. DCMD_BURST32 | DCMD_WIDTH4,
  44. };
  45. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  46. .name = "I2S PCM Stereo in",
  47. .dev_addr = __PREG(SADR),
  48. .drcmr = &DRCMRRXSADR,
  49. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  50. DCMD_BURST32 | DCMD_WIDTH4,
  51. };
  52. static struct pxa2xx_gpio gpio_bus[] = {
  53. { /* I2S SoC Slave */
  54. .rx = GPIO29_SDATA_IN_I2S_MD,
  55. .tx = GPIO30_SDATA_OUT_I2S_MD,
  56. .clk = GPIO28_BITCLK_IN_I2S_MD,
  57. .frm = GPIO31_SYNC_I2S_MD,
  58. },
  59. { /* I2S SoC Master */
  60. #ifdef CONFIG_PXA27x
  61. .sys = GPIO113_I2S_SYSCLK_MD,
  62. #else
  63. .sys = GPIO32_SYSCLK_I2S_MD,
  64. #endif
  65. .rx = GPIO29_SDATA_IN_I2S_MD,
  66. .tx = GPIO30_SDATA_OUT_I2S_MD,
  67. .clk = GPIO28_BITCLK_OUT_I2S_MD,
  68. .frm = GPIO31_SYNC_I2S_MD,
  69. },
  70. };
  71. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
  72. {
  73. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  74. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  75. if (!cpu_dai->active) {
  76. SACR0 |= SACR0_RST;
  77. SACR0 = 0;
  78. }
  79. return 0;
  80. }
  81. /* wait for I2S controller to be ready */
  82. static int pxa_i2s_wait(void)
  83. {
  84. int i;
  85. /* flush the Rx FIFO */
  86. for(i = 0; i < 16; i++)
  87. SADR;
  88. return 0;
  89. }
  90. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
  91. unsigned int fmt)
  92. {
  93. /* interface format */
  94. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  95. case SND_SOC_DAIFMT_I2S:
  96. pxa_i2s.fmt = 0;
  97. break;
  98. case SND_SOC_DAIFMT_LEFT_J:
  99. pxa_i2s.fmt = SACR1_AMSL;
  100. break;
  101. }
  102. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  103. case SND_SOC_DAIFMT_CBS_CFS:
  104. pxa_i2s.master = 1;
  105. break;
  106. case SND_SOC_DAIFMT_CBM_CFS:
  107. pxa_i2s.master = 0;
  108. break;
  109. default:
  110. break;
  111. }
  112. return 0;
  113. }
  114. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
  115. int clk_id, unsigned int freq, int dir)
  116. {
  117. if (clk_id != PXA2XX_I2S_SYSCLK)
  118. return -ENODEV;
  119. if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
  120. pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
  121. return 0;
  122. }
  123. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  124. struct snd_pcm_hw_params *params)
  125. {
  126. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  127. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  128. pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
  129. pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
  130. pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
  131. pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
  132. pxa_set_cken(CKEN_I2S, 1);
  133. pxa_i2s_wait();
  134. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  135. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
  136. else
  137. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
  138. /* is port used by another stream */
  139. if (!(SACR0 & SACR0_ENB)) {
  140. SACR0 = 0;
  141. SACR1 = 0;
  142. if (pxa_i2s.master)
  143. SACR0 |= SACR0_BCKD;
  144. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  145. SACR1 |= pxa_i2s.fmt;
  146. }
  147. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  148. SAIMR |= SAIMR_TFS;
  149. else
  150. SAIMR |= SAIMR_RFS;
  151. switch (params_rate(params)) {
  152. case 8000:
  153. SADIV = 0x48;
  154. break;
  155. case 11025:
  156. SADIV = 0x34;
  157. break;
  158. case 16000:
  159. SADIV = 0x24;
  160. break;
  161. case 22050:
  162. SADIV = 0x1a;
  163. break;
  164. case 44100:
  165. SADIV = 0xd;
  166. break;
  167. case 48000:
  168. SADIV = 0xc;
  169. break;
  170. case 96000: /* not in manual and possibly slightly inaccurate */
  171. SADIV = 0x6;
  172. break;
  173. }
  174. return 0;
  175. }
  176. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  177. {
  178. int ret = 0;
  179. switch (cmd) {
  180. case SNDRV_PCM_TRIGGER_START:
  181. SACR0 |= SACR0_ENB;
  182. break;
  183. case SNDRV_PCM_TRIGGER_RESUME:
  184. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  185. case SNDRV_PCM_TRIGGER_STOP:
  186. case SNDRV_PCM_TRIGGER_SUSPEND:
  187. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  188. break;
  189. default:
  190. ret = -EINVAL;
  191. }
  192. return ret;
  193. }
  194. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
  195. {
  196. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  197. SACR1 |= SACR1_DRPL;
  198. SAIMR &= ~SAIMR_TFS;
  199. } else {
  200. SACR1 |= SACR1_DREC;
  201. SAIMR &= ~SAIMR_RFS;
  202. }
  203. if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
  204. SACR0 &= ~SACR0_ENB;
  205. pxa_i2s_wait();
  206. pxa_set_cken(CKEN_I2S, 0);
  207. }
  208. }
  209. #ifdef CONFIG_PM
  210. static int pxa2xx_i2s_suspend(struct platform_device *dev,
  211. struct snd_soc_cpu_dai *dai)
  212. {
  213. if (!dai->active)
  214. return 0;
  215. /* store registers */
  216. pxa_i2s.sacr0 = SACR0;
  217. pxa_i2s.sacr1 = SACR1;
  218. pxa_i2s.saimr = SAIMR;
  219. pxa_i2s.sadiv = SADIV;
  220. /* deactivate link */
  221. SACR0 &= ~SACR0_ENB;
  222. pxa_i2s_wait();
  223. return 0;
  224. }
  225. static int pxa2xx_i2s_resume(struct platform_device *pdev,
  226. struct snd_soc_cpu_dai *dai)
  227. {
  228. if (!dai->active)
  229. return 0;
  230. pxa_i2s_wait();
  231. SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
  232. SACR1 = pxa_i2s.sacr1;
  233. SAIMR = pxa_i2s.saimr;
  234. SADIV = pxa_i2s.sadiv;
  235. SACR0 |= SACR0_ENB;
  236. return 0;
  237. }
  238. #else
  239. #define pxa2xx_i2s_suspend NULL
  240. #define pxa2xx_i2s_resume NULL
  241. #endif
  242. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  243. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  244. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  245. struct snd_soc_cpu_dai pxa_i2s_dai = {
  246. .name = "pxa2xx-i2s",
  247. .id = 0,
  248. .type = SND_SOC_DAI_I2S,
  249. .suspend = pxa2xx_i2s_suspend,
  250. .resume = pxa2xx_i2s_resume,
  251. .playback = {
  252. .channels_min = 2,
  253. .channels_max = 2,
  254. .rates = PXA2XX_I2S_RATES,
  255. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  256. .capture = {
  257. .channels_min = 2,
  258. .channels_max = 2,
  259. .rates = PXA2XX_I2S_RATES,
  260. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  261. .ops = {
  262. .startup = pxa2xx_i2s_startup,
  263. .shutdown = pxa2xx_i2s_shutdown,
  264. .trigger = pxa2xx_i2s_trigger,
  265. .hw_params = pxa2xx_i2s_hw_params,},
  266. .dai_ops = {
  267. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  268. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  269. },
  270. };
  271. EXPORT_SYMBOL_GPL(pxa_i2s_dai);
  272. /* Module information */
  273. MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
  274. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  275. MODULE_LICENSE("GPL");