mmu.c 45 KB

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  1. /*
  2. * Kernel-based Virtual Machine driver for Linux
  3. *
  4. * This module enables machines with Intel VT-x extensions to run virtual
  5. * machines without emulation or binary translation.
  6. *
  7. * MMU support
  8. *
  9. * Copyright (C) 2006 Qumranet, Inc.
  10. *
  11. * Authors:
  12. * Yaniv Kamay <yaniv@qumranet.com>
  13. * Avi Kivity <avi@qumranet.com>
  14. *
  15. * This work is licensed under the terms of the GNU GPL, version 2. See
  16. * the COPYING file in the top-level directory.
  17. *
  18. */
  19. #include "vmx.h"
  20. #include "mmu.h"
  21. #include <linux/kvm_host.h>
  22. #include <linux/types.h>
  23. #include <linux/string.h>
  24. #include <linux/mm.h>
  25. #include <linux/highmem.h>
  26. #include <linux/module.h>
  27. #include <linux/swap.h>
  28. #include <asm/page.h>
  29. #include <asm/cmpxchg.h>
  30. #include <asm/io.h>
  31. #undef MMU_DEBUG
  32. #undef AUDIT
  33. #ifdef AUDIT
  34. static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
  35. #else
  36. static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
  37. #endif
  38. #ifdef MMU_DEBUG
  39. #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
  40. #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
  41. #else
  42. #define pgprintk(x...) do { } while (0)
  43. #define rmap_printk(x...) do { } while (0)
  44. #endif
  45. #if defined(MMU_DEBUG) || defined(AUDIT)
  46. static int dbg = 1;
  47. #endif
  48. #ifndef MMU_DEBUG
  49. #define ASSERT(x) do { } while (0)
  50. #else
  51. #define ASSERT(x) \
  52. if (!(x)) { \
  53. printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
  54. __FILE__, __LINE__, #x); \
  55. }
  56. #endif
  57. #define PT64_PT_BITS 9
  58. #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
  59. #define PT32_PT_BITS 10
  60. #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
  61. #define PT_WRITABLE_SHIFT 1
  62. #define PT_PRESENT_MASK (1ULL << 0)
  63. #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
  64. #define PT_USER_MASK (1ULL << 2)
  65. #define PT_PWT_MASK (1ULL << 3)
  66. #define PT_PCD_MASK (1ULL << 4)
  67. #define PT_ACCESSED_MASK (1ULL << 5)
  68. #define PT_DIRTY_MASK (1ULL << 6)
  69. #define PT_PAGE_SIZE_MASK (1ULL << 7)
  70. #define PT_PAT_MASK (1ULL << 7)
  71. #define PT_GLOBAL_MASK (1ULL << 8)
  72. #define PT64_NX_SHIFT 63
  73. #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
  74. #define PT_PAT_SHIFT 7
  75. #define PT_DIR_PAT_SHIFT 12
  76. #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
  77. #define PT32_DIR_PSE36_SIZE 4
  78. #define PT32_DIR_PSE36_SHIFT 13
  79. #define PT32_DIR_PSE36_MASK \
  80. (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
  81. #define PT_FIRST_AVAIL_BITS_SHIFT 9
  82. #define PT64_SECOND_AVAIL_BITS_SHIFT 52
  83. #define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
  84. #define VALID_PAGE(x) ((x) != INVALID_PAGE)
  85. #define PT64_LEVEL_BITS 9
  86. #define PT64_LEVEL_SHIFT(level) \
  87. (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
  88. #define PT64_LEVEL_MASK(level) \
  89. (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
  90. #define PT64_INDEX(address, level)\
  91. (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
  92. #define PT32_LEVEL_BITS 10
  93. #define PT32_LEVEL_SHIFT(level) \
  94. (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
  95. #define PT32_LEVEL_MASK(level) \
  96. (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
  97. #define PT32_INDEX(address, level)\
  98. (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
  99. #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
  100. #define PT64_DIR_BASE_ADDR_MASK \
  101. (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
  102. #define PT32_BASE_ADDR_MASK PAGE_MASK
  103. #define PT32_DIR_BASE_ADDR_MASK \
  104. (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
  105. #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
  106. | PT64_NX_MASK)
  107. #define PFERR_PRESENT_MASK (1U << 0)
  108. #define PFERR_WRITE_MASK (1U << 1)
  109. #define PFERR_USER_MASK (1U << 2)
  110. #define PFERR_FETCH_MASK (1U << 4)
  111. #define PT64_ROOT_LEVEL 4
  112. #define PT32_ROOT_LEVEL 2
  113. #define PT32E_ROOT_LEVEL 3
  114. #define PT_DIRECTORY_LEVEL 2
  115. #define PT_PAGE_TABLE_LEVEL 1
  116. #define RMAP_EXT 4
  117. #define ACC_EXEC_MASK 1
  118. #define ACC_WRITE_MASK PT_WRITABLE_MASK
  119. #define ACC_USER_MASK PT_USER_MASK
  120. #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
  121. struct kvm_rmap_desc {
  122. u64 *shadow_ptes[RMAP_EXT];
  123. struct kvm_rmap_desc *more;
  124. };
  125. static struct kmem_cache *pte_chain_cache;
  126. static struct kmem_cache *rmap_desc_cache;
  127. static struct kmem_cache *mmu_page_header_cache;
  128. static u64 __read_mostly shadow_trap_nonpresent_pte;
  129. static u64 __read_mostly shadow_notrap_nonpresent_pte;
  130. void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
  131. {
  132. shadow_trap_nonpresent_pte = trap_pte;
  133. shadow_notrap_nonpresent_pte = notrap_pte;
  134. }
  135. EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
  136. static int is_write_protection(struct kvm_vcpu *vcpu)
  137. {
  138. return vcpu->arch.cr0 & X86_CR0_WP;
  139. }
  140. static int is_cpuid_PSE36(void)
  141. {
  142. return 1;
  143. }
  144. static int is_nx(struct kvm_vcpu *vcpu)
  145. {
  146. return vcpu->arch.shadow_efer & EFER_NX;
  147. }
  148. static int is_present_pte(unsigned long pte)
  149. {
  150. return pte & PT_PRESENT_MASK;
  151. }
  152. static int is_shadow_present_pte(u64 pte)
  153. {
  154. pte &= ~PT_SHADOW_IO_MARK;
  155. return pte != shadow_trap_nonpresent_pte
  156. && pte != shadow_notrap_nonpresent_pte;
  157. }
  158. static int is_writeble_pte(unsigned long pte)
  159. {
  160. return pte & PT_WRITABLE_MASK;
  161. }
  162. static int is_dirty_pte(unsigned long pte)
  163. {
  164. return pte & PT_DIRTY_MASK;
  165. }
  166. static int is_io_pte(unsigned long pte)
  167. {
  168. return pte & PT_SHADOW_IO_MARK;
  169. }
  170. static int is_rmap_pte(u64 pte)
  171. {
  172. return pte != shadow_trap_nonpresent_pte
  173. && pte != shadow_notrap_nonpresent_pte;
  174. }
  175. static gfn_t pse36_gfn_delta(u32 gpte)
  176. {
  177. int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
  178. return (gpte & PT32_DIR_PSE36_MASK) << shift;
  179. }
  180. static void set_shadow_pte(u64 *sptep, u64 spte)
  181. {
  182. #ifdef CONFIG_X86_64
  183. set_64bit((unsigned long *)sptep, spte);
  184. #else
  185. set_64bit((unsigned long long *)sptep, spte);
  186. #endif
  187. }
  188. static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
  189. struct kmem_cache *base_cache, int min)
  190. {
  191. void *obj;
  192. if (cache->nobjs >= min)
  193. return 0;
  194. while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
  195. obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
  196. if (!obj)
  197. return -ENOMEM;
  198. cache->objects[cache->nobjs++] = obj;
  199. }
  200. return 0;
  201. }
  202. static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
  203. {
  204. while (mc->nobjs)
  205. kfree(mc->objects[--mc->nobjs]);
  206. }
  207. static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
  208. int min)
  209. {
  210. struct page *page;
  211. if (cache->nobjs >= min)
  212. return 0;
  213. while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
  214. page = alloc_page(GFP_KERNEL);
  215. if (!page)
  216. return -ENOMEM;
  217. set_page_private(page, 0);
  218. cache->objects[cache->nobjs++] = page_address(page);
  219. }
  220. return 0;
  221. }
  222. static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
  223. {
  224. while (mc->nobjs)
  225. free_page((unsigned long)mc->objects[--mc->nobjs]);
  226. }
  227. static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
  228. {
  229. int r;
  230. r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
  231. pte_chain_cache, 4);
  232. if (r)
  233. goto out;
  234. r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
  235. rmap_desc_cache, 1);
  236. if (r)
  237. goto out;
  238. r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
  239. if (r)
  240. goto out;
  241. r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
  242. mmu_page_header_cache, 4);
  243. out:
  244. return r;
  245. }
  246. static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
  247. {
  248. mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
  249. mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
  250. mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
  251. mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
  252. }
  253. static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
  254. size_t size)
  255. {
  256. void *p;
  257. BUG_ON(!mc->nobjs);
  258. p = mc->objects[--mc->nobjs];
  259. memset(p, 0, size);
  260. return p;
  261. }
  262. static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
  263. {
  264. return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
  265. sizeof(struct kvm_pte_chain));
  266. }
  267. static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
  268. {
  269. kfree(pc);
  270. }
  271. static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
  272. {
  273. return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
  274. sizeof(struct kvm_rmap_desc));
  275. }
  276. static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
  277. {
  278. kfree(rd);
  279. }
  280. /*
  281. * Take gfn and return the reverse mapping to it.
  282. * Note: gfn must be unaliased before this function get called
  283. */
  284. static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn)
  285. {
  286. struct kvm_memory_slot *slot;
  287. slot = gfn_to_memslot(kvm, gfn);
  288. return &slot->rmap[gfn - slot->base_gfn];
  289. }
  290. /*
  291. * Reverse mapping data structures:
  292. *
  293. * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
  294. * that points to page_address(page).
  295. *
  296. * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
  297. * containing more mappings.
  298. */
  299. static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
  300. {
  301. struct kvm_mmu_page *sp;
  302. struct kvm_rmap_desc *desc;
  303. unsigned long *rmapp;
  304. int i;
  305. if (!is_rmap_pte(*spte))
  306. return;
  307. gfn = unalias_gfn(vcpu->kvm, gfn);
  308. sp = page_header(__pa(spte));
  309. sp->gfns[spte - sp->spt] = gfn;
  310. rmapp = gfn_to_rmap(vcpu->kvm, gfn);
  311. if (!*rmapp) {
  312. rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
  313. *rmapp = (unsigned long)spte;
  314. } else if (!(*rmapp & 1)) {
  315. rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
  316. desc = mmu_alloc_rmap_desc(vcpu);
  317. desc->shadow_ptes[0] = (u64 *)*rmapp;
  318. desc->shadow_ptes[1] = spte;
  319. *rmapp = (unsigned long)desc | 1;
  320. } else {
  321. rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
  322. desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
  323. while (desc->shadow_ptes[RMAP_EXT-1] && desc->more)
  324. desc = desc->more;
  325. if (desc->shadow_ptes[RMAP_EXT-1]) {
  326. desc->more = mmu_alloc_rmap_desc(vcpu);
  327. desc = desc->more;
  328. }
  329. for (i = 0; desc->shadow_ptes[i]; ++i)
  330. ;
  331. desc->shadow_ptes[i] = spte;
  332. }
  333. }
  334. static void rmap_desc_remove_entry(unsigned long *rmapp,
  335. struct kvm_rmap_desc *desc,
  336. int i,
  337. struct kvm_rmap_desc *prev_desc)
  338. {
  339. int j;
  340. for (j = RMAP_EXT - 1; !desc->shadow_ptes[j] && j > i; --j)
  341. ;
  342. desc->shadow_ptes[i] = desc->shadow_ptes[j];
  343. desc->shadow_ptes[j] = NULL;
  344. if (j != 0)
  345. return;
  346. if (!prev_desc && !desc->more)
  347. *rmapp = (unsigned long)desc->shadow_ptes[0];
  348. else
  349. if (prev_desc)
  350. prev_desc->more = desc->more;
  351. else
  352. *rmapp = (unsigned long)desc->more | 1;
  353. mmu_free_rmap_desc(desc);
  354. }
  355. static void rmap_remove(struct kvm *kvm, u64 *spte)
  356. {
  357. struct kvm_rmap_desc *desc;
  358. struct kvm_rmap_desc *prev_desc;
  359. struct kvm_mmu_page *sp;
  360. struct page *page;
  361. unsigned long *rmapp;
  362. int i;
  363. if (!is_rmap_pte(*spte))
  364. return;
  365. sp = page_header(__pa(spte));
  366. page = pfn_to_page((*spte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT);
  367. mark_page_accessed(page);
  368. if (is_writeble_pte(*spte))
  369. kvm_release_page_dirty(page);
  370. else
  371. kvm_release_page_clean(page);
  372. rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt]);
  373. if (!*rmapp) {
  374. printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
  375. BUG();
  376. } else if (!(*rmapp & 1)) {
  377. rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
  378. if ((u64 *)*rmapp != spte) {
  379. printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
  380. spte, *spte);
  381. BUG();
  382. }
  383. *rmapp = 0;
  384. } else {
  385. rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
  386. desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
  387. prev_desc = NULL;
  388. while (desc) {
  389. for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i)
  390. if (desc->shadow_ptes[i] == spte) {
  391. rmap_desc_remove_entry(rmapp,
  392. desc, i,
  393. prev_desc);
  394. return;
  395. }
  396. prev_desc = desc;
  397. desc = desc->more;
  398. }
  399. BUG();
  400. }
  401. }
  402. static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
  403. {
  404. struct kvm_rmap_desc *desc;
  405. struct kvm_rmap_desc *prev_desc;
  406. u64 *prev_spte;
  407. int i;
  408. if (!*rmapp)
  409. return NULL;
  410. else if (!(*rmapp & 1)) {
  411. if (!spte)
  412. return (u64 *)*rmapp;
  413. return NULL;
  414. }
  415. desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
  416. prev_desc = NULL;
  417. prev_spte = NULL;
  418. while (desc) {
  419. for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i) {
  420. if (prev_spte == spte)
  421. return desc->shadow_ptes[i];
  422. prev_spte = desc->shadow_ptes[i];
  423. }
  424. desc = desc->more;
  425. }
  426. return NULL;
  427. }
  428. static void rmap_write_protect(struct kvm *kvm, u64 gfn)
  429. {
  430. unsigned long *rmapp;
  431. u64 *spte;
  432. int write_protected = 0;
  433. gfn = unalias_gfn(kvm, gfn);
  434. rmapp = gfn_to_rmap(kvm, gfn);
  435. spte = rmap_next(kvm, rmapp, NULL);
  436. while (spte) {
  437. BUG_ON(!spte);
  438. BUG_ON(!(*spte & PT_PRESENT_MASK));
  439. rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
  440. if (is_writeble_pte(*spte)) {
  441. set_shadow_pte(spte, *spte & ~PT_WRITABLE_MASK);
  442. write_protected = 1;
  443. }
  444. spte = rmap_next(kvm, rmapp, spte);
  445. }
  446. if (write_protected)
  447. kvm_flush_remote_tlbs(kvm);
  448. }
  449. #ifdef MMU_DEBUG
  450. static int is_empty_shadow_page(u64 *spt)
  451. {
  452. u64 *pos;
  453. u64 *end;
  454. for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
  455. if ((*pos & ~PT_SHADOW_IO_MARK) != shadow_trap_nonpresent_pte) {
  456. printk(KERN_ERR "%s: %p %llx\n", __FUNCTION__,
  457. pos, *pos);
  458. return 0;
  459. }
  460. return 1;
  461. }
  462. #endif
  463. static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
  464. {
  465. ASSERT(is_empty_shadow_page(sp->spt));
  466. list_del(&sp->link);
  467. __free_page(virt_to_page(sp->spt));
  468. __free_page(virt_to_page(sp->gfns));
  469. kfree(sp);
  470. ++kvm->arch.n_free_mmu_pages;
  471. }
  472. static unsigned kvm_page_table_hashfn(gfn_t gfn)
  473. {
  474. return gfn;
  475. }
  476. static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
  477. u64 *parent_pte)
  478. {
  479. struct kvm_mmu_page *sp;
  480. sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
  481. sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
  482. sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
  483. set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
  484. list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
  485. ASSERT(is_empty_shadow_page(sp->spt));
  486. sp->slot_bitmap = 0;
  487. sp->multimapped = 0;
  488. sp->parent_pte = parent_pte;
  489. --vcpu->kvm->arch.n_free_mmu_pages;
  490. return sp;
  491. }
  492. static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
  493. struct kvm_mmu_page *sp, u64 *parent_pte)
  494. {
  495. struct kvm_pte_chain *pte_chain;
  496. struct hlist_node *node;
  497. int i;
  498. if (!parent_pte)
  499. return;
  500. if (!sp->multimapped) {
  501. u64 *old = sp->parent_pte;
  502. if (!old) {
  503. sp->parent_pte = parent_pte;
  504. return;
  505. }
  506. sp->multimapped = 1;
  507. pte_chain = mmu_alloc_pte_chain(vcpu);
  508. INIT_HLIST_HEAD(&sp->parent_ptes);
  509. hlist_add_head(&pte_chain->link, &sp->parent_ptes);
  510. pte_chain->parent_ptes[0] = old;
  511. }
  512. hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
  513. if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
  514. continue;
  515. for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
  516. if (!pte_chain->parent_ptes[i]) {
  517. pte_chain->parent_ptes[i] = parent_pte;
  518. return;
  519. }
  520. }
  521. pte_chain = mmu_alloc_pte_chain(vcpu);
  522. BUG_ON(!pte_chain);
  523. hlist_add_head(&pte_chain->link, &sp->parent_ptes);
  524. pte_chain->parent_ptes[0] = parent_pte;
  525. }
  526. static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
  527. u64 *parent_pte)
  528. {
  529. struct kvm_pte_chain *pte_chain;
  530. struct hlist_node *node;
  531. int i;
  532. if (!sp->multimapped) {
  533. BUG_ON(sp->parent_pte != parent_pte);
  534. sp->parent_pte = NULL;
  535. return;
  536. }
  537. hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
  538. for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
  539. if (!pte_chain->parent_ptes[i])
  540. break;
  541. if (pte_chain->parent_ptes[i] != parent_pte)
  542. continue;
  543. while (i + 1 < NR_PTE_CHAIN_ENTRIES
  544. && pte_chain->parent_ptes[i + 1]) {
  545. pte_chain->parent_ptes[i]
  546. = pte_chain->parent_ptes[i + 1];
  547. ++i;
  548. }
  549. pte_chain->parent_ptes[i] = NULL;
  550. if (i == 0) {
  551. hlist_del(&pte_chain->link);
  552. mmu_free_pte_chain(pte_chain);
  553. if (hlist_empty(&sp->parent_ptes)) {
  554. sp->multimapped = 0;
  555. sp->parent_pte = NULL;
  556. }
  557. }
  558. return;
  559. }
  560. BUG();
  561. }
  562. static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
  563. {
  564. unsigned index;
  565. struct hlist_head *bucket;
  566. struct kvm_mmu_page *sp;
  567. struct hlist_node *node;
  568. pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn);
  569. index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
  570. bucket = &kvm->arch.mmu_page_hash[index];
  571. hlist_for_each_entry(sp, node, bucket, hash_link)
  572. if (sp->gfn == gfn && !sp->role.metaphysical) {
  573. pgprintk("%s: found role %x\n",
  574. __FUNCTION__, sp->role.word);
  575. return sp;
  576. }
  577. return NULL;
  578. }
  579. static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
  580. gfn_t gfn,
  581. gva_t gaddr,
  582. unsigned level,
  583. int metaphysical,
  584. unsigned access,
  585. u64 *parent_pte)
  586. {
  587. union kvm_mmu_page_role role;
  588. unsigned index;
  589. unsigned quadrant;
  590. struct hlist_head *bucket;
  591. struct kvm_mmu_page *sp;
  592. struct hlist_node *node;
  593. role.word = 0;
  594. role.glevels = vcpu->arch.mmu.root_level;
  595. role.level = level;
  596. role.metaphysical = metaphysical;
  597. role.access = access;
  598. if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
  599. quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
  600. quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
  601. role.quadrant = quadrant;
  602. }
  603. pgprintk("%s: looking gfn %lx role %x\n", __FUNCTION__,
  604. gfn, role.word);
  605. index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
  606. bucket = &vcpu->kvm->arch.mmu_page_hash[index];
  607. hlist_for_each_entry(sp, node, bucket, hash_link)
  608. if (sp->gfn == gfn && sp->role.word == role.word) {
  609. mmu_page_add_parent_pte(vcpu, sp, parent_pte);
  610. pgprintk("%s: found\n", __FUNCTION__);
  611. return sp;
  612. }
  613. ++vcpu->kvm->stat.mmu_cache_miss;
  614. sp = kvm_mmu_alloc_page(vcpu, parent_pte);
  615. if (!sp)
  616. return sp;
  617. pgprintk("%s: adding gfn %lx role %x\n", __FUNCTION__, gfn, role.word);
  618. sp->gfn = gfn;
  619. sp->role = role;
  620. hlist_add_head(&sp->hash_link, bucket);
  621. vcpu->arch.mmu.prefetch_page(vcpu, sp);
  622. if (!metaphysical)
  623. rmap_write_protect(vcpu->kvm, gfn);
  624. return sp;
  625. }
  626. static void kvm_mmu_page_unlink_children(struct kvm *kvm,
  627. struct kvm_mmu_page *sp)
  628. {
  629. unsigned i;
  630. u64 *pt;
  631. u64 ent;
  632. pt = sp->spt;
  633. if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
  634. for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
  635. if (is_shadow_present_pte(pt[i]))
  636. rmap_remove(kvm, &pt[i]);
  637. pt[i] = shadow_trap_nonpresent_pte;
  638. }
  639. kvm_flush_remote_tlbs(kvm);
  640. return;
  641. }
  642. for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
  643. ent = pt[i];
  644. pt[i] = shadow_trap_nonpresent_pte;
  645. if (!is_shadow_present_pte(ent))
  646. continue;
  647. ent &= PT64_BASE_ADDR_MASK;
  648. mmu_page_remove_parent_pte(page_header(ent), &pt[i]);
  649. }
  650. kvm_flush_remote_tlbs(kvm);
  651. }
  652. static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
  653. {
  654. mmu_page_remove_parent_pte(sp, parent_pte);
  655. }
  656. static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
  657. {
  658. int i;
  659. for (i = 0; i < KVM_MAX_VCPUS; ++i)
  660. if (kvm->vcpus[i])
  661. kvm->vcpus[i]->arch.last_pte_updated = NULL;
  662. }
  663. static void kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
  664. {
  665. u64 *parent_pte;
  666. ++kvm->stat.mmu_shadow_zapped;
  667. while (sp->multimapped || sp->parent_pte) {
  668. if (!sp->multimapped)
  669. parent_pte = sp->parent_pte;
  670. else {
  671. struct kvm_pte_chain *chain;
  672. chain = container_of(sp->parent_ptes.first,
  673. struct kvm_pte_chain, link);
  674. parent_pte = chain->parent_ptes[0];
  675. }
  676. BUG_ON(!parent_pte);
  677. kvm_mmu_put_page(sp, parent_pte);
  678. set_shadow_pte(parent_pte, shadow_trap_nonpresent_pte);
  679. }
  680. kvm_mmu_page_unlink_children(kvm, sp);
  681. if (!sp->root_count) {
  682. hlist_del(&sp->hash_link);
  683. kvm_mmu_free_page(kvm, sp);
  684. } else
  685. list_move(&sp->link, &kvm->arch.active_mmu_pages);
  686. kvm_mmu_reset_last_pte_updated(kvm);
  687. }
  688. /*
  689. * Changing the number of mmu pages allocated to the vm
  690. * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
  691. */
  692. void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
  693. {
  694. /*
  695. * If we set the number of mmu pages to be smaller be than the
  696. * number of actived pages , we must to free some mmu pages before we
  697. * change the value
  698. */
  699. if ((kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages) >
  700. kvm_nr_mmu_pages) {
  701. int n_used_mmu_pages = kvm->arch.n_alloc_mmu_pages
  702. - kvm->arch.n_free_mmu_pages;
  703. while (n_used_mmu_pages > kvm_nr_mmu_pages) {
  704. struct kvm_mmu_page *page;
  705. page = container_of(kvm->arch.active_mmu_pages.prev,
  706. struct kvm_mmu_page, link);
  707. kvm_mmu_zap_page(kvm, page);
  708. n_used_mmu_pages--;
  709. }
  710. kvm->arch.n_free_mmu_pages = 0;
  711. }
  712. else
  713. kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
  714. - kvm->arch.n_alloc_mmu_pages;
  715. kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
  716. }
  717. static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
  718. {
  719. unsigned index;
  720. struct hlist_head *bucket;
  721. struct kvm_mmu_page *sp;
  722. struct hlist_node *node, *n;
  723. int r;
  724. pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn);
  725. r = 0;
  726. index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
  727. bucket = &kvm->arch.mmu_page_hash[index];
  728. hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
  729. if (sp->gfn == gfn && !sp->role.metaphysical) {
  730. pgprintk("%s: gfn %lx role %x\n", __FUNCTION__, gfn,
  731. sp->role.word);
  732. kvm_mmu_zap_page(kvm, sp);
  733. r = 1;
  734. }
  735. return r;
  736. }
  737. static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
  738. {
  739. struct kvm_mmu_page *sp;
  740. while ((sp = kvm_mmu_lookup_page(kvm, gfn)) != NULL) {
  741. pgprintk("%s: zap %lx %x\n", __FUNCTION__, gfn, sp->role.word);
  742. kvm_mmu_zap_page(kvm, sp);
  743. }
  744. }
  745. static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
  746. {
  747. int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
  748. struct kvm_mmu_page *sp = page_header(__pa(pte));
  749. __set_bit(slot, &sp->slot_bitmap);
  750. }
  751. struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
  752. {
  753. struct page *page;
  754. gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
  755. if (gpa == UNMAPPED_GVA)
  756. return NULL;
  757. down_read(&current->mm->mmap_sem);
  758. page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
  759. up_read(&current->mm->mmap_sem);
  760. return page;
  761. }
  762. static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
  763. unsigned pt_access, unsigned pte_access,
  764. int user_fault, int write_fault, int dirty,
  765. int *ptwrite, gfn_t gfn, struct page *page)
  766. {
  767. u64 spte;
  768. int was_rmapped = is_rmap_pte(*shadow_pte);
  769. int was_writeble = is_writeble_pte(*shadow_pte);
  770. pgprintk("%s: spte %llx access %x write_fault %d"
  771. " user_fault %d gfn %lx\n",
  772. __FUNCTION__, *shadow_pte, pt_access,
  773. write_fault, user_fault, gfn);
  774. /*
  775. * We don't set the accessed bit, since we sometimes want to see
  776. * whether the guest actually used the pte (in order to detect
  777. * demand paging).
  778. */
  779. spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
  780. if (!dirty)
  781. pte_access &= ~ACC_WRITE_MASK;
  782. if (!(pte_access & ACC_EXEC_MASK))
  783. spte |= PT64_NX_MASK;
  784. spte |= PT_PRESENT_MASK;
  785. if (pte_access & ACC_USER_MASK)
  786. spte |= PT_USER_MASK;
  787. if (is_error_page(page)) {
  788. set_shadow_pte(shadow_pte,
  789. shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
  790. kvm_release_page_clean(page);
  791. return;
  792. }
  793. spte |= page_to_phys(page);
  794. if ((pte_access & ACC_WRITE_MASK)
  795. || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
  796. struct kvm_mmu_page *shadow;
  797. spte |= PT_WRITABLE_MASK;
  798. if (user_fault) {
  799. mmu_unshadow(vcpu->kvm, gfn);
  800. goto unshadowed;
  801. }
  802. shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
  803. if (shadow) {
  804. pgprintk("%s: found shadow page for %lx, marking ro\n",
  805. __FUNCTION__, gfn);
  806. pte_access &= ~ACC_WRITE_MASK;
  807. if (is_writeble_pte(spte)) {
  808. spte &= ~PT_WRITABLE_MASK;
  809. kvm_x86_ops->tlb_flush(vcpu);
  810. }
  811. if (write_fault)
  812. *ptwrite = 1;
  813. }
  814. }
  815. unshadowed:
  816. if (pte_access & ACC_WRITE_MASK)
  817. mark_page_dirty(vcpu->kvm, gfn);
  818. pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
  819. set_shadow_pte(shadow_pte, spte);
  820. page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
  821. if (!was_rmapped) {
  822. rmap_add(vcpu, shadow_pte, gfn);
  823. if (!is_rmap_pte(*shadow_pte))
  824. kvm_release_page_clean(page);
  825. } else {
  826. if (was_writeble)
  827. kvm_release_page_dirty(page);
  828. else
  829. kvm_release_page_clean(page);
  830. }
  831. if (!ptwrite || !*ptwrite)
  832. vcpu->arch.last_pte_updated = shadow_pte;
  833. }
  834. static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
  835. {
  836. }
  837. static int __nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write,
  838. gfn_t gfn, struct page *page)
  839. {
  840. int level = PT32E_ROOT_LEVEL;
  841. hpa_t table_addr = vcpu->arch.mmu.root_hpa;
  842. int pt_write = 0;
  843. for (; ; level--) {
  844. u32 index = PT64_INDEX(v, level);
  845. u64 *table;
  846. ASSERT(VALID_PAGE(table_addr));
  847. table = __va(table_addr);
  848. if (level == 1) {
  849. mmu_set_spte(vcpu, &table[index], ACC_ALL, ACC_ALL,
  850. 0, write, 1, &pt_write, gfn, page);
  851. return pt_write || is_io_pte(table[index]);
  852. }
  853. if (table[index] == shadow_trap_nonpresent_pte) {
  854. struct kvm_mmu_page *new_table;
  855. gfn_t pseudo_gfn;
  856. pseudo_gfn = (v & PT64_DIR_BASE_ADDR_MASK)
  857. >> PAGE_SHIFT;
  858. new_table = kvm_mmu_get_page(vcpu, pseudo_gfn,
  859. v, level - 1,
  860. 1, ACC_ALL, &table[index]);
  861. if (!new_table) {
  862. pgprintk("nonpaging_map: ENOMEM\n");
  863. kvm_release_page_clean(page);
  864. return -ENOMEM;
  865. }
  866. table[index] = __pa(new_table->spt) | PT_PRESENT_MASK
  867. | PT_WRITABLE_MASK | PT_USER_MASK;
  868. }
  869. table_addr = table[index] & PT64_BASE_ADDR_MASK;
  870. }
  871. }
  872. static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
  873. {
  874. int r;
  875. struct page *page;
  876. down_read(&vcpu->kvm->slots_lock);
  877. down_read(&current->mm->mmap_sem);
  878. page = gfn_to_page(vcpu->kvm, gfn);
  879. up_read(&current->mm->mmap_sem);
  880. spin_lock(&vcpu->kvm->mmu_lock);
  881. kvm_mmu_free_some_pages(vcpu);
  882. r = __nonpaging_map(vcpu, v, write, gfn, page);
  883. spin_unlock(&vcpu->kvm->mmu_lock);
  884. up_read(&vcpu->kvm->slots_lock);
  885. return r;
  886. }
  887. static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
  888. struct kvm_mmu_page *sp)
  889. {
  890. int i;
  891. for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
  892. sp->spt[i] = shadow_trap_nonpresent_pte;
  893. }
  894. static void mmu_free_roots(struct kvm_vcpu *vcpu)
  895. {
  896. int i;
  897. struct kvm_mmu_page *sp;
  898. if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
  899. return;
  900. spin_lock(&vcpu->kvm->mmu_lock);
  901. #ifdef CONFIG_X86_64
  902. if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
  903. hpa_t root = vcpu->arch.mmu.root_hpa;
  904. sp = page_header(root);
  905. --sp->root_count;
  906. vcpu->arch.mmu.root_hpa = INVALID_PAGE;
  907. spin_unlock(&vcpu->kvm->mmu_lock);
  908. return;
  909. }
  910. #endif
  911. for (i = 0; i < 4; ++i) {
  912. hpa_t root = vcpu->arch.mmu.pae_root[i];
  913. if (root) {
  914. root &= PT64_BASE_ADDR_MASK;
  915. sp = page_header(root);
  916. --sp->root_count;
  917. }
  918. vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
  919. }
  920. spin_unlock(&vcpu->kvm->mmu_lock);
  921. vcpu->arch.mmu.root_hpa = INVALID_PAGE;
  922. }
  923. static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
  924. {
  925. int i;
  926. gfn_t root_gfn;
  927. struct kvm_mmu_page *sp;
  928. root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
  929. #ifdef CONFIG_X86_64
  930. if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
  931. hpa_t root = vcpu->arch.mmu.root_hpa;
  932. ASSERT(!VALID_PAGE(root));
  933. sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
  934. PT64_ROOT_LEVEL, 0, ACC_ALL, NULL);
  935. root = __pa(sp->spt);
  936. ++sp->root_count;
  937. vcpu->arch.mmu.root_hpa = root;
  938. return;
  939. }
  940. #endif
  941. for (i = 0; i < 4; ++i) {
  942. hpa_t root = vcpu->arch.mmu.pae_root[i];
  943. ASSERT(!VALID_PAGE(root));
  944. if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
  945. if (!is_present_pte(vcpu->arch.pdptrs[i])) {
  946. vcpu->arch.mmu.pae_root[i] = 0;
  947. continue;
  948. }
  949. root_gfn = vcpu->arch.pdptrs[i] >> PAGE_SHIFT;
  950. } else if (vcpu->arch.mmu.root_level == 0)
  951. root_gfn = 0;
  952. sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
  953. PT32_ROOT_LEVEL, !is_paging(vcpu),
  954. ACC_ALL, NULL);
  955. root = __pa(sp->spt);
  956. ++sp->root_count;
  957. vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
  958. }
  959. vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
  960. }
  961. static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
  962. {
  963. return vaddr;
  964. }
  965. static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
  966. u32 error_code)
  967. {
  968. gfn_t gfn;
  969. int r;
  970. pgprintk("%s: gva %lx error %x\n", __FUNCTION__, gva, error_code);
  971. r = mmu_topup_memory_caches(vcpu);
  972. if (r)
  973. return r;
  974. ASSERT(vcpu);
  975. ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
  976. gfn = gva >> PAGE_SHIFT;
  977. return nonpaging_map(vcpu, gva & PAGE_MASK,
  978. error_code & PFERR_WRITE_MASK, gfn);
  979. }
  980. static void nonpaging_free(struct kvm_vcpu *vcpu)
  981. {
  982. mmu_free_roots(vcpu);
  983. }
  984. static int nonpaging_init_context(struct kvm_vcpu *vcpu)
  985. {
  986. struct kvm_mmu *context = &vcpu->arch.mmu;
  987. context->new_cr3 = nonpaging_new_cr3;
  988. context->page_fault = nonpaging_page_fault;
  989. context->gva_to_gpa = nonpaging_gva_to_gpa;
  990. context->free = nonpaging_free;
  991. context->prefetch_page = nonpaging_prefetch_page;
  992. context->root_level = 0;
  993. context->shadow_root_level = PT32E_ROOT_LEVEL;
  994. context->root_hpa = INVALID_PAGE;
  995. return 0;
  996. }
  997. void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
  998. {
  999. ++vcpu->stat.tlb_flush;
  1000. kvm_x86_ops->tlb_flush(vcpu);
  1001. }
  1002. static void paging_new_cr3(struct kvm_vcpu *vcpu)
  1003. {
  1004. pgprintk("%s: cr3 %lx\n", __FUNCTION__, vcpu->arch.cr3);
  1005. mmu_free_roots(vcpu);
  1006. }
  1007. static void inject_page_fault(struct kvm_vcpu *vcpu,
  1008. u64 addr,
  1009. u32 err_code)
  1010. {
  1011. kvm_inject_page_fault(vcpu, addr, err_code);
  1012. }
  1013. static void paging_free(struct kvm_vcpu *vcpu)
  1014. {
  1015. nonpaging_free(vcpu);
  1016. }
  1017. #define PTTYPE 64
  1018. #include "paging_tmpl.h"
  1019. #undef PTTYPE
  1020. #define PTTYPE 32
  1021. #include "paging_tmpl.h"
  1022. #undef PTTYPE
  1023. static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
  1024. {
  1025. struct kvm_mmu *context = &vcpu->arch.mmu;
  1026. ASSERT(is_pae(vcpu));
  1027. context->new_cr3 = paging_new_cr3;
  1028. context->page_fault = paging64_page_fault;
  1029. context->gva_to_gpa = paging64_gva_to_gpa;
  1030. context->prefetch_page = paging64_prefetch_page;
  1031. context->free = paging_free;
  1032. context->root_level = level;
  1033. context->shadow_root_level = level;
  1034. context->root_hpa = INVALID_PAGE;
  1035. return 0;
  1036. }
  1037. static int paging64_init_context(struct kvm_vcpu *vcpu)
  1038. {
  1039. return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
  1040. }
  1041. static int paging32_init_context(struct kvm_vcpu *vcpu)
  1042. {
  1043. struct kvm_mmu *context = &vcpu->arch.mmu;
  1044. context->new_cr3 = paging_new_cr3;
  1045. context->page_fault = paging32_page_fault;
  1046. context->gva_to_gpa = paging32_gva_to_gpa;
  1047. context->free = paging_free;
  1048. context->prefetch_page = paging32_prefetch_page;
  1049. context->root_level = PT32_ROOT_LEVEL;
  1050. context->shadow_root_level = PT32E_ROOT_LEVEL;
  1051. context->root_hpa = INVALID_PAGE;
  1052. return 0;
  1053. }
  1054. static int paging32E_init_context(struct kvm_vcpu *vcpu)
  1055. {
  1056. return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
  1057. }
  1058. static int init_kvm_mmu(struct kvm_vcpu *vcpu)
  1059. {
  1060. ASSERT(vcpu);
  1061. ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
  1062. if (!is_paging(vcpu))
  1063. return nonpaging_init_context(vcpu);
  1064. else if (is_long_mode(vcpu))
  1065. return paging64_init_context(vcpu);
  1066. else if (is_pae(vcpu))
  1067. return paging32E_init_context(vcpu);
  1068. else
  1069. return paging32_init_context(vcpu);
  1070. }
  1071. static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
  1072. {
  1073. ASSERT(vcpu);
  1074. if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
  1075. vcpu->arch.mmu.free(vcpu);
  1076. vcpu->arch.mmu.root_hpa = INVALID_PAGE;
  1077. }
  1078. }
  1079. int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
  1080. {
  1081. destroy_kvm_mmu(vcpu);
  1082. return init_kvm_mmu(vcpu);
  1083. }
  1084. EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
  1085. int kvm_mmu_load(struct kvm_vcpu *vcpu)
  1086. {
  1087. int r;
  1088. r = mmu_topup_memory_caches(vcpu);
  1089. if (r)
  1090. goto out;
  1091. spin_lock(&vcpu->kvm->mmu_lock);
  1092. kvm_mmu_free_some_pages(vcpu);
  1093. mmu_alloc_roots(vcpu);
  1094. spin_unlock(&vcpu->kvm->mmu_lock);
  1095. kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
  1096. kvm_mmu_flush_tlb(vcpu);
  1097. out:
  1098. return r;
  1099. }
  1100. EXPORT_SYMBOL_GPL(kvm_mmu_load);
  1101. void kvm_mmu_unload(struct kvm_vcpu *vcpu)
  1102. {
  1103. mmu_free_roots(vcpu);
  1104. }
  1105. static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
  1106. struct kvm_mmu_page *sp,
  1107. u64 *spte)
  1108. {
  1109. u64 pte;
  1110. struct kvm_mmu_page *child;
  1111. pte = *spte;
  1112. if (is_shadow_present_pte(pte)) {
  1113. if (sp->role.level == PT_PAGE_TABLE_LEVEL)
  1114. rmap_remove(vcpu->kvm, spte);
  1115. else {
  1116. child = page_header(pte & PT64_BASE_ADDR_MASK);
  1117. mmu_page_remove_parent_pte(child, spte);
  1118. }
  1119. }
  1120. set_shadow_pte(spte, shadow_trap_nonpresent_pte);
  1121. }
  1122. static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
  1123. struct kvm_mmu_page *sp,
  1124. u64 *spte,
  1125. const void *new, int bytes,
  1126. int offset_in_pte)
  1127. {
  1128. if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
  1129. ++vcpu->kvm->stat.mmu_pde_zapped;
  1130. return;
  1131. }
  1132. ++vcpu->kvm->stat.mmu_pte_updated;
  1133. if (sp->role.glevels == PT32_ROOT_LEVEL)
  1134. paging32_update_pte(vcpu, sp, spte, new, bytes, offset_in_pte);
  1135. else
  1136. paging64_update_pte(vcpu, sp, spte, new, bytes, offset_in_pte);
  1137. }
  1138. static bool need_remote_flush(u64 old, u64 new)
  1139. {
  1140. if (!is_shadow_present_pte(old))
  1141. return false;
  1142. if (!is_shadow_present_pte(new))
  1143. return true;
  1144. if ((old ^ new) & PT64_BASE_ADDR_MASK)
  1145. return true;
  1146. old ^= PT64_NX_MASK;
  1147. new ^= PT64_NX_MASK;
  1148. return (old & ~new & PT64_PERM_MASK) != 0;
  1149. }
  1150. static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
  1151. {
  1152. if (need_remote_flush(old, new))
  1153. kvm_flush_remote_tlbs(vcpu->kvm);
  1154. else
  1155. kvm_mmu_flush_tlb(vcpu);
  1156. }
  1157. static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
  1158. {
  1159. u64 *spte = vcpu->arch.last_pte_updated;
  1160. return !!(spte && (*spte & PT_ACCESSED_MASK));
  1161. }
  1162. static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
  1163. const u8 *new, int bytes)
  1164. {
  1165. gfn_t gfn;
  1166. int r;
  1167. u64 gpte = 0;
  1168. struct page *page;
  1169. if (bytes != 4 && bytes != 8)
  1170. return;
  1171. /*
  1172. * Assume that the pte write on a page table of the same type
  1173. * as the current vcpu paging mode. This is nearly always true
  1174. * (might be false while changing modes). Note it is verified later
  1175. * by update_pte().
  1176. */
  1177. if (is_pae(vcpu)) {
  1178. /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
  1179. if ((bytes == 4) && (gpa % 4 == 0)) {
  1180. r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
  1181. if (r)
  1182. return;
  1183. memcpy((void *)&gpte + (gpa % 8), new, 4);
  1184. } else if ((bytes == 8) && (gpa % 8 == 0)) {
  1185. memcpy((void *)&gpte, new, 8);
  1186. }
  1187. } else {
  1188. if ((bytes == 4) && (gpa % 4 == 0))
  1189. memcpy((void *)&gpte, new, 4);
  1190. }
  1191. if (!is_present_pte(gpte))
  1192. return;
  1193. gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
  1194. down_read(&current->mm->mmap_sem);
  1195. page = gfn_to_page(vcpu->kvm, gfn);
  1196. up_read(&current->mm->mmap_sem);
  1197. vcpu->arch.update_pte.gfn = gfn;
  1198. vcpu->arch.update_pte.page = gfn_to_page(vcpu->kvm, gfn);
  1199. }
  1200. void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
  1201. const u8 *new, int bytes)
  1202. {
  1203. gfn_t gfn = gpa >> PAGE_SHIFT;
  1204. struct kvm_mmu_page *sp;
  1205. struct hlist_node *node, *n;
  1206. struct hlist_head *bucket;
  1207. unsigned index;
  1208. u64 entry;
  1209. u64 *spte;
  1210. unsigned offset = offset_in_page(gpa);
  1211. unsigned pte_size;
  1212. unsigned page_offset;
  1213. unsigned misaligned;
  1214. unsigned quadrant;
  1215. int level;
  1216. int flooded = 0;
  1217. int npte;
  1218. pgprintk("%s: gpa %llx bytes %d\n", __FUNCTION__, gpa, bytes);
  1219. mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
  1220. spin_lock(&vcpu->kvm->mmu_lock);
  1221. kvm_mmu_free_some_pages(vcpu);
  1222. ++vcpu->kvm->stat.mmu_pte_write;
  1223. kvm_mmu_audit(vcpu, "pre pte write");
  1224. if (gfn == vcpu->arch.last_pt_write_gfn
  1225. && !last_updated_pte_accessed(vcpu)) {
  1226. ++vcpu->arch.last_pt_write_count;
  1227. if (vcpu->arch.last_pt_write_count >= 3)
  1228. flooded = 1;
  1229. } else {
  1230. vcpu->arch.last_pt_write_gfn = gfn;
  1231. vcpu->arch.last_pt_write_count = 1;
  1232. vcpu->arch.last_pte_updated = NULL;
  1233. }
  1234. index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
  1235. bucket = &vcpu->kvm->arch.mmu_page_hash[index];
  1236. hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
  1237. if (sp->gfn != gfn || sp->role.metaphysical)
  1238. continue;
  1239. pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
  1240. misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
  1241. misaligned |= bytes < 4;
  1242. if (misaligned || flooded) {
  1243. /*
  1244. * Misaligned accesses are too much trouble to fix
  1245. * up; also, they usually indicate a page is not used
  1246. * as a page table.
  1247. *
  1248. * If we're seeing too many writes to a page,
  1249. * it may no longer be a page table, or we may be
  1250. * forking, in which case it is better to unmap the
  1251. * page.
  1252. */
  1253. pgprintk("misaligned: gpa %llx bytes %d role %x\n",
  1254. gpa, bytes, sp->role.word);
  1255. kvm_mmu_zap_page(vcpu->kvm, sp);
  1256. ++vcpu->kvm->stat.mmu_flooded;
  1257. continue;
  1258. }
  1259. page_offset = offset;
  1260. level = sp->role.level;
  1261. npte = 1;
  1262. if (sp->role.glevels == PT32_ROOT_LEVEL) {
  1263. page_offset <<= 1; /* 32->64 */
  1264. /*
  1265. * A 32-bit pde maps 4MB while the shadow pdes map
  1266. * only 2MB. So we need to double the offset again
  1267. * and zap two pdes instead of one.
  1268. */
  1269. if (level == PT32_ROOT_LEVEL) {
  1270. page_offset &= ~7; /* kill rounding error */
  1271. page_offset <<= 1;
  1272. npte = 2;
  1273. }
  1274. quadrant = page_offset >> PAGE_SHIFT;
  1275. page_offset &= ~PAGE_MASK;
  1276. if (quadrant != sp->role.quadrant)
  1277. continue;
  1278. }
  1279. spte = &sp->spt[page_offset / sizeof(*spte)];
  1280. while (npte--) {
  1281. entry = *spte;
  1282. mmu_pte_write_zap_pte(vcpu, sp, spte);
  1283. mmu_pte_write_new_pte(vcpu, sp, spte, new, bytes,
  1284. page_offset & (pte_size - 1));
  1285. mmu_pte_write_flush_tlb(vcpu, entry, *spte);
  1286. ++spte;
  1287. }
  1288. }
  1289. kvm_mmu_audit(vcpu, "post pte write");
  1290. spin_unlock(&vcpu->kvm->mmu_lock);
  1291. if (vcpu->arch.update_pte.page) {
  1292. kvm_release_page_clean(vcpu->arch.update_pte.page);
  1293. vcpu->arch.update_pte.page = NULL;
  1294. }
  1295. }
  1296. int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
  1297. {
  1298. gpa_t gpa;
  1299. int r;
  1300. down_read(&vcpu->kvm->slots_lock);
  1301. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
  1302. up_read(&vcpu->kvm->slots_lock);
  1303. spin_lock(&vcpu->kvm->mmu_lock);
  1304. r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
  1305. spin_unlock(&vcpu->kvm->mmu_lock);
  1306. return r;
  1307. }
  1308. void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
  1309. {
  1310. while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) {
  1311. struct kvm_mmu_page *sp;
  1312. sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
  1313. struct kvm_mmu_page, link);
  1314. kvm_mmu_zap_page(vcpu->kvm, sp);
  1315. ++vcpu->kvm->stat.mmu_recycled;
  1316. }
  1317. }
  1318. int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
  1319. {
  1320. int r;
  1321. enum emulation_result er;
  1322. r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
  1323. if (r < 0)
  1324. goto out;
  1325. if (!r) {
  1326. r = 1;
  1327. goto out;
  1328. }
  1329. r = mmu_topup_memory_caches(vcpu);
  1330. if (r)
  1331. goto out;
  1332. er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0);
  1333. switch (er) {
  1334. case EMULATE_DONE:
  1335. return 1;
  1336. case EMULATE_DO_MMIO:
  1337. ++vcpu->stat.mmio_exits;
  1338. return 0;
  1339. case EMULATE_FAIL:
  1340. kvm_report_emulation_failure(vcpu, "pagetable");
  1341. return 1;
  1342. default:
  1343. BUG();
  1344. }
  1345. out:
  1346. return r;
  1347. }
  1348. EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
  1349. static void free_mmu_pages(struct kvm_vcpu *vcpu)
  1350. {
  1351. struct kvm_mmu_page *sp;
  1352. while (!list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
  1353. sp = container_of(vcpu->kvm->arch.active_mmu_pages.next,
  1354. struct kvm_mmu_page, link);
  1355. kvm_mmu_zap_page(vcpu->kvm, sp);
  1356. }
  1357. free_page((unsigned long)vcpu->arch.mmu.pae_root);
  1358. }
  1359. static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
  1360. {
  1361. struct page *page;
  1362. int i;
  1363. ASSERT(vcpu);
  1364. if (vcpu->kvm->arch.n_requested_mmu_pages)
  1365. vcpu->kvm->arch.n_free_mmu_pages =
  1366. vcpu->kvm->arch.n_requested_mmu_pages;
  1367. else
  1368. vcpu->kvm->arch.n_free_mmu_pages =
  1369. vcpu->kvm->arch.n_alloc_mmu_pages;
  1370. /*
  1371. * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
  1372. * Therefore we need to allocate shadow page tables in the first
  1373. * 4GB of memory, which happens to fit the DMA32 zone.
  1374. */
  1375. page = alloc_page(GFP_KERNEL | __GFP_DMA32);
  1376. if (!page)
  1377. goto error_1;
  1378. vcpu->arch.mmu.pae_root = page_address(page);
  1379. for (i = 0; i < 4; ++i)
  1380. vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
  1381. return 0;
  1382. error_1:
  1383. free_mmu_pages(vcpu);
  1384. return -ENOMEM;
  1385. }
  1386. int kvm_mmu_create(struct kvm_vcpu *vcpu)
  1387. {
  1388. ASSERT(vcpu);
  1389. ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
  1390. return alloc_mmu_pages(vcpu);
  1391. }
  1392. int kvm_mmu_setup(struct kvm_vcpu *vcpu)
  1393. {
  1394. ASSERT(vcpu);
  1395. ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
  1396. return init_kvm_mmu(vcpu);
  1397. }
  1398. void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
  1399. {
  1400. ASSERT(vcpu);
  1401. destroy_kvm_mmu(vcpu);
  1402. free_mmu_pages(vcpu);
  1403. mmu_free_memory_caches(vcpu);
  1404. }
  1405. void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
  1406. {
  1407. struct kvm_mmu_page *sp;
  1408. list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
  1409. int i;
  1410. u64 *pt;
  1411. if (!test_bit(slot, &sp->slot_bitmap))
  1412. continue;
  1413. pt = sp->spt;
  1414. for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
  1415. /* avoid RMW */
  1416. if (pt[i] & PT_WRITABLE_MASK)
  1417. pt[i] &= ~PT_WRITABLE_MASK;
  1418. }
  1419. }
  1420. void kvm_mmu_zap_all(struct kvm *kvm)
  1421. {
  1422. struct kvm_mmu_page *sp, *node;
  1423. spin_lock(&kvm->mmu_lock);
  1424. list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
  1425. kvm_mmu_zap_page(kvm, sp);
  1426. spin_unlock(&kvm->mmu_lock);
  1427. kvm_flush_remote_tlbs(kvm);
  1428. }
  1429. void kvm_mmu_module_exit(void)
  1430. {
  1431. if (pte_chain_cache)
  1432. kmem_cache_destroy(pte_chain_cache);
  1433. if (rmap_desc_cache)
  1434. kmem_cache_destroy(rmap_desc_cache);
  1435. if (mmu_page_header_cache)
  1436. kmem_cache_destroy(mmu_page_header_cache);
  1437. }
  1438. int kvm_mmu_module_init(void)
  1439. {
  1440. pte_chain_cache = kmem_cache_create("kvm_pte_chain",
  1441. sizeof(struct kvm_pte_chain),
  1442. 0, 0, NULL);
  1443. if (!pte_chain_cache)
  1444. goto nomem;
  1445. rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
  1446. sizeof(struct kvm_rmap_desc),
  1447. 0, 0, NULL);
  1448. if (!rmap_desc_cache)
  1449. goto nomem;
  1450. mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
  1451. sizeof(struct kvm_mmu_page),
  1452. 0, 0, NULL);
  1453. if (!mmu_page_header_cache)
  1454. goto nomem;
  1455. return 0;
  1456. nomem:
  1457. kvm_mmu_module_exit();
  1458. return -ENOMEM;
  1459. }
  1460. /*
  1461. * Caculate mmu pages needed for kvm.
  1462. */
  1463. unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
  1464. {
  1465. int i;
  1466. unsigned int nr_mmu_pages;
  1467. unsigned int nr_pages = 0;
  1468. for (i = 0; i < kvm->nmemslots; i++)
  1469. nr_pages += kvm->memslots[i].npages;
  1470. nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
  1471. nr_mmu_pages = max(nr_mmu_pages,
  1472. (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
  1473. return nr_mmu_pages;
  1474. }
  1475. #ifdef AUDIT
  1476. static const char *audit_msg;
  1477. static gva_t canonicalize(gva_t gva)
  1478. {
  1479. #ifdef CONFIG_X86_64
  1480. gva = (long long)(gva << 16) >> 16;
  1481. #endif
  1482. return gva;
  1483. }
  1484. static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
  1485. gva_t va, int level)
  1486. {
  1487. u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
  1488. int i;
  1489. gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
  1490. for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
  1491. u64 ent = pt[i];
  1492. if (ent == shadow_trap_nonpresent_pte)
  1493. continue;
  1494. va = canonicalize(va);
  1495. if (level > 1) {
  1496. if (ent == shadow_notrap_nonpresent_pte)
  1497. printk(KERN_ERR "audit: (%s) nontrapping pte"
  1498. " in nonleaf level: levels %d gva %lx"
  1499. " level %d pte %llx\n", audit_msg,
  1500. vcpu->arch.mmu.root_level, va, level, ent);
  1501. audit_mappings_page(vcpu, ent, va, level - 1);
  1502. } else {
  1503. gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
  1504. struct page *page = gpa_to_page(vcpu, gpa);
  1505. hpa_t hpa = page_to_phys(page);
  1506. if (is_shadow_present_pte(ent)
  1507. && (ent & PT64_BASE_ADDR_MASK) != hpa)
  1508. printk(KERN_ERR "xx audit error: (%s) levels %d"
  1509. " gva %lx gpa %llx hpa %llx ent %llx %d\n",
  1510. audit_msg, vcpu->arch.mmu.root_level,
  1511. va, gpa, hpa, ent,
  1512. is_shadow_present_pte(ent));
  1513. else if (ent == shadow_notrap_nonpresent_pte
  1514. && !is_error_hpa(hpa))
  1515. printk(KERN_ERR "audit: (%s) notrap shadow,"
  1516. " valid guest gva %lx\n", audit_msg, va);
  1517. kvm_release_page_clean(page);
  1518. }
  1519. }
  1520. }
  1521. static void audit_mappings(struct kvm_vcpu *vcpu)
  1522. {
  1523. unsigned i;
  1524. if (vcpu->arch.mmu.root_level == 4)
  1525. audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
  1526. else
  1527. for (i = 0; i < 4; ++i)
  1528. if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
  1529. audit_mappings_page(vcpu,
  1530. vcpu->arch.mmu.pae_root[i],
  1531. i << 30,
  1532. 2);
  1533. }
  1534. static int count_rmaps(struct kvm_vcpu *vcpu)
  1535. {
  1536. int nmaps = 0;
  1537. int i, j, k;
  1538. for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
  1539. struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
  1540. struct kvm_rmap_desc *d;
  1541. for (j = 0; j < m->npages; ++j) {
  1542. unsigned long *rmapp = &m->rmap[j];
  1543. if (!*rmapp)
  1544. continue;
  1545. if (!(*rmapp & 1)) {
  1546. ++nmaps;
  1547. continue;
  1548. }
  1549. d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
  1550. while (d) {
  1551. for (k = 0; k < RMAP_EXT; ++k)
  1552. if (d->shadow_ptes[k])
  1553. ++nmaps;
  1554. else
  1555. break;
  1556. d = d->more;
  1557. }
  1558. }
  1559. }
  1560. return nmaps;
  1561. }
  1562. static int count_writable_mappings(struct kvm_vcpu *vcpu)
  1563. {
  1564. int nmaps = 0;
  1565. struct kvm_mmu_page *sp;
  1566. int i;
  1567. list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
  1568. u64 *pt = sp->spt;
  1569. if (sp->role.level != PT_PAGE_TABLE_LEVEL)
  1570. continue;
  1571. for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
  1572. u64 ent = pt[i];
  1573. if (!(ent & PT_PRESENT_MASK))
  1574. continue;
  1575. if (!(ent & PT_WRITABLE_MASK))
  1576. continue;
  1577. ++nmaps;
  1578. }
  1579. }
  1580. return nmaps;
  1581. }
  1582. static void audit_rmap(struct kvm_vcpu *vcpu)
  1583. {
  1584. int n_rmap = count_rmaps(vcpu);
  1585. int n_actual = count_writable_mappings(vcpu);
  1586. if (n_rmap != n_actual)
  1587. printk(KERN_ERR "%s: (%s) rmap %d actual %d\n",
  1588. __FUNCTION__, audit_msg, n_rmap, n_actual);
  1589. }
  1590. static void audit_write_protection(struct kvm_vcpu *vcpu)
  1591. {
  1592. struct kvm_mmu_page *sp;
  1593. struct kvm_memory_slot *slot;
  1594. unsigned long *rmapp;
  1595. gfn_t gfn;
  1596. list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
  1597. if (sp->role.metaphysical)
  1598. continue;
  1599. slot = gfn_to_memslot(vcpu->kvm, sp->gfn);
  1600. gfn = unalias_gfn(vcpu->kvm, sp->gfn);
  1601. rmapp = &slot->rmap[gfn - slot->base_gfn];
  1602. if (*rmapp)
  1603. printk(KERN_ERR "%s: (%s) shadow page has writable"
  1604. " mappings: gfn %lx role %x\n",
  1605. __FUNCTION__, audit_msg, sp->gfn,
  1606. sp->role.word);
  1607. }
  1608. }
  1609. static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
  1610. {
  1611. int olddbg = dbg;
  1612. dbg = 0;
  1613. audit_msg = msg;
  1614. audit_rmap(vcpu);
  1615. audit_write_protection(vcpu);
  1616. audit_mappings(vcpu);
  1617. dbg = olddbg;
  1618. }
  1619. #endif