intel_sdvo.c 85 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845
  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. /**
  110. * This is set if we detect output of sdvo device as LVDS and
  111. * have a valid fixed mode to use with the panel.
  112. */
  113. bool is_lvds;
  114. /**
  115. * This is sdvo fixed pannel mode pointer
  116. */
  117. struct drm_display_mode *sdvo_lvds_fixed_mode;
  118. /* DDC bus used by this SDVO encoder */
  119. uint8_t ddc_bus;
  120. /*
  121. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  122. */
  123. uint8_t dtd_sdvo_flags;
  124. };
  125. struct intel_sdvo_connector {
  126. struct intel_connector base;
  127. /* Mark the type of connector */
  128. uint16_t output_flag;
  129. enum hdmi_force_audio force_audio;
  130. /* This contains all current supported TV format */
  131. u8 tv_format_supported[TV_FORMAT_NUM];
  132. int format_supported_num;
  133. struct drm_property *tv_format;
  134. /* add the property for the SDVO-TV */
  135. struct drm_property *left;
  136. struct drm_property *right;
  137. struct drm_property *top;
  138. struct drm_property *bottom;
  139. struct drm_property *hpos;
  140. struct drm_property *vpos;
  141. struct drm_property *contrast;
  142. struct drm_property *saturation;
  143. struct drm_property *hue;
  144. struct drm_property *sharpness;
  145. struct drm_property *flicker_filter;
  146. struct drm_property *flicker_filter_adaptive;
  147. struct drm_property *flicker_filter_2d;
  148. struct drm_property *tv_chroma_filter;
  149. struct drm_property *tv_luma_filter;
  150. struct drm_property *dot_crawl;
  151. /* add the property for the SDVO-TV/LVDS */
  152. struct drm_property *brightness;
  153. /* Add variable to record current setting for the above property */
  154. u32 left_margin, right_margin, top_margin, bottom_margin;
  155. /* this is to get the range of margin.*/
  156. u32 max_hscan, max_vscan;
  157. u32 max_hpos, cur_hpos;
  158. u32 max_vpos, cur_vpos;
  159. u32 cur_brightness, max_brightness;
  160. u32 cur_contrast, max_contrast;
  161. u32 cur_saturation, max_saturation;
  162. u32 cur_hue, max_hue;
  163. u32 cur_sharpness, max_sharpness;
  164. u32 cur_flicker_filter, max_flicker_filter;
  165. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  166. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  167. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  168. u32 cur_tv_luma_filter, max_tv_luma_filter;
  169. u32 cur_dot_crawl, max_dot_crawl;
  170. };
  171. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  172. {
  173. return container_of(encoder, struct intel_sdvo, base.base);
  174. }
  175. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  176. {
  177. return container_of(intel_attached_encoder(connector),
  178. struct intel_sdvo, base);
  179. }
  180. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  181. {
  182. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  183. }
  184. static bool
  185. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  186. static bool
  187. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  188. struct intel_sdvo_connector *intel_sdvo_connector,
  189. int type);
  190. static bool
  191. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  192. struct intel_sdvo_connector *intel_sdvo_connector);
  193. /**
  194. * Writes the SDVOB or SDVOC with the given value, but always writes both
  195. * SDVOB and SDVOC to work around apparent hardware issues (according to
  196. * comments in the BIOS).
  197. */
  198. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  199. {
  200. struct drm_device *dev = intel_sdvo->base.base.dev;
  201. struct drm_i915_private *dev_priv = dev->dev_private;
  202. u32 bval = val, cval = val;
  203. int i;
  204. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  205. I915_WRITE(intel_sdvo->sdvo_reg, val);
  206. I915_READ(intel_sdvo->sdvo_reg);
  207. return;
  208. }
  209. if (intel_sdvo->sdvo_reg == SDVOB) {
  210. cval = I915_READ(SDVOC);
  211. } else {
  212. bval = I915_READ(SDVOB);
  213. }
  214. /*
  215. * Write the registers twice for luck. Sometimes,
  216. * writing them only once doesn't appear to 'stick'.
  217. * The BIOS does this too. Yay, magic
  218. */
  219. for (i = 0; i < 2; i++)
  220. {
  221. I915_WRITE(SDVOB, bval);
  222. I915_READ(SDVOB);
  223. I915_WRITE(SDVOC, cval);
  224. I915_READ(SDVOC);
  225. }
  226. }
  227. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  228. {
  229. struct i2c_msg msgs[] = {
  230. {
  231. .addr = intel_sdvo->slave_addr,
  232. .flags = 0,
  233. .len = 1,
  234. .buf = &addr,
  235. },
  236. {
  237. .addr = intel_sdvo->slave_addr,
  238. .flags = I2C_M_RD,
  239. .len = 1,
  240. .buf = ch,
  241. }
  242. };
  243. int ret;
  244. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  245. return true;
  246. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  247. return false;
  248. }
  249. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  250. /** Mapping of command numbers to names, for debug output */
  251. static const struct _sdvo_cmd_name {
  252. u8 cmd;
  253. const char *name;
  254. } sdvo_cmd_names[] = {
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  298. /* Add the op code for SDVO enhancements */
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  343. /* HDMI op code */
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  363. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  364. };
  365. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  366. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  367. const void *args, int args_len)
  368. {
  369. int i;
  370. DRM_DEBUG_KMS("%s: W: %02X ",
  371. SDVO_NAME(intel_sdvo), cmd);
  372. for (i = 0; i < args_len; i++)
  373. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  374. for (; i < 8; i++)
  375. DRM_LOG_KMS(" ");
  376. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  377. if (cmd == sdvo_cmd_names[i].cmd) {
  378. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  379. break;
  380. }
  381. }
  382. if (i == ARRAY_SIZE(sdvo_cmd_names))
  383. DRM_LOG_KMS("(%02X)", cmd);
  384. DRM_LOG_KMS("\n");
  385. }
  386. static const char *cmd_status_names[] = {
  387. "Power on",
  388. "Success",
  389. "Not supported",
  390. "Invalid arg",
  391. "Pending",
  392. "Target not specified",
  393. "Scaling not supported"
  394. };
  395. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  396. const void *args, int args_len)
  397. {
  398. u8 *buf, status;
  399. struct i2c_msg *msgs;
  400. int i, ret = true;
  401. /* Would be simpler to allocate both in one go ? */
  402. buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
  403. if (!buf)
  404. return false;
  405. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  406. if (!msgs) {
  407. kfree(buf);
  408. return false;
  409. }
  410. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  411. for (i = 0; i < args_len; i++) {
  412. msgs[i].addr = intel_sdvo->slave_addr;
  413. msgs[i].flags = 0;
  414. msgs[i].len = 2;
  415. msgs[i].buf = buf + 2 *i;
  416. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  417. buf[2*i + 1] = ((u8*)args)[i];
  418. }
  419. msgs[i].addr = intel_sdvo->slave_addr;
  420. msgs[i].flags = 0;
  421. msgs[i].len = 2;
  422. msgs[i].buf = buf + 2*i;
  423. buf[2*i + 0] = SDVO_I2C_OPCODE;
  424. buf[2*i + 1] = cmd;
  425. /* the following two are to read the response */
  426. status = SDVO_I2C_CMD_STATUS;
  427. msgs[i+1].addr = intel_sdvo->slave_addr;
  428. msgs[i+1].flags = 0;
  429. msgs[i+1].len = 1;
  430. msgs[i+1].buf = &status;
  431. msgs[i+2].addr = intel_sdvo->slave_addr;
  432. msgs[i+2].flags = I2C_M_RD;
  433. msgs[i+2].len = 1;
  434. msgs[i+2].buf = &status;
  435. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  436. if (ret < 0) {
  437. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  438. ret = false;
  439. goto out;
  440. }
  441. if (ret != i+3) {
  442. /* failure in I2C transfer */
  443. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  444. ret = false;
  445. }
  446. out:
  447. kfree(msgs);
  448. kfree(buf);
  449. return ret;
  450. }
  451. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  452. void *response, int response_len)
  453. {
  454. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  455. u8 status;
  456. int i;
  457. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  458. /*
  459. * The documentation states that all commands will be
  460. * processed within 15µs, and that we need only poll
  461. * the status byte a maximum of 3 times in order for the
  462. * command to be complete.
  463. *
  464. * Check 5 times in case the hardware failed to read the docs.
  465. *
  466. * Also beware that the first response by many devices is to
  467. * reply PENDING and stall for time. TVs are notorious for
  468. * requiring longer than specified to complete their replies.
  469. * Originally (in the DDX long ago), the delay was only ever 15ms
  470. * with an additional delay of 30ms applied for TVs added later after
  471. * many experiments. To accommodate both sets of delays, we do a
  472. * sequence of slow checks if the device is falling behind and fails
  473. * to reply within 5*15µs.
  474. */
  475. if (!intel_sdvo_read_byte(intel_sdvo,
  476. SDVO_I2C_CMD_STATUS,
  477. &status))
  478. goto log_fail;
  479. while (status == SDVO_CMD_STATUS_PENDING && --retry) {
  480. if (retry < 10)
  481. msleep(15);
  482. else
  483. udelay(15);
  484. if (!intel_sdvo_read_byte(intel_sdvo,
  485. SDVO_I2C_CMD_STATUS,
  486. &status))
  487. goto log_fail;
  488. }
  489. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  490. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  491. else
  492. DRM_LOG_KMS("(??? %d)", status);
  493. if (status != SDVO_CMD_STATUS_SUCCESS)
  494. goto log_fail;
  495. /* Read the command response */
  496. for (i = 0; i < response_len; i++) {
  497. if (!intel_sdvo_read_byte(intel_sdvo,
  498. SDVO_I2C_RETURN_0 + i,
  499. &((u8 *)response)[i]))
  500. goto log_fail;
  501. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  502. }
  503. DRM_LOG_KMS("\n");
  504. return true;
  505. log_fail:
  506. DRM_LOG_KMS("... failed\n");
  507. return false;
  508. }
  509. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  510. {
  511. if (mode->clock >= 100000)
  512. return 1;
  513. else if (mode->clock >= 50000)
  514. return 2;
  515. else
  516. return 4;
  517. }
  518. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  519. u8 ddc_bus)
  520. {
  521. /* This must be the immediately preceding write before the i2c xfer */
  522. return intel_sdvo_write_cmd(intel_sdvo,
  523. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  524. &ddc_bus, 1);
  525. }
  526. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  527. {
  528. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  529. return false;
  530. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  531. }
  532. static bool
  533. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  534. {
  535. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  536. return false;
  537. return intel_sdvo_read_response(intel_sdvo, value, len);
  538. }
  539. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  540. {
  541. struct intel_sdvo_set_target_input_args targets = {0};
  542. return intel_sdvo_set_value(intel_sdvo,
  543. SDVO_CMD_SET_TARGET_INPUT,
  544. &targets, sizeof(targets));
  545. }
  546. /**
  547. * Return whether each input is trained.
  548. *
  549. * This function is making an assumption about the layout of the response,
  550. * which should be checked against the docs.
  551. */
  552. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  553. {
  554. struct intel_sdvo_get_trained_inputs_response response;
  555. BUILD_BUG_ON(sizeof(response) != 1);
  556. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  557. &response, sizeof(response)))
  558. return false;
  559. *input_1 = response.input0_trained;
  560. *input_2 = response.input1_trained;
  561. return true;
  562. }
  563. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  564. u16 outputs)
  565. {
  566. return intel_sdvo_set_value(intel_sdvo,
  567. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  568. &outputs, sizeof(outputs));
  569. }
  570. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  571. u16 *outputs)
  572. {
  573. return intel_sdvo_get_value(intel_sdvo,
  574. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  575. outputs, sizeof(*outputs));
  576. }
  577. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  578. int mode)
  579. {
  580. u8 state = SDVO_ENCODER_STATE_ON;
  581. switch (mode) {
  582. case DRM_MODE_DPMS_ON:
  583. state = SDVO_ENCODER_STATE_ON;
  584. break;
  585. case DRM_MODE_DPMS_STANDBY:
  586. state = SDVO_ENCODER_STATE_STANDBY;
  587. break;
  588. case DRM_MODE_DPMS_SUSPEND:
  589. state = SDVO_ENCODER_STATE_SUSPEND;
  590. break;
  591. case DRM_MODE_DPMS_OFF:
  592. state = SDVO_ENCODER_STATE_OFF;
  593. break;
  594. }
  595. return intel_sdvo_set_value(intel_sdvo,
  596. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  597. }
  598. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  599. int *clock_min,
  600. int *clock_max)
  601. {
  602. struct intel_sdvo_pixel_clock_range clocks;
  603. BUILD_BUG_ON(sizeof(clocks) != 4);
  604. if (!intel_sdvo_get_value(intel_sdvo,
  605. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  606. &clocks, sizeof(clocks)))
  607. return false;
  608. /* Convert the values from units of 10 kHz to kHz. */
  609. *clock_min = clocks.min * 10;
  610. *clock_max = clocks.max * 10;
  611. return true;
  612. }
  613. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  614. u16 outputs)
  615. {
  616. return intel_sdvo_set_value(intel_sdvo,
  617. SDVO_CMD_SET_TARGET_OUTPUT,
  618. &outputs, sizeof(outputs));
  619. }
  620. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  621. struct intel_sdvo_dtd *dtd)
  622. {
  623. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  624. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  625. }
  626. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  627. struct intel_sdvo_dtd *dtd)
  628. {
  629. return intel_sdvo_set_timing(intel_sdvo,
  630. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  631. }
  632. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  633. struct intel_sdvo_dtd *dtd)
  634. {
  635. return intel_sdvo_set_timing(intel_sdvo,
  636. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  637. }
  638. static bool
  639. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  640. uint16_t clock,
  641. uint16_t width,
  642. uint16_t height)
  643. {
  644. struct intel_sdvo_preferred_input_timing_args args;
  645. memset(&args, 0, sizeof(args));
  646. args.clock = clock;
  647. args.width = width;
  648. args.height = height;
  649. args.interlace = 0;
  650. if (intel_sdvo->is_lvds &&
  651. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  652. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  653. args.scaled = 1;
  654. return intel_sdvo_set_value(intel_sdvo,
  655. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  656. &args, sizeof(args));
  657. }
  658. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  659. struct intel_sdvo_dtd *dtd)
  660. {
  661. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  662. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  663. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  664. &dtd->part1, sizeof(dtd->part1)) &&
  665. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  666. &dtd->part2, sizeof(dtd->part2));
  667. }
  668. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  669. {
  670. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  671. }
  672. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  673. const struct drm_display_mode *mode)
  674. {
  675. uint16_t width, height;
  676. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  677. uint16_t h_sync_offset, v_sync_offset;
  678. int mode_clock;
  679. width = mode->hdisplay;
  680. height = mode->vdisplay;
  681. /* do some mode translations */
  682. h_blank_len = mode->htotal - mode->hdisplay;
  683. h_sync_len = mode->hsync_end - mode->hsync_start;
  684. v_blank_len = mode->vtotal - mode->vdisplay;
  685. v_sync_len = mode->vsync_end - mode->vsync_start;
  686. h_sync_offset = mode->hsync_start - mode->hdisplay;
  687. v_sync_offset = mode->vsync_start - mode->vdisplay;
  688. mode_clock = mode->clock;
  689. mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
  690. mode_clock /= 10;
  691. dtd->part1.clock = mode_clock;
  692. dtd->part1.h_active = width & 0xff;
  693. dtd->part1.h_blank = h_blank_len & 0xff;
  694. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  695. ((h_blank_len >> 8) & 0xf);
  696. dtd->part1.v_active = height & 0xff;
  697. dtd->part1.v_blank = v_blank_len & 0xff;
  698. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  699. ((v_blank_len >> 8) & 0xf);
  700. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  701. dtd->part2.h_sync_width = h_sync_len & 0xff;
  702. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  703. (v_sync_len & 0xf);
  704. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  705. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  706. ((v_sync_len & 0x30) >> 4);
  707. dtd->part2.dtd_flags = 0x18;
  708. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  709. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  710. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  711. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  712. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  713. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  714. dtd->part2.sdvo_flags = 0;
  715. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  716. dtd->part2.reserved = 0;
  717. }
  718. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  719. const struct intel_sdvo_dtd *dtd)
  720. {
  721. mode->hdisplay = dtd->part1.h_active;
  722. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  723. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  724. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  725. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  726. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  727. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  728. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  729. mode->vdisplay = dtd->part1.v_active;
  730. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  731. mode->vsync_start = mode->vdisplay;
  732. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  733. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  734. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  735. mode->vsync_end = mode->vsync_start +
  736. (dtd->part2.v_sync_off_width & 0xf);
  737. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  738. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  739. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  740. mode->clock = dtd->part1.clock * 10;
  741. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  742. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  743. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  744. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  745. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  746. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  747. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  748. }
  749. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  750. {
  751. struct intel_sdvo_encode encode;
  752. BUILD_BUG_ON(sizeof(encode) != 2);
  753. return intel_sdvo_get_value(intel_sdvo,
  754. SDVO_CMD_GET_SUPP_ENCODE,
  755. &encode, sizeof(encode));
  756. }
  757. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  758. uint8_t mode)
  759. {
  760. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  761. }
  762. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  763. uint8_t mode)
  764. {
  765. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  766. }
  767. #if 0
  768. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  769. {
  770. int i, j;
  771. uint8_t set_buf_index[2];
  772. uint8_t av_split;
  773. uint8_t buf_size;
  774. uint8_t buf[48];
  775. uint8_t *pos;
  776. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  777. for (i = 0; i <= av_split; i++) {
  778. set_buf_index[0] = i; set_buf_index[1] = 0;
  779. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  780. set_buf_index, 2);
  781. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  782. intel_sdvo_read_response(encoder, &buf_size, 1);
  783. pos = buf;
  784. for (j = 0; j <= buf_size; j += 8) {
  785. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  786. NULL, 0);
  787. intel_sdvo_read_response(encoder, pos, 8);
  788. pos += 8;
  789. }
  790. }
  791. }
  792. #endif
  793. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  794. unsigned if_index, uint8_t tx_rate,
  795. uint8_t *data, unsigned length)
  796. {
  797. uint8_t set_buf_index[2] = { if_index, 0 };
  798. uint8_t hbuf_size, tmp[8];
  799. int i;
  800. if (!intel_sdvo_set_value(intel_sdvo,
  801. SDVO_CMD_SET_HBUF_INDEX,
  802. set_buf_index, 2))
  803. return false;
  804. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  805. &hbuf_size, 1))
  806. return false;
  807. /* Buffer size is 0 based, hooray! */
  808. hbuf_size++;
  809. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  810. if_index, length, hbuf_size);
  811. for (i = 0; i < hbuf_size; i += 8) {
  812. memset(tmp, 0, 8);
  813. if (i < length)
  814. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  815. if (!intel_sdvo_set_value(intel_sdvo,
  816. SDVO_CMD_SET_HBUF_DATA,
  817. tmp, 8))
  818. return false;
  819. }
  820. return intel_sdvo_set_value(intel_sdvo,
  821. SDVO_CMD_SET_HBUF_TXRATE,
  822. &tx_rate, 1);
  823. }
  824. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  825. {
  826. struct dip_infoframe avi_if = {
  827. .type = DIP_TYPE_AVI,
  828. .ver = DIP_VERSION_AVI,
  829. .len = DIP_LEN_AVI,
  830. };
  831. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  832. intel_dip_infoframe_csum(&avi_if);
  833. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  834. * we must not send the ecc field, either. */
  835. memcpy(sdvo_data, &avi_if, 3);
  836. sdvo_data[3] = avi_if.checksum;
  837. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  838. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  839. SDVO_HBUF_TX_VSYNC,
  840. sdvo_data, sizeof(sdvo_data));
  841. }
  842. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  843. {
  844. struct intel_sdvo_tv_format format;
  845. uint32_t format_map;
  846. format_map = 1 << intel_sdvo->tv_format_index;
  847. memset(&format, 0, sizeof(format));
  848. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  849. BUILD_BUG_ON(sizeof(format) != 6);
  850. return intel_sdvo_set_value(intel_sdvo,
  851. SDVO_CMD_SET_TV_FORMAT,
  852. &format, sizeof(format));
  853. }
  854. static bool
  855. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  856. const struct drm_display_mode *mode)
  857. {
  858. struct intel_sdvo_dtd output_dtd;
  859. if (!intel_sdvo_set_target_output(intel_sdvo,
  860. intel_sdvo->attached_output))
  861. return false;
  862. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  863. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  864. return false;
  865. return true;
  866. }
  867. /* Asks the sdvo controller for the preferred input mode given the output mode.
  868. * Unfortunately we have to set up the full output mode to do that. */
  869. static bool
  870. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  871. const struct drm_display_mode *mode,
  872. struct drm_display_mode *adjusted_mode)
  873. {
  874. struct intel_sdvo_dtd input_dtd;
  875. /* Reset the input timing to the screen. Assume always input 0. */
  876. if (!intel_sdvo_set_target_input(intel_sdvo))
  877. return false;
  878. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  879. mode->clock / 10,
  880. mode->hdisplay,
  881. mode->vdisplay))
  882. return false;
  883. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  884. &input_dtd))
  885. return false;
  886. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  887. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  888. return true;
  889. }
  890. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  891. const struct drm_display_mode *mode,
  892. struct drm_display_mode *adjusted_mode)
  893. {
  894. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  895. int multiplier;
  896. /* We need to construct preferred input timings based on our
  897. * output timings. To do that, we have to set the output
  898. * timings, even though this isn't really the right place in
  899. * the sequence to do it. Oh well.
  900. */
  901. if (intel_sdvo->is_tv) {
  902. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  903. return false;
  904. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  905. mode,
  906. adjusted_mode);
  907. } else if (intel_sdvo->is_lvds) {
  908. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  909. intel_sdvo->sdvo_lvds_fixed_mode))
  910. return false;
  911. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  912. mode,
  913. adjusted_mode);
  914. }
  915. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  916. * SDVO device will factor out the multiplier during mode_set.
  917. */
  918. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  919. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  920. if (intel_sdvo->color_range_auto) {
  921. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  922. if (intel_sdvo->has_hdmi_monitor &&
  923. drm_mode_cea_vic(adjusted_mode) > 1)
  924. intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
  925. else
  926. intel_sdvo->color_range = 0;
  927. }
  928. if (intel_sdvo->color_range)
  929. adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
  930. return true;
  931. }
  932. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  933. struct drm_display_mode *mode,
  934. struct drm_display_mode *adjusted_mode)
  935. {
  936. struct drm_device *dev = encoder->dev;
  937. struct drm_i915_private *dev_priv = dev->dev_private;
  938. struct drm_crtc *crtc = encoder->crtc;
  939. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  940. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  941. u32 sdvox;
  942. struct intel_sdvo_in_out_map in_out;
  943. struct intel_sdvo_dtd input_dtd, output_dtd;
  944. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  945. int rate;
  946. if (!mode)
  947. return;
  948. /* First, set the input mapping for the first input to our controlled
  949. * output. This is only correct if we're a single-input device, in
  950. * which case the first input is the output from the appropriate SDVO
  951. * channel on the motherboard. In a two-input device, the first input
  952. * will be SDVOB and the second SDVOC.
  953. */
  954. in_out.in0 = intel_sdvo->attached_output;
  955. in_out.in1 = 0;
  956. intel_sdvo_set_value(intel_sdvo,
  957. SDVO_CMD_SET_IN_OUT_MAP,
  958. &in_out, sizeof(in_out));
  959. /* Set the output timings to the screen */
  960. if (!intel_sdvo_set_target_output(intel_sdvo,
  961. intel_sdvo->attached_output))
  962. return;
  963. /* lvds has a special fixed output timing. */
  964. if (intel_sdvo->is_lvds)
  965. intel_sdvo_get_dtd_from_mode(&output_dtd,
  966. intel_sdvo->sdvo_lvds_fixed_mode);
  967. else
  968. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  969. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  970. DRM_INFO("Setting output timings on %s failed\n",
  971. SDVO_NAME(intel_sdvo));
  972. /* Set the input timing to the screen. Assume always input 0. */
  973. if (!intel_sdvo_set_target_input(intel_sdvo))
  974. return;
  975. if (intel_sdvo->has_hdmi_monitor) {
  976. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  977. intel_sdvo_set_colorimetry(intel_sdvo,
  978. SDVO_COLORIMETRY_RGB256);
  979. intel_sdvo_set_avi_infoframe(intel_sdvo);
  980. } else
  981. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  982. if (intel_sdvo->is_tv &&
  983. !intel_sdvo_set_tv_format(intel_sdvo))
  984. return;
  985. /* We have tried to get input timing in mode_fixup, and filled into
  986. * adjusted_mode.
  987. */
  988. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  989. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  990. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  991. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  992. DRM_INFO("Setting input timings on %s failed\n",
  993. SDVO_NAME(intel_sdvo));
  994. switch (pixel_multiplier) {
  995. default:
  996. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  997. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  998. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  999. }
  1000. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1001. return;
  1002. /* Set the SDVO control regs. */
  1003. if (INTEL_INFO(dev)->gen >= 4) {
  1004. /* The real mode polarity is set by the SDVO commands, using
  1005. * struct intel_sdvo_dtd. */
  1006. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1007. if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
  1008. sdvox |= intel_sdvo->color_range;
  1009. if (INTEL_INFO(dev)->gen < 5)
  1010. sdvox |= SDVO_BORDER_ENABLE;
  1011. } else {
  1012. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1013. switch (intel_sdvo->sdvo_reg) {
  1014. case SDVOB:
  1015. sdvox &= SDVOB_PRESERVE_MASK;
  1016. break;
  1017. case SDVOC:
  1018. sdvox &= SDVOC_PRESERVE_MASK;
  1019. break;
  1020. }
  1021. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1022. }
  1023. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1024. sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
  1025. else
  1026. sdvox |= TRANSCODER(intel_crtc->pipe);
  1027. if (intel_sdvo->has_hdmi_audio)
  1028. sdvox |= SDVO_AUDIO_ENABLE;
  1029. if (INTEL_INFO(dev)->gen >= 4) {
  1030. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1031. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1032. /* done in crtc_mode_set as it lives inside the dpll register */
  1033. } else {
  1034. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  1035. }
  1036. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1037. INTEL_INFO(dev)->gen < 5)
  1038. sdvox |= SDVO_STALL_SELECT;
  1039. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1040. }
  1041. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1042. {
  1043. struct intel_sdvo_connector *intel_sdvo_connector =
  1044. to_intel_sdvo_connector(&connector->base);
  1045. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1046. u16 active_outputs;
  1047. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1048. if (active_outputs & intel_sdvo_connector->output_flag)
  1049. return true;
  1050. else
  1051. return false;
  1052. }
  1053. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1054. enum pipe *pipe)
  1055. {
  1056. struct drm_device *dev = encoder->base.dev;
  1057. struct drm_i915_private *dev_priv = dev->dev_private;
  1058. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1059. u32 tmp;
  1060. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1061. if (!(tmp & SDVO_ENABLE))
  1062. return false;
  1063. if (HAS_PCH_CPT(dev))
  1064. *pipe = PORT_TO_PIPE_CPT(tmp);
  1065. else
  1066. *pipe = PORT_TO_PIPE(tmp);
  1067. return true;
  1068. }
  1069. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1070. {
  1071. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1072. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1073. u32 temp;
  1074. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1075. if (0)
  1076. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1077. DRM_MODE_DPMS_OFF);
  1078. temp = I915_READ(intel_sdvo->sdvo_reg);
  1079. if ((temp & SDVO_ENABLE) != 0) {
  1080. /* HW workaround for IBX, we need to move the port to
  1081. * transcoder A before disabling it. */
  1082. if (HAS_PCH_IBX(encoder->base.dev)) {
  1083. struct drm_crtc *crtc = encoder->base.crtc;
  1084. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1085. if (temp & SDVO_PIPE_B_SELECT) {
  1086. temp &= ~SDVO_PIPE_B_SELECT;
  1087. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1088. POSTING_READ(intel_sdvo->sdvo_reg);
  1089. /* Again we need to write this twice. */
  1090. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1091. POSTING_READ(intel_sdvo->sdvo_reg);
  1092. /* Transcoder selection bits only update
  1093. * effectively on vblank. */
  1094. if (crtc)
  1095. intel_wait_for_vblank(encoder->base.dev, pipe);
  1096. else
  1097. msleep(50);
  1098. }
  1099. }
  1100. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1101. }
  1102. }
  1103. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1104. {
  1105. struct drm_device *dev = encoder->base.dev;
  1106. struct drm_i915_private *dev_priv = dev->dev_private;
  1107. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1108. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1109. u32 temp;
  1110. bool input1, input2;
  1111. int i;
  1112. u8 status;
  1113. temp = I915_READ(intel_sdvo->sdvo_reg);
  1114. if ((temp & SDVO_ENABLE) == 0) {
  1115. /* HW workaround for IBX, we need to move the port
  1116. * to transcoder A before disabling it. */
  1117. if (HAS_PCH_IBX(dev)) {
  1118. struct drm_crtc *crtc = encoder->base.crtc;
  1119. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1120. /* Restore the transcoder select bit. */
  1121. if (pipe == PIPE_B)
  1122. temp |= SDVO_PIPE_B_SELECT;
  1123. }
  1124. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1125. }
  1126. for (i = 0; i < 2; i++)
  1127. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1128. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1129. /* Warn if the device reported failure to sync.
  1130. * A lot of SDVO devices fail to notify of sync, but it's
  1131. * a given it the status is a success, we succeeded.
  1132. */
  1133. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1134. DRM_DEBUG_KMS("First %s output reported failure to "
  1135. "sync\n", SDVO_NAME(intel_sdvo));
  1136. }
  1137. if (0)
  1138. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1139. DRM_MODE_DPMS_ON);
  1140. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1141. }
  1142. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1143. {
  1144. struct drm_crtc *crtc;
  1145. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1146. /* dvo supports only 2 dpms states. */
  1147. if (mode != DRM_MODE_DPMS_ON)
  1148. mode = DRM_MODE_DPMS_OFF;
  1149. if (mode == connector->dpms)
  1150. return;
  1151. connector->dpms = mode;
  1152. /* Only need to change hw state when actually enabled */
  1153. crtc = intel_sdvo->base.base.crtc;
  1154. if (!crtc) {
  1155. intel_sdvo->base.connectors_active = false;
  1156. return;
  1157. }
  1158. if (mode != DRM_MODE_DPMS_ON) {
  1159. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1160. if (0)
  1161. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1162. intel_sdvo->base.connectors_active = false;
  1163. intel_crtc_update_dpms(crtc);
  1164. } else {
  1165. intel_sdvo->base.connectors_active = true;
  1166. intel_crtc_update_dpms(crtc);
  1167. if (0)
  1168. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1169. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1170. }
  1171. intel_modeset_check_state(connector->dev);
  1172. }
  1173. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1174. struct drm_display_mode *mode)
  1175. {
  1176. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1177. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1178. return MODE_NO_DBLESCAN;
  1179. if (intel_sdvo->pixel_clock_min > mode->clock)
  1180. return MODE_CLOCK_LOW;
  1181. if (intel_sdvo->pixel_clock_max < mode->clock)
  1182. return MODE_CLOCK_HIGH;
  1183. if (intel_sdvo->is_lvds) {
  1184. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1185. return MODE_PANEL;
  1186. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1187. return MODE_PANEL;
  1188. }
  1189. return MODE_OK;
  1190. }
  1191. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1192. {
  1193. BUILD_BUG_ON(sizeof(*caps) != 8);
  1194. if (!intel_sdvo_get_value(intel_sdvo,
  1195. SDVO_CMD_GET_DEVICE_CAPS,
  1196. caps, sizeof(*caps)))
  1197. return false;
  1198. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1199. " vendor_id: %d\n"
  1200. " device_id: %d\n"
  1201. " device_rev_id: %d\n"
  1202. " sdvo_version_major: %d\n"
  1203. " sdvo_version_minor: %d\n"
  1204. " sdvo_inputs_mask: %d\n"
  1205. " smooth_scaling: %d\n"
  1206. " sharp_scaling: %d\n"
  1207. " up_scaling: %d\n"
  1208. " down_scaling: %d\n"
  1209. " stall_support: %d\n"
  1210. " output_flags: %d\n",
  1211. caps->vendor_id,
  1212. caps->device_id,
  1213. caps->device_rev_id,
  1214. caps->sdvo_version_major,
  1215. caps->sdvo_version_minor,
  1216. caps->sdvo_inputs_mask,
  1217. caps->smooth_scaling,
  1218. caps->sharp_scaling,
  1219. caps->up_scaling,
  1220. caps->down_scaling,
  1221. caps->stall_support,
  1222. caps->output_flags);
  1223. return true;
  1224. }
  1225. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1226. {
  1227. struct drm_device *dev = intel_sdvo->base.base.dev;
  1228. uint16_t hotplug;
  1229. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1230. * on the line. */
  1231. if (IS_I945G(dev) || IS_I945GM(dev))
  1232. return 0;
  1233. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1234. &hotplug, sizeof(hotplug)))
  1235. return 0;
  1236. return hotplug;
  1237. }
  1238. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1239. {
  1240. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1241. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1242. &intel_sdvo->hotplug_active, 2);
  1243. }
  1244. static bool
  1245. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1246. {
  1247. /* Is there more than one type of output? */
  1248. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1249. }
  1250. static struct edid *
  1251. intel_sdvo_get_edid(struct drm_connector *connector)
  1252. {
  1253. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1254. return drm_get_edid(connector, &sdvo->ddc);
  1255. }
  1256. /* Mac mini hack -- use the same DDC as the analog connector */
  1257. static struct edid *
  1258. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1259. {
  1260. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1261. return drm_get_edid(connector,
  1262. intel_gmbus_get_adapter(dev_priv,
  1263. dev_priv->crt_ddc_pin));
  1264. }
  1265. static enum drm_connector_status
  1266. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1267. {
  1268. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1269. enum drm_connector_status status;
  1270. struct edid *edid;
  1271. edid = intel_sdvo_get_edid(connector);
  1272. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1273. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1274. /*
  1275. * Don't use the 1 as the argument of DDC bus switch to get
  1276. * the EDID. It is used for SDVO SPD ROM.
  1277. */
  1278. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1279. intel_sdvo->ddc_bus = ddc;
  1280. edid = intel_sdvo_get_edid(connector);
  1281. if (edid)
  1282. break;
  1283. }
  1284. /*
  1285. * If we found the EDID on the other bus,
  1286. * assume that is the correct DDC bus.
  1287. */
  1288. if (edid == NULL)
  1289. intel_sdvo->ddc_bus = saved_ddc;
  1290. }
  1291. /*
  1292. * When there is no edid and no monitor is connected with VGA
  1293. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1294. */
  1295. if (edid == NULL)
  1296. edid = intel_sdvo_get_analog_edid(connector);
  1297. status = connector_status_unknown;
  1298. if (edid != NULL) {
  1299. /* DDC bus is shared, match EDID to connector type */
  1300. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1301. status = connector_status_connected;
  1302. if (intel_sdvo->is_hdmi) {
  1303. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1304. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1305. }
  1306. } else
  1307. status = connector_status_disconnected;
  1308. kfree(edid);
  1309. }
  1310. if (status == connector_status_connected) {
  1311. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1312. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1313. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1314. }
  1315. return status;
  1316. }
  1317. static bool
  1318. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1319. struct edid *edid)
  1320. {
  1321. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1322. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1323. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1324. connector_is_digital, monitor_is_digital);
  1325. return connector_is_digital == monitor_is_digital;
  1326. }
  1327. static enum drm_connector_status
  1328. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1329. {
  1330. uint16_t response;
  1331. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1332. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1333. enum drm_connector_status ret;
  1334. if (!intel_sdvo_get_value(intel_sdvo,
  1335. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1336. &response, 2))
  1337. return connector_status_unknown;
  1338. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1339. response & 0xff, response >> 8,
  1340. intel_sdvo_connector->output_flag);
  1341. if (response == 0)
  1342. return connector_status_disconnected;
  1343. intel_sdvo->attached_output = response;
  1344. intel_sdvo->has_hdmi_monitor = false;
  1345. intel_sdvo->has_hdmi_audio = false;
  1346. if ((intel_sdvo_connector->output_flag & response) == 0)
  1347. ret = connector_status_disconnected;
  1348. else if (IS_TMDS(intel_sdvo_connector))
  1349. ret = intel_sdvo_tmds_sink_detect(connector);
  1350. else {
  1351. struct edid *edid;
  1352. /* if we have an edid check it matches the connection */
  1353. edid = intel_sdvo_get_edid(connector);
  1354. if (edid == NULL)
  1355. edid = intel_sdvo_get_analog_edid(connector);
  1356. if (edid != NULL) {
  1357. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1358. edid))
  1359. ret = connector_status_connected;
  1360. else
  1361. ret = connector_status_disconnected;
  1362. kfree(edid);
  1363. } else
  1364. ret = connector_status_connected;
  1365. }
  1366. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1367. if (ret == connector_status_connected) {
  1368. intel_sdvo->is_tv = false;
  1369. intel_sdvo->is_lvds = false;
  1370. intel_sdvo->base.needs_tv_clock = false;
  1371. if (response & SDVO_TV_MASK) {
  1372. intel_sdvo->is_tv = true;
  1373. intel_sdvo->base.needs_tv_clock = true;
  1374. }
  1375. if (response & SDVO_LVDS_MASK)
  1376. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1377. }
  1378. return ret;
  1379. }
  1380. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1381. {
  1382. struct edid *edid;
  1383. /* set the bus switch and get the modes */
  1384. edid = intel_sdvo_get_edid(connector);
  1385. /*
  1386. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1387. * link between analog and digital outputs. So, if the regular SDVO
  1388. * DDC fails, check to see if the analog output is disconnected, in
  1389. * which case we'll look there for the digital DDC data.
  1390. */
  1391. if (edid == NULL)
  1392. edid = intel_sdvo_get_analog_edid(connector);
  1393. if (edid != NULL) {
  1394. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1395. edid)) {
  1396. drm_mode_connector_update_edid_property(connector, edid);
  1397. drm_add_edid_modes(connector, edid);
  1398. }
  1399. kfree(edid);
  1400. }
  1401. }
  1402. /*
  1403. * Set of SDVO TV modes.
  1404. * Note! This is in reply order (see loop in get_tv_modes).
  1405. * XXX: all 60Hz refresh?
  1406. */
  1407. static const struct drm_display_mode sdvo_tv_modes[] = {
  1408. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1409. 416, 0, 200, 201, 232, 233, 0,
  1410. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1411. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1412. 416, 0, 240, 241, 272, 273, 0,
  1413. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1414. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1415. 496, 0, 300, 301, 332, 333, 0,
  1416. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1417. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1418. 736, 0, 350, 351, 382, 383, 0,
  1419. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1420. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1421. 736, 0, 400, 401, 432, 433, 0,
  1422. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1423. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1424. 736, 0, 480, 481, 512, 513, 0,
  1425. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1426. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1427. 800, 0, 480, 481, 512, 513, 0,
  1428. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1429. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1430. 800, 0, 576, 577, 608, 609, 0,
  1431. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1432. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1433. 816, 0, 350, 351, 382, 383, 0,
  1434. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1435. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1436. 816, 0, 400, 401, 432, 433, 0,
  1437. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1438. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1439. 816, 0, 480, 481, 512, 513, 0,
  1440. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1441. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1442. 816, 0, 540, 541, 572, 573, 0,
  1443. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1444. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1445. 816, 0, 576, 577, 608, 609, 0,
  1446. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1447. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1448. 864, 0, 576, 577, 608, 609, 0,
  1449. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1450. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1451. 896, 0, 600, 601, 632, 633, 0,
  1452. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1453. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1454. 928, 0, 624, 625, 656, 657, 0,
  1455. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1456. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1457. 1016, 0, 766, 767, 798, 799, 0,
  1458. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1459. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1460. 1120, 0, 768, 769, 800, 801, 0,
  1461. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1462. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1463. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1464. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1465. };
  1466. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1467. {
  1468. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1469. struct intel_sdvo_sdtv_resolution_request tv_res;
  1470. uint32_t reply = 0, format_map = 0;
  1471. int i;
  1472. /* Read the list of supported input resolutions for the selected TV
  1473. * format.
  1474. */
  1475. format_map = 1 << intel_sdvo->tv_format_index;
  1476. memcpy(&tv_res, &format_map,
  1477. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1478. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1479. return;
  1480. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1481. if (!intel_sdvo_write_cmd(intel_sdvo,
  1482. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1483. &tv_res, sizeof(tv_res)))
  1484. return;
  1485. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1486. return;
  1487. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1488. if (reply & (1 << i)) {
  1489. struct drm_display_mode *nmode;
  1490. nmode = drm_mode_duplicate(connector->dev,
  1491. &sdvo_tv_modes[i]);
  1492. if (nmode)
  1493. drm_mode_probed_add(connector, nmode);
  1494. }
  1495. }
  1496. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1497. {
  1498. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1499. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1500. struct drm_display_mode *newmode;
  1501. /*
  1502. * Attempt to get the mode list from DDC.
  1503. * Assume that the preferred modes are
  1504. * arranged in priority order.
  1505. */
  1506. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1507. if (list_empty(&connector->probed_modes) == false)
  1508. goto end;
  1509. /* Fetch modes from VBT */
  1510. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1511. newmode = drm_mode_duplicate(connector->dev,
  1512. dev_priv->sdvo_lvds_vbt_mode);
  1513. if (newmode != NULL) {
  1514. /* Guarantee the mode is preferred */
  1515. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1516. DRM_MODE_TYPE_DRIVER);
  1517. drm_mode_probed_add(connector, newmode);
  1518. }
  1519. }
  1520. end:
  1521. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1522. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1523. intel_sdvo->sdvo_lvds_fixed_mode =
  1524. drm_mode_duplicate(connector->dev, newmode);
  1525. intel_sdvo->is_lvds = true;
  1526. break;
  1527. }
  1528. }
  1529. }
  1530. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1531. {
  1532. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1533. if (IS_TV(intel_sdvo_connector))
  1534. intel_sdvo_get_tv_modes(connector);
  1535. else if (IS_LVDS(intel_sdvo_connector))
  1536. intel_sdvo_get_lvds_modes(connector);
  1537. else
  1538. intel_sdvo_get_ddc_modes(connector);
  1539. return !list_empty(&connector->probed_modes);
  1540. }
  1541. static void
  1542. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1543. {
  1544. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1545. struct drm_device *dev = connector->dev;
  1546. if (intel_sdvo_connector->left)
  1547. drm_property_destroy(dev, intel_sdvo_connector->left);
  1548. if (intel_sdvo_connector->right)
  1549. drm_property_destroy(dev, intel_sdvo_connector->right);
  1550. if (intel_sdvo_connector->top)
  1551. drm_property_destroy(dev, intel_sdvo_connector->top);
  1552. if (intel_sdvo_connector->bottom)
  1553. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1554. if (intel_sdvo_connector->hpos)
  1555. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1556. if (intel_sdvo_connector->vpos)
  1557. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1558. if (intel_sdvo_connector->saturation)
  1559. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1560. if (intel_sdvo_connector->contrast)
  1561. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1562. if (intel_sdvo_connector->hue)
  1563. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1564. if (intel_sdvo_connector->sharpness)
  1565. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1566. if (intel_sdvo_connector->flicker_filter)
  1567. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1568. if (intel_sdvo_connector->flicker_filter_2d)
  1569. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1570. if (intel_sdvo_connector->flicker_filter_adaptive)
  1571. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1572. if (intel_sdvo_connector->tv_luma_filter)
  1573. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1574. if (intel_sdvo_connector->tv_chroma_filter)
  1575. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1576. if (intel_sdvo_connector->dot_crawl)
  1577. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1578. if (intel_sdvo_connector->brightness)
  1579. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1580. }
  1581. static void intel_sdvo_destroy(struct drm_connector *connector)
  1582. {
  1583. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1584. if (intel_sdvo_connector->tv_format)
  1585. drm_property_destroy(connector->dev,
  1586. intel_sdvo_connector->tv_format);
  1587. intel_sdvo_destroy_enhance_property(connector);
  1588. drm_sysfs_connector_remove(connector);
  1589. drm_connector_cleanup(connector);
  1590. kfree(intel_sdvo_connector);
  1591. }
  1592. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1593. {
  1594. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1595. struct edid *edid;
  1596. bool has_audio = false;
  1597. if (!intel_sdvo->is_hdmi)
  1598. return false;
  1599. edid = intel_sdvo_get_edid(connector);
  1600. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1601. has_audio = drm_detect_monitor_audio(edid);
  1602. kfree(edid);
  1603. return has_audio;
  1604. }
  1605. static int
  1606. intel_sdvo_set_property(struct drm_connector *connector,
  1607. struct drm_property *property,
  1608. uint64_t val)
  1609. {
  1610. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1611. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1612. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1613. uint16_t temp_value;
  1614. uint8_t cmd;
  1615. int ret;
  1616. ret = drm_object_property_set_value(&connector->base, property, val);
  1617. if (ret)
  1618. return ret;
  1619. if (property == dev_priv->force_audio_property) {
  1620. int i = val;
  1621. bool has_audio;
  1622. if (i == intel_sdvo_connector->force_audio)
  1623. return 0;
  1624. intel_sdvo_connector->force_audio = i;
  1625. if (i == HDMI_AUDIO_AUTO)
  1626. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1627. else
  1628. has_audio = (i == HDMI_AUDIO_ON);
  1629. if (has_audio == intel_sdvo->has_hdmi_audio)
  1630. return 0;
  1631. intel_sdvo->has_hdmi_audio = has_audio;
  1632. goto done;
  1633. }
  1634. if (property == dev_priv->broadcast_rgb_property) {
  1635. switch (val) {
  1636. case INTEL_BROADCAST_RGB_AUTO:
  1637. intel_sdvo->color_range_auto = true;
  1638. break;
  1639. case INTEL_BROADCAST_RGB_FULL:
  1640. intel_sdvo->color_range_auto = false;
  1641. intel_sdvo->color_range = 0;
  1642. break;
  1643. case INTEL_BROADCAST_RGB_LIMITED:
  1644. intel_sdvo->color_range_auto = false;
  1645. intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
  1646. break;
  1647. default:
  1648. return -EINVAL;
  1649. }
  1650. goto done;
  1651. }
  1652. #define CHECK_PROPERTY(name, NAME) \
  1653. if (intel_sdvo_connector->name == property) { \
  1654. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1655. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1656. cmd = SDVO_CMD_SET_##NAME; \
  1657. intel_sdvo_connector->cur_##name = temp_value; \
  1658. goto set_value; \
  1659. }
  1660. if (property == intel_sdvo_connector->tv_format) {
  1661. if (val >= TV_FORMAT_NUM)
  1662. return -EINVAL;
  1663. if (intel_sdvo->tv_format_index ==
  1664. intel_sdvo_connector->tv_format_supported[val])
  1665. return 0;
  1666. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1667. goto done;
  1668. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1669. temp_value = val;
  1670. if (intel_sdvo_connector->left == property) {
  1671. drm_object_property_set_value(&connector->base,
  1672. intel_sdvo_connector->right, val);
  1673. if (intel_sdvo_connector->left_margin == temp_value)
  1674. return 0;
  1675. intel_sdvo_connector->left_margin = temp_value;
  1676. intel_sdvo_connector->right_margin = temp_value;
  1677. temp_value = intel_sdvo_connector->max_hscan -
  1678. intel_sdvo_connector->left_margin;
  1679. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1680. goto set_value;
  1681. } else if (intel_sdvo_connector->right == property) {
  1682. drm_object_property_set_value(&connector->base,
  1683. intel_sdvo_connector->left, val);
  1684. if (intel_sdvo_connector->right_margin == temp_value)
  1685. return 0;
  1686. intel_sdvo_connector->left_margin = temp_value;
  1687. intel_sdvo_connector->right_margin = temp_value;
  1688. temp_value = intel_sdvo_connector->max_hscan -
  1689. intel_sdvo_connector->left_margin;
  1690. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1691. goto set_value;
  1692. } else if (intel_sdvo_connector->top == property) {
  1693. drm_object_property_set_value(&connector->base,
  1694. intel_sdvo_connector->bottom, val);
  1695. if (intel_sdvo_connector->top_margin == temp_value)
  1696. return 0;
  1697. intel_sdvo_connector->top_margin = temp_value;
  1698. intel_sdvo_connector->bottom_margin = temp_value;
  1699. temp_value = intel_sdvo_connector->max_vscan -
  1700. intel_sdvo_connector->top_margin;
  1701. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1702. goto set_value;
  1703. } else if (intel_sdvo_connector->bottom == property) {
  1704. drm_object_property_set_value(&connector->base,
  1705. intel_sdvo_connector->top, val);
  1706. if (intel_sdvo_connector->bottom_margin == temp_value)
  1707. return 0;
  1708. intel_sdvo_connector->top_margin = temp_value;
  1709. intel_sdvo_connector->bottom_margin = temp_value;
  1710. temp_value = intel_sdvo_connector->max_vscan -
  1711. intel_sdvo_connector->top_margin;
  1712. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1713. goto set_value;
  1714. }
  1715. CHECK_PROPERTY(hpos, HPOS)
  1716. CHECK_PROPERTY(vpos, VPOS)
  1717. CHECK_PROPERTY(saturation, SATURATION)
  1718. CHECK_PROPERTY(contrast, CONTRAST)
  1719. CHECK_PROPERTY(hue, HUE)
  1720. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1721. CHECK_PROPERTY(sharpness, SHARPNESS)
  1722. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1723. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1724. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1725. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1726. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1727. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1728. }
  1729. return -EINVAL; /* unknown property */
  1730. set_value:
  1731. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1732. return -EIO;
  1733. done:
  1734. if (intel_sdvo->base.base.crtc)
  1735. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1736. return 0;
  1737. #undef CHECK_PROPERTY
  1738. }
  1739. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1740. .mode_fixup = intel_sdvo_mode_fixup,
  1741. .mode_set = intel_sdvo_mode_set,
  1742. .disable = intel_encoder_noop,
  1743. };
  1744. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1745. .dpms = intel_sdvo_dpms,
  1746. .detect = intel_sdvo_detect,
  1747. .fill_modes = drm_helper_probe_single_connector_modes,
  1748. .set_property = intel_sdvo_set_property,
  1749. .destroy = intel_sdvo_destroy,
  1750. };
  1751. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1752. .get_modes = intel_sdvo_get_modes,
  1753. .mode_valid = intel_sdvo_mode_valid,
  1754. .best_encoder = intel_best_encoder,
  1755. };
  1756. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1757. {
  1758. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1759. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1760. drm_mode_destroy(encoder->dev,
  1761. intel_sdvo->sdvo_lvds_fixed_mode);
  1762. i2c_del_adapter(&intel_sdvo->ddc);
  1763. intel_encoder_destroy(encoder);
  1764. }
  1765. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1766. .destroy = intel_sdvo_enc_destroy,
  1767. };
  1768. static void
  1769. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1770. {
  1771. uint16_t mask = 0;
  1772. unsigned int num_bits;
  1773. /* Make a mask of outputs less than or equal to our own priority in the
  1774. * list.
  1775. */
  1776. switch (sdvo->controlled_output) {
  1777. case SDVO_OUTPUT_LVDS1:
  1778. mask |= SDVO_OUTPUT_LVDS1;
  1779. case SDVO_OUTPUT_LVDS0:
  1780. mask |= SDVO_OUTPUT_LVDS0;
  1781. case SDVO_OUTPUT_TMDS1:
  1782. mask |= SDVO_OUTPUT_TMDS1;
  1783. case SDVO_OUTPUT_TMDS0:
  1784. mask |= SDVO_OUTPUT_TMDS0;
  1785. case SDVO_OUTPUT_RGB1:
  1786. mask |= SDVO_OUTPUT_RGB1;
  1787. case SDVO_OUTPUT_RGB0:
  1788. mask |= SDVO_OUTPUT_RGB0;
  1789. break;
  1790. }
  1791. /* Count bits to find what number we are in the priority list. */
  1792. mask &= sdvo->caps.output_flags;
  1793. num_bits = hweight16(mask);
  1794. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1795. if (num_bits > 3)
  1796. num_bits = 3;
  1797. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1798. sdvo->ddc_bus = 1 << num_bits;
  1799. }
  1800. /**
  1801. * Choose the appropriate DDC bus for control bus switch command for this
  1802. * SDVO output based on the controlled output.
  1803. *
  1804. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1805. * outputs, then LVDS outputs.
  1806. */
  1807. static void
  1808. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1809. struct intel_sdvo *sdvo, u32 reg)
  1810. {
  1811. struct sdvo_device_mapping *mapping;
  1812. if (sdvo->is_sdvob)
  1813. mapping = &(dev_priv->sdvo_mappings[0]);
  1814. else
  1815. mapping = &(dev_priv->sdvo_mappings[1]);
  1816. if (mapping->initialized)
  1817. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1818. else
  1819. intel_sdvo_guess_ddc_bus(sdvo);
  1820. }
  1821. static void
  1822. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1823. struct intel_sdvo *sdvo, u32 reg)
  1824. {
  1825. struct sdvo_device_mapping *mapping;
  1826. u8 pin;
  1827. if (sdvo->is_sdvob)
  1828. mapping = &dev_priv->sdvo_mappings[0];
  1829. else
  1830. mapping = &dev_priv->sdvo_mappings[1];
  1831. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1832. pin = mapping->i2c_pin;
  1833. else
  1834. pin = GMBUS_PORT_DPB;
  1835. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1836. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1837. * our code totally fails once we start using gmbus. Hence fall back to
  1838. * bit banging for now. */
  1839. intel_gmbus_force_bit(sdvo->i2c, true);
  1840. }
  1841. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  1842. static void
  1843. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  1844. {
  1845. intel_gmbus_force_bit(sdvo->i2c, false);
  1846. }
  1847. static bool
  1848. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1849. {
  1850. return intel_sdvo_check_supp_encode(intel_sdvo);
  1851. }
  1852. static u8
  1853. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1854. {
  1855. struct drm_i915_private *dev_priv = dev->dev_private;
  1856. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1857. if (sdvo->is_sdvob) {
  1858. my_mapping = &dev_priv->sdvo_mappings[0];
  1859. other_mapping = &dev_priv->sdvo_mappings[1];
  1860. } else {
  1861. my_mapping = &dev_priv->sdvo_mappings[1];
  1862. other_mapping = &dev_priv->sdvo_mappings[0];
  1863. }
  1864. /* If the BIOS described our SDVO device, take advantage of it. */
  1865. if (my_mapping->slave_addr)
  1866. return my_mapping->slave_addr;
  1867. /* If the BIOS only described a different SDVO device, use the
  1868. * address that it isn't using.
  1869. */
  1870. if (other_mapping->slave_addr) {
  1871. if (other_mapping->slave_addr == 0x70)
  1872. return 0x72;
  1873. else
  1874. return 0x70;
  1875. }
  1876. /* No SDVO device info is found for another DVO port,
  1877. * so use mapping assumption we had before BIOS parsing.
  1878. */
  1879. if (sdvo->is_sdvob)
  1880. return 0x70;
  1881. else
  1882. return 0x72;
  1883. }
  1884. static void
  1885. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1886. struct intel_sdvo *encoder)
  1887. {
  1888. drm_connector_init(encoder->base.base.dev,
  1889. &connector->base.base,
  1890. &intel_sdvo_connector_funcs,
  1891. connector->base.base.connector_type);
  1892. drm_connector_helper_add(&connector->base.base,
  1893. &intel_sdvo_connector_helper_funcs);
  1894. connector->base.base.interlace_allowed = 1;
  1895. connector->base.base.doublescan_allowed = 0;
  1896. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1897. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  1898. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1899. drm_sysfs_connector_add(&connector->base.base);
  1900. }
  1901. static void
  1902. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  1903. struct intel_sdvo_connector *connector)
  1904. {
  1905. struct drm_device *dev = connector->base.base.dev;
  1906. intel_attach_force_audio_property(&connector->base.base);
  1907. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  1908. intel_attach_broadcast_rgb_property(&connector->base.base);
  1909. intel_sdvo->color_range_auto = true;
  1910. }
  1911. }
  1912. static bool
  1913. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1914. {
  1915. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1916. struct drm_connector *connector;
  1917. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1918. struct intel_connector *intel_connector;
  1919. struct intel_sdvo_connector *intel_sdvo_connector;
  1920. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1921. if (!intel_sdvo_connector)
  1922. return false;
  1923. if (device == 0) {
  1924. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1925. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1926. } else if (device == 1) {
  1927. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1928. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1929. }
  1930. intel_connector = &intel_sdvo_connector->base;
  1931. connector = &intel_connector->base;
  1932. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  1933. intel_sdvo_connector->output_flag) {
  1934. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1935. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  1936. /* Some SDVO devices have one-shot hotplug interrupts.
  1937. * Ensure that they get re-enabled when an interrupt happens.
  1938. */
  1939. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1940. intel_sdvo_enable_hotplug(intel_encoder);
  1941. } else {
  1942. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1943. }
  1944. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1945. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1946. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1947. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1948. intel_sdvo->is_hdmi = true;
  1949. }
  1950. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1951. if (intel_sdvo->is_hdmi)
  1952. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  1953. return true;
  1954. }
  1955. static bool
  1956. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1957. {
  1958. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1959. struct drm_connector *connector;
  1960. struct intel_connector *intel_connector;
  1961. struct intel_sdvo_connector *intel_sdvo_connector;
  1962. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1963. if (!intel_sdvo_connector)
  1964. return false;
  1965. intel_connector = &intel_sdvo_connector->base;
  1966. connector = &intel_connector->base;
  1967. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1968. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1969. intel_sdvo->controlled_output |= type;
  1970. intel_sdvo_connector->output_flag = type;
  1971. intel_sdvo->is_tv = true;
  1972. intel_sdvo->base.needs_tv_clock = true;
  1973. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1974. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1975. goto err;
  1976. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1977. goto err;
  1978. return true;
  1979. err:
  1980. intel_sdvo_destroy(connector);
  1981. return false;
  1982. }
  1983. static bool
  1984. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1985. {
  1986. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1987. struct drm_connector *connector;
  1988. struct intel_connector *intel_connector;
  1989. struct intel_sdvo_connector *intel_sdvo_connector;
  1990. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1991. if (!intel_sdvo_connector)
  1992. return false;
  1993. intel_connector = &intel_sdvo_connector->base;
  1994. connector = &intel_connector->base;
  1995. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1996. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1997. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1998. if (device == 0) {
  1999. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2000. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2001. } else if (device == 1) {
  2002. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2003. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2004. }
  2005. intel_sdvo_connector_init(intel_sdvo_connector,
  2006. intel_sdvo);
  2007. return true;
  2008. }
  2009. static bool
  2010. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2011. {
  2012. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2013. struct drm_connector *connector;
  2014. struct intel_connector *intel_connector;
  2015. struct intel_sdvo_connector *intel_sdvo_connector;
  2016. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2017. if (!intel_sdvo_connector)
  2018. return false;
  2019. intel_connector = &intel_sdvo_connector->base;
  2020. connector = &intel_connector->base;
  2021. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2022. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2023. if (device == 0) {
  2024. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2025. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2026. } else if (device == 1) {
  2027. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2028. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2029. }
  2030. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2031. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2032. goto err;
  2033. return true;
  2034. err:
  2035. intel_sdvo_destroy(connector);
  2036. return false;
  2037. }
  2038. static bool
  2039. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2040. {
  2041. intel_sdvo->is_tv = false;
  2042. intel_sdvo->base.needs_tv_clock = false;
  2043. intel_sdvo->is_lvds = false;
  2044. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2045. if (flags & SDVO_OUTPUT_TMDS0)
  2046. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2047. return false;
  2048. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2049. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2050. return false;
  2051. /* TV has no XXX1 function block */
  2052. if (flags & SDVO_OUTPUT_SVID0)
  2053. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2054. return false;
  2055. if (flags & SDVO_OUTPUT_CVBS0)
  2056. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2057. return false;
  2058. if (flags & SDVO_OUTPUT_YPRPB0)
  2059. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2060. return false;
  2061. if (flags & SDVO_OUTPUT_RGB0)
  2062. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2063. return false;
  2064. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2065. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2066. return false;
  2067. if (flags & SDVO_OUTPUT_LVDS0)
  2068. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2069. return false;
  2070. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2071. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2072. return false;
  2073. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2074. unsigned char bytes[2];
  2075. intel_sdvo->controlled_output = 0;
  2076. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2077. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2078. SDVO_NAME(intel_sdvo),
  2079. bytes[0], bytes[1]);
  2080. return false;
  2081. }
  2082. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2083. return true;
  2084. }
  2085. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2086. {
  2087. struct drm_device *dev = intel_sdvo->base.base.dev;
  2088. struct drm_connector *connector, *tmp;
  2089. list_for_each_entry_safe(connector, tmp,
  2090. &dev->mode_config.connector_list, head) {
  2091. if (intel_attached_encoder(connector) == &intel_sdvo->base)
  2092. intel_sdvo_destroy(connector);
  2093. }
  2094. }
  2095. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2096. struct intel_sdvo_connector *intel_sdvo_connector,
  2097. int type)
  2098. {
  2099. struct drm_device *dev = intel_sdvo->base.base.dev;
  2100. struct intel_sdvo_tv_format format;
  2101. uint32_t format_map, i;
  2102. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2103. return false;
  2104. BUILD_BUG_ON(sizeof(format) != 6);
  2105. if (!intel_sdvo_get_value(intel_sdvo,
  2106. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2107. &format, sizeof(format)))
  2108. return false;
  2109. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2110. if (format_map == 0)
  2111. return false;
  2112. intel_sdvo_connector->format_supported_num = 0;
  2113. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2114. if (format_map & (1 << i))
  2115. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2116. intel_sdvo_connector->tv_format =
  2117. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2118. "mode", intel_sdvo_connector->format_supported_num);
  2119. if (!intel_sdvo_connector->tv_format)
  2120. return false;
  2121. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2122. drm_property_add_enum(
  2123. intel_sdvo_connector->tv_format, i,
  2124. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2125. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2126. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2127. intel_sdvo_connector->tv_format, 0);
  2128. return true;
  2129. }
  2130. #define ENHANCEMENT(name, NAME) do { \
  2131. if (enhancements.name) { \
  2132. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2133. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2134. return false; \
  2135. intel_sdvo_connector->max_##name = data_value[0]; \
  2136. intel_sdvo_connector->cur_##name = response; \
  2137. intel_sdvo_connector->name = \
  2138. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2139. if (!intel_sdvo_connector->name) return false; \
  2140. drm_object_attach_property(&connector->base, \
  2141. intel_sdvo_connector->name, \
  2142. intel_sdvo_connector->cur_##name); \
  2143. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2144. data_value[0], data_value[1], response); \
  2145. } \
  2146. } while (0)
  2147. static bool
  2148. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2149. struct intel_sdvo_connector *intel_sdvo_connector,
  2150. struct intel_sdvo_enhancements_reply enhancements)
  2151. {
  2152. struct drm_device *dev = intel_sdvo->base.base.dev;
  2153. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2154. uint16_t response, data_value[2];
  2155. /* when horizontal overscan is supported, Add the left/right property */
  2156. if (enhancements.overscan_h) {
  2157. if (!intel_sdvo_get_value(intel_sdvo,
  2158. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2159. &data_value, 4))
  2160. return false;
  2161. if (!intel_sdvo_get_value(intel_sdvo,
  2162. SDVO_CMD_GET_OVERSCAN_H,
  2163. &response, 2))
  2164. return false;
  2165. intel_sdvo_connector->max_hscan = data_value[0];
  2166. intel_sdvo_connector->left_margin = data_value[0] - response;
  2167. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2168. intel_sdvo_connector->left =
  2169. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2170. if (!intel_sdvo_connector->left)
  2171. return false;
  2172. drm_object_attach_property(&connector->base,
  2173. intel_sdvo_connector->left,
  2174. intel_sdvo_connector->left_margin);
  2175. intel_sdvo_connector->right =
  2176. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2177. if (!intel_sdvo_connector->right)
  2178. return false;
  2179. drm_object_attach_property(&connector->base,
  2180. intel_sdvo_connector->right,
  2181. intel_sdvo_connector->right_margin);
  2182. DRM_DEBUG_KMS("h_overscan: max %d, "
  2183. "default %d, current %d\n",
  2184. data_value[0], data_value[1], response);
  2185. }
  2186. if (enhancements.overscan_v) {
  2187. if (!intel_sdvo_get_value(intel_sdvo,
  2188. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2189. &data_value, 4))
  2190. return false;
  2191. if (!intel_sdvo_get_value(intel_sdvo,
  2192. SDVO_CMD_GET_OVERSCAN_V,
  2193. &response, 2))
  2194. return false;
  2195. intel_sdvo_connector->max_vscan = data_value[0];
  2196. intel_sdvo_connector->top_margin = data_value[0] - response;
  2197. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2198. intel_sdvo_connector->top =
  2199. drm_property_create_range(dev, 0,
  2200. "top_margin", 0, data_value[0]);
  2201. if (!intel_sdvo_connector->top)
  2202. return false;
  2203. drm_object_attach_property(&connector->base,
  2204. intel_sdvo_connector->top,
  2205. intel_sdvo_connector->top_margin);
  2206. intel_sdvo_connector->bottom =
  2207. drm_property_create_range(dev, 0,
  2208. "bottom_margin", 0, data_value[0]);
  2209. if (!intel_sdvo_connector->bottom)
  2210. return false;
  2211. drm_object_attach_property(&connector->base,
  2212. intel_sdvo_connector->bottom,
  2213. intel_sdvo_connector->bottom_margin);
  2214. DRM_DEBUG_KMS("v_overscan: max %d, "
  2215. "default %d, current %d\n",
  2216. data_value[0], data_value[1], response);
  2217. }
  2218. ENHANCEMENT(hpos, HPOS);
  2219. ENHANCEMENT(vpos, VPOS);
  2220. ENHANCEMENT(saturation, SATURATION);
  2221. ENHANCEMENT(contrast, CONTRAST);
  2222. ENHANCEMENT(hue, HUE);
  2223. ENHANCEMENT(sharpness, SHARPNESS);
  2224. ENHANCEMENT(brightness, BRIGHTNESS);
  2225. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2226. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2227. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2228. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2229. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2230. if (enhancements.dot_crawl) {
  2231. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2232. return false;
  2233. intel_sdvo_connector->max_dot_crawl = 1;
  2234. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2235. intel_sdvo_connector->dot_crawl =
  2236. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2237. if (!intel_sdvo_connector->dot_crawl)
  2238. return false;
  2239. drm_object_attach_property(&connector->base,
  2240. intel_sdvo_connector->dot_crawl,
  2241. intel_sdvo_connector->cur_dot_crawl);
  2242. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2243. }
  2244. return true;
  2245. }
  2246. static bool
  2247. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2248. struct intel_sdvo_connector *intel_sdvo_connector,
  2249. struct intel_sdvo_enhancements_reply enhancements)
  2250. {
  2251. struct drm_device *dev = intel_sdvo->base.base.dev;
  2252. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2253. uint16_t response, data_value[2];
  2254. ENHANCEMENT(brightness, BRIGHTNESS);
  2255. return true;
  2256. }
  2257. #undef ENHANCEMENT
  2258. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2259. struct intel_sdvo_connector *intel_sdvo_connector)
  2260. {
  2261. union {
  2262. struct intel_sdvo_enhancements_reply reply;
  2263. uint16_t response;
  2264. } enhancements;
  2265. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2266. enhancements.response = 0;
  2267. intel_sdvo_get_value(intel_sdvo,
  2268. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2269. &enhancements, sizeof(enhancements));
  2270. if (enhancements.response == 0) {
  2271. DRM_DEBUG_KMS("No enhancement is supported\n");
  2272. return true;
  2273. }
  2274. if (IS_TV(intel_sdvo_connector))
  2275. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2276. else if (IS_LVDS(intel_sdvo_connector))
  2277. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2278. else
  2279. return true;
  2280. }
  2281. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2282. struct i2c_msg *msgs,
  2283. int num)
  2284. {
  2285. struct intel_sdvo *sdvo = adapter->algo_data;
  2286. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2287. return -EIO;
  2288. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2289. }
  2290. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2291. {
  2292. struct intel_sdvo *sdvo = adapter->algo_data;
  2293. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2294. }
  2295. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2296. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2297. .functionality = intel_sdvo_ddc_proxy_func
  2298. };
  2299. static bool
  2300. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2301. struct drm_device *dev)
  2302. {
  2303. sdvo->ddc.owner = THIS_MODULE;
  2304. sdvo->ddc.class = I2C_CLASS_DDC;
  2305. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2306. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2307. sdvo->ddc.algo_data = sdvo;
  2308. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2309. return i2c_add_adapter(&sdvo->ddc) == 0;
  2310. }
  2311. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2312. {
  2313. struct drm_i915_private *dev_priv = dev->dev_private;
  2314. struct intel_encoder *intel_encoder;
  2315. struct intel_sdvo *intel_sdvo;
  2316. u32 hotplug_mask;
  2317. int i;
  2318. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2319. if (!intel_sdvo)
  2320. return false;
  2321. intel_sdvo->sdvo_reg = sdvo_reg;
  2322. intel_sdvo->is_sdvob = is_sdvob;
  2323. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2324. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2325. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2326. goto err_i2c_bus;
  2327. /* encoder type will be decided later */
  2328. intel_encoder = &intel_sdvo->base;
  2329. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2330. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2331. /* Read the regs to test if we can talk to the device */
  2332. for (i = 0; i < 0x40; i++) {
  2333. u8 byte;
  2334. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2335. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2336. SDVO_NAME(intel_sdvo));
  2337. goto err;
  2338. }
  2339. }
  2340. hotplug_mask = 0;
  2341. if (IS_G4X(dev)) {
  2342. hotplug_mask = intel_sdvo->is_sdvob ?
  2343. SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
  2344. } else if (IS_GEN4(dev)) {
  2345. hotplug_mask = intel_sdvo->is_sdvob ?
  2346. SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
  2347. } else {
  2348. hotplug_mask = intel_sdvo->is_sdvob ?
  2349. SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
  2350. }
  2351. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2352. intel_encoder->disable = intel_disable_sdvo;
  2353. intel_encoder->enable = intel_enable_sdvo;
  2354. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2355. /* In default case sdvo lvds is false */
  2356. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2357. goto err;
  2358. if (intel_sdvo_output_setup(intel_sdvo,
  2359. intel_sdvo->caps.output_flags) != true) {
  2360. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2361. SDVO_NAME(intel_sdvo));
  2362. /* Output_setup can leave behind connectors! */
  2363. goto err_output;
  2364. }
  2365. /*
  2366. * Cloning SDVO with anything is often impossible, since the SDVO
  2367. * encoder can request a special input timing mode. And even if that's
  2368. * not the case we have evidence that cloning a plain unscaled mode with
  2369. * VGA doesn't really work. Furthermore the cloning flags are way too
  2370. * simplistic anyway to express such constraints, so just give up on
  2371. * cloning for SDVO encoders.
  2372. */
  2373. intel_sdvo->base.cloneable = false;
  2374. /* Only enable the hotplug irq if we need it, to work around noisy
  2375. * hotplug lines.
  2376. */
  2377. if (intel_sdvo->hotplug_active)
  2378. dev_priv->hotplug_supported_mask |= hotplug_mask;
  2379. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2380. /* Set the input timing to the screen. Assume always input 0. */
  2381. if (!intel_sdvo_set_target_input(intel_sdvo))
  2382. goto err_output;
  2383. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2384. &intel_sdvo->pixel_clock_min,
  2385. &intel_sdvo->pixel_clock_max))
  2386. goto err_output;
  2387. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2388. "clock range %dMHz - %dMHz, "
  2389. "input 1: %c, input 2: %c, "
  2390. "output 1: %c, output 2: %c\n",
  2391. SDVO_NAME(intel_sdvo),
  2392. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2393. intel_sdvo->caps.device_rev_id,
  2394. intel_sdvo->pixel_clock_min / 1000,
  2395. intel_sdvo->pixel_clock_max / 1000,
  2396. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2397. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2398. /* check currently supported outputs */
  2399. intel_sdvo->caps.output_flags &
  2400. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2401. intel_sdvo->caps.output_flags &
  2402. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2403. return true;
  2404. err_output:
  2405. intel_sdvo_output_cleanup(intel_sdvo);
  2406. err:
  2407. drm_encoder_cleanup(&intel_encoder->base);
  2408. i2c_del_adapter(&intel_sdvo->ddc);
  2409. err_i2c_bus:
  2410. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2411. kfree(intel_sdvo);
  2412. return false;
  2413. }